SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/staging/rtl8192e/r8192E_dm.c

   1 /*++
   2 Copyright-c Realtek Semiconductor Corp. All rights reserved.
   3
   4 Module Name:
   5         r8192U_dm.c
   6
   7 Abstract:
   8         HW dynamic mechanism.
   9
  10 Major Change History:
  11         When            Who                             What
  12         ----------      --------------- -------------------------------
  13         2008-05-14      amy                     create version 0 porting from windows code.
  14
  15 --*/
  16 #include "r8192E.h"
  17 #include "r8192E_dm.h"
  18 #include "r8192E_hw.h"
  19 #include "r819xE_phy.h"
  20 #include "r819xE_phyreg.h"
  21 #include "r8190_rtl8256.h"
  22 /*---------------------------Define Local Constant---------------------------*/
  23 //
  24 // Indicate different AP vendor for IOT issue.
  25 //
  26 #ifdef  RTL8190P
  27 static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
  28 { 0x5e4322,     0x5e4322,       0x5e4322,       0x604322,       0xa44f,         0x5e4322};
  29 static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
  30 { 0x5e4322,     0xa44f,         0x5e4322,       0x604322,       0x5e4322,       0x5e4322};
  31 #else
  32 #ifdef RTL8192E
  33 static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
  34 { 0x5e4322,     0x5e4322,       0x5e4322,       0x604322,       0xa44f,         0x5e4322};
  35 static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
  36 { 0x5e4322,     0xa44f,         0x5e4322,       0x604322,       0x5e4322,       0x5e4322};
  37 #else
  38 static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
  39 { 0x5e4322,     0x5e4322,       0x5e4322,       0x604322,       0xa44f,         0x5ea44f};
  40 static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
  41 { 0x5e4322,     0xa44f,         0x5e4322,       0x604322,       0x5ea44f,       0x5ea44f};
  42 #endif
  43 #endif
  44
  45 #define RTK_UL_EDCA 0xa44f
  46 #define RTK_DL_EDCA 0x5e4322
  47 /*---------------------------Define Local Constant---------------------------*/
  48
  49
  50 /*------------------------Define global variable-----------------------------*/
  51 // Debug variable ?
  52 dig_t   dm_digtable;
  53 // Store current shoftware write register content for MAC PHY.
  54 u8              dm_shadow[16][256] = {{0}};
  55 // For Dynamic Rx Path Selection by Signal Strength
  56 DRxPathSel      DM_RxPathSelTable;
  57 /*------------------------Define global variable-----------------------------*/
  58
  59
  60 /*------------------------Define local variable------------------------------*/
  61 /*------------------------Define local variable------------------------------*/
  62
  63
  64 /*--------------------Define export function prototype-----------------------*/
  65 extern  void    init_hal_dm(struct net_device *dev);
  66 extern  void deinit_hal_dm(struct net_device *dev);
  67
  68 extern void hal_dm_watchdog(struct net_device *dev);
  69
  70
  71 extern  void    init_rate_adaptive(struct net_device *dev);
  72 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
  73 extern  void    dm_txpower_trackingcallback(struct work_struct *work);
  74 #else
  75 extern  void    dm_txpower_trackingcallback(struct net_device *dev);
  76 #endif
  77
  78 extern  void    dm_cck_txpower_adjust(struct net_device *dev,bool  binch14);
  79 extern  void    dm_restore_dynamic_mechanism_state(struct net_device *dev);
  80 extern  void    dm_backup_dynamic_mechanism_state(struct net_device *dev);
  81 extern  void    dm_change_dynamic_initgain_thresh(struct net_device *dev,
  82                                                                 u32             dm_type,
  83                                                                 u32             dm_value);
  84 extern  void    DM_ChangeFsyncSetting(struct net_device *dev,
  85                                                                                                 s32             DM_Type,
  86                                                                                                 s32             DM_Value);
  87 extern  void dm_force_tx_fw_info(struct net_device *dev,
  88                                                                                 u32             force_type,
  89                                                                                 u32             force_value);
  90 extern  void    dm_init_edca_turbo(struct net_device *dev);
  91 extern  void    dm_rf_operation_test_callback(unsigned long data);
  92 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
  93 extern  void    dm_rf_pathcheck_workitemcallback(struct work_struct *work);
  94 #else
  95 extern  void    dm_rf_pathcheck_workitemcallback(struct net_device *dev);
  96 #endif
  97 extern  void dm_fsync_timer_callback(unsigned long data);
  98 #if 0
  99 extern  bool    dm_check_lbus_status(struct net_device *dev);
 100 #endif
 101 extern  void dm_check_fsync(struct net_device *dev);
 102 extern  void    dm_shadow_init(struct net_device *dev);
 103 extern  void dm_initialize_txpower_tracking(struct net_device *dev);
 104
 105 #ifdef RTL8192E
 106 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
 107 extern  void    dm_gpio_change_rf_callback(struct work_struct *work);
 108 #else
 109 extern  void    dm_gpio_change_rf_callback(struct net_device *dev);
 110 #endif
 111 #endif
 112
 113
 114
 115 /*--------------------Define export function prototype-----------------------*/
 116
 117
 118 /*---------------------Define local function prototype-----------------------*/
 119 // DM --> Rate Adaptive
 120 static  void    dm_check_rate_adaptive(struct net_device *dev);
 121
 122 // DM --> Bandwidth switch
 123 static  void    dm_init_bandwidth_autoswitch(struct net_device *dev);
 124 static  void    dm_bandwidth_autoswitch(        struct net_device *dev);
 125
 126 // DM --> TX power control
 127 //static        void    dm_initialize_txpower_tracking(struct net_device *dev);
 128
 129 static  void    dm_check_txpower_tracking(struct net_device *dev);
 130
 131
 132
 133 //static        void    dm_txpower_reset_recovery(struct net_device *dev);
 134
 135
 136 // DM --> BB init gain restore
 137 #ifndef RTL8192U
 138 static  void    dm_bb_initialgain_restore(struct net_device *dev);
 139
 140
 141 // DM --> BB init gain backup
 142 static  void    dm_bb_initialgain_backup(struct net_device *dev);
 143 #endif
 144
 145 // DM --> Dynamic Init Gain by RSSI
 146 static  void    dm_dig_init(struct net_device *dev);
 147 static  void    dm_ctrl_initgain_byrssi(struct net_device *dev);
 148 static  void    dm_ctrl_initgain_byrssi_highpwr(struct net_device *dev);
 149 static  void    dm_ctrl_initgain_byrssi_by_driverrssi(  struct net_device *dev);
 150 static  void    dm_ctrl_initgain_byrssi_by_fwfalse_alarm(struct net_device *dev);
 151 static  void    dm_initial_gain(struct net_device *dev);
 152 static  void    dm_pd_th(struct net_device *dev);
 153 static  void    dm_cs_ratio(struct net_device *dev);
 154
 155 static  void dm_init_ctstoself(struct net_device *dev);
 156 // DM --> EDCA turboe mode control
 157 static  void    dm_check_edca_turbo(struct net_device *dev);
 158
 159 // DM --> HW RF control
 160 static  void    dm_check_rfctrl_gpio(struct net_device *dev);
 161
 162 #ifndef RTL8190P
 163 //static        void    dm_gpio_change_rf(struct net_device *dev);
 164 #endif
 165 // DM --> Check PBC
 166 static  void dm_check_pbc_gpio(struct net_device *dev);
 167
 168
 169 // DM --> Check current RX RF path state
 170 static  void    dm_check_rx_path_selection(struct net_device *dev);
 171 static  void dm_init_rxpath_selection(struct net_device *dev);
 172 static  void dm_rxpath_sel_byrssi(struct net_device *dev);
 173
 174
 175 // DM --> Fsync for broadcom ap
 176 static void dm_init_fsync(struct net_device *dev);
 177 static void dm_deInit_fsync(struct net_device *dev);
 178
 179 //Added by vivi, 20080522
 180 static  void    dm_check_txrateandretrycount(struct net_device *dev);
 181
 182 /*---------------------Define local function prototype-----------------------*/
 183
 184 /*---------------------Define of Tx Power Control For Near/Far Range --------*/   //Add by Jacken 2008/02/18
 185 static  void    dm_init_dynamic_txpower(struct net_device *dev);
 186 static  void    dm_dynamic_txpower(struct net_device *dev);
 187
 188
 189 // DM --> For rate adaptive and DIG, we must send RSSI to firmware
 190 static  void dm_send_rssi_tofw(struct net_device *dev);
 191 static  void    dm_ctstoself(struct net_device *dev);
 192 /*---------------------------Define function prototype------------------------*/
 193 //================================================================================
 194 //      HW Dynamic mechanism interface.
 195 //================================================================================
 196
 197 //
 198 //      Description:
 199 //              Prepare SW resource for HW dynamic mechanism.
 200 //
 201 //      Assumption:
 202 //              This function is only invoked at driver intialization once.
 203 //
 204 //
 205 void init_hal_dm(struct net_device *dev)
 206 {
 207         struct r8192_priv *priv = ieee80211_priv(dev);
 208
 209         // Undecorated Smoothed Signal Strength, it can utilized to dynamic mechanism.
 210         priv->undecorated_smoothed_pwdb = -1;
 211
 212         //Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code.
 213         dm_init_dynamic_txpower(dev);
 214         init_rate_adaptive(dev);
 215         //dm_initialize_txpower_tracking(dev);
 216         dm_dig_init(dev);
 217         dm_init_edca_turbo(dev);
 218         dm_init_bandwidth_autoswitch(dev);
 219         dm_init_fsync(dev);
 220         dm_init_rxpath_selection(dev);
 221         dm_init_ctstoself(dev);
 222 #ifdef RTL8192E
 223 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
 224         INIT_DELAYED_WORK(&priv->gpio_change_rf_wq,  dm_gpio_change_rf_callback);
 225 #else
 226         INIT_WORK(&priv->gpio_change_rf_wq, (void(*)(void*)) dm_gpio_change_rf_callback,dev);
 227 #endif
 228 #endif
 229
 230 }       // InitHalDm
 231
 232 void deinit_hal_dm(struct net_device *dev)
 233 {
 234
 235         dm_deInit_fsync(dev);
 236
 237 }
 238
 239
 240 #ifdef USB_RX_AGGREGATION_SUPPORT
 241 void dm_CheckRxAggregation(struct net_device *dev) {
 242         struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
 243         PRT_HIGH_THROUGHPUT     pHTInfo = priv->ieee80211->pHTInfo;
 244         static unsigned long    lastTxOkCnt = 0;
 245         static unsigned long    lastRxOkCnt = 0;
 246         unsigned long           curTxOkCnt = 0;
 247         unsigned long           curRxOkCnt = 0;
 248
 249 /*
 250         if (pHalData->bForcedUsbRxAggr) {
 251                 if (pHalData->ForcedUsbRxAggrInfo == 0) {
 252                         if (pHalData->bCurrentRxAggrEnable) {
 253                                 Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, FALSE);
 254                         }
 255                 } else {
 256                         if (!pHalData->bCurrentRxAggrEnable || (pHalData->ForcedUsbRxAggrInfo != pHalData->LastUsbRxAggrInfoSetting)) {
 257                                 Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, TRUE);
 258                         }
 259                 }
 260                 return;
 261         }
 262
 263 */
 264         curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
 265         curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
 266
 267         if((curTxOkCnt + curRxOkCnt) < 15000000) {
 268                 return;
 269         }
 270
 271         if(curTxOkCnt > 4*curRxOkCnt) {
 272                 if (priv->bCurrentRxAggrEnable) {
 273                         write_nic_dword(dev, 0x1a8, 0);
 274                         priv->bCurrentRxAggrEnable = false;
 275                 }
 276         }else{
 277                 if (!priv->bCurrentRxAggrEnable && !pHTInfo->bCurrentRT2RTAggregation) {
 278                         u32 ulValue;
 279                         ulValue = (pHTInfo->UsbRxFwAggrEn<<24) | (pHTInfo->UsbRxFwAggrPageNum<<16) |
 280                                 (pHTInfo->UsbRxFwAggrPacketNum<<8) | (pHTInfo->UsbRxFwAggrTimeout);
 281                         /*
 282                          * If usb rx firmware aggregation is enabled,
 283                          * when anyone of three threshold conditions above is reached,
 284                          * firmware will send aggregated packet to driver.
 285                          */
 286                         write_nic_dword(dev, 0x1a8, ulValue);
 287                         priv->bCurrentRxAggrEnable = true;
 288                 }
 289         }
 290
 291         lastTxOkCnt = priv->stats.txbytesunicast;
 292         lastRxOkCnt = priv->stats.rxbytesunicast;
 293 }       // dm_CheckEdcaTurbo
 294 #endif
 295
 296
 297
 298 void hal_dm_watchdog(struct net_device *dev)
 299 {
 300         //struct r8192_priv *priv = ieee80211_priv(dev);
 301
 302         //static u8     previous_bssid[6] ={0};
 303
 304         /*Add by amy 2008/05/15 ,porting from windows code.*/
 305         dm_check_rate_adaptive(dev);
 306         dm_dynamic_txpower(dev);
 307         dm_check_txrateandretrycount(dev);
 308
 309         dm_check_txpower_tracking(dev);
 310
 311         dm_ctrl_initgain_byrssi(dev);
 312         dm_check_edca_turbo(dev);
 313         dm_bandwidth_autoswitch(dev);
 314
 315         dm_check_rfctrl_gpio(dev);
 316         dm_check_rx_path_selection(dev);
 317         dm_check_fsync(dev);
 318
 319         // Add by amy 2008-05-15 porting from windows code.
 320         dm_check_pbc_gpio(dev);
 321         dm_send_rssi_tofw(dev);
 322         dm_ctstoself(dev);
 323
 324 #ifdef USB_RX_AGGREGATION_SUPPORT
 325         dm_CheckRxAggregation(dev);
 326 #endif
 327 }       //HalDmWatchDog
 328
 329
 330 /*
 331   * Decide Rate Adaptive Set according to distance (signal strength)
 332   *     01/11/2008      MHC             Modify input arguments and RATR table level.
 333   *     01/16/2008      MHC             RF_Type is assigned in ReadAdapterInfo(). We must call
 334   *                                             the function after making sure RF_Type.
 335   */
 336 void init_rate_adaptive(struct net_device * dev)
 337 {
 338
 339         struct r8192_priv *priv = ieee80211_priv(dev);
 340         prate_adaptive                  pra = (prate_adaptive)&priv->rate_adaptive;
 341
 342         pra->ratr_state = DM_RATR_STA_MAX;
 343         pra->high2low_rssi_thresh_for_ra = RateAdaptiveTH_High;
 344         pra->low2high_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M+5;
 345         pra->low2high_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M+5;
 346
 347         pra->high_rssi_thresh_for_ra = RateAdaptiveTH_High+5;
 348         pra->low_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M;
 349         pra->low_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M;
 350
 351         if(priv->CustomerID == RT_CID_819x_Netcore)
 352                 pra->ping_rssi_enable = 1;
 353         else
 354                 pra->ping_rssi_enable = 0;
 355         pra->ping_rssi_thresh_for_ra = 15;
 356
 357
 358         if (priv->rf_type == RF_2T4R)
 359         {
 360                 // 07/10/08 MH Modify for RA smooth scheme.
 361                 /* 2008/01/11 MH Modify 2T RATR table for different RSSI. 080515 porting by amy from windows code.*/
 362                 pra->upper_rssi_threshold_ratr          =       0x8f0f0000;
 363                 pra->middle_rssi_threshold_ratr         =       0x8f0ff000;
 364                 pra->low_rssi_threshold_ratr            =       0x8f0ff001;
 365                 pra->low_rssi_threshold_ratr_40M        =       0x8f0ff005;
 366                 pra->low_rssi_threshold_ratr_20M        =       0x8f0ff001;
 367                 pra->ping_rssi_ratr     =       0x0000000d;//cosa add for test
 368         }
 369         else if (priv->rf_type == RF_1T2R)
 370         {
 371                 pra->upper_rssi_threshold_ratr          =       0x000f0000;
 372                 pra->middle_rssi_threshold_ratr         =       0x000ff000;
 373                 pra->low_rssi_threshold_ratr            =       0x000ff001;
 374                 pra->low_rssi_threshold_ratr_40M        =       0x000ff005;
 375                 pra->low_rssi_threshold_ratr_20M        =       0x000ff001;
 376                 pra->ping_rssi_ratr     =       0x0000000d;//cosa add for test
 377         }
 378
 379 }       // InitRateAdaptive
 380
 381
 382 /*-----------------------------------------------------------------------------
 383  * Function:    dm_check_rate_adaptive()
 384  *
 385  * Overview:
 386  *
 387  * Input:               NONE
 388  *
 389  * Output:              NONE
 390  *
 391  * Return:              NONE
 392  *
 393  * Revised History:
 394  *      When            Who             Remark
 395  *      05/26/08        amy     Create version 0 proting from windows code.
 396  *
 397  *---------------------------------------------------------------------------*/
 398 static void dm_check_rate_adaptive(struct net_device * dev)
 399 {
 400         struct r8192_priv *priv = ieee80211_priv(dev);
 401         PRT_HIGH_THROUGHPUT     pHTInfo = priv->ieee80211->pHTInfo;
 402         prate_adaptive                  pra = (prate_adaptive)&priv->rate_adaptive;
 403         u32                                             currentRATR, targetRATR = 0;
 404         u32                                             LowRSSIThreshForRA = 0, HighRSSIThreshForRA = 0;
 405         bool                                            bshort_gi_enabled = false;
 406         static u8                                       ping_rssi_state=0;
 407
 408
 409         if(!priv->up)
 410         {
 411                 RT_TRACE(COMP_RATE, "<---- dm_check_rate_adaptive(): driver is going to unload\n");
 412                 return;
 413         }
 414
 415         if(pra->rate_adaptive_disabled)//this variable is set by ioctl.
 416                 return;
 417
 418         // TODO: Only 11n mode is implemented currently,
 419         if( !(priv->ieee80211->mode == WIRELESS_MODE_N_24G ||
 420                  priv->ieee80211->mode == WIRELESS_MODE_N_5G))
 421                  return;
 422
 423         if( priv->ieee80211->state == IEEE80211_LINKED )
 424         {
 425         //      RT_TRACE(COMP_RATE, "dm_CheckRateAdaptive(): \t");
 426
 427                 //
 428                 // Check whether Short GI is enabled
 429                 //
 430                 bshort_gi_enabled = (pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI40MHz) ||
 431                         (!pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI20MHz);
 432
 433
 434                 pra->upper_rssi_threshold_ratr =
 435                                 (pra->upper_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
 436
 437                 pra->middle_rssi_threshold_ratr =
 438                                 (pra->middle_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
 439
 440                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
 441                 {
 442                         pra->low_rssi_threshold_ratr =
 443                                 (pra->low_rssi_threshold_ratr_40M & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
 444                 }
 445                 else
 446                 {
 447                         pra->low_rssi_threshold_ratr =
 448                         (pra->low_rssi_threshold_ratr_20M & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
 449                 }
 450                 //cosa add for test
 451                 pra->ping_rssi_ratr =
 452                                 (pra->ping_rssi_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
 453
 454                 /* 2007/10/08 MH We support RA smooth scheme now. When it is the first
 455                    time to link with AP. We will not change upper/lower threshold. If
 456                    STA stay in high or low level, we must change two different threshold
 457                    to prevent jumping frequently. */
 458                 if (pra->ratr_state == DM_RATR_STA_HIGH)
 459                 {
 460                         HighRSSIThreshForRA     = pra->high2low_rssi_thresh_for_ra;
 461                         LowRSSIThreshForRA      = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)?
 462                                         (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M);
 463                 }
 464                 else if (pra->ratr_state == DM_RATR_STA_LOW)
 465                 {
 466                         HighRSSIThreshForRA     = pra->high_rssi_thresh_for_ra;
 467                         LowRSSIThreshForRA      = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)?
 468                                         (pra->low2high_rssi_thresh_for_ra40M):(pra->low2high_rssi_thresh_for_ra20M);
 469                 }
 470                 else
 471                 {
 472                         HighRSSIThreshForRA     = pra->high_rssi_thresh_for_ra;
 473                         LowRSSIThreshForRA      = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)?
 474                                         (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M);
 475                 }
 476
 477                 //DbgPrint("[DM] THresh H/L=%d/%d\n\r", RATR.HighRSSIThreshForRA, RATR.LowRSSIThreshForRA);
 478                 if(priv->undecorated_smoothed_pwdb >= (long)HighRSSIThreshForRA)
 479                 {
 480                         //DbgPrint("[DM] RSSI=%d STA=HIGH\n\r", pHalData->UndecoratedSmoothedPWDB);
 481                         pra->ratr_state = DM_RATR_STA_HIGH;
 482                         targetRATR = pra->upper_rssi_threshold_ratr;
 483                 }else if(priv->undecorated_smoothed_pwdb >= (long)LowRSSIThreshForRA)
 484                 {
 485                         //DbgPrint("[DM] RSSI=%d STA=Middle\n\r", pHalData->UndecoratedSmoothedPWDB);
 486                         pra->ratr_state = DM_RATR_STA_MIDDLE;
 487                         targetRATR = pra->middle_rssi_threshold_ratr;
 488                 }else
 489                 {
 490                         //DbgPrint("[DM] RSSI=%d STA=LOW\n\r", pHalData->UndecoratedSmoothedPWDB);
 491                         pra->ratr_state = DM_RATR_STA_LOW;
 492                         targetRATR = pra->low_rssi_threshold_ratr;
 493                 }
 494
 495                         //cosa add for test
 496                 if(pra->ping_rssi_enable)
 497                 {
 498                         //pHalData->UndecoratedSmoothedPWDB = 19;
 499                         if(priv->undecorated_smoothed_pwdb < (long)(pra->ping_rssi_thresh_for_ra+5))
 500                         {
 501                                 if( (priv->undecorated_smoothed_pwdb < (long)pra->ping_rssi_thresh_for_ra) ||
 502                                         ping_rssi_state )
 503                                 {
 504                                         //DbgPrint("TestRSSI = %d, set RATR to 0x%x \n", pHalData->UndecoratedSmoothedPWDB, pRA->TestRSSIRATR);
 505                                         pra->ratr_state = DM_RATR_STA_LOW;
 506                                         targetRATR = pra->ping_rssi_ratr;
 507                                         ping_rssi_state = 1;
 508                                 }
 509                                 //else
 510                                 //      DbgPrint("TestRSSI is between the range. \n");
 511                         }
 512                         else
 513                         {
 514                                 //DbgPrint("TestRSSI Recover to 0x%x \n", targetRATR);
 515                                 ping_rssi_state = 0;
 516                         }
 517                 }
 518
 519                 // 2008.04.01
 520 #if 1
 521                 // For RTL819X, if pairwisekey = wep/tkip, we support only MCS0~7.
 522                 if(priv->ieee80211->GetHalfNmodeSupportByAPsHandler(dev))
 523                         targetRATR &=  0xf00fffff;
 524 #endif
 525
 526                 //
 527                 // Check whether updating of RATR0 is required
 528                 //
 529                 currentRATR = read_nic_dword(dev, RATR0);
 530                 if( targetRATR !=  currentRATR )
 531                 {
 532                         u32 ratr_value;
 533                         ratr_value = targetRATR;
 534                         RT_TRACE(COMP_RATE,"currentRATR = %x, targetRATR = %x\n", currentRATR, targetRATR);
 535                         if(priv->rf_type == RF_1T2R)
 536                         {
 537                                 ratr_value &= ~(RATE_ALL_OFDM_2SS);
 538                         }
 539                         write_nic_dword(dev, RATR0, ratr_value);
 540                         write_nic_byte(dev, UFWP, 1);
 541
 542                         pra->last_ratr = targetRATR;
 543                 }
 544
 545         }
 546         else
 547         {
 548                 pra->ratr_state = DM_RATR_STA_MAX;
 549         }
 550
 551 }       // dm_CheckRateAdaptive
 552
 553
 554 static void dm_init_bandwidth_autoswitch(struct net_device * dev)
 555 {
 556         struct r8192_priv *priv = ieee80211_priv(dev);
 557
 558         priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz = BW_AUTO_SWITCH_LOW_HIGH;
 559         priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz = BW_AUTO_SWITCH_HIGH_LOW;
 560         priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false;
 561         priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable = false;
 562
 563 }       // dm_init_bandwidth_autoswitch
 564
 565
 566 static void dm_bandwidth_autoswitch(struct net_device * dev)
 567 {
 568         struct r8192_priv *priv = ieee80211_priv(dev);
 569
 570         if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ||!priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable){
 571                 return;
 572         }else{
 573                 if(priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz == false){//If send packets in 40 Mhz in 20/40
 574                         if(priv->undecorated_smoothed_pwdb <= priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz)
 575                                 priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = true;
 576                 }else{//in force send packets in 20 Mhz in 20/40
 577                         if(priv->undecorated_smoothed_pwdb >= priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz)
 578                                 priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false;
 579
 580                 }
 581         }
 582 }       // dm_BandwidthAutoSwitch
 583
 584 //OFDM default at 0db, index=6.
 585 #ifndef RTL8190P
 586 static u32 OFDMSwingTable[OFDM_Table_Length] = {
 587         0x7f8001fe,     // 0, +6db
 588         0x71c001c7,     // 1, +5db
 589         0x65400195,     // 2, +4db
 590         0x5a400169,     // 3, +3db
 591         0x50800142,     // 4, +2db
 592         0x47c0011f,     // 5, +1db
 593         0x40000100,     // 6, +0db ===> default, upper for higher temprature, lower for low temprature
 594         0x390000e4,     // 7, -1db
 595         0x32c000cb,     // 8, -2db
 596         0x2d4000b5,     // 9, -3db
 597         0x288000a2,     // 10, -4db
 598         0x24000090,     // 11, -5db
 599         0x20000080,     // 12, -6db
 600         0x1c800072,     // 13, -7db
 601         0x19800066,     // 14, -8db
 602         0x26c0005b,     // 15, -9db
 603         0x24400051,     // 16, -10db
 604         0x12000048,     // 17, -11db
 605         0x10000040      // 18, -12db
 606 };
 607 static u8       CCKSwingTable_Ch1_Ch13[CCK_Table_length][8] = {
 608         {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},       // 0, +0db ===> CCK40M default
 609         {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},       // 1, -1db
 610         {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},       // 2, -2db
 611         {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},       // 3, -3db
 612         {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},       // 4, -4db
 613         {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},       // 5, -5db
 614         {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},       // 6, -6db ===> CCK20M default
 615         {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},       // 7, -7db
 616         {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},       // 8, -8db
 617         {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},       // 9, -9db
 618         {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},       // 10, -10db
 619         {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}        // 11, -11db
 620 };
 621
 622 static u8       CCKSwingTable_Ch14[CCK_Table_length][8] = {
 623         {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},       // 0, +0db  ===> CCK40M default
 624         {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},       // 1, -1db
 625         {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},       // 2, -2db
 626         {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},       // 3, -3db
 627         {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},       // 4, -4db
 628         {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},       // 5, -5db
 629         {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},       // 6, -6db  ===> CCK20M default
 630         {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},       // 7, -7db
 631         {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},       // 8, -8db
 632         {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},       // 9, -9db
 633         {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},       // 10, -10db
 634         {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}        // 11, -11db
 635 };
 636 #endif
 637 #define         Pw_Track_Flag                           0x11d
 638 #define         Tssi_Mea_Value                          0x13c
 639 #define         Tssi_Report_Value1                      0x134
 640 #define         Tssi_Report_Value2                      0x13e
 641 #define         FW_Busy_Flag                            0x13f
 642 static void dm_TXPowerTrackingCallback_TSSI(struct net_device * dev)
 643         {
 644         struct r8192_priv *priv = ieee80211_priv(dev);
 645         bool                                            bHighpowerstate, viviflag = FALSE;
 646         DCMD_TXCMD_T                    tx_cmd;
 647         u8                                      powerlevelOFDM24G;
 648         int                                     i =0, j = 0, k = 0;
 649         u8                                              RF_Type, tmp_report[5]={0, 0, 0, 0, 0};
 650         u32                                             Value;
 651         u8                                              Pwr_Flag;
 652         u16                                     Avg_TSSI_Meas, TSSI_13dBm, Avg_TSSI_Meas_from_driver=0;
 653 #ifdef RTL8192U
 654         RT_STATUS                               rtStatus = RT_STATUS_SUCCESS;
 655 #endif
 656 //      bool rtStatus = true;
 657         u32                                             delta=0;
 658         RT_TRACE(COMP_POWER_TRACKING,"%s()\n",__FUNCTION__);
 659 //      write_nic_byte(dev, 0x1ba, 0);
 660         write_nic_byte(dev, Pw_Track_Flag, 0);
 661         write_nic_byte(dev, FW_Busy_Flag, 0);
 662         priv->ieee80211->bdynamic_txpower_enable = false;
 663         bHighpowerstate = priv->bDynamicTxHighPower;
 664
 665         powerlevelOFDM24G = (u8)(priv->Pwr_Track>>24);
 666         RF_Type = priv->rf_type;
 667         Value = (RF_Type<<8) | powerlevelOFDM24G;
 668
 669         RT_TRACE(COMP_POWER_TRACKING, "powerlevelOFDM24G = %x\n", powerlevelOFDM24G);
 670
 671         for(j = 0; j<=30; j++)
 672 {       //fill tx_cmd
 673
 674         tx_cmd.Op               = TXCMD_SET_TX_PWR_TRACKING;
 675         tx_cmd.Length   = 4;
 676         tx_cmd.Value            = Value;
 677 #ifdef RTL8192U
 678         rtStatus = SendTxCommandPacket(dev, &tx_cmd, 12);
 679         if (rtStatus == RT_STATUS_FAILURE)
 680         {
 681                 RT_TRACE(COMP_POWER_TRACKING, "Set configuration with tx cmd queue fail!\n");
 682         }
 683 #else
 684         cmpk_message_handle_tx(dev, (u8*)&tx_cmd, DESC_PACKET_TYPE_INIT, sizeof(DCMD_TXCMD_T));
 685 #endif
 686         mdelay(1);
 687         //DbgPrint("hi, vivi, strange\n");
 688         for(i = 0;i <= 30; i++)
 689         {
 690                 Pwr_Flag = read_nic_byte(dev, Pw_Track_Flag);
 691
 692                 if (Pwr_Flag == 0)
 693                 {
 694                         mdelay(1);
 695                         continue;
 696                 }
 697
 698                 Avg_TSSI_Meas = read_nic_word(dev, Tssi_Mea_Value);
 699
 700                 if(Avg_TSSI_Meas == 0)
 701                 {
 702                         write_nic_byte(dev, Pw_Track_Flag, 0);
 703                         write_nic_byte(dev, FW_Busy_Flag, 0);
 704                         return;
 705                 }
 706
 707                 for(k = 0;k < 5; k++)
 708                 {
 709                         if(k !=4)
 710                                 tmp_report[k] = read_nic_byte(dev, Tssi_Report_Value1+k);
 711                         else
 712                                 tmp_report[k] = read_nic_byte(dev, Tssi_Report_Value2);
 713
 714                         RT_TRACE(COMP_POWER_TRACKING, "TSSI_report_value = %d\n", tmp_report[k]);
 715                 }
 716
 717                 //check if the report value is right
 718                 for(k = 0;k < 5; k++)
 719                 {
 720                         if(tmp_report[k] <= 20)
 721                         {
 722                                 viviflag =TRUE;
 723                                 break;
 724                         }
 725                 }
 726                 if(viviflag ==TRUE)
 727                 {
 728                         write_nic_byte(dev, Pw_Track_Flag, 0);
 729                         viviflag = FALSE;
 730                         RT_TRACE(COMP_POWER_TRACKING, "we filted this data\n");
 731                         for(k = 0;k < 5; k++)
 732                                 tmp_report[k] = 0;
 733                         break;
 734                 }
 735
 736                 for(k = 0;k < 5; k++)
 737                 {
 738                         Avg_TSSI_Meas_from_driver += tmp_report[k];
 739                 }
 740
 741                 Avg_TSSI_Meas_from_driver = Avg_TSSI_Meas_from_driver*100/5;
 742                 RT_TRACE(COMP_POWER_TRACKING, "Avg_TSSI_Meas_from_driver = %d\n", Avg_TSSI_Meas_from_driver);
 743                 TSSI_13dBm = priv->TSSI_13dBm;
 744                 RT_TRACE(COMP_POWER_TRACKING, "TSSI_13dBm = %d\n", TSSI_13dBm);
 745
 746                 //if(abs(Avg_TSSI_Meas_from_driver - TSSI_13dBm) <= E_FOR_TX_POWER_TRACK)
 747                 // For MacOS-compatible
 748                 if(Avg_TSSI_Meas_from_driver > TSSI_13dBm)
 749                         delta = Avg_TSSI_Meas_from_driver - TSSI_13dBm;
 750                 else
 751                         delta = TSSI_13dBm - Avg_TSSI_Meas_from_driver;
 752
 753                 if(delta <= E_FOR_TX_POWER_TRACK)
 754                 {
 755                         priv->ieee80211->bdynamic_txpower_enable = TRUE;
 756                         write_nic_byte(dev, Pw_Track_Flag, 0);
 757                         write_nic_byte(dev, FW_Busy_Flag, 0);
 758                         RT_TRACE(COMP_POWER_TRACKING, "tx power track is done\n");
 759                         RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
 760                         RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
 761 #ifdef RTL8190P
 762                         RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex = %d\n", priv->rfc_txpowertrackingindex);
 763                         RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_real = %d\n", priv->rfc_txpowertrackingindex_real);
 764 #endif
 765                         RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_difference = %d\n", priv->CCKPresentAttentuation_difference);
 766                         RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
 767                         return;
 768                 }
 769                 else
 770                 {
 771                         if(Avg_TSSI_Meas_from_driver < TSSI_13dBm - E_FOR_TX_POWER_TRACK)
 772                         {
 773                                 if (RF_Type == RF_2T4R)
 774                                 {
 775
 776                                                 if((priv->rfa_txpowertrackingindex > 0) &&(priv->rfc_txpowertrackingindex > 0))
 777                                 {
 778                                         priv->rfa_txpowertrackingindex--;
 779                                         if(priv->rfa_txpowertrackingindex_real > 4)
 780                                         {
 781                                                 priv->rfa_txpowertrackingindex_real--;
 782                                                 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value);
 783                                         }
 784
 785                                         priv->rfc_txpowertrackingindex--;
 786                                         if(priv->rfc_txpowertrackingindex_real > 4)
 787                                         {
 788                                                 priv->rfc_txpowertrackingindex_real--;
 789                                                 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value);
 790                                         }
 791                                                 }
 792                                                 else
 793                                                 {
 794                                                                 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[4].txbbgain_value);
 795                                                                 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[4].txbbgain_value);
 796                                 }
 797                         }
 798                         else
 799                         {
 800                                                 if(priv->rfc_txpowertrackingindex > 0)
 801                                                 {
 802                                                         priv->rfc_txpowertrackingindex--;
 803                                                         if(priv->rfc_txpowertrackingindex_real > 4)
 804                                                         {
 805                                                                 priv->rfc_txpowertrackingindex_real--;
 806                                                                 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value);
 807                                                         }
 808                                                 }
 809                                                 else
 810                                                         rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[4].txbbgain_value);
 811                                 }
 812                         }
 813                         else
 814                         {
 815                                 if (RF_Type == RF_2T4R)
 816                                 {
 817                                         if((priv->rfa_txpowertrackingindex < TxBBGainTableLength - 1) &&(priv->rfc_txpowertrackingindex < TxBBGainTableLength - 1))
 818                                 {
 819                                         priv->rfa_txpowertrackingindex++;
 820                                         priv->rfa_txpowertrackingindex_real++;
 821                                         rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value);
 822                                         priv->rfc_txpowertrackingindex++;
 823                                         priv->rfc_txpowertrackingindex_real++;
 824                                         rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value);
 825                                 }
 826                                         else
 827                                         {
 828                                                 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value);
 829                                                 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value);
 830                         }
 831                                 }
 832                                 else
 833                                 {
 834                                         if(priv->rfc_txpowertrackingindex < (TxBBGainTableLength - 1))
 835                                         {
 836                                                         priv->rfc_txpowertrackingindex++;
 837                                                         priv->rfc_txpowertrackingindex_real++;
 838                                                         rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value);
 839                                         }
 840                                         else
 841                                                         rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value);
 842                                 }
 843                         }
 844                         if (RF_Type == RF_2T4R)
 845                         priv->CCKPresentAttentuation_difference
 846                                 = priv->rfa_txpowertrackingindex - priv->rfa_txpowertracking_default;
 847                         else
 848                                 priv->CCKPresentAttentuation_difference
 849                                         = priv->rfc_txpowertrackingindex - priv->rfc_txpowertracking_default;
 850
 851                         if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
 852                                 priv->CCKPresentAttentuation
 853                                 = priv->CCKPresentAttentuation_20Mdefault + priv->CCKPresentAttentuation_difference;
 854                         else
 855                                 priv->CCKPresentAttentuation
 856                                 = priv->CCKPresentAttentuation_40Mdefault + priv->CCKPresentAttentuation_difference;
 857
 858                         if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
 859                                         priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
 860                         if(priv->CCKPresentAttentuation < 0)
 861                                         priv->CCKPresentAttentuation = 0;
 862
 863                         if(1)
 864                         {
 865                                 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
 866                                 {
 867                                         priv->bcck_in_ch14 = TRUE;
 868                                         dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
 869                                 }
 870                                 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
 871                                 {
 872                                         priv->bcck_in_ch14 = FALSE;
 873                                         dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
 874                                 }
 875                                 else
 876                                         dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
 877                         }
 878                 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
 879                 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
 880 #ifdef RTL8190P
 881                 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex = %d\n", priv->rfc_txpowertrackingindex);
 882                 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_real = %d\n", priv->rfc_txpowertrackingindex_real);
 883 #endif
 884                 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_difference = %d\n", priv->CCKPresentAttentuation_difference);
 885                 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
 886
 887                 if (priv->CCKPresentAttentuation_difference <= -12||priv->CCKPresentAttentuation_difference >= 24)
 888                 {
 889                         priv->ieee80211->bdynamic_txpower_enable = TRUE;
 890                         write_nic_byte(dev, Pw_Track_Flag, 0);
 891                         write_nic_byte(dev, FW_Busy_Flag, 0);
 892                         RT_TRACE(COMP_POWER_TRACKING, "tx power track--->limited\n");
 893                         return;
 894                 }
 895
 896
 897         }
 898                 write_nic_byte(dev, Pw_Track_Flag, 0);
 899                 Avg_TSSI_Meas_from_driver = 0;
 900                 for(k = 0;k < 5; k++)
 901                         tmp_report[k] = 0;
 902                 break;
 903         }
 904         write_nic_byte(dev, FW_Busy_Flag, 0);
 905 }
 906                 priv->ieee80211->bdynamic_txpower_enable = TRUE;
 907                 write_nic_byte(dev, Pw_Track_Flag, 0);
 908 }
 909 #ifndef RTL8190P
 910 static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device * dev)
 911 {
 912 #define ThermalMeterVal 9
 913         struct r8192_priv *priv = ieee80211_priv(dev);
 914         u32 tmpRegA, TempCCk;
 915         u8 tmpOFDMindex, tmpCCKindex, tmpCCK20Mindex, tmpCCK40Mindex, tmpval;
 916         int i =0, CCKSwingNeedUpdate=0;
 917
 918         if(!priv->btxpower_trackingInit)
 919         {
 920                 //Query OFDM default setting
 921                 tmpRegA= rtl8192_QueryBBReg(dev, rOFDM0_XATxIQImbalance, bMaskDWord);
 922                 for(i=0; i<OFDM_Table_Length; i++)      //find the index
 923                 {
 924                         if(tmpRegA == OFDMSwingTable[i])
 925                         {
 926                                 priv->OFDM_index= (u8)i;
 927                                 RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, OFDM_index=0x%x\n",
 928                                         rOFDM0_XATxIQImbalance, tmpRegA, priv->OFDM_index);
 929                         }
 930                 }
 931
 932                 //Query CCK default setting From 0xa22
 933                 TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2);
 934                 for(i=0 ; i<CCK_Table_length ; i++)
 935                 {
 936                         if(TempCCk == (u32)CCKSwingTable_Ch1_Ch13[i][0])
 937                         {
 938                                 priv->CCK_index =(u8) i;
 939                                 RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, CCK_index=0x%x\n",
 940                                         rCCK0_TxFilter1, TempCCk, priv->CCK_index);
 941                 break;
 942         }
 943 }
 944                 priv->btxpower_trackingInit = TRUE;
 945                 //pHalData->TXPowercount = 0;
 946                 return;
 947         }
 948
 949         //==========================
 950         // this is only for test, should be masked
 951 #if 0
 952 {
 953         //UINT32        eRFPath;
 954         //UINT32        start_rf, end_rf;
 955         UINT32  curr_addr;
 956         //UINT32        reg_addr;
 957         //UINT32        reg_addr_end;
 958         UINT32  reg_value;
 959         //start_rf              = RF90_PATH_A;
 960         //end_rf                        = RF90_PATH_B;//RF90_PATH_MAX;
 961         //reg_addr              = 0x0;
 962         //reg_addr_end  = 0x2F;
 963
 964                 for (curr_addr = 0; curr_addr < 0x2d; curr_addr++)
 965                 {
 966                         reg_value = PHY_QueryRFReg(     Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A,
 967                                                                                 curr_addr, bMaskDWord);
 968                 }
 969
 970         pHalData->TXPowercount = 0;
 971         return;
 972 }
 973 #endif
 974         //==========================
 975
 976         // read and filter out unreasonable value
 977         tmpRegA = rtl8192_phy_QueryRFReg(dev, RF90_PATH_A, 0x12, 0x078);        // 0x12: RF Reg[10:7]
 978         RT_TRACE(COMP_POWER_TRACKING, "Readback ThermalMeterA = %d \n", tmpRegA);
 979         if(tmpRegA < 3 || tmpRegA > 13)
 980                 return;
 981         if(tmpRegA >= 12)       // if over 12, TP will be bad when high temprature
 982                 tmpRegA = 12;
 983         RT_TRACE(COMP_POWER_TRACKING, "Valid ThermalMeterA = %d \n", tmpRegA);
 984         priv->ThermalMeter[0] = ThermalMeterVal;        //We use fixed value by Bryant's suggestion
 985         priv->ThermalMeter[1] = ThermalMeterVal;        //We use fixed value by Bryant's suggestion
 986
 987         //Get current RF-A temprature index
 988         if(priv->ThermalMeter[0] >= (u8)tmpRegA)        //lower temprature
 989         {
 990                 tmpOFDMindex = tmpCCK20Mindex = 6+(priv->ThermalMeter[0]-(u8)tmpRegA);
 991                 tmpCCK40Mindex = tmpCCK20Mindex - 6;
 992                 if(tmpOFDMindex >= OFDM_Table_Length)
 993                         tmpOFDMindex = OFDM_Table_Length-1;
 994                 if(tmpCCK20Mindex >= CCK_Table_length)
 995                         tmpCCK20Mindex = CCK_Table_length-1;
 996                 if(tmpCCK40Mindex >= CCK_Table_length)
 997                         tmpCCK40Mindex = CCK_Table_length-1;
 998         }
 999         else
1000         {
1001                 tmpval = ((u8)tmpRegA - priv->ThermalMeter[0]);
1002                 if(tmpval >= 6)                                                         // higher temprature
1003                         tmpOFDMindex = tmpCCK20Mindex = 0;              // max to +6dB
1004                 else
1005                         tmpOFDMindex = tmpCCK20Mindex = 6 - tmpval;
1006                 tmpCCK40Mindex = 0;
1007         }
1008         //DbgPrint("%ddb, tmpOFDMindex = %d, tmpCCK20Mindex = %d, tmpCCK40Mindex = %d",
1009                 //((u1Byte)tmpRegA - pHalData->ThermalMeter[0]),
1010                 //tmpOFDMindex, tmpCCK20Mindex, tmpCCK40Mindex);
1011         if(priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)       //40M
1012                 tmpCCKindex = tmpCCK40Mindex;
1013         else
1014                 tmpCCKindex = tmpCCK20Mindex;
1015
1016         //record for bandwidth swith
1017         priv->Record_CCK_20Mindex = tmpCCK20Mindex;
1018         priv->Record_CCK_40Mindex = tmpCCK40Mindex;
1019         RT_TRACE(COMP_POWER_TRACKING, "Record_CCK_20Mindex / Record_CCK_40Mindex = %d / %d.\n",
1020                 priv->Record_CCK_20Mindex, priv->Record_CCK_40Mindex);
1021
1022         if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
1023         {
1024                 priv->bcck_in_ch14 = TRUE;
1025                 CCKSwingNeedUpdate = 1;
1026         }
1027         else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
1028         {
1029                 priv->bcck_in_ch14 = FALSE;
1030                 CCKSwingNeedUpdate = 1;
1031         }
1032
1033         if(priv->CCK_index != tmpCCKindex)
1034 {
1035                 priv->CCK_index = tmpCCKindex;
1036                 CCKSwingNeedUpdate = 1;
1037         }
1038
1039         if(CCKSwingNeedUpdate)
1040         {
1041                 //DbgPrint("Update CCK Swing, CCK_index = %d\n", pHalData->CCK_index);
1042                 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1043         }
1044         if(priv->OFDM_index != tmpOFDMindex)
1045         {
1046                 priv->OFDM_index = tmpOFDMindex;
1047                 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[priv->OFDM_index]);
1048                 RT_TRACE(COMP_POWER_TRACKING, "Update OFDMSwing[%d] = 0x%x\n",
1049                         priv->OFDM_index, OFDMSwingTable[priv->OFDM_index]);
1050         }
1051         priv->txpower_count = 0;
1052 }
1053 #endif
1054 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
1055 void dm_txpower_trackingcallback(struct work_struct *work)
1056 {
1057         struct delayed_work *dwork = container_of(work,struct delayed_work,work);
1058        struct r8192_priv *priv = container_of(dwork,struct r8192_priv,txpower_tracking_wq);
1059        struct net_device *dev = priv->ieee80211->dev;
1060 #else
1061 extern  void    dm_txpower_trackingcallback(struct net_device *dev)
1062 {
1063 #ifndef RTL8190P
1064         struct r8192_priv *priv = ieee80211_priv(dev);
1065 #endif
1066 #endif
1067
1068 #ifdef RTL8190P
1069         dm_TXPowerTrackingCallback_TSSI(dev);
1070 #else
1071         //if(priv->bDcut == TRUE)
1072         if(priv->IC_Cut >= IC_VersionCut_D)
1073                 dm_TXPowerTrackingCallback_TSSI(dev);
1074         else
1075                 dm_TXPowerTrackingCallback_ThermalMeter(dev);
1076 #endif
1077 }
1078
1079
1080 static void dm_InitializeTXPowerTracking_TSSI(struct net_device *dev)
1081 {
1082
1083         struct r8192_priv *priv = ieee80211_priv(dev);
1084
1085         //Initial the Tx BB index and mapping value
1086         priv->txbbgain_table[0].txbb_iq_amplifygain =                   12;
1087         priv->txbbgain_table[0].txbbgain_value=0x7f8001fe;
1088         priv->txbbgain_table[1].txbb_iq_amplifygain =                   11;
1089         priv->txbbgain_table[1].txbbgain_value=0x788001e2;
1090         priv->txbbgain_table[2].txbb_iq_amplifygain =                   10;
1091         priv->txbbgain_table[2].txbbgain_value=0x71c001c7;
1092         priv->txbbgain_table[3].txbb_iq_amplifygain =                   9;
1093         priv->txbbgain_table[3].txbbgain_value=0x6b8001ae;
1094         priv->txbbgain_table[4].txbb_iq_amplifygain =                  8;
1095         priv->txbbgain_table[4].txbbgain_value=0x65400195;
1096         priv->txbbgain_table[5].txbb_iq_amplifygain =                  7;
1097         priv->txbbgain_table[5].txbbgain_value=0x5fc0017f;
1098         priv->txbbgain_table[6].txbb_iq_amplifygain =                  6;
1099         priv->txbbgain_table[6].txbbgain_value=0x5a400169;
1100         priv->txbbgain_table[7].txbb_iq_amplifygain =                  5;
1101         priv->txbbgain_table[7].txbbgain_value=0x55400155;
1102         priv->txbbgain_table[8].txbb_iq_amplifygain =                  4;
1103         priv->txbbgain_table[8].txbbgain_value=0x50800142;
1104         priv->txbbgain_table[9].txbb_iq_amplifygain =                  3;
1105         priv->txbbgain_table[9].txbbgain_value=0x4c000130;
1106         priv->txbbgain_table[10].txbb_iq_amplifygain =                 2;
1107         priv->txbbgain_table[10].txbbgain_value=0x47c0011f;
1108         priv->txbbgain_table[11].txbb_iq_amplifygain =                 1;
1109         priv->txbbgain_table[11].txbbgain_value=0x43c0010f;
1110         priv->txbbgain_table[12].txbb_iq_amplifygain =                 0;
1111         priv->txbbgain_table[12].txbbgain_value=0x40000100;
1112         priv->txbbgain_table[13].txbb_iq_amplifygain =                 -1;
1113         priv->txbbgain_table[13].txbbgain_value=0x3c8000f2;
1114         priv->txbbgain_table[14].txbb_iq_amplifygain =               -2;
1115         priv->txbbgain_table[14].txbbgain_value=0x390000e4;
1116         priv->txbbgain_table[15].txbb_iq_amplifygain =               -3;
1117         priv->txbbgain_table[15].txbbgain_value=0x35c000d7;
1118         priv->txbbgain_table[16].txbb_iq_amplifygain =               -4;
1119         priv->txbbgain_table[16].txbbgain_value=0x32c000cb;
1120         priv->txbbgain_table[17].txbb_iq_amplifygain =               -5;
1121         priv->txbbgain_table[17].txbbgain_value=0x300000c0;
1122         priv->txbbgain_table[18].txbb_iq_amplifygain =                      -6;
1123         priv->txbbgain_table[18].txbbgain_value=0x2d4000b5;
1124         priv->txbbgain_table[19].txbb_iq_amplifygain =               -7;
1125         priv->txbbgain_table[19].txbbgain_value=0x2ac000ab;
1126         priv->txbbgain_table[20].txbb_iq_amplifygain =               -8;
1127         priv->txbbgain_table[20].txbbgain_value=0x288000a2;
1128         priv->txbbgain_table[21].txbb_iq_amplifygain =               -9;
1129         priv->txbbgain_table[21].txbbgain_value=0x26000098;
1130         priv->txbbgain_table[22].txbb_iq_amplifygain =               -10;
1131         priv->txbbgain_table[22].txbbgain_value=0x24000090;
1132         priv->txbbgain_table[23].txbb_iq_amplifygain =               -11;
1133         priv->txbbgain_table[23].txbbgain_value=0x22000088;
1134         priv->txbbgain_table[24].txbb_iq_amplifygain =               -12;
1135         priv->txbbgain_table[24].txbbgain_value=0x20000080;
1136         priv->txbbgain_table[25].txbb_iq_amplifygain =               -13;
1137         priv->txbbgain_table[25].txbbgain_value=0x1a00006c;
1138         priv->txbbgain_table[26].txbb_iq_amplifygain =               -14;
1139         priv->txbbgain_table[26].txbbgain_value=0x1c800072;
1140         priv->txbbgain_table[27].txbb_iq_amplifygain =               -15;
1141         priv->txbbgain_table[27].txbbgain_value=0x18000060;
1142         priv->txbbgain_table[28].txbb_iq_amplifygain =               -16;
1143         priv->txbbgain_table[28].txbbgain_value=0x19800066;
1144         priv->txbbgain_table[29].txbb_iq_amplifygain =               -17;
1145         priv->txbbgain_table[29].txbbgain_value=0x15800056;
1146         priv->txbbgain_table[30].txbb_iq_amplifygain =               -18;
1147         priv->txbbgain_table[30].txbbgain_value=0x26c0005b;
1148         priv->txbbgain_table[31].txbb_iq_amplifygain =               -19;
1149         priv->txbbgain_table[31].txbbgain_value=0x14400051;
1150         priv->txbbgain_table[32].txbb_iq_amplifygain =               -20;
1151         priv->txbbgain_table[32].txbbgain_value=0x24400051;
1152         priv->txbbgain_table[33].txbb_iq_amplifygain =               -21;
1153         priv->txbbgain_table[33].txbbgain_value=0x1300004c;
1154         priv->txbbgain_table[34].txbb_iq_amplifygain =               -22;
1155         priv->txbbgain_table[34].txbbgain_value=0x12000048;
1156         priv->txbbgain_table[35].txbb_iq_amplifygain =               -23;
1157         priv->txbbgain_table[35].txbbgain_value=0x11000044;
1158         priv->txbbgain_table[36].txbb_iq_amplifygain =               -24;
1159         priv->txbbgain_table[36].txbbgain_value=0x10000040;
1160
1161         //ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29
1162         //This Table is for CH1~CH13
1163         priv->cck_txbbgain_table[0].ccktxbb_valuearray[0] = 0x36;
1164         priv->cck_txbbgain_table[0].ccktxbb_valuearray[1] = 0x35;
1165         priv->cck_txbbgain_table[0].ccktxbb_valuearray[2] = 0x2e;
1166         priv->cck_txbbgain_table[0].ccktxbb_valuearray[3] = 0x25;
1167         priv->cck_txbbgain_table[0].ccktxbb_valuearray[4] = 0x1c;
1168         priv->cck_txbbgain_table[0].ccktxbb_valuearray[5] = 0x12;
1169         priv->cck_txbbgain_table[0].ccktxbb_valuearray[6] = 0x09;
1170         priv->cck_txbbgain_table[0].ccktxbb_valuearray[7] = 0x04;
1171
1172         priv->cck_txbbgain_table[1].ccktxbb_valuearray[0] = 0x33;
1173         priv->cck_txbbgain_table[1].ccktxbb_valuearray[1] = 0x32;
1174         priv->cck_txbbgain_table[1].ccktxbb_valuearray[2] = 0x2b;
1175         priv->cck_txbbgain_table[1].ccktxbb_valuearray[3] = 0x23;
1176         priv->cck_txbbgain_table[1].ccktxbb_valuearray[4] = 0x1a;
1177         priv->cck_txbbgain_table[1].ccktxbb_valuearray[5] = 0x11;
1178         priv->cck_txbbgain_table[1].ccktxbb_valuearray[6] = 0x08;
1179         priv->cck_txbbgain_table[1].ccktxbb_valuearray[7] = 0x04;
1180
1181         priv->cck_txbbgain_table[2].ccktxbb_valuearray[0] = 0x30;
1182         priv->cck_txbbgain_table[2].ccktxbb_valuearray[1] = 0x2f;
1183         priv->cck_txbbgain_table[2].ccktxbb_valuearray[2] = 0x29;
1184         priv->cck_txbbgain_table[2].ccktxbb_valuearray[3] = 0x21;
1185         priv->cck_txbbgain_table[2].ccktxbb_valuearray[4] = 0x19;
1186         priv->cck_txbbgain_table[2].ccktxbb_valuearray[5] = 0x10;
1187         priv->cck_txbbgain_table[2].ccktxbb_valuearray[6] = 0x08;
1188         priv->cck_txbbgain_table[2].ccktxbb_valuearray[7] = 0x03;
1189
1190         priv->cck_txbbgain_table[3].ccktxbb_valuearray[0] = 0x2d;
1191         priv->cck_txbbgain_table[3].ccktxbb_valuearray[1] = 0x2d;
1192         priv->cck_txbbgain_table[3].ccktxbb_valuearray[2] = 0x27;
1193         priv->cck_txbbgain_table[3].ccktxbb_valuearray[3] = 0x1f;
1194         priv->cck_txbbgain_table[3].ccktxbb_valuearray[4] = 0x18;
1195         priv->cck_txbbgain_table[3].ccktxbb_valuearray[5] = 0x0f;
1196         priv->cck_txbbgain_table[3].ccktxbb_valuearray[6] = 0x08;
1197         priv->cck_txbbgain_table[3].ccktxbb_valuearray[7] = 0x03;
1198
1199         priv->cck_txbbgain_table[4].ccktxbb_valuearray[0] = 0x2b;
1200         priv->cck_txbbgain_table[4].ccktxbb_valuearray[1] = 0x2a;
1201         priv->cck_txbbgain_table[4].ccktxbb_valuearray[2] = 0x25;
1202         priv->cck_txbbgain_table[4].ccktxbb_valuearray[3] = 0x1e;
1203         priv->cck_txbbgain_table[4].ccktxbb_valuearray[4] = 0x16;
1204         priv->cck_txbbgain_table[4].ccktxbb_valuearray[5] = 0x0e;
1205         priv->cck_txbbgain_table[4].ccktxbb_valuearray[6] = 0x07;
1206         priv->cck_txbbgain_table[4].ccktxbb_valuearray[7] = 0x03;
1207
1208         priv->cck_txbbgain_table[5].ccktxbb_valuearray[0] = 0x28;
1209         priv->cck_txbbgain_table[5].ccktxbb_valuearray[1] = 0x28;
1210         priv->cck_txbbgain_table[5].ccktxbb_valuearray[2] = 0x22;
1211         priv->cck_txbbgain_table[5].ccktxbb_valuearray[3] = 0x1c;
1212         priv->cck_txbbgain_table[5].ccktxbb_valuearray[4] = 0x15;
1213         priv->cck_txbbgain_table[5].ccktxbb_valuearray[5] = 0x0d;
1214         priv->cck_txbbgain_table[5].ccktxbb_valuearray[6] = 0x07;
1215         priv->cck_txbbgain_table[5].ccktxbb_valuearray[7] = 0x03;
1216
1217         priv->cck_txbbgain_table[6].ccktxbb_valuearray[0] = 0x26;
1218         priv->cck_txbbgain_table[6].ccktxbb_valuearray[1] = 0x25;
1219         priv->cck_txbbgain_table[6].ccktxbb_valuearray[2] = 0x21;
1220         priv->cck_txbbgain_table[6].ccktxbb_valuearray[3] = 0x1b;
1221         priv->cck_txbbgain_table[6].ccktxbb_valuearray[4] = 0x14;
1222         priv->cck_txbbgain_table[6].ccktxbb_valuearray[5] = 0x0d;
1223         priv->cck_txbbgain_table[6].ccktxbb_valuearray[6] = 0x06;
1224         priv->cck_txbbgain_table[6].ccktxbb_valuearray[7] = 0x03;
1225
1226         priv->cck_txbbgain_table[7].ccktxbb_valuearray[0] = 0x24;
1227         priv->cck_txbbgain_table[7].ccktxbb_valuearray[1] = 0x23;
1228         priv->cck_txbbgain_table[7].ccktxbb_valuearray[2] = 0x1f;
1229         priv->cck_txbbgain_table[7].ccktxbb_valuearray[3] = 0x19;
1230         priv->cck_txbbgain_table[7].ccktxbb_valuearray[4] = 0x13;
1231         priv->cck_txbbgain_table[7].ccktxbb_valuearray[5] = 0x0c;
1232         priv->cck_txbbgain_table[7].ccktxbb_valuearray[6] = 0x06;
1233         priv->cck_txbbgain_table[7].ccktxbb_valuearray[7] = 0x03;
1234
1235         priv->cck_txbbgain_table[8].ccktxbb_valuearray[0] = 0x22;
1236         priv->cck_txbbgain_table[8].ccktxbb_valuearray[1] = 0x21;
1237         priv->cck_txbbgain_table[8].ccktxbb_valuearray[2] = 0x1d;
1238         priv->cck_txbbgain_table[8].ccktxbb_valuearray[3] = 0x18;
1239         priv->cck_txbbgain_table[8].ccktxbb_valuearray[4] = 0x11;
1240         priv->cck_txbbgain_table[8].ccktxbb_valuearray[5] = 0x0b;
1241         priv->cck_txbbgain_table[8].ccktxbb_valuearray[6] = 0x06;
1242         priv->cck_txbbgain_table[8].ccktxbb_valuearray[7] = 0x02;
1243
1244         priv->cck_txbbgain_table[9].ccktxbb_valuearray[0] = 0x20;
1245         priv->cck_txbbgain_table[9].ccktxbb_valuearray[1] = 0x20;
1246         priv->cck_txbbgain_table[9].ccktxbb_valuearray[2] = 0x1b;
1247         priv->cck_txbbgain_table[9].ccktxbb_valuearray[3] = 0x16;
1248         priv->cck_txbbgain_table[9].ccktxbb_valuearray[4] = 0x11;
1249         priv->cck_txbbgain_table[9].ccktxbb_valuearray[5] = 0x08;
1250         priv->cck_txbbgain_table[9].ccktxbb_valuearray[6] = 0x05;
1251         priv->cck_txbbgain_table[9].ccktxbb_valuearray[7] = 0x02;
1252
1253         priv->cck_txbbgain_table[10].ccktxbb_valuearray[0] = 0x1f;
1254         priv->cck_txbbgain_table[10].ccktxbb_valuearray[1] = 0x1e;
1255         priv->cck_txbbgain_table[10].ccktxbb_valuearray[2] = 0x1a;
1256         priv->cck_txbbgain_table[10].ccktxbb_valuearray[3] = 0x15;
1257         priv->cck_txbbgain_table[10].ccktxbb_valuearray[4] = 0x10;
1258         priv->cck_txbbgain_table[10].ccktxbb_valuearray[5] = 0x0a;
1259         priv->cck_txbbgain_table[10].ccktxbb_valuearray[6] = 0x05;
1260         priv->cck_txbbgain_table[10].ccktxbb_valuearray[7] = 0x02;
1261
1262         priv->cck_txbbgain_table[11].ccktxbb_valuearray[0] = 0x1d;
1263         priv->cck_txbbgain_table[11].ccktxbb_valuearray[1] = 0x1c;
1264         priv->cck_txbbgain_table[11].ccktxbb_valuearray[2] = 0x18;
1265         priv->cck_txbbgain_table[11].ccktxbb_valuearray[3] = 0x14;
1266         priv->cck_txbbgain_table[11].ccktxbb_valuearray[4] = 0x0f;
1267         priv->cck_txbbgain_table[11].ccktxbb_valuearray[5] = 0x0a;
1268         priv->cck_txbbgain_table[11].ccktxbb_valuearray[6] = 0x05;
1269         priv->cck_txbbgain_table[11].ccktxbb_valuearray[7] = 0x02;
1270
1271         priv->cck_txbbgain_table[12].ccktxbb_valuearray[0] = 0x1b;
1272         priv->cck_txbbgain_table[12].ccktxbb_valuearray[1] = 0x1a;
1273         priv->cck_txbbgain_table[12].ccktxbb_valuearray[2] = 0x17;
1274         priv->cck_txbbgain_table[12].ccktxbb_valuearray[3] = 0x13;
1275         priv->cck_txbbgain_table[12].ccktxbb_valuearray[4] = 0x0e;
1276         priv->cck_txbbgain_table[12].ccktxbb_valuearray[5] = 0x09;
1277         priv->cck_txbbgain_table[12].ccktxbb_valuearray[6] = 0x04;
1278         priv->cck_txbbgain_table[12].ccktxbb_valuearray[7] = 0x02;
1279
1280         priv->cck_txbbgain_table[13].ccktxbb_valuearray[0] = 0x1a;
1281         priv->cck_txbbgain_table[13].ccktxbb_valuearray[1] = 0x19;
1282         priv->cck_txbbgain_table[13].ccktxbb_valuearray[2] = 0x16;
1283         priv->cck_txbbgain_table[13].ccktxbb_valuearray[3] = 0x12;
1284         priv->cck_txbbgain_table[13].ccktxbb_valuearray[4] = 0x0d;
1285         priv->cck_txbbgain_table[13].ccktxbb_valuearray[5] = 0x09;
1286         priv->cck_txbbgain_table[13].ccktxbb_valuearray[6] = 0x04;
1287         priv->cck_txbbgain_table[13].ccktxbb_valuearray[7] = 0x02;
1288
1289         priv->cck_txbbgain_table[14].ccktxbb_valuearray[0] = 0x18;
1290         priv->cck_txbbgain_table[14].ccktxbb_valuearray[1] = 0x17;
1291         priv->cck_txbbgain_table[14].ccktxbb_valuearray[2] = 0x15;
1292         priv->cck_txbbgain_table[14].ccktxbb_valuearray[3] = 0x11;
1293         priv->cck_txbbgain_table[14].ccktxbb_valuearray[4] = 0x0c;
1294         priv->cck_txbbgain_table[14].ccktxbb_valuearray[5] = 0x08;
1295         priv->cck_txbbgain_table[14].ccktxbb_valuearray[6] = 0x04;
1296         priv->cck_txbbgain_table[14].ccktxbb_valuearray[7] = 0x02;
1297
1298         priv->cck_txbbgain_table[15].ccktxbb_valuearray[0] = 0x17;
1299         priv->cck_txbbgain_table[15].ccktxbb_valuearray[1] = 0x16;
1300         priv->cck_txbbgain_table[15].ccktxbb_valuearray[2] = 0x13;
1301         priv->cck_txbbgain_table[15].ccktxbb_valuearray[3] = 0x10;
1302         priv->cck_txbbgain_table[15].ccktxbb_valuearray[4] = 0x0c;
1303         priv->cck_txbbgain_table[15].ccktxbb_valuearray[5] = 0x08;
1304         priv->cck_txbbgain_table[15].ccktxbb_valuearray[6] = 0x04;
1305         priv->cck_txbbgain_table[15].ccktxbb_valuearray[7] = 0x02;
1306
1307         priv->cck_txbbgain_table[16].ccktxbb_valuearray[0] = 0x16;
1308         priv->cck_txbbgain_table[16].ccktxbb_valuearray[1] = 0x15;
1309         priv->cck_txbbgain_table[16].ccktxbb_valuearray[2] = 0x12;
1310         priv->cck_txbbgain_table[16].ccktxbb_valuearray[3] = 0x0f;
1311         priv->cck_txbbgain_table[16].ccktxbb_valuearray[4] = 0x0b;
1312         priv->cck_txbbgain_table[16].ccktxbb_valuearray[5] = 0x07;
1313         priv->cck_txbbgain_table[16].ccktxbb_valuearray[6] = 0x04;
1314         priv->cck_txbbgain_table[16].ccktxbb_valuearray[7] = 0x01;
1315
1316         priv->cck_txbbgain_table[17].ccktxbb_valuearray[0] = 0x14;
1317         priv->cck_txbbgain_table[17].ccktxbb_valuearray[1] = 0x14;
1318         priv->cck_txbbgain_table[17].ccktxbb_valuearray[2] = 0x11;
1319         priv->cck_txbbgain_table[17].ccktxbb_valuearray[3] = 0x0e;
1320         priv->cck_txbbgain_table[17].ccktxbb_valuearray[4] = 0x0b;
1321         priv->cck_txbbgain_table[17].ccktxbb_valuearray[5] = 0x07;
1322         priv->cck_txbbgain_table[17].ccktxbb_valuearray[6] = 0x03;
1323         priv->cck_txbbgain_table[17].ccktxbb_valuearray[7] = 0x02;
1324
1325         priv->cck_txbbgain_table[18].ccktxbb_valuearray[0] = 0x13;
1326         priv->cck_txbbgain_table[18].ccktxbb_valuearray[1] = 0x13;
1327         priv->cck_txbbgain_table[18].ccktxbb_valuearray[2] = 0x10;
1328         priv->cck_txbbgain_table[18].ccktxbb_valuearray[3] = 0x0d;
1329         priv->cck_txbbgain_table[18].ccktxbb_valuearray[4] = 0x0a;
1330         priv->cck_txbbgain_table[18].ccktxbb_valuearray[5] = 0x06;
1331         priv->cck_txbbgain_table[18].ccktxbb_valuearray[6] = 0x03;
1332         priv->cck_txbbgain_table[18].ccktxbb_valuearray[7] = 0x01;
1333
1334         priv->cck_txbbgain_table[19].ccktxbb_valuearray[0] = 0x12;
1335         priv->cck_txbbgain_table[19].ccktxbb_valuearray[1] = 0x12;
1336         priv->cck_txbbgain_table[19].ccktxbb_valuearray[2] = 0x0f;
1337         priv->cck_txbbgain_table[19].ccktxbb_valuearray[3] = 0x0c;
1338         priv->cck_txbbgain_table[19].ccktxbb_valuearray[4] = 0x09;
1339         priv->cck_txbbgain_table[19].ccktxbb_valuearray[5] = 0x06;
1340         priv->cck_txbbgain_table[19].ccktxbb_valuearray[6] = 0x03;
1341         priv->cck_txbbgain_table[19].ccktxbb_valuearray[7] = 0x01;
1342
1343         priv->cck_txbbgain_table[20].ccktxbb_valuearray[0] = 0x11;
1344         priv->cck_txbbgain_table[20].ccktxbb_valuearray[1] = 0x11;
1345         priv->cck_txbbgain_table[20].ccktxbb_valuearray[2] = 0x0f;
1346         priv->cck_txbbgain_table[20].ccktxbb_valuearray[3] = 0x0c;
1347         priv->cck_txbbgain_table[20].ccktxbb_valuearray[4] = 0x09;
1348         priv->cck_txbbgain_table[20].ccktxbb_valuearray[5] = 0x06;
1349         priv->cck_txbbgain_table[20].ccktxbb_valuearray[6] = 0x03;
1350         priv->cck_txbbgain_table[20].ccktxbb_valuearray[7] = 0x01;
1351
1352         priv->cck_txbbgain_table[21].ccktxbb_valuearray[0] = 0x10;
1353         priv->cck_txbbgain_table[21].ccktxbb_valuearray[1] = 0x10;
1354         priv->cck_txbbgain_table[21].ccktxbb_valuearray[2] = 0x0e;
1355         priv->cck_txbbgain_table[21].ccktxbb_valuearray[3] = 0x0b;
1356         priv->cck_txbbgain_table[21].ccktxbb_valuearray[4] = 0x08;
1357         priv->cck_txbbgain_table[21].ccktxbb_valuearray[5] = 0x05;
1358         priv->cck_txbbgain_table[21].ccktxbb_valuearray[6] = 0x03;
1359         priv->cck_txbbgain_table[21].ccktxbb_valuearray[7] = 0x01;
1360
1361         priv->cck_txbbgain_table[22].ccktxbb_valuearray[0] = 0x0f;
1362         priv->cck_txbbgain_table[22].ccktxbb_valuearray[1] = 0x0f;
1363         priv->cck_txbbgain_table[22].ccktxbb_valuearray[2] = 0x0d;
1364         priv->cck_txbbgain_table[22].ccktxbb_valuearray[3] = 0x0b;
1365         priv->cck_txbbgain_table[22].ccktxbb_valuearray[4] = 0x08;
1366         priv->cck_txbbgain_table[22].ccktxbb_valuearray[5] = 0x05;
1367         priv->cck_txbbgain_table[22].ccktxbb_valuearray[6] = 0x03;
1368         priv->cck_txbbgain_table[22].ccktxbb_valuearray[7] = 0x01;
1369
1370         //ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29
1371         //This Table is for CH14
1372         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[0] = 0x36;
1373         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[1] = 0x35;
1374         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[2] = 0x2e;
1375         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[3] = 0x1b;
1376         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[4] = 0x00;
1377         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[5] = 0x00;
1378         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[6] = 0x00;
1379         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[7] = 0x00;
1380
1381         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[0] = 0x33;
1382         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[1] = 0x32;
1383         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[2] = 0x2b;
1384         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[3] = 0x19;
1385         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[4] = 0x00;
1386         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[5] = 0x00;
1387         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[6] = 0x00;
1388         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[7] = 0x00;
1389
1390         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[0] = 0x30;
1391         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[1] = 0x2f;
1392         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[2] = 0x29;
1393         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[3] = 0x18;
1394         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[4] = 0x00;
1395         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[5] = 0x00;
1396         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[6] = 0x00;
1397         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[7] = 0x00;
1398
1399         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[0] = 0x2d;
1400         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[1] = 0x2d;
1401         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[2] = 0x27;
1402         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[3] = 0x17;
1403         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[4] = 0x00;
1404         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[5] = 0x00;
1405         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[6] = 0x00;
1406         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[7] = 0x00;
1407
1408         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[0] = 0x2b;
1409         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[1] = 0x2a;
1410         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[2] = 0x25;
1411         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[3] = 0x15;
1412         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[4] = 0x00;
1413         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[5] = 0x00;
1414         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[6] = 0x00;
1415         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[7] = 0x00;
1416
1417         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[0] = 0x28;
1418         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[1] = 0x28;
1419         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[2] = 0x22;
1420         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[3] = 0x14;
1421         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[4] = 0x00;
1422         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[5] = 0x00;
1423         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[6] = 0x00;
1424         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[7] = 0x00;
1425
1426         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[0] = 0x26;
1427         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[1] = 0x25;
1428         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[2] = 0x21;
1429         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[3] = 0x13;
1430         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[4] = 0x00;
1431         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[5] = 0x00;
1432         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[6] = 0x00;
1433         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[7] = 0x00;
1434
1435         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[0] = 0x24;
1436         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[1] = 0x23;
1437         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[2] = 0x1f;
1438         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[3] = 0x12;
1439         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[4] = 0x00;
1440         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[5] = 0x00;
1441         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[6] = 0x00;
1442         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[7] = 0x00;
1443
1444         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[0] = 0x22;
1445         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[1] = 0x21;
1446         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[2] = 0x1d;
1447         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[3] = 0x11;
1448         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[4] = 0x00;
1449         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[5] = 0x00;
1450         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[6] = 0x00;
1451         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[7] = 0x00;
1452
1453         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[0] = 0x20;
1454         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[1] = 0x20;
1455         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[2] = 0x1b;
1456         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[3] = 0x10;
1457         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[4] = 0x00;
1458         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[5] = 0x00;
1459         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[6] = 0x00;
1460         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[7] = 0x00;
1461
1462         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[0] = 0x1f;
1463         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[1] = 0x1e;
1464         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[2] = 0x1a;
1465         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[3] = 0x0f;
1466         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[4] = 0x00;
1467         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[5] = 0x00;
1468         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[6] = 0x00;
1469         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[7] = 0x00;
1470
1471         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[0] = 0x1d;
1472         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[1] = 0x1c;
1473         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[2] = 0x18;
1474         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[3] = 0x0e;
1475         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[4] = 0x00;
1476         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[5] = 0x00;
1477         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[6] = 0x00;
1478         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[7] = 0x00;
1479
1480         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[0] = 0x1b;
1481         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[1] = 0x1a;
1482         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[2] = 0x17;
1483         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[3] = 0x0e;
1484         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[4] = 0x00;
1485         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[5] = 0x00;
1486         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[6] = 0x00;
1487         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[7] = 0x00;
1488
1489         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[0] = 0x1a;
1490         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[1] = 0x19;
1491         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[2] = 0x16;
1492         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[3] = 0x0d;
1493         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[4] = 0x00;
1494         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[5] = 0x00;
1495         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[6] = 0x00;
1496         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[7] = 0x00;
1497
1498         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[0] = 0x18;
1499         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[1] = 0x17;
1500         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[2] = 0x15;
1501         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[3] = 0x0c;
1502         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[4] = 0x00;
1503         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[5] = 0x00;
1504         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[6] = 0x00;
1505         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[7] = 0x00;
1506
1507         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[0] = 0x17;
1508         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[1] = 0x16;
1509         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[2] = 0x13;
1510         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[3] = 0x0b;
1511         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[4] = 0x00;
1512         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[5] = 0x00;
1513         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[6] = 0x00;
1514         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[7] = 0x00;
1515
1516         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[0] = 0x16;
1517         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[1] = 0x15;
1518         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[2] = 0x12;
1519         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[3] = 0x0b;
1520         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[4] = 0x00;
1521         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[5] = 0x00;
1522         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[6] = 0x00;
1523         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[7] = 0x00;
1524
1525         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[0] = 0x14;
1526         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[1] = 0x14;
1527         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[2] = 0x11;
1528         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[3] = 0x0a;
1529         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[4] = 0x00;
1530         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[5] = 0x00;
1531         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[6] = 0x00;
1532         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[7] = 0x00;
1533
1534         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[0] = 0x13;
1535         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[1] = 0x13;
1536         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[2] = 0x10;
1537         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[3] = 0x0a;
1538         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[4] = 0x00;
1539         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[5] = 0x00;
1540         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[6] = 0x00;
1541         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[7] = 0x00;
1542
1543         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[0] = 0x12;
1544         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[1] = 0x12;
1545         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[2] = 0x0f;
1546         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[3] = 0x09;
1547         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[4] = 0x00;
1548         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[5] = 0x00;
1549         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[6] = 0x00;
1550         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[7] = 0x00;
1551
1552         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[0] = 0x11;
1553         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[1] = 0x11;
1554         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[2] = 0x0f;
1555         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[3] = 0x09;
1556         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[4] = 0x00;
1557         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[5] = 0x00;
1558         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[6] = 0x00;
1559         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[7] = 0x00;
1560
1561         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[0] = 0x10;
1562         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[1] = 0x10;
1563         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[2] = 0x0e;
1564         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[3] = 0x08;
1565         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[4] = 0x00;
1566         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[5] = 0x00;
1567         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[6] = 0x00;
1568         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[7] = 0x00;
1569
1570         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[0] = 0x0f;
1571         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[1] = 0x0f;
1572         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[2] = 0x0d;
1573         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[3] = 0x08;
1574         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[4] = 0x00;
1575         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[5] = 0x00;
1576         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[6] = 0x00;
1577         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[7] = 0x00;
1578
1579         priv->btxpower_tracking = TRUE;
1580         priv->txpower_count       = 0;
1581         priv->btxpower_trackingInit = FALSE;
1582
1583 }
1584 #ifndef RTL8190P
1585 static void dm_InitializeTXPowerTracking_ThermalMeter(struct net_device *dev)
1586 {
1587         struct r8192_priv *priv = ieee80211_priv(dev);
1588
1589         // Tx Power tracking by Theremal Meter require Firmware R/W 3-wire. This mechanism
1590         // can be enabled only when Firmware R/W 3-wire is enabled. Otherwise, frequent r/w
1591         // 3-wire by driver cause RF goes into wrong state.
1592         if(priv->ieee80211->FwRWRF)
1593                 priv->btxpower_tracking = TRUE;
1594         else
1595                 priv->btxpower_tracking = FALSE;
1596         priv->txpower_count       = 0;
1597         priv->btxpower_trackingInit = FALSE;
1598 }
1599 #endif
1600
1601 void dm_initialize_txpower_tracking(struct net_device *dev)
1602 {
1603 #ifndef RTL8190P
1604         struct r8192_priv *priv = ieee80211_priv(dev);
1605 #endif
1606 #ifdef RTL8190P
1607         dm_InitializeTXPowerTracking_TSSI(dev);
1608 #else
1609         //if(priv->bDcut == TRUE)
1610         if(priv->IC_Cut >= IC_VersionCut_D)
1611                 dm_InitializeTXPowerTracking_TSSI(dev);
1612         else
1613                 dm_InitializeTXPowerTracking_ThermalMeter(dev);
1614 #endif
1615 }       // dm_InitializeTXPowerTracking
1616
1617
1618 static void dm_CheckTXPowerTracking_TSSI(struct net_device *dev)
1619 {
1620         struct r8192_priv *priv = ieee80211_priv(dev);
1621         static u32 tx_power_track_counter = 0;
1622         RT_TRACE(COMP_POWER_TRACKING,"%s()\n",__FUNCTION__);
1623         if(read_nic_byte(dev, 0x11e) ==1)
1624                 return;
1625         if(!priv->btxpower_tracking)
1626                 return;
1627         tx_power_track_counter++;
1628
1629
1630          if(tx_power_track_counter > 90)
1631                 {
1632                         #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
1633                                 queue_delayed_work(priv->priv_wq,&priv->txpower_tracking_wq,0);
1634                         #else
1635                                 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
1636                                 schedule_task(&priv->txpower_tracking_wq);
1637                                 #else
1638                                 queue_work(priv->priv_wq,&priv->txpower_tracking_wq);
1639                                 #endif
1640                         #endif
1641                 tx_power_track_counter =0;
1642                 }
1643
1644 }
1645
1646 #ifndef RTL8190P
1647 static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device *dev)
1648 {
1649         struct r8192_priv *priv = ieee80211_priv(dev);
1650         static u8       TM_Trigger=0;
1651 #if 0
1652         u1Byte                                  i;
1653         u4Byte tmpRegA;
1654         for(i=0; i<50; i++)
1655         {
1656                 tmpRegA = PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x12, 0x078);    // 0x12: RF Reg[10:7]
1657                 PHY_SetRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1658                 //delay_us(100);
1659                 PHY_SetRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1660                 //delay_us(100);
1661         }
1662         DbgPrint("Trigger and readback ThermalMeter, write RF reg0x2 = 0x4d to 0x4f for 50 times\n");
1663 #else
1664         //DbgPrint("dm_CheckTXPowerTracking() \n");
1665         if(!priv->btxpower_tracking)
1666                 return;
1667         else
1668         {
1669                 if(priv->txpower_count  <= 2)
1670                 {
1671                         priv->txpower_count++;
1672                         return;
1673                 }
1674         }
1675
1676         if(!TM_Trigger)
1677         {
1678                 //Attention!! You have to wirte all 12bits data to RF, or it may cause RF to crash
1679                 //actually write reg0x02 bit1=0, then bit1=1.
1680                 //DbgPrint("Trigger ThermalMeter, write RF reg0x2 = 0x4d to 0x4f\n");
1681                 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1682                 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1683                 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1684                 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1685                 TM_Trigger = 1;
1686                 return;
1687         }
1688         else
1689                 {
1690                 //DbgPrint("Schedule TxPowerTrackingWorkItem\n");
1691                         #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
1692                         queue_delayed_work(priv->priv_wq,&priv->txpower_tracking_wq,0);
1693                         #else
1694                                 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
1695                                 schedule_task(&priv->txpower_tracking_wq);
1696                                 #else
1697                                 queue_work(priv->priv_wq,&priv->txpower_tracking_wq);
1698                                 #endif
1699                         #endif
1700                 TM_Trigger = 0;
1701                 }
1702 #endif
1703         }
1704 #endif
1705
1706 static void dm_check_txpower_tracking(struct net_device *dev)
1707 {
1708 #ifndef RTL8190P
1709         struct r8192_priv *priv = ieee80211_priv(dev);
1710         //static u32 tx_power_track_counter = 0;
1711 #endif
1712 #ifdef  RTL8190P
1713         dm_CheckTXPowerTracking_TSSI(dev);
1714 #else
1715         //if(priv->bDcut == TRUE)
1716         if(priv->IC_Cut >= IC_VersionCut_D)
1717                 dm_CheckTXPowerTracking_TSSI(dev);
1718         else
1719                 dm_CheckTXPowerTracking_ThermalMeter(dev);
1720 #endif
1721
1722 }       // dm_CheckTXPowerTracking
1723
1724
1725 static void dm_CCKTxPowerAdjust_TSSI(struct net_device *dev, bool  bInCH14)
1726 {
1727         u32 TempVal;
1728         struct r8192_priv *priv = ieee80211_priv(dev);
1729         //Write 0xa22 0xa23
1730         TempVal = 0;
1731         if(!bInCH14){
1732                 //Write 0xa22 0xa23
1733                 TempVal =       (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[0] +
1734                                         (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[1]<<8)) ;
1735
1736                 rtl8192_setBBreg(dev, rCCK0_TxFilter1,bMaskHWord, TempVal);
1737                 //Write 0xa24 ~ 0xa27
1738                 TempVal = 0;
1739                 TempVal =       (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[2] +
1740                                         (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[3]<<8) +
1741                                         (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[4]<<16 )+
1742                                         (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[5]<<24));
1743                 rtl8192_setBBreg(dev, rCCK0_TxFilter2,bMaskDWord, TempVal);
1744                 //Write 0xa28  0xa29
1745                 TempVal = 0;
1746                 TempVal =       (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[6] +
1747                                         (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[7]<<8)) ;
1748
1749                 rtl8192_setBBreg(dev, rCCK0_DebugPort,bMaskLWord, TempVal);
1750         }
1751         else
1752         {
1753                 TempVal =       (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[0] +
1754                                         (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[1]<<8)) ;
1755
1756                 rtl8192_setBBreg(dev, rCCK0_TxFilter1,bMaskHWord, TempVal);
1757                 //Write 0xa24 ~ 0xa27
1758                 TempVal = 0;
1759                 TempVal =       (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[2] +
1760                                         (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[3]<<8) +
1761                                         (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[4]<<16 )+
1762                                         (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[5]<<24));
1763                 rtl8192_setBBreg(dev, rCCK0_TxFilter2,bMaskDWord, TempVal);
1764                 //Write 0xa28  0xa29
1765                 TempVal = 0;
1766                 TempVal =       (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[6] +
1767                                         (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[7]<<8)) ;
1768
1769                 rtl8192_setBBreg(dev, rCCK0_DebugPort,bMaskLWord, TempVal);
1770         }
1771
1772
1773 }
1774 #ifndef RTL8190P
1775 static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev,    bool  bInCH14)
1776 {
1777         u32 TempVal;
1778         struct r8192_priv *priv = ieee80211_priv(dev);
1779
1780         TempVal = 0;
1781         if(!bInCH14)
1782         {
1783                 //Write 0xa22 0xa23
1784                 TempVal =       CCKSwingTable_Ch1_Ch13[priv->CCK_index][0] +
1785                                         (CCKSwingTable_Ch1_Ch13[priv->CCK_index][1]<<8) ;
1786                 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1787                 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1788                         rCCK0_TxFilter1, TempVal);
1789                 //Write 0xa24 ~ 0xa27
1790                 TempVal = 0;
1791                 TempVal =       CCKSwingTable_Ch1_Ch13[priv->CCK_index][2] +
1792                                         (CCKSwingTable_Ch1_Ch13[priv->CCK_index][3]<<8) +
1793                                         (CCKSwingTable_Ch1_Ch13[priv->CCK_index][4]<<16 )+
1794                                         (CCKSwingTable_Ch1_Ch13[priv->CCK_index][5]<<24);
1795                 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1796                 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1797                         rCCK0_TxFilter2, TempVal);
1798                 //Write 0xa28  0xa29
1799                 TempVal = 0;
1800                 TempVal =       CCKSwingTable_Ch1_Ch13[priv->CCK_index][6] +
1801                                         (CCKSwingTable_Ch1_Ch13[priv->CCK_index][7]<<8) ;
1802
1803                 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1804                 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1805                         rCCK0_DebugPort, TempVal);
1806         }
1807         else
1808         {
1809 //              priv->CCKTxPowerAdjustCntNotCh14++;     //cosa add for debug.
1810                 //Write 0xa22 0xa23
1811                 TempVal =       CCKSwingTable_Ch14[priv->CCK_index][0] +
1812                                         (CCKSwingTable_Ch14[priv->CCK_index][1]<<8) ;
1813
1814                 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1815                 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1816                         rCCK0_TxFilter1, TempVal);
1817                 //Write 0xa24 ~ 0xa27
1818                 TempVal = 0;
1819                 TempVal =       CCKSwingTable_Ch14[priv->CCK_index][2] +
1820                                         (CCKSwingTable_Ch14[priv->CCK_index][3]<<8) +
1821                                         (CCKSwingTable_Ch14[priv->CCK_index][4]<<16 )+
1822                                         (CCKSwingTable_Ch14[priv->CCK_index][5]<<24);
1823                 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1824                 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1825                         rCCK0_TxFilter2, TempVal);
1826                 //Write 0xa28  0xa29
1827                 TempVal = 0;
1828                 TempVal =       CCKSwingTable_Ch14[priv->CCK_index][6] +
1829                                         (CCKSwingTable_Ch14[priv->CCK_index][7]<<8) ;
1830
1831                 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1832                 RT_TRACE(COMP_POWER_TRACKING,"CCK chnl 14, reg 0x%x = 0x%x\n",
1833                         rCCK0_DebugPort, TempVal);
1834         }
1835         }
1836 #endif
1837
1838
1839 void dm_cck_txpower_adjust(struct net_device *dev, bool binch14)
1840 {       // dm_CCKTxPowerAdjust
1841 #ifndef RTL8190P
1842         struct r8192_priv *priv = ieee80211_priv(dev);
1843 #endif
1844 #ifdef RTL8190P
1845         dm_CCKTxPowerAdjust_TSSI(dev, binch14);
1846 #else
1847         //if(priv->bDcut == TRUE)
1848         if(priv->IC_Cut >= IC_VersionCut_D)
1849                 dm_CCKTxPowerAdjust_TSSI(dev, binch14);
1850         else
1851                 dm_CCKTxPowerAdjust_ThermalMeter(dev, binch14);
1852 #endif
1853 }
1854
1855
1856 #ifndef  RTL8192U
1857 static void dm_txpower_reset_recovery(
1858         struct net_device *dev
1859 )
1860 {
1861         struct r8192_priv *priv = ieee80211_priv(dev);
1862
1863         RT_TRACE(COMP_POWER_TRACKING, "Start Reset Recovery ==>\n");
1864         rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value);
1865         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc80 is %08x\n",priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value);
1866         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFA_txPowerTrackingIndex is %x\n",priv->rfa_txpowertrackingindex);
1867         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF A I/Q Amplify Gain is %ld\n",priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbb_iq_amplifygain);
1868         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: CCK Attenuation is %d dB\n",priv->CCKPresentAttentuation);
1869         dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1870
1871         rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);
1872         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc90 is %08x\n",priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);
1873         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFC_txPowerTrackingIndex is %x\n",priv->rfc_txpowertrackingindex);
1874         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF C I/Q Amplify Gain is %ld\n",priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbb_iq_amplifygain);
1875
1876 }       // dm_TXPowerResetRecovery
1877
1878 void dm_restore_dynamic_mechanism_state(struct net_device *dev)
1879 {
1880         struct r8192_priv *priv = ieee80211_priv(dev);
1881         u32     reg_ratr = priv->rate_adaptive.last_ratr;
1882
1883         if(!priv->up)
1884         {
1885                 RT_TRACE(COMP_RATE, "<---- dm_restore_dynamic_mechanism_state(): driver is going to unload\n");
1886                 return;
1887         }
1888
1889         //
1890         // Restore previous state for rate adaptive
1891         //
1892         if(priv->rate_adaptive.rate_adaptive_disabled)
1893                 return;
1894         // TODO: Only 11n mode is implemented currently,
1895         if( !(priv->ieee80211->mode==WIRELESS_MODE_N_24G ||
1896                  priv->ieee80211->mode==WIRELESS_MODE_N_5G))
1897                  return;
1898         {
1899                         /* 2007/11/15 MH Copy from 8190PCI. */
1900                         u32 ratr_value;
1901                         ratr_value = reg_ratr;
1902                         if(priv->rf_type == RF_1T2R)    // 1T2R, Spatial Stream 2 should be disabled
1903                         {
1904                                 ratr_value &=~ (RATE_ALL_OFDM_2SS);
1905                                 //DbgPrint("HW_VAR_TATR_0 from 0x%x ==> 0x%x\n", ((pu4Byte)(val))[0], ratr_value);
1906                         }
1907                         //DbgPrint("set HW_VAR_TATR_0 = 0x%x\n", ratr_value);
1908                         //cosa PlatformEFIOWrite4Byte(Adapter, RATR0, ((pu4Byte)(val))[0]);
1909                         write_nic_dword(dev, RATR0, ratr_value);
1910                         write_nic_byte(dev, UFWP, 1);
1911 #if 0           // Disable old code.
1912                         u1Byte index;
1913                         u4Byte input_value;
1914                         index = (u1Byte)((((pu4Byte)(val))[0]) >> 28);
1915                         input_value = (((pu4Byte)(val))[0]) & 0x0fffffff;
1916                         // TODO: Correct it. Emily 2007.01.11
1917                         PlatformEFIOWrite4Byte(Adapter, RATR0+index*4, input_value);
1918 #endif
1919         }
1920         //Resore TX Power Tracking Index
1921         if(priv->btxpower_trackingInit && priv->btxpower_tracking){
1922                 dm_txpower_reset_recovery(dev);
1923         }
1924
1925         //
1926         //Restore BB Initial Gain
1927         //
1928         dm_bb_initialgain_restore(dev);
1929
1930 }       // DM_RestoreDynamicMechanismState
1931
1932 static void dm_bb_initialgain_restore(struct net_device *dev)
1933 {
1934         struct r8192_priv *priv = ieee80211_priv(dev);
1935         u32 bit_mask = 0x7f; //Bit0~ Bit6
1936
1937         if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1938                 return;
1939
1940         //Disable Initial Gain
1941         //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);
1942         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   // Only clear byte 1 and rewrite.
1943         rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1);
1944         rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1);
1945         rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bit_mask, (u32)priv->initgain_backup.xcagccore1);
1946         rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bit_mask, (u32)priv->initgain_backup.xdagccore1);
1947         bit_mask  = bMaskByte2;
1948         rtl8192_setBBreg(dev, rCCK0_CCA, bit_mask, (u32)priv->initgain_backup.cca);
1949
1950         RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
1951         RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
1952         RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
1953         RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
1954         RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
1955         //Enable Initial Gain
1956         //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x100);
1957         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);   // Only clear byte 1 and rewrite.
1958
1959 }       // dm_BBInitialGainRestore
1960
1961
1962 void dm_backup_dynamic_mechanism_state(struct net_device *dev)
1963 {
1964         struct r8192_priv *priv = ieee80211_priv(dev);
1965
1966         // Fsync to avoid reset
1967         priv->bswitch_fsync  = false;
1968         priv->bfsync_processing = false;
1969         //Backup BB InitialGain
1970         dm_bb_initialgain_backup(dev);
1971
1972 }       // DM_BackupDynamicMechanismState
1973
1974
1975 static void dm_bb_initialgain_backup(struct net_device *dev)
1976 {
1977         struct r8192_priv *priv = ieee80211_priv(dev);
1978         u32 bit_mask = bMaskByte0; //Bit0~ Bit6
1979
1980         if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1981                 return;
1982
1983         //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);
1984         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   // Only clear byte 1 and rewrite.
1985         priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bit_mask);
1986         priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bit_mask);
1987         priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bit_mask);
1988         priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bit_mask);
1989         bit_mask  = bMaskByte2;
1990         priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bit_mask);
1991
1992         RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
1993         RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
1994         RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
1995         RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
1996         RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
1997
1998 }   // dm_BBInitialGainBakcup
1999
2000 #endif
2001 /*-----------------------------------------------------------------------------
2002  * Function:    dm_change_dynamic_initgain_thresh()
2003  *
2004  * Overview:
2005  *
2006  * Input:               NONE
2007  *
2008  * Output:              NONE
2009  *
2010  * Return:              NONE
2011  *
2012  * Revised History:
2013  *      When            Who             Remark
2014  *      05/29/2008      amy             Create Version 0 porting from windows code.
2015  *
2016  *---------------------------------------------------------------------------*/
2017 void dm_change_dynamic_initgain_thresh(struct net_device *dev, u32 dm_type, u32 dm_value)
2018 {
2019         if (dm_type == DIG_TYPE_THRESH_HIGH)
2020         {
2021                 dm_digtable.rssi_high_thresh = dm_value;
2022         }
2023         else if (dm_type == DIG_TYPE_THRESH_LOW)
2024         {
2025                 dm_digtable.rssi_low_thresh = dm_value;
2026         }
2027         else if (dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH)
2028         {
2029                 dm_digtable.rssi_high_power_highthresh = dm_value;
2030         }
2031         else if (dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH)
2032         {
2033                 dm_digtable.rssi_high_power_highthresh = dm_value;
2034         }
2035         else if (dm_type == DIG_TYPE_ENABLE)
2036         {
2037                 dm_digtable.dig_state           = DM_STA_DIG_MAX;
2038                 dm_digtable.dig_enable_flag     = true;
2039         }
2040         else if (dm_type == DIG_TYPE_DISABLE)
2041         {
2042                 dm_digtable.dig_state           = DM_STA_DIG_MAX;
2043                 dm_digtable.dig_enable_flag     = false;
2044         }
2045         else if (dm_type == DIG_TYPE_DBG_MODE)
2046         {
2047                 if(dm_value >= DM_DBG_MAX)
2048                         dm_value = DM_DBG_OFF;
2049                 dm_digtable.dbg_mode            = (u8)dm_value;
2050         }
2051         else if (dm_type == DIG_TYPE_RSSI)
2052         {
2053                 if(dm_value > 100)
2054                         dm_value = 30;
2055                 dm_digtable.rssi_val                    = (long)dm_value;
2056         }
2057         else if (dm_type == DIG_TYPE_ALGORITHM)
2058         {
2059                 if (dm_value >= DIG_ALGO_MAX)
2060                         dm_value = DIG_ALGO_BY_FALSE_ALARM;
2061                 if(dm_digtable.dig_algorithm != (u8)dm_value)
2062                         dm_digtable.dig_algorithm_switch = 1;
2063                 dm_digtable.dig_algorithm       = (u8)dm_value;
2064         }
2065         else if (dm_type == DIG_TYPE_BACKOFF)
2066         {
2067                 if(dm_value > 30)
2068                         dm_value = 30;
2069                 dm_digtable.backoff_val         = (u8)dm_value;
2070         }
2071         else if(dm_type == DIG_TYPE_RX_GAIN_MIN)
2072         {
2073                 if(dm_value == 0)
2074                         dm_value = 0x1;
2075                 dm_digtable.rx_gain_range_min = (u8)dm_value;
2076         }
2077         else if(dm_type == DIG_TYPE_RX_GAIN_MAX)
2078         {
2079                 if(dm_value > 0x50)
2080                         dm_value = 0x50;
2081                 dm_digtable.rx_gain_range_max = (u8)dm_value;
2082         }
2083 }       /* DM_ChangeDynamicInitGainThresh */
2084
2085 static void dm_change_fsync_setting(struct net_device *dev, s32 DM_Type, s32 DM_Value)
2086 {
2087         struct r8192_priv *priv = ieee80211_priv(dev);
2088
2089         if (DM_Type == 0)       // monitor 0xc38 register
2090         {
2091                 if(DM_Value > 1)
2092                         DM_Value = 1;
2093                 priv->framesyncMonitor = (u8)DM_Value;
2094                 //DbgPrint("pHalData->framesyncMonitor = %d", pHalData->framesyncMonitor);
2095         }
2096 }
2097
2098 static void dm_change_rxpath_selection_setting(struct net_device *dev, s32 DM_Type, s32 DM_Value)
2099 {
2100         struct r8192_priv *priv = ieee80211_priv(dev);
2101         prate_adaptive  pRA = (prate_adaptive)&(priv->rate_adaptive);
2102
2103
2104         if(DM_Type == 0)
2105         {
2106                 if(DM_Value > 1)
2107                         DM_Value = 1;
2108                 DM_RxPathSelTable.Enable = (u8)DM_Value;
2109         }
2110         else if(DM_Type == 1)
2111         {
2112                 if(DM_Value > 1)
2113                         DM_Value = 1;
2114                 DM_RxPathSelTable.DbgMode = (u8)DM_Value;
2115         }
2116         else if(DM_Type == 2)
2117         {
2118                 if(DM_Value > 40)
2119                         DM_Value = 40;
2120                 DM_RxPathSelTable.SS_TH_low = (u8)DM_Value;
2121         }
2122         else if(DM_Type == 3)
2123         {
2124                 if(DM_Value > 25)
2125                         DM_Value = 25;
2126                 DM_RxPathSelTable.diff_TH = (u8)DM_Value;
2127         }
2128         else if(DM_Type == 4)
2129         {
2130                 if(DM_Value >= CCK_Rx_Version_MAX)
2131                         DM_Value = CCK_Rx_Version_1;
2132                 DM_RxPathSelTable.cck_method= (u8)DM_Value;
2133         }
2134         else if(DM_Type == 10)
2135         {
2136                 if(DM_Value > 100)
2137                         DM_Value = 50;
2138                 DM_RxPathSelTable.rf_rssi[0] = (u8)DM_Value;
2139         }
2140         else if(DM_Type == 11)
2141         {
2142                 if(DM_Value > 100)
2143                         DM_Value = 50;
2144                 DM_RxPathSelTable.rf_rssi[1] = (u8)DM_Value;
2145         }
2146         else if(DM_Type == 12)
2147         {
2148                 if(DM_Value > 100)
2149                         DM_Value = 50;
2150                 DM_RxPathSelTable.rf_rssi[2] = (u8)DM_Value;
2151         }
2152         else if(DM_Type == 13)
2153         {
2154                 if(DM_Value > 100)
2155                         DM_Value = 50;
2156                 DM_RxPathSelTable.rf_rssi[3] = (u8)DM_Value;
2157         }
2158         else if(DM_Type == 20)
2159         {
2160                 if(DM_Value > 1)
2161                         DM_Value = 1;
2162                 pRA->ping_rssi_enable = (u8)DM_Value;
2163         }
2164         else if(DM_Type == 21)
2165         {
2166                 if(DM_Value > 30)
2167                         DM_Value = 30;
2168                 pRA->ping_rssi_thresh_for_ra = DM_Value;
2169         }
2170 }
2171
2172 #if 0
2173 void dm_force_tx_fw_info(struct net_device *dev, u32 force_type, u32 force_value)
2174 {
2175         struct r8192_priv *priv = ieee80211_priv(dev);
2176
2177         if (force_type == 0)    // don't force TxSC
2178         {
2179                 //DbgPrint("Set Force SubCarrier Off\n");
2180                 priv->tx_fwinfo_force_subcarriermode = 0;
2181         }
2182         else if(force_type == 1) //force
2183         {
2184                 //DbgPrint("Set Force SubCarrier On\n");
2185                 priv->tx_fwinfo_force_subcarriermode = 1;
2186                 if(force_value > 3)
2187                         force_value = 3;
2188                 priv->tx_fwinfo_force_subcarrierval = (u8)force_value;
2189         }
2190 }
2191 #endif
2192
2193 /*-----------------------------------------------------------------------------
2194  * Function:    dm_dig_init()
2195  *
2196  * Overview:    Set DIG scheme init value.
2197  *
2198  * Input:               NONE
2199  *
2200  * Output:              NONE
2201  *
2202  * Return:              NONE
2203  *
2204  * Revised History:
2205  *      When            Who             Remark
2206  *      05/15/2008      amy             Create Version 0 porting from windows code.
2207  *
2208  *---------------------------------------------------------------------------*/
2209 static void dm_dig_init(struct net_device *dev)
2210 {
2211         struct r8192_priv *priv = ieee80211_priv(dev);
2212         /* 2007/10/05 MH Disable DIG scheme now. Not tested. */
2213         dm_digtable.dig_enable_flag     = true;
2214         dm_digtable.dig_algorithm = DIG_ALGO_BY_RSSI;
2215         dm_digtable.dbg_mode = DM_DBG_OFF;      //off=by real rssi value, on=by DM_DigTable.Rssi_val for new dig
2216         dm_digtable.dig_algorithm_switch = 0;
2217
2218         /* 2007/10/04 MH Define init gain threshol. */
2219         dm_digtable.dig_state           = DM_STA_DIG_MAX;
2220         dm_digtable.dig_highpwr_state   = DM_STA_DIG_MAX;
2221         dm_digtable.initialgain_lowerbound_state = false;
2222
2223         dm_digtable.rssi_low_thresh     = DM_DIG_THRESH_LOW;
2224         dm_digtable.rssi_high_thresh    = DM_DIG_THRESH_HIGH;
2225
2226         dm_digtable.rssi_high_power_lowthresh = DM_DIG_HIGH_PWR_THRESH_LOW;
2227         dm_digtable.rssi_high_power_highthresh = DM_DIG_HIGH_PWR_THRESH_HIGH;
2228
2229         dm_digtable.rssi_val = 50;      //for new dig debug rssi value
2230         dm_digtable.backoff_val = DM_DIG_BACKOFF;
2231         dm_digtable.rx_gain_range_max = DM_DIG_MAX;
2232         if(priv->CustomerID == RT_CID_819x_Netcore)
2233                 dm_digtable.rx_gain_range_min = DM_DIG_MIN_Netcore;
2234         else
2235                 dm_digtable.rx_gain_range_min = DM_DIG_MIN;
2236
2237 }       /* dm_dig_init */
2238
2239
2240 /*-----------------------------------------------------------------------------
2241  * Function:    dm_ctrl_initgain_byrssi()
2242  *
2243  * Overview:    Driver must monitor RSSI and notify firmware to change initial
2244  *                              gain according to different threshold. BB team provide the
2245  *                              suggested solution.
2246  *
2247  * Input:                       struct net_device *dev
2248  *
2249  * Output:              NONE
2250  *
2251  * Return:              NONE
2252  *
2253  * Revised History:
2254  *      When            Who             Remark
2255  *      05/27/2008      amy             Create Version 0 porting from windows code.
2256  *---------------------------------------------------------------------------*/
2257 static void dm_ctrl_initgain_byrssi(struct net_device *dev)
2258 {
2259
2260         if (dm_digtable.dig_enable_flag == false)
2261                 return;
2262
2263         if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
2264                 dm_ctrl_initgain_byrssi_by_fwfalse_alarm(dev);
2265         else if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
2266                 dm_ctrl_initgain_byrssi_by_driverrssi(dev);
2267         else
2268                 return;
2269 }
2270
2271
2272 static void dm_ctrl_initgain_byrssi_by_driverrssi(
2273         struct net_device *dev)
2274 {
2275         struct r8192_priv *priv = ieee80211_priv(dev);
2276         u8 i;
2277         static u8       fw_dig=0;
2278
2279         if (dm_digtable.dig_enable_flag == false)
2280                 return;
2281
2282         //DbgPrint("Dig by Sw Rssi \n");
2283         if(dm_digtable.dig_algorithm_switch)    // if swithed algorithm, we have to disable FW Dig.
2284                 fw_dig = 0;
2285         if(fw_dig <= 3) // execute several times to make sure the FW Dig is disabled
2286         {// FW DIG Off
2287                 for(i=0; i<3; i++)
2288                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   // Only clear byte 1 and rewrite.
2289                 fw_dig++;
2290                 dm_digtable.dig_state = DM_STA_DIG_OFF; //fw dig off.
2291         }
2292
2293         if(priv->ieee80211->state == IEEE80211_LINKED)
2294                 dm_digtable.cur_connect_state = DIG_CONNECT;
2295         else
2296                 dm_digtable.cur_connect_state = DIG_DISCONNECT;
2297
2298         //DbgPrint("DM_DigTable.PreConnectState = %d, DM_DigTable.CurConnectState = %d \n",
2299                 //DM_DigTable.PreConnectState, DM_DigTable.CurConnectState);
2300
2301         if(dm_digtable.dbg_mode == DM_DBG_OFF)
2302                 dm_digtable.rssi_val = priv->undecorated_smoothed_pwdb;
2303         //DbgPrint("DM_DigTable.Rssi_val = %d \n", DM_DigTable.Rssi_val);
2304         dm_initial_gain(dev);
2305         dm_pd_th(dev);
2306         dm_cs_ratio(dev);
2307         if(dm_digtable.dig_algorithm_switch)
2308                 dm_digtable.dig_algorithm_switch = 0;
2309         dm_digtable.pre_connect_state = dm_digtable.cur_connect_state;
2310
2311 }       /* dm_CtrlInitGainByRssi */
2312
2313 static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
2314         struct net_device *dev)
2315 {
2316         struct r8192_priv *priv = ieee80211_priv(dev);
2317         static u32 reset_cnt = 0;
2318         u8 i;
2319
2320         if (dm_digtable.dig_enable_flag == false)
2321                 return;
2322
2323         if(dm_digtable.dig_algorithm_switch)
2324         {
2325                 dm_digtable.dig_state = DM_STA_DIG_MAX;
2326                 // Fw DIG On.
2327                 for(i=0; i<3; i++)
2328                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);   // Only clear byte 1 and rewrite.
2329                 dm_digtable.dig_algorithm_switch = 0;
2330         }
2331
2332         if (priv->ieee80211->state != IEEE80211_LINKED)
2333                 return;
2334
2335         // For smooth, we can not change DIG state.
2336         if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_low_thresh) &&
2337                 (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_thresh))
2338         {
2339                 return;
2340         }
2341         //DbgPrint("Dig by Fw False Alarm\n");
2342         //if (DM_DigTable.Dig_State == DM_STA_DIG_OFF)
2343         /*DbgPrint("DIG Check\n\r RSSI=%d LOW=%d HIGH=%d STATE=%d",
2344         pHalData->UndecoratedSmoothedPWDB, DM_DigTable.RssiLowThresh,
2345         DM_DigTable.RssiHighThresh, DM_DigTable.Dig_State);*/
2346         /* 1. When RSSI decrease, We have to judge if it is smaller than a treshold
2347                   and then execute below step. */
2348         if ((priv->undecorated_smoothed_pwdb <= dm_digtable.rssi_low_thresh))
2349         {
2350                 /* 2008/02/05 MH When we execute silent reset, the DIG PHY parameters
2351                    will be reset to init value. We must prevent the condition. */
2352                 if (dm_digtable.dig_state == DM_STA_DIG_OFF &&
2353                         (priv->reset_count == reset_cnt))
2354                 {
2355                         return;
2356                 }
2357                 else
2358                 {
2359                         reset_cnt = priv->reset_count;
2360                 }
2361
2362                 // If DIG is off, DIG high power state must reset.
2363                 dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX;
2364                 dm_digtable.dig_state = DM_STA_DIG_OFF;
2365
2366                 // 1.1 DIG Off.
2367                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   // Only clear byte 1 and rewrite.
2368
2369                 // 1.2 Set initial gain.
2370                 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17);
2371                 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17);
2372                 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x17);
2373                 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x17);
2374
2375                 // 1.3 Lower PD_TH for OFDM.
2376                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2377                 {
2378                         /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
2379                         // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2380                         #ifdef RTL8190P
2381                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
2382                         #else
2383                                 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
2384                                 #endif
2385                         /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2386                                 write_nic_byte(pAdapter, rOFDM0_RxDetector1, 0x40);
2387                         */
2388                         //else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
2389
2390
2391                         //else
2392                                 //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x40);
2393                 }
2394                 else
2395                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2396
2397                 // 1.4 Lower CS ratio for CCK.
2398                 write_nic_byte(dev, 0xa0a, 0x08);
2399
2400                 // 1.5 Higher EDCCA.
2401                 //PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x325);
2402                 return;
2403
2404         }
2405
2406         /* 2. When RSSI increase, We have to judge if it is larger than a treshold
2407                   and then execute below step.  */
2408         if ((priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh) )
2409         {
2410                 u8 reset_flag = 0;
2411
2412                 if (dm_digtable.dig_state == DM_STA_DIG_ON &&
2413                         (priv->reset_count == reset_cnt))
2414                 {
2415                         dm_ctrl_initgain_byrssi_highpwr(dev);
2416                         return;
2417                 }
2418                 else
2419                 {
2420                         if (priv->reset_count != reset_cnt)
2421                                 reset_flag = 1;
2422
2423                         reset_cnt = priv->reset_count;
2424                 }
2425
2426                 dm_digtable.dig_state = DM_STA_DIG_ON;
2427                 //DbgPrint("DIG ON\n\r");
2428
2429                 // 2.1 Set initial gain.
2430                 // 2008/02/26 MH SD3-Jerry suggest to prevent dirty environment.
2431                 if (reset_flag == 1)
2432                 {
2433                         write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x2c);
2434                         write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x2c);
2435                         write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x2c);
2436                         write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x2c);
2437                 }
2438                 else
2439                 {
2440                 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x20);
2441                 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x20);
2442                 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x20);
2443                 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x20);
2444                 }
2445
2446                 // 2.2 Higher PD_TH for OFDM.
2447                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2448                 {
2449                         /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
2450                         // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2451                         #ifdef RTL8190P
2452                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2453                         #else
2454                                 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
2455                                 #endif
2456                         /*
2457                         else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2458                                 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2459                         */
2460                         //else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
2461
2462                         //else
2463                                 //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x42);
2464                 }
2465                 else
2466                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
2467
2468                 // 2.3 Higher CS ratio for CCK.
2469                 write_nic_byte(dev, 0xa0a, 0xcd);
2470
2471                 // 2.4 Lower EDCCA.
2472                 /* 2008/01/11 MH 90/92 series are the same. */
2473                 //PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x346);
2474
2475                 // 2.5 DIG On.
2476                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);   // Only clear byte 1 and rewrite.
2477
2478         }
2479
2480         dm_ctrl_initgain_byrssi_highpwr(dev);
2481
2482 }       /* dm_CtrlInitGainByRssi */
2483
2484
2485 /*-----------------------------------------------------------------------------
2486  * Function:    dm_ctrl_initgain_byrssi_highpwr()
2487  *
2488  * Overview:
2489  *
2490  * Input:               NONE
2491  *
2492  * Output:              NONE
2493  *
2494  * Return:              NONE
2495  *
2496  * Revised History:
2497  *      When            Who             Remark
2498  *      05/28/2008      amy             Create Version 0 porting from windows code.
2499  *
2500  *---------------------------------------------------------------------------*/
2501 static void dm_ctrl_initgain_byrssi_highpwr(
2502         struct net_device * dev)
2503 {
2504         struct r8192_priv *priv = ieee80211_priv(dev);
2505         static u32 reset_cnt_highpwr = 0;
2506
2507         // For smooth, we can not change high power DIG state in the range.
2508         if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_high_power_lowthresh) &&
2509                 (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_highthresh))
2510         {
2511                 return;
2512         }
2513
2514         /* 3. When RSSI >75% or <70%, it is a high power issue. We have to judge if
2515                   it is larger than a treshold and then execute below step.  */
2516         // 2008/02/05 MH SD3-Jerry Modify PD_TH for high power issue.
2517         if (priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_power_highthresh)
2518         {
2519                 if (dm_digtable.dig_highpwr_state == DM_STA_DIG_ON &&
2520                         (priv->reset_count == reset_cnt_highpwr))
2521                         return;
2522                 else
2523                         dm_digtable.dig_highpwr_state = DM_STA_DIG_ON;
2524
2525                 // 3.1 Higher PD_TH for OFDM for high power state.
2526                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2527                 {
2528                         #ifdef RTL8190P
2529                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2530                         #else
2531                                 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
2532                                 #endif
2533
2534                         /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2535                                 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2536                         */
2537
2538                 }
2539                 else
2540                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);
2541         }
2542         else
2543         {
2544                 if (dm_digtable.dig_highpwr_state == DM_STA_DIG_OFF&&
2545                         (priv->reset_count == reset_cnt_highpwr))
2546                         return;
2547                 else
2548                         dm_digtable.dig_highpwr_state = DM_STA_DIG_OFF;
2549
2550                 if (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_lowthresh &&
2551                          priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh)
2552                 {
2553                         // 3.2 Recover PD_TH for OFDM for normal power region.
2554                         if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2555                         {
2556                                 #ifdef RTL8190P
2557                                 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2558                                 #else
2559                                         write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
2560                                         #endif
2561                                 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2562                                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2563                                 */
2564
2565                         }
2566                         else
2567                                 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
2568                 }
2569         }
2570
2571         reset_cnt_highpwr = priv->reset_count;
2572
2573 }       /* dm_CtrlInitGainByRssiHighPwr */
2574
2575
2576 static void dm_initial_gain(
2577         struct net_device * dev)
2578 {
2579         struct r8192_priv *priv = ieee80211_priv(dev);
2580         u8                                      initial_gain=0;
2581         static u8                               initialized=0, force_write=0;
2582         static u32                      reset_cnt=0;
2583
2584         if(dm_digtable.dig_algorithm_switch)
2585         {
2586                 initialized = 0;
2587                 reset_cnt = 0;
2588         }
2589
2590         if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state)
2591         {
2592                 if(dm_digtable.cur_connect_state == DIG_CONNECT)
2593                 {
2594                         if((dm_digtable.rssi_val+10-dm_digtable.backoff_val) > dm_digtable.rx_gain_range_max)
2595                                 dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_max;
2596                         else if((dm_digtable.rssi_val+10-dm_digtable.backoff_val) < dm_digtable.rx_gain_range_min)
2597                                 dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_min;
2598                         else
2599                                 dm_digtable.cur_ig_value = dm_digtable.rssi_val+10-dm_digtable.backoff_val;
2600                 }
2601                 else            //current state is disconnected
2602                 {
2603                         if(dm_digtable.cur_ig_value == 0)
2604                                 dm_digtable.cur_ig_value = priv->DefaultInitialGain[0];
2605                         else
2606                                 dm_digtable.cur_ig_value = dm_digtable.pre_ig_value;
2607                 }
2608         }
2609         else    // disconnected -> connected or connected -> disconnected
2610         {
2611                 dm_digtable.cur_ig_value = priv->DefaultInitialGain[0];
2612                 dm_digtable.pre_ig_value = 0;
2613         }
2614         //DbgPrint("DM_DigTable.CurIGValue = 0x%x, DM_DigTable.PreIGValue = 0x%x\n", DM_DigTable.CurIGValue, DM_DigTable.PreIGValue);
2615
2616         // if silent reset happened, we should rewrite the values back
2617         if(priv->reset_count != reset_cnt)
2618         {
2619                 force_write = 1;
2620                 reset_cnt = priv->reset_count;
2621         }
2622
2623         if(dm_digtable.pre_ig_value != read_nic_byte(dev, rOFDM0_XAAGCCore1))
2624                 force_write = 1;
2625
2626         {
2627                 if((dm_digtable.pre_ig_value != dm_digtable.cur_ig_value)
2628                         || !initialized || force_write)
2629                 {
2630                         initial_gain = (u8)dm_digtable.cur_ig_value;
2631                         //DbgPrint("Write initial gain = 0x%x\n", initial_gain);
2632                         // Set initial gain.
2633                         write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
2634                         write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
2635                         write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
2636                         write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
2637                         dm_digtable.pre_ig_value = dm_digtable.cur_ig_value;
2638                         initialized = 1;
2639                         force_write = 0;
2640                 }
2641         }
2642 }
2643
2644 static void dm_pd_th(
2645         struct net_device * dev)
2646 {
2647         struct r8192_priv *priv = ieee80211_priv(dev);
2648         static u8                               initialized=0, force_write=0;
2649         static u32                      reset_cnt = 0;
2650
2651         if(dm_digtable.dig_algorithm_switch)
2652         {
2653                 initialized = 0;
2654                 reset_cnt = 0;
2655         }
2656
2657         if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state)
2658         {
2659                 if(dm_digtable.cur_connect_state == DIG_CONNECT)
2660                 {
2661                         if (dm_digtable.rssi_val >= dm_digtable.rssi_high_power_highthresh)
2662                                 dm_digtable.curpd_thstate = DIG_PD_AT_HIGH_POWER;
2663                         else if ((dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh))
2664                                 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
2665                         else if ((dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh) &&
2666                                         (dm_digtable.rssi_val < dm_digtable.rssi_high_power_lowthresh))
2667                                 dm_digtable.curpd_thstate = DIG_PD_AT_NORMAL_POWER;
2668                         else
2669                                 dm_digtable.curpd_thstate = dm_digtable.prepd_thstate;
2670                 }
2671                 else
2672                 {
2673                         dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
2674                 }
2675         }
2676         else    // disconnected -> connected or connected -> disconnected
2677         {
2678                 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
2679         }
2680
2681         // if silent reset happened, we should rewrite the values back
2682         if(priv->reset_count != reset_cnt)
2683         {
2684                 force_write = 1;
2685                 reset_cnt = priv->reset_count;
2686         }
2687
2688         {
2689                 if((dm_digtable.prepd_thstate != dm_digtable.curpd_thstate) ||
2690                         (initialized<=3) || force_write)
2691                 {
2692                         //DbgPrint("Write PD_TH state = %d\n", DM_DigTable.CurPD_THState);
2693                         if(dm_digtable.curpd_thstate == DIG_PD_AT_LOW_POWER)
2694                         {
2695                                 // Lower PD_TH for OFDM.
2696                                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2697                                 {
2698                                         /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
2699                                         // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2700                                         #ifdef RTL8190P
2701                                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
2702                                         #else
2703                                                 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
2704                                                 #endif
2705                                         /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2706                                                 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
2707                                         */
2708                                 }
2709                                 else
2710                                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2711                         }
2712                         else if(dm_digtable.curpd_thstate == DIG_PD_AT_NORMAL_POWER)
2713                         {
2714                                 // Higher PD_TH for OFDM.
2715                                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2716                                 {
2717                                         /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
2718                                         // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2719                                         #ifdef RTL8190P
2720                                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2721                                         #else
2722                                                 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
2723                                                 #endif
2724                                         /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2725                                                 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2726                                         */
2727                                 }
2728                                 else
2729                                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
2730                         }
2731                         else if(dm_digtable.curpd_thstate == DIG_PD_AT_HIGH_POWER)
2732                         {
2733                                 // Higher PD_TH for OFDM for high power state.
2734                                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2735                                 {
2736                                         #ifdef RTL8190P
2737                                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2738                                         #else
2739                                                 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
2740                                                 #endif
2741                                         /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2742                                                 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2743                                         */
2744                                 }
2745                                 else
2746                                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);
2747                         }
2748                         dm_digtable.prepd_thstate = dm_digtable.curpd_thstate;
2749                         if(initialized <= 3)
2750                                 initialized++;
2751                         force_write = 0;
2752                 }
2753         }
2754 }
2755
2756 static  void dm_cs_ratio(
2757         struct net_device * dev)
2758 {
2759         struct r8192_priv *priv = ieee80211_priv(dev);
2760         static u8                               initialized=0,force_write=0;
2761         static u32                      reset_cnt = 0;
2762
2763         if(dm_digtable.dig_algorithm_switch)
2764         {
2765                 initialized = 0;
2766                 reset_cnt = 0;
2767         }
2768
2769         if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state)
2770         {
2771                 if(dm_digtable.cur_connect_state == DIG_CONNECT)
2772                 {
2773                         if ((dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh))
2774                                 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2775                         else if ((dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh) )
2776                                 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_HIGHER;
2777                         else
2778                                 dm_digtable.curcs_ratio_state = dm_digtable.precs_ratio_state;
2779                 }
2780                 else
2781                 {
2782                         dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2783                 }
2784         }
2785         else    // disconnected -> connected or connected -> disconnected
2786         {
2787                 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2788         }
2789
2790         // if silent reset happened, we should rewrite the values back
2791         if(priv->reset_count != reset_cnt)
2792         {
2793                 force_write = 1;
2794                 reset_cnt = priv->reset_count;
2795         }
2796
2797
2798         {
2799                 if((dm_digtable.precs_ratio_state != dm_digtable.curcs_ratio_state) ||
2800                         !initialized || force_write)
2801                 {
2802                         //DbgPrint("Write CS_ratio state = %d\n", DM_DigTable.CurCS_ratioState);
2803                         if(dm_digtable.curcs_ratio_state == DIG_CS_RATIO_LOWER)
2804                         {
2805                                 // Lower CS ratio for CCK.
2806                                 write_nic_byte(dev, 0xa0a, 0x08);
2807                         }
2808                         else if(dm_digtable.curcs_ratio_state == DIG_CS_RATIO_HIGHER)
2809                         {
2810                                 // Higher CS ratio for CCK.
2811                                 write_nic_byte(dev, 0xa0a, 0xcd);
2812                         }
2813                         dm_digtable.precs_ratio_state = dm_digtable.curcs_ratio_state;
2814                         initialized = 1;
2815                         force_write = 0;
2816                 }
2817         }
2818 }
2819
2820 void dm_init_edca_turbo(struct net_device *dev)
2821 {
2822         struct r8192_priv *priv = ieee80211_priv(dev);
2823
2824         priv->bcurrent_turbo_EDCA = false;
2825         priv->ieee80211->bis_any_nonbepkts = false;
2826         priv->bis_cur_rdlstate = false;
2827 }       // dm_init_edca_turbo
2828
2829 #if 1
2830 static void dm_check_edca_turbo(
2831         struct net_device * dev)
2832 {
2833         struct r8192_priv *priv = ieee80211_priv(dev);
2834         PRT_HIGH_THROUGHPUT     pHTInfo = priv->ieee80211->pHTInfo;
2835         //PSTA_QOS                      pStaQos = pMgntInfo->pStaQos;
2836
2837         // Keep past Tx/Rx packet count for RT-to-RT EDCA turbo.
2838         static unsigned long                    lastTxOkCnt = 0;
2839         static unsigned long                    lastRxOkCnt = 0;
2840         unsigned long                           curTxOkCnt = 0;
2841         unsigned long                           curRxOkCnt = 0;
2842
2843         //
2844         // Do not be Turbo if it's under WiFi config and Qos Enabled, because the EDCA parameters
2845         // should follow the settings from QAP. By Bruce, 2007-12-07.
2846         //
2847         #if 1
2848         if(priv->ieee80211->state != IEEE80211_LINKED)
2849                 goto dm_CheckEdcaTurbo_EXIT;
2850         #endif
2851         // We do not turn on EDCA turbo mode for some AP that has IOT issue
2852         if(priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO)
2853                 goto dm_CheckEdcaTurbo_EXIT;
2854
2855 //      printk("========>%s():bis_any_nonbepkts is %d\n",__FUNCTION__,priv->bis_any_nonbepkts);
2856         // Check the status for current condition.
2857         if(!priv->ieee80211->bis_any_nonbepkts)
2858         {
2859                 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
2860                 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
2861                 // For RT-AP, we needs to turn it on when Rx>Tx
2862                 if(curRxOkCnt > 4*curTxOkCnt)
2863                 {
2864                         //printk("%s():curRxOkCnt > 4*curTxOkCnt\n");
2865                         if(!priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA)
2866                         {
2867                                 write_nic_dword(dev, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]);
2868                                 priv->bis_cur_rdlstate = true;
2869                         }
2870                 }
2871                 else
2872                 {
2873
2874                         //printk("%s():curRxOkCnt < 4*curTxOkCnt\n");
2875                         if(priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA)
2876                         {
2877                                 write_nic_dword(dev, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]);
2878                                 priv->bis_cur_rdlstate = false;
2879                         }
2880
2881                 }
2882
2883                 priv->bcurrent_turbo_EDCA = true;
2884         }
2885         else
2886         {
2887                 //
2888                 // Turn Off EDCA turbo here.
2889                 // Restore original EDCA according to the declaration of AP.
2890                 //
2891                  if(priv->bcurrent_turbo_EDCA)
2892                 {
2893
2894                         {
2895                                 u8              u1bAIFS;
2896                                 u32             u4bAcParam;
2897                                 struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters;
2898                                 u8 mode = priv->ieee80211->mode;
2899
2900                         // For Each time updating EDCA parameter, reset EDCA turbo mode status.
2901                                 dm_init_edca_turbo(dev);
2902                                 u1bAIFS = qos_parameters->aifs[0] * ((mode&(IEEE_G|IEEE_N_24G)) ?9:20) + aSifsTime;
2903                                 u4bAcParam = ((((u32)(qos_parameters->tx_op_limit[0]))<< AC_PARAM_TXOP_LIMIT_OFFSET)|
2904                                         (((u32)(qos_parameters->cw_max[0]))<< AC_PARAM_ECW_MAX_OFFSET)|
2905                                         (((u32)(qos_parameters->cw_min[0]))<< AC_PARAM_ECW_MIN_OFFSET)|
2906                                         ((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET));
2907                                 printk("===>u4bAcParam:%x, ", u4bAcParam);
2908                         //write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam);
2909                                 write_nic_dword(dev, EDCAPARA_BE,  u4bAcParam);
2910
2911                         // Check ACM bit.
2912                         // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
2913                                 {
2914                         // TODO:  Modified this part and try to set acm control in only 1 IO processing!!
2915
2916                                         PACI_AIFSN      pAciAifsn = (PACI_AIFSN)&(qos_parameters->aifs[0]);
2917                                         u8              AcmCtrl = read_nic_byte( dev, AcmHwCtrl );
2918                                         if( pAciAifsn->f.ACM )
2919                                         { // ACM bit is 1.
2920                                                 AcmCtrl |= AcmHw_BeqEn;
2921                                         }
2922                                         else
2923                                         { // ACM bit is 0.
2924                                                 AcmCtrl &= (~AcmHw_BeqEn);
2925                                         }
2926
2927                                         RT_TRACE( COMP_QOS,"SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl ) ;
2928                                         write_nic_byte(dev, AcmHwCtrl, AcmCtrl );
2929                                 }
2930                         }
2931                         priv->bcurrent_turbo_EDCA = false;
2932                 }
2933         }
2934
2935
2936 dm_CheckEdcaTurbo_EXIT:
2937         // Set variables for next time.
2938         priv->ieee80211->bis_any_nonbepkts = false;
2939         lastTxOkCnt = priv->stats.txbytesunicast;
2940         lastRxOkCnt = priv->stats.rxbytesunicast;
2941 }       // dm_CheckEdcaTurbo
2942 #endif
2943
2944 static void DM_CTSToSelfSetting(struct net_device *dev, u32 DM_Type, u32 DM_Value)
2945 {
2946         struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
2947
2948         if (DM_Type == 0)       // CTS to self disable/enable
2949         {
2950                 if(DM_Value > 1)
2951                         DM_Value = 1;
2952                 priv->ieee80211->bCTSToSelfEnable = (bool)DM_Value;
2953                 //DbgPrint("pMgntInfo->bCTSToSelfEnable = %d\n", pMgntInfo->bCTSToSelfEnable);
2954         }
2955         else if(DM_Type == 1) //CTS to self Th
2956         {
2957                 if(DM_Value >= 50)
2958                         DM_Value = 50;
2959                 priv->ieee80211->CTSToSelfTH = (u8)DM_Value;
2960                 //DbgPrint("pMgntInfo->CTSToSelfTH = %d\n", pMgntInfo->CTSToSelfTH);
2961         }
2962 }
2963
2964 static void dm_init_ctstoself(struct net_device * dev)
2965 {
2966         struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
2967
2968         priv->ieee80211->bCTSToSelfEnable = TRUE;
2969         priv->ieee80211->CTSToSelfTH = CTSToSelfTHVal;
2970 }
2971
2972 static void dm_ctstoself(struct net_device *dev)
2973 {
2974         struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
2975         PRT_HIGH_THROUGHPUT     pHTInfo = priv->ieee80211->pHTInfo;
2976         static unsigned long                            lastTxOkCnt = 0;
2977         static unsigned long                            lastRxOkCnt = 0;
2978         unsigned long                                           curTxOkCnt = 0;
2979         unsigned long                                           curRxOkCnt = 0;
2980
2981         if(priv->ieee80211->bCTSToSelfEnable != TRUE)
2982         {
2983                 pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
2984                 return;
2985         }
2986         /*
2987         1. Uplink
2988         2. Linksys350/Linksys300N
2989         3. <50 disable, >55 enable
2990         */
2991
2992         if(pHTInfo->IOTPeer == HT_IOT_PEER_BROADCOM)
2993         {
2994                 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
2995                 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
2996                 if(curRxOkCnt > 4*curTxOkCnt)   //downlink, disable CTS to self
2997                 {
2998                         pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
2999                         //DbgPrint("dm_CTSToSelf() ==> CTS to self disabled -- downlink\n");
3000                 }
3001                 else    //uplink
3002                 {
3003                 #if 1
3004                         pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF;
3005                 #else
3006                         if(priv->undecorated_smoothed_pwdb < priv->ieee80211->CTSToSelfTH)      // disable CTS to self
3007                         {
3008                                 pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
3009                                 //DbgPrint("dm_CTSToSelf() ==> CTS to self disabled\n");
3010                         }
3011                         else if(priv->undecorated_smoothed_pwdb >= (priv->ieee80211->CTSToSelfTH+5))    // enable CTS to self
3012                         {
3013                                 pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF;
3014                                 //DbgPrint("dm_CTSToSelf() ==> CTS to self enabled\n");
3015                         }
3016                 #endif
3017                 }
3018
3019                 lastTxOkCnt = priv->stats.txbytesunicast;
3020                 lastRxOkCnt = priv->stats.rxbytesunicast;
3021         }
3022 }
3023
3024
3025 #if 0
3026 /*-----------------------------------------------------------------------------
3027  * Function:    dm_rf_operation_test_callback()
3028  *
3029  * Overview:    Only for RF operation test now.
3030  *
3031  * Input:               NONE
3032  *
3033  * Output:              NONE
3034  *
3035  * Return:              NONE
3036  *
3037  * Revised History:
3038  *      When            Who             Remark
3039  *      05/29/2008      amy             Create Version 0 porting from windows code.
3040  *
3041  *---------------------------------------------------------------------------*/
3042 void dm_rf_operation_test_callback(unsigned long dev)
3043 {
3044 //      struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
3045         u8 erfpath;
3046
3047
3048         for(erfpath=0; erfpath<4; erfpath++)
3049         {
3050                 //DbgPrint("Set RF-%d\n\r", eRFPath);
3051                 //PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3d7);
3052                 udelay(100);
3053         }
3054
3055         {
3056                 //PlatformSetPeriodicTimer(Adapter, &pHalData->RfTest1Timer, 500);
3057         }
3058
3059         // For test
3060         {
3061                 //u8 i;
3062                 //PlatformSetPeriodicTimer(Adapter, &pHalData->RfTest1Timer, 500);
3063 #if 0
3064                 for(i=0; i<50; i++)
3065                 {
3066                         // Write Test
3067                         PHY_SetRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
3068                         //delay_us(100);
3069                         PHY_SetRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
3070                         //delay_us(100);
3071                         PHY_SetRFReg(Adapter, RF90_PATH_C, 0x02, bMask12Bits, 0x4d);
3072                         //delay_us(100);
3073                         PHY_SetRFReg(Adapter, RF90_PATH_C, 0x02, bMask12Bits, 0x4f);
3074                         //delay_us(100);
3075
3076 #if 0
3077                         // Read test
3078                         PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits);
3079                         //delay_us(100);
3080                         PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits);
3081                         //delay_us(100);
3082                         PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x12, bMask12Bits);
3083                         //delay_us(100);
3084                         PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x12, bMask12Bits);
3085                         //delay_us(100);
3086                         PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x21, bMask12Bits);
3087                         //delay_us(100);
3088                         PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x21, bMask12Bits);
3089                         //delay_us(100);
3090 #endif
3091                 }
3092 #endif
3093         }
3094
3095 }       /* DM_RfOperationTestCallBack */
3096 #endif
3097
3098 /*-----------------------------------------------------------------------------
3099  * Function:    dm_check_rfctrl_gpio()
3100  *
3101  * Overview:    Copy 8187B template for 9xseries.
3102  *
3103  * Input:               NONE
3104  *
3105  * Output:              NONE
3106  *
3107  * Return:              NONE
3108  *
3109  * Revised History:
3110  *      When            Who             Remark
3111  *      05/28/2008      amy             Create Version 0 porting from windows code.
3112  *
3113  *---------------------------------------------------------------------------*/
3114 #if 1
3115 static void dm_check_rfctrl_gpio(struct net_device * dev)
3116 {
3117 #ifdef RTL8192E
3118         struct r8192_priv *priv = ieee80211_priv(dev);
3119 #endif
3120
3121         // Walk around for DTM test, we will not enable HW - radio on/off because r/w
3122         // page 1 register before Lextra bus is enabled cause system fails when resuming
3123         // from S4. 20080218, Emily
3124
3125         // Stop to execute workitem to prevent S3/S4 bug.
3126 #ifdef RTL8190P
3127         return;
3128 #endif
3129 #ifdef RTL8192U
3130         return;
3131 #endif
3132 #ifdef RTL8192E
3133         #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
3134                 queue_delayed_work(priv->priv_wq,&priv->gpio_change_rf_wq,0);
3135         #else
3136                 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
3137                         schedule_task(&priv->gpio_change_rf_wq);
3138                 #else
3139                         queue_work(priv->priv_wq,&priv->gpio_change_rf_wq);
3140                 #endif
3141         #endif
3142 #endif
3143
3144 }       /* dm_CheckRfCtrlGPIO */
3145
3146 #endif
3147 /*-----------------------------------------------------------------------------
3148  * Function:    dm_check_pbc_gpio()
3149  *
3150  * Overview:    Check if PBC button is pressed.
3151  *
3152  * Input:               NONE
3153  *
3154  * Output:              NONE
3155  *
3156  * Return:              NONE
3157  *
3158  * Revised History:
3159  *      When            Who             Remark
3160  *      05/28/2008      amy     Create Version 0 porting from windows code.
3161  *
3162  *---------------------------------------------------------------------------*/
3163 static  void    dm_check_pbc_gpio(struct net_device *dev)
3164 {
3165 #ifdef RTL8192U
3166         struct r8192_priv *priv = ieee80211_priv(dev);
3167         u8 tmp1byte;
3168
3169
3170         tmp1byte = read_nic_byte(dev,GPI);
3171         if(tmp1byte == 0xff)
3172         return;
3173
3174         if (tmp1byte&BIT6 || tmp1byte&BIT0)
3175         {
3176                 // Here we only set bPbcPressed to TRUE
3177                 // After trigger PBC, the variable will be set to FALSE
3178                 RT_TRACE(COMP_IO, "CheckPbcGPIO - PBC is pressed\n");
3179                 priv->bpbc_pressed = true;
3180         }
3181 #endif
3182
3183 }
3184
3185 #ifdef RTL8192E
3186
3187 /*-----------------------------------------------------------------------------
3188  * Function:    dm_GPIOChangeRF
3189  * Overview:    PCI will not support workitem call back HW radio on-off control.
3190  *
3191  * Input:               NONE
3192  *
3193  * Output:              NONE
3194  *
3195  * Return:              NONE
3196  *
3197  * Revised History:
3198  *      When            Who             Remark
3199  *      02/21/2008      MHC             Create Version 0.
3200  *
3201  *---------------------------------------------------------------------------*/
3202 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
3203 void dm_gpio_change_rf_callback(struct work_struct *work)
3204 {
3205         struct delayed_work *dwork = container_of(work,struct delayed_work,work);
3206        struct r8192_priv *priv = container_of(dwork,struct r8192_priv,gpio_change_rf_wq);
3207        struct net_device *dev = priv->ieee80211->dev;
3208 #else
3209 extern  void    dm_gpio_change_rf_callback(struct net_device *dev)
3210 {
3211         struct r8192_priv *priv = ieee80211_priv(dev);
3212 #endif
3213         u8 tmp1byte;
3214         RT_RF_POWER_STATE       eRfPowerStateToSet;
3215         bool bActuallySet = false;
3216
3217                 bActuallySet=false;
3218
3219                 if(!priv->up)
3220                 {
3221                 RT_TRACE((COMP_INIT | COMP_POWER | COMP_RF),"dm_gpio_change_rf_callback(): Callback function breaks out!!\n");
3222                 }
3223                 else
3224                 {
3225                         // 0x108 GPIO input register is read only
3226                         //set 0x108 B1= 1: RF-ON; 0: RF-OFF.
3227                         tmp1byte = read_nic_byte(dev,GPI);
3228
3229                         eRfPowerStateToSet = (tmp1byte&BIT1) ?  eRfOn : eRfOff;
3230
3231                         if( (priv->bHwRadioOff == true) && (eRfPowerStateToSet == eRfOn))
3232                         {
3233                         RT_TRACE(COMP_RF, "gpiochangeRF  - HW Radio ON\n");
3234
3235                                 priv->bHwRadioOff = false;
3236                                 bActuallySet = true;
3237                         }
3238                         else if ( (priv->bHwRadioOff == false) && (eRfPowerStateToSet == eRfOff))
3239                         {
3240                         RT_TRACE(COMP_RF, "gpiochangeRF  - HW Radio OFF\n");
3241                                 priv->bHwRadioOff = true;
3242                                 bActuallySet = true;
3243                         }
3244
3245                         if(bActuallySet)
3246                         {
3247                         priv->bHwRfOffAction = 1;
3248                                 MgntActSet_RF_State(dev, eRfPowerStateToSet, RF_CHANGE_BY_HW);
3249                                 //DrvIFIndicateCurrentPhyStatus(pAdapter);
3250
3251                 }
3252                 else
3253                 {
3254                         msleep(2000);
3255                         }
3256
3257                 }
3258
3259 }       /* dm_GPIOChangeRF */
3260
3261 #endif
3262 /*-----------------------------------------------------------------------------
3263  * Function:    DM_RFPathCheckWorkItemCallBack()
3264  *
3265  * Overview:    Check if Current RF RX path is enabled
3266  *
3267  * Input:               NONE
3268  *
3269  * Output:              NONE
3270  *
3271  * Return:              NONE
3272  *
3273  * Revised History:
3274  *      When            Who             Remark
3275  *      01/30/2008      MHC             Create Version 0.
3276  *
3277  *---------------------------------------------------------------------------*/
3278 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
3279 void dm_rf_pathcheck_workitemcallback(struct work_struct *work)
3280 {
3281         struct delayed_work *dwork = container_of(work,struct delayed_work,work);
3282        struct r8192_priv *priv = container_of(dwork,struct r8192_priv,rfpath_check_wq);
3283        struct net_device *dev =priv->ieee80211->dev;
3284 #else
3285 extern  void    dm_rf_pathcheck_workitemcallback(struct net_device *dev)
3286 {
3287         struct r8192_priv *priv = ieee80211_priv(dev);
3288 #endif
3289         //bool bactually_set = false;
3290         u8 rfpath = 0, i;
3291
3292
3293         /* 2008/01/30 MH After discussing with SD3 Jerry, 0xc04/0xd04 register will
3294            always be the same. We only read 0xc04 now. */
3295         rfpath = read_nic_byte(dev, 0xc04);
3296
3297         // Check Bit 0-3, it means if RF A-D is enabled.
3298         for (i = 0; i < RF90_PATH_MAX; i++)
3299         {
3300                 if (rfpath & (0x01<<i))
3301                         priv->brfpath_rxenable[i] = 1;
3302                 else
3303                         priv->brfpath_rxenable[i] = 0;
3304         }
3305         if(!DM_RxPathSelTable.Enable)
3306                 return;
3307
3308         dm_rxpath_sel_byrssi(dev);
3309 }       /* DM_RFPathCheckWorkItemCallBack */
3310
3311 static void dm_init_rxpath_selection(struct net_device * dev)
3312 {
3313         u8 i;
3314         struct r8192_priv *priv = ieee80211_priv(dev);
3315         DM_RxPathSelTable.Enable = 1;   //default enabled
3316         DM_RxPathSelTable.SS_TH_low = RxPathSelection_SS_TH_low;
3317         DM_RxPathSelTable.diff_TH = RxPathSelection_diff_TH;
3318         if(priv->CustomerID == RT_CID_819x_Netcore)
3319                 DM_RxPathSelTable.cck_method = CCK_Rx_Version_2;
3320         else
3321                 DM_RxPathSelTable.cck_method = CCK_Rx_Version_1;
3322         DM_RxPathSelTable.DbgMode = DM_DBG_OFF;
3323         DM_RxPathSelTable.disabledRF = 0;
3324         for(i=0; i<4; i++)
3325         {
3326                 DM_RxPathSelTable.rf_rssi[i] = 50;
3327                 DM_RxPathSelTable.cck_pwdb_sta[i] = -64;
3328                 DM_RxPathSelTable.rf_enable_rssi_th[i] = 100;
3329         }
3330 }
3331
3332 static void dm_rxpath_sel_byrssi(struct net_device * dev)
3333 {
3334         struct r8192_priv *priv = ieee80211_priv(dev);
3335         u8                              i, max_rssi_index=0, min_rssi_index=0, sec_rssi_index=0, rf_num=0;
3336         u8                              tmp_max_rssi=0, tmp_min_rssi=0, tmp_sec_rssi=0;
3337         u8                              cck_default_Rx=0x2;     //RF-C
3338         u8                              cck_optional_Rx=0x3;//RF-D
3339         long                            tmp_cck_max_pwdb=0, tmp_cck_min_pwdb=0, tmp_cck_sec_pwdb=0;
3340         u8                              cck_rx_ver2_max_index=0, cck_rx_ver2_min_index=0, cck_rx_ver2_sec_index=0;
3341         u8                              cur_rf_rssi;
3342         long                            cur_cck_pwdb;
3343         static u8                       disabled_rf_cnt=0, cck_Rx_Path_initialized=0;
3344         u8                              update_cck_rx_path;
3345
3346         if(priv->rf_type != RF_2T4R)
3347                 return;
3348
3349         if(!cck_Rx_Path_initialized)
3350         {
3351                 DM_RxPathSelTable.cck_Rx_path = (read_nic_byte(dev, 0xa07)&0xf);
3352                 cck_Rx_Path_initialized = 1;
3353         }
3354
3355         DM_RxPathSelTable.disabledRF = 0xf;
3356         DM_RxPathSelTable.disabledRF &=~ (read_nic_byte(dev, 0xc04));
3357
3358         if(priv->ieee80211->mode == WIRELESS_MODE_B)
3359         {
3360                 DM_RxPathSelTable.cck_method = CCK_Rx_Version_2;        //pure B mode, fixed cck version2
3361                 //DbgPrint("Pure B mode, use cck rx version2 \n");
3362         }
3363
3364         //decide max/sec/min rssi index
3365         for (i=0; i<RF90_PATH_MAX; i++)
3366         {
3367                 if(!DM_RxPathSelTable.DbgMode)
3368                         DM_RxPathSelTable.rf_rssi[i] = priv->stats.rx_rssi_percentage[i];
3369
3370                 if(priv->brfpath_rxenable[i])
3371                 {
3372                         rf_num++;
3373                         cur_rf_rssi = DM_RxPathSelTable.rf_rssi[i];
3374
3375                         if(rf_num == 1) // find first enabled rf path and the rssi values
3376                         {       //initialize, set all rssi index to the same one
3377                                 max_rssi_index = min_rssi_index = sec_rssi_index = i;
3378                                 tmp_max_rssi = tmp_min_rssi = tmp_sec_rssi = cur_rf_rssi;
3379                         }
3380                         else if(rf_num == 2)
3381                         {       // we pick up the max index first, and let sec and min to be the same one
3382                                 if(cur_rf_rssi >= tmp_max_rssi)
3383                                 {
3384                                         tmp_max_rssi = cur_rf_rssi;
3385                                         max_rssi_index = i;
3386                                 }
3387                                 else
3388                                 {
3389                                         tmp_sec_rssi = tmp_min_rssi = cur_rf_rssi;
3390                                         sec_rssi_index = min_rssi_index = i;
3391                                 }
3392                         }
3393                         else
3394                         {
3395                                 if(cur_rf_rssi > tmp_max_rssi)
3396                                 {
3397                                         tmp_sec_rssi = tmp_max_rssi;
3398                                         sec_rssi_index = max_rssi_index;
3399                                         tmp_max_rssi = cur_rf_rssi;
3400                                         max_rssi_index = i;
3401                                 }
3402                                 else if(cur_rf_rssi == tmp_max_rssi)
3403                                 {       // let sec and min point to the different index
3404                                         tmp_sec_rssi = cur_rf_rssi;
3405                                         sec_rssi_index = i;
3406                                 }
3407                                 else if((cur_rf_rssi < tmp_max_rssi) &&(cur_rf_rssi > tmp_sec_rssi))
3408                                 {
3409                                         tmp_sec_rssi = cur_rf_rssi;
3410                                         sec_rssi_index = i;
3411                                 }
3412                                 else if(cur_rf_rssi == tmp_sec_rssi)
3413                                 {
3414                                         if(tmp_sec_rssi == tmp_min_rssi)
3415                                         {       // let sec and min point to the different index
3416                                                 tmp_sec_rssi = cur_rf_rssi;
3417                                                 sec_rssi_index = i;
3418                                         }
3419                                         else
3420                                         {
3421                                                 // This case we don't need to set any index
3422                                         }
3423                                 }
3424                                 else if((cur_rf_rssi < tmp_sec_rssi) && (cur_rf_rssi > tmp_min_rssi))
3425                                 {
3426                                         // This case we don't need to set any index
3427                                 }
3428                                 else if(cur_rf_rssi == tmp_min_rssi)
3429                                 {
3430                                         if(tmp_sec_rssi == tmp_min_rssi)
3431                                         {       // let sec and min point to the different index
3432                                                 tmp_min_rssi = cur_rf_rssi;
3433                                                 min_rssi_index = i;
3434                                         }
3435                                         else
3436                                         {
3437                                                 // This case we don't need to set any index
3438                                         }
3439                                 }
3440                                 else if(cur_rf_rssi < tmp_min_rssi)
3441                                 {
3442                                         tmp_min_rssi = cur_rf_rssi;
3443                                         min_rssi_index = i;
3444                                 }
3445                         }
3446                 }
3447         }
3448
3449         rf_num = 0;
3450         // decide max/sec/min cck pwdb index
3451         if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_2)
3452         {
3453                 for (i=0; i<RF90_PATH_MAX; i++)
3454                 {
3455                         if(priv->brfpath_rxenable[i])
3456                         {
3457                                 rf_num++;
3458                                 cur_cck_pwdb =  DM_RxPathSelTable.cck_pwdb_sta[i];
3459
3460                                 if(rf_num == 1) // find first enabled rf path and the rssi values
3461                                 {       //initialize, set all rssi index to the same one
3462                                         cck_rx_ver2_max_index = cck_rx_ver2_min_index = cck_rx_ver2_sec_index = i;
3463                                         tmp_cck_max_pwdb = tmp_cck_min_pwdb = tmp_cck_sec_pwdb = cur_cck_pwdb;
3464                                 }
3465                                 else if(rf_num == 2)
3466                                 {       // we pick up the max index first, and let sec and min to be the same one
3467                                         if(cur_cck_pwdb >= tmp_cck_max_pwdb)
3468                                         {
3469                                                 tmp_cck_max_pwdb = cur_cck_pwdb;
3470                                                 cck_rx_ver2_max_index = i;
3471                                         }
3472                                         else
3473                                         {
3474                                                 tmp_cck_sec_pwdb = tmp_cck_min_pwdb = cur_cck_pwdb;
3475                                                 cck_rx_ver2_sec_index = cck_rx_ver2_min_index = i;
3476                                         }
3477                                 }
3478                                 else
3479                                 {
3480                                         if(cur_cck_pwdb > tmp_cck_max_pwdb)
3481                                         {
3482                                                 tmp_cck_sec_pwdb = tmp_cck_max_pwdb;
3483                                                 cck_rx_ver2_sec_index = cck_rx_ver2_max_index;
3484                                                 tmp_cck_max_pwdb = cur_cck_pwdb;
3485                                                 cck_rx_ver2_max_index = i;
3486                                         }
3487                                         else if(cur_cck_pwdb == tmp_cck_max_pwdb)
3488                                         {       // let sec and min point to the different index
3489                                                 tmp_cck_sec_pwdb = cur_cck_pwdb;
3490                                                 cck_rx_ver2_sec_index = i;
3491                                         }
3492                                         else if((cur_cck_pwdb < tmp_cck_max_pwdb) &&(cur_cck_pwdb > tmp_cck_sec_pwdb))
3493                                         {
3494                                                 tmp_cck_sec_pwdb = cur_cck_pwdb;
3495                                                 cck_rx_ver2_sec_index = i;
3496                                         }
3497                                         else if(cur_cck_pwdb == tmp_cck_sec_pwdb)
3498                                         {
3499                                                 if(tmp_cck_sec_pwdb == tmp_cck_min_pwdb)
3500                                                 {       // let sec and min point to the different index
3501                                                         tmp_cck_sec_pwdb = cur_cck_pwdb;
3502                                                         cck_rx_ver2_sec_index = i;
3503                                                 }
3504                                                 else
3505                                                 {
3506                                                         // This case we don't need to set any index
3507                                                 }
3508                                         }
3509                                         else if((cur_cck_pwdb < tmp_cck_sec_pwdb) && (cur_cck_pwdb > tmp_cck_min_pwdb))
3510                                         {
3511                                                 // This case we don't need to set any index
3512                                         }
3513                                         else if(cur_cck_pwdb == tmp_cck_min_pwdb)
3514                                         {
3515                                                 if(tmp_cck_sec_pwdb == tmp_cck_min_pwdb)
3516                                                 {       // let sec and min point to the different index
3517                                                         tmp_cck_min_pwdb = cur_cck_pwdb;
3518                                                         cck_rx_ver2_min_index = i;
3519                                                 }
3520                                                 else
3521                                                 {
3522                                                         // This case we don't need to set any index
3523                                                 }
3524                                         }
3525                                         else if(cur_cck_pwdb < tmp_cck_min_pwdb)
3526                                         {
3527                                                 tmp_cck_min_pwdb = cur_cck_pwdb;
3528                                                 cck_rx_ver2_min_index = i;
3529                                         }
3530                                 }
3531
3532                         }
3533                 }
3534         }
3535
3536
3537         // Set CCK Rx path
3538         // reg0xA07[3:2]=cck default rx path, reg0xa07[1:0]=cck optional rx path.
3539         update_cck_rx_path = 0;
3540         if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_2)
3541         {
3542                 cck_default_Rx = cck_rx_ver2_max_index;
3543                 cck_optional_Rx = cck_rx_ver2_sec_index;
3544                 if(tmp_cck_max_pwdb != -64)
3545                         update_cck_rx_path = 1;
3546         }
3547
3548         if(tmp_min_rssi < DM_RxPathSelTable.SS_TH_low && disabled_rf_cnt < 2)
3549         {
3550                 if((tmp_max_rssi - tmp_min_rssi) >= DM_RxPathSelTable.diff_TH)
3551                 {
3552                         //record the enabled rssi threshold
3553                         DM_RxPathSelTable.rf_enable_rssi_th[min_rssi_index] = tmp_max_rssi+5;
3554                         //disable the BB Rx path, OFDM
3555                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<min_rssi_index, 0x0);  // 0xc04[3:0]
3556                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<min_rssi_index, 0x0);  // 0xd04[3:0]
3557                         disabled_rf_cnt++;
3558                 }
3559                 if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_1)
3560                 {
3561                         cck_default_Rx = max_rssi_index;
3562                         cck_optional_Rx = sec_rssi_index;
3563                         if(tmp_max_rssi)
3564                                 update_cck_rx_path = 1;
3565                 }
3566         }
3567
3568         if(update_cck_rx_path)
3569         {
3570                 DM_RxPathSelTable.cck_Rx_path = (cck_default_Rx<<2)|(cck_optional_Rx);
3571                 rtl8192_setBBreg(dev, rCCK0_AFESetting, 0x0f000000, DM_RxPathSelTable.cck_Rx_path);
3572         }
3573
3574         if(DM_RxPathSelTable.disabledRF)
3575         {
3576                 for(i=0; i<4; i++)
3577                 {
3578                         if((DM_RxPathSelTable.disabledRF>>i) & 0x1)     //disabled rf
3579                         {
3580                                 if(tmp_max_rssi >= DM_RxPathSelTable.rf_enable_rssi_th[i])
3581                                 {
3582                                         //enable the BB Rx path
3583                                         //DbgPrint("RF-%d is enabled. \n", 0x1<<i);
3584                                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<i, 0x1);       // 0xc04[3:0]
3585                                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<i, 0x1);       // 0xd04[3:0]
3586                                         DM_RxPathSelTable.rf_enable_rssi_th[i] = 100;
3587                                         disabled_rf_cnt--;
3588                                 }
3589                         }
3590                 }
3591         }
3592 }
3593
3594 /*-----------------------------------------------------------------------------
3595  * Function:    dm_check_rx_path_selection()
3596  *
3597  * Overview:    Call a workitem to check current RXRF path and Rx Path selection by RSSI.
3598  *
3599  * Input:               NONE
3600  *
3601  * Output:              NONE
3602  *
3603  * Return:              NONE
3604  *
3605  * Revised History:
3606  *      When            Who             Remark
3607  *      05/28/2008      amy             Create Version 0 porting from windows code.
3608  *
3609  *---------------------------------------------------------------------------*/
3610 static  void    dm_check_rx_path_selection(struct net_device *dev)
3611 {
3612         struct r8192_priv *priv = ieee80211_priv(dev);
3613 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
3614         queue_delayed_work(priv->priv_wq,&priv->rfpath_check_wq,0);
3615 #else
3616 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
3617         schedule_task(&priv->rfpath_check_wq);
3618 #else
3619         queue_work(priv->priv_wq,&priv->rfpath_check_wq);
3620 #endif
3621 #endif
3622 }       /* dm_CheckRxRFPath */
3623
3624
3625 static void dm_init_fsync (struct net_device *dev)
3626 {
3627         struct r8192_priv *priv = ieee80211_priv(dev);
3628
3629         priv->ieee80211->fsync_time_interval = 500;
3630         priv->ieee80211->fsync_rate_bitmap = 0x0f000800;
3631         priv->ieee80211->fsync_rssi_threshold = 30;
3632 #ifdef RTL8190P
3633         priv->ieee80211->bfsync_enable = true;
3634 #else
3635         priv->ieee80211->bfsync_enable = false;
3636 #endif
3637         priv->ieee80211->fsync_multiple_timeinterval = 3;
3638         priv->ieee80211->fsync_firstdiff_ratethreshold= 100;
3639         priv->ieee80211->fsync_seconddiff_ratethreshold= 200;
3640         priv->ieee80211->fsync_state = Default_Fsync;
3641         priv->framesyncMonitor = 1;     // current default 0xc38 monitor on
3642
3643         init_timer(&priv->fsync_timer);
3644         priv->fsync_timer.data = (unsigned long)dev;
3645         priv->fsync_timer.function = dm_fsync_timer_callback;
3646 }
3647
3648
3649 static void dm_deInit_fsync(struct net_device *dev)
3650 {
3651         struct r8192_priv *priv = ieee80211_priv(dev);
3652         del_timer_sync(&priv->fsync_timer);
3653 }
3654
3655 void dm_fsync_timer_callback(unsigned long data)
3656 {
3657         struct net_device *dev = (struct net_device *)data;
3658         struct r8192_priv *priv = ieee80211_priv((struct net_device *)data);
3659         u32 rate_index, rate_count = 0, rate_count_diff=0;
3660         bool            bSwitchFromCountDiff = false;
3661         bool            bDoubleTimeInterval = false;
3662
3663         if(     priv->ieee80211->state == IEEE80211_LINKED &&
3664                 priv->ieee80211->bfsync_enable &&
3665                 (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC))
3666         {
3667                  // Count rate 54, MCS [7], [12, 13, 14, 15]
3668                 u32 rate_bitmap;
3669                 for(rate_index = 0; rate_index <= 27; rate_index++)
3670                 {
3671                         rate_bitmap  = 1 << rate_index;
3672                         if(priv->ieee80211->fsync_rate_bitmap &  rate_bitmap)
3673                                 rate_count+= priv->stats.received_rate_histogram[1][rate_index];
3674                 }
3675
3676                 if(rate_count < priv->rate_record)
3677                         rate_count_diff = 0xffffffff - rate_count + priv->rate_record;
3678                 else
3679                         rate_count_diff = rate_count - priv->rate_record;
3680                 if(rate_count_diff < priv->rateCountDiffRecord)
3681                 {
3682
3683                         u32 DiffNum = priv->rateCountDiffRecord - rate_count_diff;
3684                         // Contiune count
3685                         if(DiffNum >= priv->ieee80211->fsync_seconddiff_ratethreshold)
3686                                 priv->ContiuneDiffCount++;
3687                         else
3688                                 priv->ContiuneDiffCount = 0;
3689
3690                         // Contiune count over
3691                         if(priv->ContiuneDiffCount >=2)
3692                         {
3693                                 bSwitchFromCountDiff = true;
3694                                 priv->ContiuneDiffCount = 0;
3695                         }
3696                 }
3697                 else
3698                 {
3699                         // Stop contiune count
3700                         priv->ContiuneDiffCount = 0;
3701                 }
3702
3703                 //If Count diff <= FsyncRateCountThreshold
3704                 if(rate_count_diff <= priv->ieee80211->fsync_firstdiff_ratethreshold)
3705                 {
3706                         bSwitchFromCountDiff = true;
3707                         priv->ContiuneDiffCount = 0;
3708                 }
3709                 priv->rate_record = rate_count;
3710                 priv->rateCountDiffRecord = rate_count_diff;
3711                 RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff , priv->bswitch_fsync);
3712                 // if we never receive those mcs rate and rssi > 30 % then switch fsyn
3713                 if(priv->undecorated_smoothed_pwdb > priv->ieee80211->fsync_rssi_threshold && bSwitchFromCountDiff)
3714                 {
3715                         bDoubleTimeInterval = true;
3716                         priv->bswitch_fsync = !priv->bswitch_fsync;
3717                         if(priv->bswitch_fsync)
3718                         {
3719                         #ifdef RTL8190P
3720                                 write_nic_byte(dev,0xC36, 0x00);
3721                         #else
3722                                 write_nic_byte(dev,0xC36, 0x1c);
3723                         #endif
3724                                 write_nic_byte(dev, 0xC3e, 0x90);
3725                         }
3726                         else
3727                         {
3728                         #ifdef RTL8190P
3729                                 write_nic_byte(dev, 0xC36, 0x40);
3730                         #else
3731                                 write_nic_byte(dev, 0xC36, 0x5c);
3732                         #endif
3733                                 write_nic_byte(dev, 0xC3e, 0x96);
3734                         }
3735                 }
3736                 else if(priv->undecorated_smoothed_pwdb <= priv->ieee80211->fsync_rssi_threshold)
3737                 {
3738                         if(priv->bswitch_fsync)
3739                         {
3740                                 priv->bswitch_fsync  = false;
3741                         #ifdef RTL8190P
3742                                 write_nic_byte(dev, 0xC36, 0x40);
3743                         #else
3744                                 write_nic_byte(dev, 0xC36, 0x5c);
3745                         #endif
3746                                 write_nic_byte(dev, 0xC3e, 0x96);
3747                         }
3748                 }
3749                 if(bDoubleTimeInterval){
3750                         if(timer_pending(&priv->fsync_timer))
3751                                 del_timer_sync(&priv->fsync_timer);
3752                         priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval*priv->ieee80211->fsync_multiple_timeinterval);
3753                         add_timer(&priv->fsync_timer);
3754                 }
3755                 else{
3756                         if(timer_pending(&priv->fsync_timer))
3757                                 del_timer_sync(&priv->fsync_timer);
3758                         priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval);
3759                         add_timer(&priv->fsync_timer);
3760                 }
3761         }
3762         else
3763         {
3764                 // Let Register return to default value;
3765                 if(priv->bswitch_fsync)
3766                 {
3767                         priv->bswitch_fsync  = false;
3768                 #ifdef RTL8190P
3769                         write_nic_byte(dev, 0xC36, 0x40);
3770                 #else
3771                         write_nic_byte(dev, 0xC36, 0x5c);
3772                 #endif
3773                         write_nic_byte(dev, 0xC3e, 0x96);
3774                 }
3775                 priv->ContiuneDiffCount = 0;
3776         #ifdef RTL8190P
3777                 write_nic_dword(dev, rOFDM0_RxDetector2, 0x164052cd);
3778         #else
3779                 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
3780         #endif
3781         }
3782         RT_TRACE(COMP_HALDM, "ContiuneDiffCount %d\n", priv->ContiuneDiffCount);
3783         RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff , priv->bswitch_fsync);
3784 }
3785
3786 static void dm_StartHWFsync(struct net_device *dev)
3787 {
3788         RT_TRACE(COMP_HALDM, "%s\n", __FUNCTION__);
3789         write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cf);
3790         write_nic_byte(dev, 0xc3b, 0x41);
3791 }
3792
3793 static void dm_EndSWFsync(struct net_device *dev)
3794 {
3795         struct r8192_priv *priv = ieee80211_priv(dev);
3796
3797         RT_TRACE(COMP_HALDM, "%s\n", __FUNCTION__);
3798         del_timer_sync(&(priv->fsync_timer));
3799
3800         // Let Register return to default value;
3801         if(priv->bswitch_fsync)
3802         {
3803                 priv->bswitch_fsync  = false;
3804
3805                 #ifdef RTL8190P
3806                         write_nic_byte(dev, 0xC36, 0x40);
3807                 #else
3808                 write_nic_byte(dev, 0xC36, 0x5c);
3809 #endif
3810
3811                 write_nic_byte(dev, 0xC3e, 0x96);
3812         }
3813
3814         priv->ContiuneDiffCount = 0;
3815 #ifndef RTL8190P
3816         write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
3817 #endif
3818
3819 }
3820
3821 static void dm_StartSWFsync(struct net_device *dev)
3822 {
3823         struct r8192_priv *priv = ieee80211_priv(dev);
3824         u32                     rateIndex;
3825         u32                     rateBitmap;
3826
3827         RT_TRACE(COMP_HALDM,"%s\n", __FUNCTION__);
3828         // Initial rate record to zero, start to record.
3829         priv->rate_record = 0;
3830         // Initial contiune diff count to zero, start to record.
3831         priv->ContiuneDiffCount = 0;
3832         priv->rateCountDiffRecord = 0;
3833         priv->bswitch_fsync  = false;
3834
3835         if(priv->ieee80211->mode == WIRELESS_MODE_N_24G)
3836         {
3837                 priv->ieee80211->fsync_firstdiff_ratethreshold= 600;
3838                 priv->ieee80211->fsync_seconddiff_ratethreshold = 0xffff;
3839         }
3840         else
3841         {
3842                 priv->ieee80211->fsync_firstdiff_ratethreshold= 200;
3843                 priv->ieee80211->fsync_seconddiff_ratethreshold = 200;
3844         }
3845         for(rateIndex = 0; rateIndex <= 27; rateIndex++)
3846         {
3847                 rateBitmap  = 1 << rateIndex;
3848                 if(priv->ieee80211->fsync_rate_bitmap &  rateBitmap)
3849                         priv->rate_record += priv->stats.received_rate_histogram[1][rateIndex];
3850         }
3851         if(timer_pending(&priv->fsync_timer))
3852                 del_timer_sync(&priv->fsync_timer);
3853         priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval);
3854         add_timer(&priv->fsync_timer);
3855
3856 #ifndef RTL8190P
3857         write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cd);
3858 #endif
3859
3860 }
3861
3862 static void dm_EndHWFsync(struct net_device *dev)
3863 {
3864         RT_TRACE(COMP_HALDM,"%s\n", __FUNCTION__);
3865         write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
3866         write_nic_byte(dev, 0xc3b, 0x49);
3867
3868 }
3869
3870 void dm_check_fsync(struct net_device *dev)
3871 {
3872 #define RegC38_Default                          0
3873 #define RegC38_NonFsync_Other_AP        1
3874 #define RegC38_Fsync_AP_BCM             2
3875         struct r8192_priv *priv = ieee80211_priv(dev);
3876         //u32                   framesyncC34;
3877         static u8               reg_c38_State=RegC38_Default;
3878         static u32      reset_cnt=0;
3879
3880         RT_TRACE(COMP_HALDM, "RSSI %d TimeInterval %d MultipleTimeInterval %d\n", priv->ieee80211->fsync_rssi_threshold, priv->ieee80211->fsync_time_interval, priv->ieee80211->fsync_multiple_timeinterval);
3881         RT_TRACE(COMP_HALDM, "RateBitmap 0x%x FirstDiffRateThreshold %d SecondDiffRateThreshold %d\n", priv->ieee80211->fsync_rate_bitmap, priv->ieee80211->fsync_firstdiff_ratethreshold, priv->ieee80211->fsync_seconddiff_ratethreshold);
3882
3883         if(     priv->ieee80211->state == IEEE80211_LINKED &&
3884                 (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC))
3885         {
3886                 if(priv->ieee80211->bfsync_enable == 0)
3887                 {
3888                         switch(priv->ieee80211->fsync_state)
3889                         {
3890                                 case Default_Fsync:
3891                                         dm_StartHWFsync(dev);
3892                                         priv->ieee80211->fsync_state = HW_Fsync;
3893                                         break;
3894                                 case SW_Fsync:
3895                                         dm_EndSWFsync(dev);
3896                                         dm_StartHWFsync(dev);
3897                                         priv->ieee80211->fsync_state = HW_Fsync;
3898                                         break;
3899                                 case HW_Fsync:
3900                                 default:
3901                                         break;
3902                         }
3903                 }
3904                 else
3905                 {
3906                         switch(priv->ieee80211->fsync_state)
3907                         {
3908                                 case Default_Fsync:
3909                                         dm_StartSWFsync(dev);
3910                                         priv->ieee80211->fsync_state = SW_Fsync;
3911                                         break;
3912                                 case HW_Fsync:
3913                                         dm_EndHWFsync(dev);
3914                                         dm_StartSWFsync(dev);
3915                                         priv->ieee80211->fsync_state = SW_Fsync;
3916                                         break;
3917                                 case SW_Fsync:
3918                                 default:
3919                                         break;
3920
3921                         }
3922                 }
3923                 if(priv->framesyncMonitor)
3924                 {
3925                         if(reg_c38_State != RegC38_Fsync_AP_BCM)
3926                         {       //For broadcom AP we write different default value
3927                                 #ifdef RTL8190P
3928                                         write_nic_byte(dev, rOFDM0_RxDetector3, 0x15);
3929                                 #else
3930                                         write_nic_byte(dev, rOFDM0_RxDetector3, 0x95);
3931                                 #endif
3932
3933                                 reg_c38_State = RegC38_Fsync_AP_BCM;
3934                         }
3935                 }
3936         }
3937         else
3938         {
3939                 switch(priv->ieee80211->fsync_state)
3940                 {
3941                         case HW_Fsync:
3942                                 dm_EndHWFsync(dev);
3943                                 priv->ieee80211->fsync_state = Default_Fsync;
3944                                 break;
3945                         case SW_Fsync:
3946                                 dm_EndSWFsync(dev);
3947                                 priv->ieee80211->fsync_state = Default_Fsync;
3948                                 break;
3949                         case Default_Fsync:
3950                         default:
3951                                 break;
3952                 }
3953
3954                 if(priv->framesyncMonitor)
3955                 {
3956                         if(priv->ieee80211->state == IEEE80211_LINKED)
3957                         {
3958                                 if(priv->undecorated_smoothed_pwdb <= RegC38_TH)
3959                                 {
3960                                         if(reg_c38_State != RegC38_NonFsync_Other_AP)
3961                                         {
3962                                                 #ifdef RTL8190P
3963                                                         write_nic_byte(dev, rOFDM0_RxDetector3, 0x10);
3964                                                 #else
3965                                                         write_nic_byte(dev, rOFDM0_RxDetector3, 0x90);
3966                                                 #endif
3967
3968                                                 reg_c38_State = RegC38_NonFsync_Other_AP;
3969                                         #if 0//cosa
3970                                                 if (Adapter->HardwareType == HARDWARE_TYPE_RTL8190P)
3971                                                         DbgPrint("Fsync is idle, rssi<=35, write 0xc38 = 0x%x \n", 0x10);
3972                                                 else
3973                                                         DbgPrint("Fsync is idle, rssi<=35, write 0xc38 = 0x%x \n", 0x90);
3974                                         #endif
3975                                         }
3976                                 }
3977                                 else if(priv->undecorated_smoothed_pwdb >= (RegC38_TH+5))
3978                                 {
3979                                         if(reg_c38_State)
3980                                         {
3981                                                 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
3982                                                 reg_c38_State = RegC38_Default;
3983                                                 //DbgPrint("Fsync is idle, rssi>=40, write 0xc38 = 0x%x \n", pHalData->framesync);
3984                                         }
3985                                 }
3986                         }
3987                         else
3988                         {
3989                                 if(reg_c38_State)
3990                                 {
3991                                         write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
3992                                         reg_c38_State = RegC38_Default;
3993                                         //DbgPrint("Fsync is idle, not connected, write 0xc38 = 0x%x \n", pHalData->framesync);
3994                                 }
3995                         }
3996                 }
3997         }
3998         if(priv->framesyncMonitor)
3999         {
4000                 if(priv->reset_count != reset_cnt)
4001                 {       //After silent reset, the reg_c38_State will be returned to default value
4002                         write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
4003                         reg_c38_State = RegC38_Default;
4004                         reset_cnt = priv->reset_count;
4005                         //DbgPrint("reg_c38_State = 0 for silent reset. \n");
4006                 }
4007         }
4008         else
4009         {
4010                 if(reg_c38_State)
4011                 {
4012                         write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
4013                         reg_c38_State = RegC38_Default;
4014                         //DbgPrint("framesync no monitor, write 0xc38 = 0x%x \n", pHalData->framesync);
4015                 }
4016         }
4017 }
4018
4019 #if 0
4020 /*-----------------------------------------------------------------------------
4021  * Function:    DM_CheckLBusStatus()
4022  *
4023  * Overview:    For 9x series, we must make sure LBUS is active for IO.
4024  *
4025  * Input:               NONE
4026  *
4027  * Output:              NONE
4028  *
4029  * Return:              NONE
4030  *
4031  * Revised History:
4032  *      When            Who             Remark
4033  *      02/22/2008      MHC             Create Version 0.
4034  *
4035  *---------------------------------------------------------------------------*/
4036 extern  s1Byte  DM_CheckLBusStatus(IN   PADAPTER        Adapter)
4037 {
4038         PMGNT_INFO      pMgntInfo=&Adapter->MgntInfo;
4039
4040 #if (HAL_CODE_BASE & RTL819X)
4041
4042 #if (HAL_CODE_BASE == RTL8192)
4043
4044 #if( DEV_BUS_TYPE==PCI_INTERFACE)
4045         //return (pMgntInfo->bLbusEnable);      // For debug only
4046         return TRUE;
4047 #endif
4048
4049 #if( DEV_BUS_TYPE==USB_INTERFACE)
4050         return TRUE;
4051 #endif
4052
4053 #endif  // #if (HAL_CODE_BASE == RTL8192)
4054
4055 #if (HAL_CODE_BASE == RTL8190)
4056         return TRUE;
4057 #endif  // #if (HAL_CODE_BASE == RTL8190)
4058
4059 #endif  // #if (HAL_CODE_BASE & RTL819X)
4060 }       /* DM_CheckLBusStatus */
4061
4062 #endif
4063
4064 /*-----------------------------------------------------------------------------
4065  * Function:    dm_shadow_init()
4066  *
4067  * Overview:    Store all NIC MAC/BB register content.
4068  *
4069  * Input:               NONE
4070  *
4071  * Output:              NONE
4072  *
4073  * Return:              NONE
4074  *
4075  * Revised History:
4076  *      When            Who             Remark
4077  *      05/29/2008      amy             Create Version 0 porting from windows code.
4078  *
4079  *---------------------------------------------------------------------------*/
4080 void dm_shadow_init(struct net_device *dev)
4081 {
4082         u8      page;
4083         u16     offset;
4084
4085         for (page = 0; page < 5; page++)
4086                 for (offset = 0; offset < 256; offset++)
4087                 {
4088                         dm_shadow[page][offset] = read_nic_byte(dev, offset+page*256);
4089                         //DbgPrint("P-%d/O-%02x=%02x\r\n", page, offset, DM_Shadow[page][offset]);
4090                 }
4091
4092         for (page = 8; page < 11; page++)
4093                 for (offset = 0; offset < 256; offset++)
4094                         dm_shadow[page][offset] = read_nic_byte(dev, offset+page*256);
4095
4096         for (page = 12; page < 15; page++)
4097                 for (offset = 0; offset < 256; offset++)
4098                         dm_shadow[page][offset] = read_nic_byte(dev, offset+page*256);
4099
4100 }   /* dm_shadow_init */
4101
4102 /*---------------------------Define function prototype------------------------*/
4103 /*-----------------------------------------------------------------------------
4104  * Function:    DM_DynamicTxPower()
4105  *
4106  * Overview:    Detect Signal strength to control TX Registry
4107                         Tx Power Control For Near/Far Range
4108  *
4109  * Input:               NONE
4110  *
4111  * Output:              NONE
4112  *
4113  * Return:              NONE
4114  *
4115  * Revised History:
4116  *      When            Who             Remark
4117  *      03/06/2008      Jacken  Create Version 0.
4118  *
4119  *---------------------------------------------------------------------------*/
4120 static void dm_init_dynamic_txpower(struct net_device *dev)
4121 {
4122         struct r8192_priv *priv = ieee80211_priv(dev);
4123
4124         //Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code.
4125         priv->ieee80211->bdynamic_txpower_enable = true;    //Default to enable Tx Power Control
4126         priv->bLastDTPFlag_High = false;
4127         priv->bLastDTPFlag_Low = false;
4128         priv->bDynamicTxHighPower = false;
4129         priv->bDynamicTxLowPower = false;
4130 }
4131
4132 static void dm_dynamic_txpower(struct net_device *dev)
4133 {
4134         struct r8192_priv *priv = ieee80211_priv(dev);
4135         unsigned int txhipower_threshhold=0;
4136         unsigned int txlowpower_threshold=0;
4137         if(priv->ieee80211->bdynamic_txpower_enable != true)
4138         {
4139                 priv->bDynamicTxHighPower = false;
4140                 priv->bDynamicTxLowPower = false;
4141                 return;
4142         }
4143         //printk("priv->ieee80211->current_network.unknown_cap_exist is %d ,priv->ieee80211->current_network.broadcom_cap_exist is %d\n",priv->ieee80211->current_network.unknown_cap_exist,priv->ieee80211->current_network.broadcom_cap_exist);
4144         if((priv->ieee80211->current_network.atheros_cap_exist ) && (priv->ieee80211->mode == IEEE_G)){
4145                 txhipower_threshhold = TX_POWER_ATHEROAP_THRESH_HIGH;
4146                 txlowpower_threshold = TX_POWER_ATHEROAP_THRESH_LOW;
4147         }
4148         else
4149         {
4150                 txhipower_threshhold = TX_POWER_NEAR_FIELD_THRESH_HIGH;
4151                 txlowpower_threshold = TX_POWER_NEAR_FIELD_THRESH_LOW;
4152         }
4153
4154 //      printk("=======>%s(): txhipower_threshhold is %d,txlowpower_threshold is %d\n",__FUNCTION__,txhipower_threshhold,txlowpower_threshold);
4155
4156         RT_TRACE(COMP_TXAGC,"priv->undecorated_smoothed_pwdb = %ld \n" , priv->undecorated_smoothed_pwdb);
4157
4158         if(priv->ieee80211->state == IEEE80211_LINKED)
4159         {
4160                 if(priv->undecorated_smoothed_pwdb >= txhipower_threshhold)
4161                 {
4162                         priv->bDynamicTxHighPower = true;
4163                         priv->bDynamicTxLowPower = false;
4164                 }
4165                 else
4166                 {
4167                         // high power state check
4168                         if(priv->undecorated_smoothed_pwdb < txlowpower_threshold && priv->bDynamicTxHighPower == true)
4169                         {
4170                                 priv->bDynamicTxHighPower = false;
4171                         }
4172                         // low power state check
4173                         if(priv->undecorated_smoothed_pwdb < 35)
4174                         {
4175                                 priv->bDynamicTxLowPower = true;
4176                         }
4177                         else if(priv->undecorated_smoothed_pwdb >= 40)
4178                         {
4179                                 priv->bDynamicTxLowPower = false;
4180                         }
4181                 }
4182         }
4183         else
4184         {
4185                 //pHalData->bTXPowerCtrlforNearFarRange = !pHalData->bTXPowerCtrlforNearFarRange;
4186                 priv->bDynamicTxHighPower = false;
4187                 priv->bDynamicTxLowPower = false;
4188         }
4189
4190         if( (priv->bDynamicTxHighPower != priv->bLastDTPFlag_High ) ||
4191                 (priv->bDynamicTxLowPower != priv->bLastDTPFlag_Low ) )
4192         {
4193                 RT_TRACE(COMP_TXAGC,"SetTxPowerLevel8190()  channel = %d \n" , priv->ieee80211->current_network.channel);
4194
4195
4196                 rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel);
4197
4198         }
4199         priv->bLastDTPFlag_High = priv->bDynamicTxHighPower;
4200         priv->bLastDTPFlag_Low = priv->bDynamicTxLowPower;
4201
4202 }       /* dm_dynamic_txpower */
4203
4204 //added by vivi, for read tx rate and retrycount
4205 static void dm_check_txrateandretrycount(struct net_device * dev)
4206 {
4207         struct r8192_priv *priv = ieee80211_priv(dev);
4208         struct ieee80211_device* ieee = priv->ieee80211;
4209         //for 11n tx rate
4210 //      priv->stats.CurrentShowTxate = read_nic_byte(dev, Current_Tx_Rate_Reg);
4211         ieee->softmac_stats.CurrentShowTxate = read_nic_byte(dev, Current_Tx_Rate_Reg);
4212         //printk("=============>tx_rate_reg:%x\n", ieee->softmac_stats.CurrentShowTxate);
4213         //for initial tx rate
4214 //      priv->stats.last_packet_rate = read_nic_byte(dev, Initial_Tx_Rate_Reg);
4215         ieee->softmac_stats.last_packet_rate = read_nic_byte(dev ,Initial_Tx_Rate_Reg);
4216         //for tx tx retry count
4217 //      priv->stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg);
4218         ieee->softmac_stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg);
4219 }
4220
4221 static void dm_send_rssi_tofw(struct net_device *dev)
4222 {
4223         DCMD_TXCMD_T                    tx_cmd;
4224         struct r8192_priv *priv = ieee80211_priv(dev);
4225
4226         // If we test chariot, we should stop the TX command ?
4227         // Because 92E will always silent reset when we send tx command. We use register
4228         // 0x1e0(byte) to botify driver.
4229         write_nic_byte(dev, DRIVER_RSSI, (u8)priv->undecorated_smoothed_pwdb);
4230         return;
4231 #if 1
4232         tx_cmd.Op               = TXCMD_SET_RX_RSSI;
4233         tx_cmd.Length   = 4;
4234         tx_cmd.Value            = priv->undecorated_smoothed_pwdb;
4235
4236         cmpk_message_handle_tx(dev, (u8*)&tx_cmd,
4237                                                                 DESC_PACKET_TYPE_INIT, sizeof(DCMD_TXCMD_T));
4238 #endif
4239 }
4240
4241 /*---------------------------Define function prototype------------------------*/
4242