SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/staging/meilhaus/me6000_ao_reg.h

   1 /**
   2  * @file me6000_ao_reg.h
   3  *
   4  * @brief ME-6000 analog output subdevice register definitions.
   5  * @note Copyright (C) 2007 Meilhaus Electronic GmbH (support@meilhaus.de)
   6  * @author Guenter Gebhardt
   7  */
   8
   9 /*
  10  * Copyright (C) 2007 Meilhaus Electronic GmbH (support@meilhaus.de)
  11  *
  12  * This file is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  */
  26
  27 #ifndef _ME6000_AO_REG_H_
  28 #define _ME6000_AO_REG_H_
  29
  30 #ifdef __KERNEL__
  31
  32 // AO
  33 #define ME6000_AO_00_CTRL_REG                                   0x00    // R/W
  34 #define ME6000_AO_00_STATUS_REG                                 0x04    // R/_
  35 #define ME6000_AO_00_FIFO_REG                                   0x08    // _/W
  36 #define ME6000_AO_00_SINGLE_REG                                 0x0C    // R/W
  37 #define ME6000_AO_00_TIMER_REG                                  0x10    // _/W
  38
  39 #define ME6000_AO_01_CTRL_REG                                   0x18    // R/W
  40 #define ME6000_AO_01_STATUS_REG                                 0x1C    // R/_
  41 #define ME6000_AO_01_FIFO_REG                                   0x20    // _/W
  42 #define ME6000_AO_01_SINGLE_REG                                 0x24    // R/W
  43 #define ME6000_AO_01_TIMER_REG                                  0x28    // _/W
  44
  45 #define ME6000_AO_02_CTRL_REG                                   0x30    // R/W
  46 #define ME6000_AO_02_STATUS_REG                                 0x34    // R/_
  47 #define ME6000_AO_02_FIFO_REG                                   0x38    // _/W
  48 #define ME6000_AO_02_SINGLE_REG                                 0x3C    // R/W
  49 #define ME6000_AO_02_TIMER_REG                                  0x40    // _/W
  50
  51 #define ME6000_AO_03_CTRL_REG                                   0x48    // R/W
  52 #define ME6000_AO_03_STATUS_REG                                 0x4C    // R/_
  53 #define ME6000_AO_03_FIFO_REG                                   0x50    // _/W
  54 #define ME6000_AO_03_SINGLE_REG                                 0x54    // R/W
  55 #define ME6000_AO_03_TIMER_REG                                  0x58    // _/W
  56
  57 #define ME6000_AO_SINGLE_STATUS_REG                             0xA4    // R/_
  58 #define ME6000_AO_SINGLE_STATUS_OFFSET                  4       //The first single subdevice => bit 0 in ME6000_AO_SINGLE_STATUS_REG.
  59
  60 #define ME6000_AO_04_STATUS_REG                                 ME6000_AO_SINGLE_STATUS_REG
  61 #define ME6000_AO_04_SINGLE_REG                                 0x74    // _/W
  62
  63 #define ME6000_AO_05_STATUS_REG                                 ME6000_AO_SINGLE_STATUS_REG
  64 #define ME6000_AO_05_SINGLE_REG                                 0x78    // _/W
  65
  66 #define ME6000_AO_06_STATUS_REG                                 ME6000_AO_SINGLE_STATUS_REG
  67 #define ME6000_AO_06_SINGLE_REG                                 0x7C    // _/W
  68
  69 #define ME6000_AO_07_STATUS_REG                                 ME6000_AO_SINGLE_STATUS_REG
  70 #define ME6000_AO_07_SINGLE_REG                                 0x80    // _/W
  71
  72 #define ME6000_AO_08_STATUS_REG                                 ME6000_AO_SINGLE_STATUS_REG
  73 #define ME6000_AO_08_SINGLE_REG                                 0x84    // _/W
  74
  75 #define ME6000_AO_09_STATUS_REG                                 ME6000_AO_SINGLE_STATUS_REG
  76 #define ME6000_AO_09_SINGLE_REG                                 0x88    // _/W
  77
  78 #define ME6000_AO_10_STATUS_REG                                 ME6000_AO_SINGLE_STATUS_REG
  79 #define ME6000_AO_10_SINGLE_REG                                 0x8C    // _/W
  80
  81 #define ME6000_AO_11_STATUS_REG                                 ME6000_AO_SINGLE_STATUS_REG
  82 #define ME6000_AO_11_SINGLE_REG                                 0x90    // _/W
  83
  84 #define ME6000_AO_12_STATUS_REG                                 ME6000_AO_SINGLE_STATUS_REG
  85 #define ME6000_AO_12_SINGLE_REG                                 0x94    // _/W
  86
  87 #define ME6000_AO_13_STATUS_REG                                 ME6000_AO_SINGLE_STATUS_REG
  88 #define ME6000_AO_13_SINGLE_REG                                 0x98    // _/W
  89
  90 #define ME6000_AO_14_STATUS_REG                                 ME6000_AO_SINGLE_STATUS_REG
  91 #define ME6000_AO_14_SINGLE_REG                                 0x9C    // _/W
  92
  93 #define ME6000_AO_15_STATUS_REG                                 ME6000_AO_SINGLE_STATUS_REG
  94 #define ME6000_AO_15_SINGLE_REG                                 0xA0    // _/W
  95
  96 //ME6000_AO_CTRL_REG
  97 #define ME6000_AO_MODE_SINGLE                                   0x00
  98 #define ME6000_AO_MODE_WRAPAROUND                               0x01
  99 #define ME6000_AO_MODE_CONTINUOUS                               0x02
 100 #define ME6000_AO_CTRL_MODE_MASK                                (ME6000_AO_MODE_WRAPAROUND | ME6000_AO_MODE_CONTINUOUS)
 101
 102 #define ME6000_AO_CTRL_BIT_MODE_WRAPAROUND              0x001
 103 #define ME6000_AO_CTRL_BIT_MODE_CONTINUOUS              0x002
 104 #define ME6000_AO_CTRL_BIT_STOP                                 0x004
 105 #define ME6000_AO_CTRL_BIT_ENABLE_FIFO                  0x008
 106 #define ME6000_AO_CTRL_BIT_ENABLE_EX_TRIG               0x010
 107 #define ME6000_AO_CTRL_BIT_EX_TRIG_EDGE                 0x020
 108 #define ME6000_AO_CTRL_BIT_ENABLE_IRQ                   0x040
 109 #define ME6000_AO_CTRL_BIT_IMMEDIATE_STOP               0x080
 110 #define ME6000_AO_CTRL_BIT_EX_TRIG_EDGE_BOTH    0x800
 111
 112 //ME6000_AO_STATUS_REG
 113 #define ME6000_AO_STATUS_BIT_FSM                                0x01
 114 #define ME6000_AO_STATUS_BIT_FF                                 0x02
 115 #define ME6000_AO_STATUS_BIT_HF                                 0x04
 116 #define ME6000_AO_STATUS_BIT_EF                                 0x08
 117
 118 #define ME6000_AO_PRELOAD_REG                                   0xA8    // R/W    ///ME6000_AO_SYNC_REG <==> ME6000_AO_PRELOAD_REG
 119 /*
 120 #define ME6000_AO_SYNC_HOLD_0                                   0x00000001
 121 #define ME6000_AO_SYNC_HOLD_1                                   0x00000002
 122 #define ME6000_AO_SYNC_HOLD_2                                   0x00000004
 123 #define ME6000_AO_SYNC_HOLD_3                                   0x00000008
 124 #define ME6000_AO_SYNC_HOLD_4                                   0x00000010
 125 #define ME6000_AO_SYNC_HOLD_5                                   0x00000020
 126 #define ME6000_AO_SYNC_HOLD_6                                   0x00000040
 127 #define ME6000_AO_SYNC_HOLD_7                                   0x00000080
 128 #define ME6000_AO_SYNC_HOLD_8                                   0x00000100
 129 #define ME6000_AO_SYNC_HOLD_9                                   0x00000200
 130 #define ME6000_AO_SYNC_HOLD_10                                  0x00000400
 131 #define ME6000_AO_SYNC_HOLD_11                                  0x00000800
 132 #define ME6000_AO_SYNC_HOLD_12                                  0x00001000
 133 #define ME6000_AO_SYNC_HOLD_13                                  0x00002000
 134 #define ME6000_AO_SYNC_HOLD_14                                  0x00004000
 135 #define ME6000_AO_SYNC_HOLD_15                                  0x00008000
 136 */
 137 #define ME6000_AO_SYNC_HOLD                                             0x00000001
 138 /*
 139 #define ME6000_AO_SYNC_EXT_TRIG_0                               0x00010000
 140 #define ME6000_AO_SYNC_EXT_TRIG_1                               0x00020000
 141 #define ME6000_AO_SYNC_EXT_TRIG_2                               0x00040000
 142 #define ME6000_AO_SYNC_EXT_TRIG_3                               0x00080000
 143 #define ME6000_AO_SYNC_EXT_TRIG_4                               0x00100000
 144 #define ME6000_AO_SYNC_EXT_TRIG_5                               0x00200000
 145 #define ME6000_AO_SYNC_EXT_TRIG_6                               0x00400000
 146 #define ME6000_AO_SYNC_EXT_TRIG_7                               0x00800000
 147 #define ME6000_AO_SYNC_EXT_TRIG_8                               0x01000000
 148 #define ME6000_AO_SYNC_EXT_TRIG_9                               0x02000000
 149 #define ME6000_AO_SYNC_EXT_TRIG_10                              0x04000000
 150 #define ME6000_AO_SYNC_EXT_TRIG_11                              0x08000000
 151 #define ME6000_AO_SYNC_EXT_TRIG_12                              0x10000000
 152 #define ME6000_AO_SYNC_EXT_TRIG_13                              0x20000000
 153 #define ME6000_AO_SYNC_EXT_TRIG_14                              0x40000000
 154 #define ME6000_AO_SYNC_EXT_TRIG_15                              0x80000000
 155 */
 156 #define ME6000_AO_SYNC_EXT_TRIG                                 0x00010000
 157
 158 #define ME6000_AO_EXT_TRIG                                              0x80000000
 159
 160 // AO-IRQ
 161 #define ME6000_AO_IRQ_STATUS_REG                                0x60    // R/_
 162 #define ME6000_AO_00_IRQ_RESET_REG                              0x64    // R/_
 163 #define ME6000_AO_01_IRQ_RESET_REG                              0x68    // R/_
 164 #define ME6000_AO_02_IRQ_RESET_REG                              0x6C    // R/_
 165 #define ME6000_AO_03_IRQ_RESET_REG                              0x70    // R/_
 166
 167 #define ME6000_IRQ_STATUS_BIT_0                                 0x01
 168 #define ME6000_IRQ_STATUS_BIT_1                                 0x02
 169 #define ME6000_IRQ_STATUS_BIT_2                                 0x04
 170 #define ME6000_IRQ_STATUS_BIT_3                                 0x08
 171
 172 #define ME6000_IRQ_STATUS_BIT_AO_HF                             ME6000_IRQ_STATUS_BIT_0
 173
 174 //DUMY register
 175 #define ME6000_AO_DUMY                                                                  0xFC
 176 #endif
 177 #endif