3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et131x_isr.c - File which contains the ISR, ISR handler, and related routines
12 * for processing interrupts from the device.
14 *------------------------------------------------------------------------------
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19 * which you should read carefully before using the software. Using this
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24 * All rights reserved.
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59 #include "et131x_version.h"
60 #include "et131x_debug.h"
61 #include "et131x_defs.h"
63 #include <linux/init.h>
64 #include <linux/module.h>
65 #include <linux/types.h>
66 #include <linux/kernel.h>
68 #include <linux/sched.h>
69 #include <linux/ptrace.h>
70 #include <linux/slab.h>
71 #include <linux/ctype.h>
72 #include <linux/string.h>
73 #include <linux/timer.h>
74 #include <linux/interrupt.h>
76 #include <linux/delay.h>
78 #include <linux/bitops.h>
79 #include <asm/system.h>
81 #include <linux/netdevice.h>
82 #include <linux/etherdevice.h>
83 #include <linux/skbuff.h>
84 #include <linux/if_arp.h>
85 #include <linux/ioport.h>
87 #include "et1310_phy.h"
88 #include "et1310_pm.h"
89 #include "et1310_jagcore.h"
90 #include "et1310_mac.h"
92 #include "et131x_adapter.h"
94 /* Data for debugging facilities */
95 #ifdef CONFIG_ET131X_DEBUG
96 extern dbg_info_t *et131x_dbginfo;
97 #endif /* CONFIG_ET131X_DEBUG */
100 * et131x_isr - The Interrupt Service Routine for the driver.
101 * @irq: the IRQ on which the interrupt was received.
102 * @dev_id: device-specific info (here a pointer to a net_device struct)
104 * Returns a value indicating if the interrupt was handled.
106 irqreturn_t et131x_isr(int irq, void *dev_id)
109 struct net_device *netdev = (struct net_device *)dev_id;
110 struct et131x_adapter *adapter = NULL;
113 if (netdev == NULL || !netif_device_present(netdev)) {
114 DBG_WARNING(et131x_dbginfo,
115 "No net_device struct or device not present\n");
120 adapter = netdev_priv(netdev);
122 /* If the adapter is in low power state, then it should not
123 * recognize any interrupt
126 /* Disable Device Interrupts */
127 et131x_disable_interrupts(adapter);
129 /* Get a copy of the value in the interrupt status register
130 * so we can process the interrupting section
132 status.value = readl(&adapter->CSRAddress->global.int_status.value);
134 if (adapter->FlowControl == TxOnly ||
135 adapter->FlowControl == Both) {
136 status.value &= ~INT_MASK_ENABLE;
138 status.value &= ~INT_MASK_ENABLE_NO_FLOW;
141 /* Make sure this is our interrupt */
143 #ifdef CONFIG_ET131X_DEBUG
144 adapter->Stats.UnhandledInterruptsPerSec++;
147 DBG_VERBOSE(et131x_dbginfo, "NOT OUR INTERRUPT\n");
148 et131x_enable_interrupts(adapter);
152 /* This is our interrupt, so process accordingly */
153 #ifdef CONFIG_ET131X_DEBUG
154 if (status.bits.rxdma_xfr_done)
155 adapter->Stats.RxDmaInterruptsPerSec++;
157 if (status.bits.txdma_isr)
158 adapter->Stats.TxDmaInterruptsPerSec++;
161 if (status.bits.watchdog_interrupt) {
162 PMP_TCB pMpTcb = adapter->TxRing.CurrSendHead;
165 if (++pMpTcb->PacketStaleCount > 1)
166 status.bits.txdma_isr = 1;
168 if (adapter->RxRing.UnfinishedReceives)
169 status.bits.rxdma_xfr_done = 1;
170 else if (pMpTcb == NULL)
171 writel(0, &adapter->CSRAddress->global.watchdog_timer);
173 status.bits.watchdog_interrupt = 0;
174 #ifdef CONFIG_ET131X_DEBUG
175 adapter->Stats.WatchDogInterruptsPerSec++;
179 if (status.value == 0) {
180 /* This interrupt has in some way been "handled" by
181 * the ISR. Either it was a spurious Rx interrupt, or
182 * it was a Tx interrupt that has been filtered by
185 et131x_enable_interrupts(adapter);
189 /* We need to save the interrupt status value for use in our
190 * DPC. We will clear the software copy of that in that
193 adapter->Stats.InterruptStatus = status;
195 /* Schedule the ISR handler as a bottom-half task in the
196 * kernel's tq_immediate queue, and mark the queue for
199 schedule_work(&adapter->task);
202 return IRQ_RETVAL(handled);
206 * et131x_isr_handler - The ISR handler
207 * @p_adapter, a pointer to the device's private adapter structure
209 * scheduled to run in a deferred context by the ISR. This is where the ISR's
210 * work actually gets done.
212 void et131x_isr_handler(struct work_struct *work)
214 struct et131x_adapter *etdev =
215 container_of(work, struct et131x_adapter, task);
216 INTERRUPT_t GlobStatus = etdev->Stats.InterruptStatus;
217 ADDRESS_MAP_t __iomem *iomem = etdev->CSRAddress;
220 * These first two are by far the most common. Once handled, we clear
221 * their two bits in the status word. If the word is now zero, we
224 /* Handle all the completed Transmit interrupts */
225 if (GlobStatus.bits.txdma_isr) {
226 DBG_TX(et131x_dbginfo, "TXDMA_ISR interrupt\n");
227 et131x_handle_send_interrupt(etdev);
230 /* Handle all the completed Receives interrupts */
231 if (GlobStatus.bits.rxdma_xfr_done) {
232 DBG_RX(et131x_dbginfo, "RXDMA_XFR_DONE interrupt\n");
233 et131x_handle_recv_interrupt(etdev);
236 GlobStatus.value &= 0xffffffd7;
238 if (GlobStatus.value) {
239 /* Handle the TXDMA Error interrupt */
240 if (GlobStatus.bits.txdma_err) {
241 TXDMA_ERROR_t TxDmaErr;
243 /* Following read also clears the register (COR) */
244 TxDmaErr.value = readl(&iomem->txdma.TxDmaError.value);
246 DBG_WARNING(et131x_dbginfo,
247 "TXDMA_ERR interrupt, error = %d\n",
251 /* Handle Free Buffer Ring 0 and 1 Low interrupt */
252 if (GlobStatus.bits.rxdma_fb_ring0_low ||
253 GlobStatus.bits.rxdma_fb_ring1_low) {
255 * This indicates the number of unused buffers in
256 * RXDMA free buffer ring 0 is <= the limit you
257 * programmed. Free buffer resources need to be
258 * returned. Free buffers are consumed as packets
259 * are passed from the network to the host. The host
260 * becomes aware of the packets from the contents of
261 * the packet status ring. This ring is queried when
262 * the packet done interrupt occurs. Packets are then
263 * passed to the OS. When the OS is done with the
264 * packets the resources can be returned to the
265 * ET1310 for re-use. This interrupt is one method of
266 * returning resources.
268 DBG_WARNING(et131x_dbginfo,
269 "RXDMA_FB_RING0_LOW or "
270 "RXDMA_FB_RING1_LOW interrupt\n");
272 /* If the user has flow control on, then we will
273 * send a pause packet, otherwise just exit
275 if (etdev->FlowControl == TxOnly ||
276 etdev->FlowControl == Both) {
279 /* Tell the device to send a pause packet via
280 * the back pressure register
283 readl(&iomem->global.pm_csr.value);
284 if (pm_csr.bits.pm_phy_sw_coma == 0) {
285 TXMAC_BP_CTRL_t bp_ctrl = { 0 };
287 bp_ctrl.bits.bp_req = 1;
288 bp_ctrl.bits.bp_xonxoff = 1;
289 writel(bp_ctrl.value,
290 &iomem->txmac.bp_ctrl.value);
295 /* Handle Packet Status Ring Low Interrupt */
296 if (GlobStatus.bits.rxdma_pkt_stat_ring_low) {
297 DBG_WARNING(et131x_dbginfo,
298 "RXDMA_PKT_STAT_RING_LOW interrupt\n");
301 * Same idea as with the two Free Buffer Rings.
302 * Packets going from the network to the host each
303 * consume a free buffer resource and a packet status
304 * resource. These resoures are passed to the OS.
305 * When the OS is done with the resources, they need
306 * to be returned to the ET1310. This is one method
307 * of returning the resources.
311 /* Handle RXDMA Error Interrupt */
312 if (GlobStatus.bits.rxdma_err) {
314 * The rxdma_error interrupt is sent when a time-out
315 * on a request issued by the JAGCore has occurred or
316 * a completion is returned with an un-successful
317 * status. In both cases the request is considered
318 * complete. The JAGCore will automatically re-try the
319 * request in question. Normally information on events
320 * like these are sent to the host using the "Advanced
321 * Error Reporting" capability. This interrupt is
322 * another way of getting similar information. The
323 * only thing required is to clear the interrupt by
324 * reading the ISR in the global resources. The
325 * JAGCore will do a re-try on the request. Normally
326 * you should never see this interrupt. If you start
327 * to see this interrupt occurring frequently then
328 * something bad has occurred. A reset might be the
333 etdev->TxMacTest.value =
334 readl(&iomem->txmac.tx_test.value);
335 DBG_WARNING(et131x_dbginfo,
336 "RxDMA_ERR interrupt, error %x\n",
337 etdev->TxMacTest.value);
340 /* Handle the Wake on LAN Event */
341 if (GlobStatus.bits.wake_on_lan) {
343 * This is a secondary interrupt for wake on LAN.
344 * The driver should never see this, if it does,
345 * something serious is wrong. We will TRAP the
346 * message when we are in DBG mode, otherwise we
349 DBG_ERROR(et131x_dbginfo, "WAKE_ON_LAN interrupt\n");
352 /* Handle the PHY interrupt */
353 if (GlobStatus.bits.phy_interrupt) {
355 MI_BMSR_t BmsrInts, BmsrData;
358 DBG_VERBOSE(et131x_dbginfo, "PHY interrupt\n");
360 /* If we are in coma mode when we get this interrupt,
361 * we need to disable it.
363 pm_csr.value = readl(&iomem->global.pm_csr.value);
364 if (pm_csr.bits.pm_phy_sw_coma == 1) {
366 * Check to see if we are in coma mode and if
367 * so, disable it because we will not be able
368 * to read PHY values until we are out.
370 DBG_VERBOSE(et131x_dbginfo,
371 "Device is in COMA mode, "
372 "need to wake up\n");
373 DisablePhyComa(etdev);
376 /* Read the PHY ISR to clear the reason for the
379 MiRead(etdev, (uint8_t) offsetof(MI_REGS_t, isr),
382 if (!etdev->ReplicaPhyLoopbk) {
384 (uint8_t) offsetof(MI_REGS_t, bmsr),
388 etdev->Bmsr.value ^ BmsrData.value;
389 etdev->Bmsr.value = BmsrData.value;
391 DBG_VERBOSE(et131x_dbginfo,
392 "Bmsr.value = 0x%04x,"
393 "Bmsr_ints.value = 0x%04x\n",
394 BmsrData.value, BmsrInts.value);
396 /* Do all the cable in / cable out stuff */
397 et131x_Mii_check(etdev, BmsrData, BmsrInts);
401 /* Let's move on to the TxMac */
402 if (GlobStatus.bits.txmac_interrupt) {
403 etdev->TxRing.TxMacErr.value =
404 readl(&iomem->txmac.err.value);
407 * When any of the errors occur and TXMAC generates
408 * an interrupt to report these errors, it usually
409 * means that TXMAC has detected an error in the data
410 * stream retrieved from the on-chip Tx Q. All of
411 * these errors are catastrophic and TXMAC won't be
412 * able to recover data when these errors occur. In
413 * a nutshell, the whole Tx path will have to be reset
414 * and re-configured afterwards.
416 DBG_WARNING(et131x_dbginfo,
417 "TXMAC interrupt, error 0x%08x\n",
418 etdev->TxRing.TxMacErr.value);
420 /* If we are debugging, we want to see this error,
421 * otherwise we just want the device to be reset and
427 /* Handle RXMAC Interrupt */
428 if (GlobStatus.bits.rxmac_interrupt) {
430 * These interrupts are catastrophic to the device,
431 * what we need to do is disable the interrupts and
432 * set the flag to cause us to reset so we can solve
435 /* MP_SET_FLAG( etdev,
436 fMP_ADAPTER_HARDWARE_ERROR); */
438 DBG_WARNING(et131x_dbginfo,
439 "RXMAC interrupt, error 0x%08x. Requesting reset\n",
440 readl(&iomem->rxmac.err_reg.value));
442 DBG_WARNING(et131x_dbginfo,
443 "Enable 0x%08x, Diag 0x%08x\n",
444 readl(&iomem->rxmac.ctrl.value),
445 readl(&iomem->rxmac.rxq_diag.value));
448 * If we are debugging, we want to see this error,
449 * otherwise we just want the device to be reset and
455 /* Handle MAC_STAT Interrupt */
456 if (GlobStatus.bits.mac_stat_interrupt) {
458 * This means at least one of the un-masked counters
459 * in the MAC_STAT block has rolled over. Use this
460 * to maintain the top, software managed bits of the
463 DBG_VERBOSE(et131x_dbginfo, "MAC_STAT interrupt\n");
464 HandleMacStatInterrupt(etdev);
467 /* Handle SLV Timeout Interrupt */
468 if (GlobStatus.bits.slv_timeout) {
470 * This means a timeout has occured on a read or
471 * write request to one of the JAGCore registers. The
472 * Global Resources block has terminated the request
473 * and on a read request, returned a "fake" value.
474 * The most likely reasons are: Bad Address or the
475 * addressed module is in a power-down state and
478 DBG_VERBOSE(et131x_dbginfo, "SLV_TIMEOUT interrupt\n");
482 et131x_enable_interrupts(etdev);