3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et1310_tx.c - Routines used to perform data transmission.
13 *------------------------------------------------------------------------------
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
19 * software indicates your acceptance of these terms and conditions. If you do
20 * not agree with these terms and conditions, do not use the software.
22 * Copyright © 2005 Agere Systems Inc.
23 * All rights reserved.
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
28 * . Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following Disclaimer as comments in the code as
30 * well as in the documentation and/or other materials provided with the
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
35 * and/or other materials provided with the distribution.
37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
43 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
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48 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
49 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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58 #include "et131x_version.h"
59 #include "et131x_defs.h"
61 #include <linux/pci.h>
62 #include <linux/init.h>
63 #include <linux/module.h>
64 #include <linux/types.h>
65 #include <linux/kernel.h>
67 #include <linux/sched.h>
68 #include <linux/ptrace.h>
69 #include <linux/slab.h>
70 #include <linux/ctype.h>
71 #include <linux/string.h>
72 #include <linux/timer.h>
73 #include <linux/interrupt.h>
75 #include <linux/delay.h>
77 #include <linux/bitops.h>
78 #include <asm/system.h>
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/skbuff.h>
83 #include <linux/if_arp.h>
84 #include <linux/ioport.h>
86 #include "et1310_phy.h"
87 #include "et1310_pm.h"
88 #include "et1310_jagcore.h"
90 #include "et131x_adapter.h"
91 #include "et131x_initpci.h"
92 #include "et131x_isr.h"
94 #include "et1310_tx.h"
97 static void et131x_update_tcb_list(struct et131x_adapter *etdev);
98 static inline void et131x_free_send_packet(struct et131x_adapter *etdev,
100 static int et131x_send_packet(struct sk_buff *skb,
101 struct et131x_adapter *etdev);
102 static int nic_send_packet(struct et131x_adapter *etdev, struct tcb *tcb);
105 * et131x_tx_dma_memory_alloc
106 * @adapter: pointer to our private adapter structure
108 * Returns 0 on success and errno on failure (as defined in errno.h).
110 * Allocates memory that will be visible both to the device and to the CPU.
111 * The OS will pass us packets, pointers to which we will insert in the Tx
112 * Descriptor queue. The device will read this queue to find the packets in
113 * memory. The device will update the "status" in memory each time it xmits a
116 int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter)
119 struct tx_ring *tx_ring = &adapter->tx_ring;
121 /* Allocate memory for the TCB's (Transmit Control Block) */
122 adapter->tx_ring.MpTcbMem = (struct tcb *)
123 kcalloc(NUM_TCB, sizeof(struct tcb), GFP_ATOMIC | GFP_DMA);
124 if (!adapter->tx_ring.MpTcbMem) {
125 dev_err(&adapter->pdev->dev, "Cannot alloc memory for TCBs\n");
129 /* Allocate enough memory for the Tx descriptor ring, and allocate
130 * some extra so that the ring can be aligned on a 4k boundary.
132 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX) + 4096 - 1;
133 tx_ring->tx_desc_ring =
134 (struct tx_desc *) pci_alloc_consistent(adapter->pdev, desc_size,
135 &tx_ring->tx_desc_ring_pa);
136 if (!adapter->tx_ring.tx_desc_ring) {
137 dev_err(&adapter->pdev->dev, "Cannot alloc memory for Tx Ring\n");
141 /* Save physical address
143 * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
144 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
145 * are ever returned, make sure the high part is retrieved here before
146 * storing the adjusted address.
148 /* Allocate memory for the Tx status block */
149 tx_ring->pTxStatusVa = pci_alloc_consistent(adapter->pdev,
150 sizeof(TX_STATUS_BLOCK_t),
151 &tx_ring->pTxStatusPa);
152 if (!adapter->tx_ring.pTxStatusPa) {
153 dev_err(&adapter->pdev->dev,
154 "Cannot alloc memory for Tx status block\n");
158 /* Allocate memory for a dummy buffer */
159 tx_ring->pTxDummyBlkVa = pci_alloc_consistent(adapter->pdev,
161 &tx_ring->pTxDummyBlkPa);
162 if (!adapter->tx_ring.pTxDummyBlkPa) {
163 dev_err(&adapter->pdev->dev,
164 "Cannot alloc memory for Tx dummy buffer\n");
172 * et131x_tx_dma_memory_free - Free all memory allocated within this module
173 * @adapter: pointer to our private adapter structure
175 * Returns 0 on success and errno on failure (as defined in errno.h).
177 void et131x_tx_dma_memory_free(struct et131x_adapter *adapter)
181 if (adapter->tx_ring.tx_desc_ring) {
182 /* Free memory relating to Tx rings here */
183 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX)
185 pci_free_consistent(adapter->pdev,
187 adapter->tx_ring.tx_desc_ring,
188 adapter->tx_ring.tx_desc_ring_pa);
189 adapter->tx_ring.tx_desc_ring = NULL;
192 /* Free memory for the Tx status block */
193 if (adapter->tx_ring.pTxStatusVa) {
194 pci_free_consistent(adapter->pdev,
195 sizeof(TX_STATUS_BLOCK_t),
196 adapter->tx_ring.pTxStatusVa,
197 adapter->tx_ring.pTxStatusPa);
199 adapter->tx_ring.pTxStatusVa = NULL;
202 /* Free memory for the dummy buffer */
203 if (adapter->tx_ring.pTxDummyBlkVa) {
204 pci_free_consistent(adapter->pdev,
206 adapter->tx_ring.pTxDummyBlkVa,
207 adapter->tx_ring.pTxDummyBlkPa);
209 adapter->tx_ring.pTxDummyBlkVa = NULL;
212 /* Free the memory for the tcb structures */
213 kfree(adapter->tx_ring.MpTcbMem);
217 * ConfigTxDmaRegs - Set up the tx dma section of the JAGCore.
218 * @etdev: pointer to our private adapter structure
220 void ConfigTxDmaRegs(struct et131x_adapter *etdev)
222 struct _TXDMA_t __iomem *txdma = &etdev->regs->txdma;
224 /* Load the hardware with the start of the transmit descriptor ring. */
225 writel((u32) ((u64)etdev->tx_ring.tx_desc_ring_pa >> 32),
227 writel((u32) etdev->tx_ring.tx_desc_ring_pa,
230 /* Initialise the transmit DMA engine */
231 writel(NUM_DESC_PER_RING_TX - 1, &txdma->pr_num_des.value);
233 /* Load the completion writeback physical address
235 * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
236 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
237 * are ever returned, make sure the high part is retrieved here before
238 * storing the adjusted address.
240 writel(0, &txdma->dma_wb_base_hi);
241 writel(etdev->tx_ring.pTxStatusPa, &txdma->dma_wb_base_lo);
243 memset(etdev->tx_ring.pTxStatusVa, 0, sizeof(TX_STATUS_BLOCK_t));
245 writel(0, &txdma->service_request);
246 etdev->tx_ring.txDmaReadyToSend = 0;
250 * et131x_tx_dma_disable - Stop of Tx_DMA on the ET1310
251 * @etdev: pointer to our adapter structure
253 void et131x_tx_dma_disable(struct et131x_adapter *etdev)
255 /* Setup the tramsmit dma configuration register */
256 writel(ET_TXDMA_CSR_HALT|ET_TXDMA_SNGL_EPKT,
257 &etdev->regs->txdma.csr);
261 * et131x_tx_dma_enable - re-start of Tx_DMA on the ET1310.
262 * @etdev: pointer to our adapter structure
264 * Mainly used after a return to the D0 (full-power) state from a lower state.
266 void et131x_tx_dma_enable(struct et131x_adapter *etdev)
268 /* Setup the transmit dma configuration register for normal
271 writel(ET_TXDMA_SNGL_EPKT|(PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT),
272 &etdev->regs->txdma.csr);
276 * et131x_init_send - Initialize send data structures
277 * @adapter: pointer to our private adapter structure
279 void et131x_init_send(struct et131x_adapter *adapter)
283 struct tx_ring *tx_ring;
285 /* Setup some convenience pointers */
286 tx_ring = &adapter->tx_ring;
287 tcb = adapter->tx_ring.MpTcbMem;
289 tx_ring->TCBReadyQueueHead = tcb;
291 /* Go through and set up each TCB */
292 for (count = 0; count < NUM_TCB; count++) {
293 memset(tcb, 0, sizeof(struct tcb));
295 /* Set the link pointer in HW TCB to the next TCB in the
296 * chain. If this is the last TCB in the chain, also set the
299 if (count < NUM_TCB - 1) {
302 tx_ring->TCBReadyQueueTail = tcb;
309 /* Curr send queue should now be empty */
310 tx_ring->CurrSendHead = NULL;
311 tx_ring->CurrSendTail = NULL;
315 * et131x_send_packets - This function is called by the OS to send packets
316 * @skb: the packet(s) to send
317 * @netdev:device on which to TX the above packet(s)
319 * Return 0 in almost all cases; non-zero value in extreme hard failure only
321 int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev)
324 struct et131x_adapter *etdev = NULL;
326 etdev = netdev_priv(netdev);
328 /* Send these packets
330 * NOTE: The Linux Tx entry point is only given one packet at a time
331 * to Tx, so the PacketCount and it's array used makes no sense here
334 /* TCB is not available */
335 if (MP_TCB_RESOURCES_NOT_AVAILABLE(etdev)) {
336 /* NOTE: If there's an error on send, no need to queue the
337 * packet under Linux; if we just send an error up to the
338 * netif layer, it will resend the skb to us.
342 /* We need to see if the link is up; if it's not, make the
343 * netif layer think we're good and drop the packet
346 * if( MP_SHOULD_FAIL_SEND( etdev ) ||
347 * etdev->DriverNoPhyAccess )
349 if (MP_SHOULD_FAIL_SEND(etdev) || !netif_carrier_ok(netdev)) {
350 dev_kfree_skb_any(skb);
353 etdev->net_stats.tx_dropped++;
355 status = et131x_send_packet(skb, etdev);
357 if (status == -ENOMEM) {
359 /* NOTE: If there's an error on send, no need
360 * to queue the packet under Linux; if we just
361 * send an error up to the netif layer, it
362 * will resend the skb to us.
364 } else if (status != 0) {
365 /* On any other error, make netif think we're
366 * OK and drop the packet
368 dev_kfree_skb_any(skb);
370 etdev->net_stats.tx_dropped++;
378 * et131x_send_packet - Do the work to send a packet
379 * @skb: the packet(s) to send
380 * @etdev: a pointer to the device's private adapter structure
382 * Return 0 in almost all cases; non-zero value in extreme hard failure only.
384 * Assumption: Send spinlock has been acquired
386 static int et131x_send_packet(struct sk_buff *skb,
387 struct et131x_adapter *etdev)
390 struct tcb *tcb = NULL;
394 /* All packets must have at least a MAC address and a protocol type */
395 if (skb->len < ETH_HLEN)
398 /* Get a TCB for this packet */
399 spin_lock_irqsave(&etdev->TCBReadyQLock, flags);
401 tcb = etdev->tx_ring.TCBReadyQueueHead;
404 spin_unlock_irqrestore(&etdev->TCBReadyQLock, flags);
408 etdev->tx_ring.TCBReadyQueueHead = tcb->Next;
410 if (etdev->tx_ring.TCBReadyQueueHead == NULL)
411 etdev->tx_ring.TCBReadyQueueTail = NULL;
413 spin_unlock_irqrestore(&etdev->TCBReadyQLock, flags);
415 tcb->PacketLength = skb->len;
418 if ((skb->data != NULL) && ((skb->len - skb->data_len) >= 6)) {
419 shbufva = (u16 *) skb->data;
421 if ((shbufva[0] == 0xffff) &&
422 (shbufva[1] == 0xffff) && (shbufva[2] == 0xffff)) {
423 tcb->Flags |= fMP_DEST_BROAD;
424 } else if ((shbufva[0] & 0x3) == 0x0001) {
425 tcb->Flags |= fMP_DEST_MULTI;
431 /* Call the NIC specific send handler. */
433 status = nic_send_packet(etdev, tcb);
436 spin_lock_irqsave(&etdev->TCBReadyQLock, flags);
438 if (etdev->tx_ring.TCBReadyQueueTail) {
439 etdev->tx_ring.TCBReadyQueueTail->Next = tcb;
441 /* Apparently ready Q is empty. */
442 etdev->tx_ring.TCBReadyQueueHead = tcb;
445 etdev->tx_ring.TCBReadyQueueTail = tcb;
446 spin_unlock_irqrestore(&etdev->TCBReadyQLock, flags);
449 WARN_ON(etdev->tx_ring.nBusySend > NUM_TCB);
454 * nic_send_packet - NIC specific send handler for version B silicon.
455 * @etdev: pointer to our adapter
456 * @tcb: pointer to struct tcb
458 * Returns 0 or errno.
460 static int nic_send_packet(struct et131x_adapter *etdev, struct tcb *tcb)
463 struct tx_desc desc[24]; /* 24 x 16 byte */
465 u32 thiscopy, remainder;
466 struct sk_buff *skb = tcb->Packet;
467 u32 nr_frags = skb_shinfo(skb)->nr_frags + 1;
468 struct skb_frag_struct *frags = &skb_shinfo(skb)->frags[0];
471 /* Part of the optimizations of this send routine restrict us to
472 * sending 24 fragments at a pass. In practice we should never see
473 * more than 5 fragments.
475 * NOTE: The older version of this function (below) can handle any
476 * number of fragments. If needed, we can call this function,
477 * although it is less efficient.
482 memset(desc, 0, sizeof(struct tx_desc) * (nr_frags + 1));
484 for (i = 0; i < nr_frags; i++) {
485 /* If there is something in this element, lets get a
486 * descriptor from the ring and get the necessary data
489 /* If the fragments are smaller than a standard MTU,
490 * then map them to a single descriptor in the Tx
491 * Desc ring. However, if they're larger, as is
492 * possible with support for jumbo packets, then
493 * split them each across 2 descriptors.
495 * This will work until we determine why the hardware
496 * doesn't seem to like large fragments.
498 if ((skb->len - skb->data_len) <= 1514) {
499 desc[frag].addr_hi = 0;
500 /* Low 16bits are length, high is vlan and
501 unused currently so zero */
502 desc[frag].len_vlan =
503 skb->len - skb->data_len;
505 /* NOTE: Here, the dma_addr_t returned from
506 * pci_map_single() is implicitly cast as a
507 * u32. Although dma_addr_t can be
508 * 64-bit, the address returned by
509 * pci_map_single() is always 32-bit
510 * addressable (as defined by the pci/dma
513 desc[frag++].addr_lo =
514 pci_map_single(etdev->pdev,
520 desc[frag].addr_hi = 0;
521 desc[frag].len_vlan =
522 (skb->len - skb->data_len) / 2;
524 /* NOTE: Here, the dma_addr_t returned from
525 * pci_map_single() is implicitly cast as a
526 * u32. Although dma_addr_t can be
527 * 64-bit, the address returned by
528 * pci_map_single() is always 32-bit
529 * addressable (as defined by the pci/dma
532 desc[frag++].addr_lo =
533 pci_map_single(etdev->pdev,
538 desc[frag].addr_hi = 0;
540 desc[frag].len_vlan =
541 (skb->len - skb->data_len) / 2;
543 /* NOTE: Here, the dma_addr_t returned from
544 * pci_map_single() is implicitly cast as a
545 * u32. Although dma_addr_t can be
546 * 64-bit, the address returned by
547 * pci_map_single() is always 32-bit
548 * addressable (as defined by the pci/dma
551 desc[frag++].addr_lo =
552 pci_map_single(etdev->pdev,
561 desc[frag].addr_hi = 0;
562 desc[frag].len_vlan =
565 /* NOTE: Here, the dma_addr_t returned from
566 * pci_map_page() is implicitly cast as a u32.
567 * Although dma_addr_t can be 64-bit, the address
568 * returned by pci_map_page() is always 32-bit
569 * addressable (as defined by the pci/dma subsystem)
571 desc[frag++].addr_lo =
572 pci_map_page(etdev->pdev,
574 frags[i - 1].page_offset,
583 if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS) {
584 if (++etdev->tx_ring.TxPacketsSinceLastinterrupt ==
585 PARM_TX_NUM_BUFS_DEF) {
586 /* Last element & Interrupt flag */
587 desc[frag - 1].flags = 0x5;
588 etdev->tx_ring.TxPacketsSinceLastinterrupt = 0;
589 } else { /* Last element */
590 desc[frag - 1].flags = 0x1;
593 desc[frag - 1].flags = 0x5;
595 desc[0].flags |= 2; /* First element flag */
597 tcb->WrIndexStart = etdev->tx_ring.txDmaReadyToSend;
598 tcb->PacketStaleCount = 0;
600 spin_lock_irqsave(&etdev->SendHWLock, flags);
602 thiscopy = NUM_DESC_PER_RING_TX -
603 INDEX10(etdev->tx_ring.txDmaReadyToSend);
605 if (thiscopy >= frag) {
609 remainder = frag - thiscopy;
612 memcpy(etdev->tx_ring.tx_desc_ring +
613 INDEX10(etdev->tx_ring.txDmaReadyToSend), desc,
614 sizeof(struct tx_desc) * thiscopy);
616 add_10bit(&etdev->tx_ring.txDmaReadyToSend, thiscopy);
618 if (INDEX10(etdev->tx_ring.txDmaReadyToSend)== 0 ||
619 INDEX10(etdev->tx_ring.txDmaReadyToSend) == NUM_DESC_PER_RING_TX) {
620 etdev->tx_ring.txDmaReadyToSend &= ~ET_DMA10_MASK;
621 etdev->tx_ring.txDmaReadyToSend ^= ET_DMA10_WRAP;
625 memcpy(etdev->tx_ring.tx_desc_ring,
627 sizeof(struct tx_desc) * remainder);
629 add_10bit(&etdev->tx_ring.txDmaReadyToSend, remainder);
632 if (INDEX10(etdev->tx_ring.txDmaReadyToSend) == 0) {
633 if (etdev->tx_ring.txDmaReadyToSend)
634 tcb->WrIndex = NUM_DESC_PER_RING_TX - 1;
636 tcb->WrIndex= ET_DMA10_WRAP | (NUM_DESC_PER_RING_TX - 1);
638 tcb->WrIndex = etdev->tx_ring.txDmaReadyToSend - 1;
640 spin_lock(&etdev->TCBSendQLock);
642 if (etdev->tx_ring.CurrSendTail)
643 etdev->tx_ring.CurrSendTail->Next = tcb;
645 etdev->tx_ring.CurrSendHead = tcb;
647 etdev->tx_ring.CurrSendTail = tcb;
649 WARN_ON(tcb->Next != NULL);
651 etdev->tx_ring.nBusySend++;
653 spin_unlock(&etdev->TCBSendQLock);
655 /* Write the new write pointer back to the device. */
656 writel(etdev->tx_ring.txDmaReadyToSend,
657 &etdev->regs->txdma.service_request);
659 /* For Gig only, we use Tx Interrupt coalescing. Enable the software
660 * timer to wake us up if this packet isn't followed by N more.
662 if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS) {
663 writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
664 &etdev->regs->global.watchdog_timer);
666 spin_unlock_irqrestore(&etdev->SendHWLock, flags);
673 * et131x_free_send_packet - Recycle a struct tcb
674 * @etdev: pointer to our adapter
675 * @tcb: pointer to struct tcb
677 * Complete the packet if necessary
678 * Assumption - Send spinlock has been acquired
680 inline void et131x_free_send_packet(struct et131x_adapter *etdev,
684 struct tx_desc *desc = NULL;
685 struct net_device_stats *stats = &etdev->net_stats;
687 if (tcb->Flags & fMP_DEST_BROAD)
688 atomic_inc(&etdev->Stats.brdcstxmt);
689 else if (tcb->Flags & fMP_DEST_MULTI)
690 atomic_inc(&etdev->Stats.multixmt);
692 atomic_inc(&etdev->Stats.unixmt);
695 stats->tx_bytes += tcb->Packet->len;
697 /* Iterate through the TX descriptors on the ring
698 * corresponding to this packet and umap the fragments
702 desc =(struct tx_desc *) (etdev->tx_ring.tx_desc_ring +
703 INDEX10(tcb->WrIndexStart));
705 pci_unmap_single(etdev->pdev,
707 desc->len_vlan, PCI_DMA_TODEVICE);
709 add_10bit(&tcb->WrIndexStart, 1);
710 if (INDEX10(tcb->WrIndexStart) >=
711 NUM_DESC_PER_RING_TX) {
712 tcb->WrIndexStart &= ~ET_DMA10_MASK;
713 tcb->WrIndexStart ^= ET_DMA10_WRAP;
715 } while (desc != (etdev->tx_ring.tx_desc_ring +
716 INDEX10(tcb->WrIndex)));
718 dev_kfree_skb_any(tcb->Packet);
721 memset(tcb, 0, sizeof(struct tcb));
723 /* Add the TCB to the Ready Q */
724 spin_lock_irqsave(&etdev->TCBReadyQLock, flags);
726 etdev->Stats.opackets++;
728 if (etdev->tx_ring.TCBReadyQueueTail) {
729 etdev->tx_ring.TCBReadyQueueTail->Next = tcb;
731 /* Apparently ready Q is empty. */
732 etdev->tx_ring.TCBReadyQueueHead = tcb;
735 etdev->tx_ring.TCBReadyQueueTail = tcb;
737 spin_unlock_irqrestore(&etdev->TCBReadyQLock, flags);
738 WARN_ON(etdev->tx_ring.nBusySend < 0);
742 * et131x_free_busy_send_packets - Free and complete the stopped active sends
743 * @etdev: pointer to our adapter
745 * Assumption - Send spinlock has been acquired
747 void et131x_free_busy_send_packets(struct et131x_adapter *etdev)
750 struct list_head *entry;
754 /* Any packets being sent? Check the first TCB on the send list */
755 spin_lock_irqsave(&etdev->TCBSendQLock, flags);
757 tcb = etdev->tx_ring.CurrSendHead;
759 while ((tcb != NULL) && (freed < NUM_TCB)) {
760 struct tcb *pNext = tcb->Next;
762 etdev->tx_ring.CurrSendHead = pNext;
765 etdev->tx_ring.CurrSendTail = NULL;
767 etdev->tx_ring.nBusySend--;
769 spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);
772 et131x_free_send_packet(etdev, tcb);
774 spin_lock_irqsave(&etdev->TCBSendQLock, flags);
776 tcb = etdev->tx_ring.CurrSendHead;
779 WARN_ON(freed == NUM_TCB);
781 spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);
783 etdev->tx_ring.nBusySend = 0;
787 * et131x_handle_send_interrupt - Interrupt handler for sending processing
788 * @etdev: pointer to our adapter
790 * Re-claim the send resources, complete sends and get more to send from
791 * the send wait queue.
793 * Assumption - Send spinlock has been acquired
795 void et131x_handle_send_interrupt(struct et131x_adapter *etdev)
797 /* Mark as completed any packets which have been sent by the device. */
798 et131x_update_tcb_list(etdev);
802 * et131x_update_tcb_list - Helper routine for Send Interrupt handler
803 * @etdev: pointer to our adapter
805 * Re-claims the send resources and completes sends. Can also be called as
806 * part of the NIC send routine when the "ServiceComplete" indication has
809 static void et131x_update_tcb_list(struct et131x_adapter *etdev)
816 serviced = readl(&etdev->regs->txdma.NewServiceComplete);
817 index = INDEX10(serviced);
819 /* Has the ring wrapped? Process any descriptors that do not have
820 * the same "wrap" indicator as the current completion indicator
822 spin_lock_irqsave(&etdev->TCBSendQLock, flags);
824 tcb = etdev->tx_ring.CurrSendHead;
827 ((serviced ^ tcb->WrIndex) & ET_DMA10_WRAP) &&
828 index < INDEX10(tcb->WrIndex)) {
829 etdev->tx_ring.nBusySend--;
830 etdev->tx_ring.CurrSendHead = tcb->Next;
831 if (tcb->Next == NULL)
832 etdev->tx_ring.CurrSendTail = NULL;
834 spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);
835 et131x_free_send_packet(etdev, tcb);
836 spin_lock_irqsave(&etdev->TCBSendQLock, flags);
838 /* Goto the next packet */
839 tcb = etdev->tx_ring.CurrSendHead;
842 !((serviced ^ tcb->WrIndex) & ET_DMA10_WRAP)
843 && index > (tcb->WrIndex & ET_DMA10_MASK)) {
844 etdev->tx_ring.nBusySend--;
845 etdev->tx_ring.CurrSendHead = tcb->Next;
846 if (tcb->Next == NULL)
847 etdev->tx_ring.CurrSendTail = NULL;
849 spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);
850 et131x_free_send_packet(etdev, tcb);
851 spin_lock_irqsave(&etdev->TCBSendQLock, flags);
853 /* Goto the next packet */
854 tcb = etdev->tx_ring.CurrSendHead;
857 /* Wake up the queue when we hit a low-water mark */
858 if (etdev->tx_ring.nBusySend <= (NUM_TCB / 3))
859 netif_wake_queue(etdev->netdev);
861 spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);