3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et1310_rx.h - Defines, structs, enums, prototypes, etc. pertaining to data
14 *------------------------------------------------------------------------------
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19 * which you should read carefully before using the software. Using this
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59 #ifndef __ET1310_RX_H__
60 #define __ET1310_RX_H__
62 #include "et1310_address_map.h"
67 /* #define FBR0_BUFFER_SIZE 256 */
70 /* #define FBR1_BUFFER_SIZE 2048 */
74 #define MAX_DESC_PER_RING_RX 1024
76 /* number of RFDs - default and min */
78 #define RFD_LOW_WATER_MARK 40
79 #define NIC_MIN_NUM_RFD 64
80 #define NIC_DEFAULT_NUM_RFD 1024
82 #define RFD_LOW_WATER_MARK 20
83 #define NIC_MIN_NUM_RFD 64
84 #define NIC_DEFAULT_NUM_RFD 256
87 #define NUM_PACKETS_HANDLED 256
89 #define ALCATEL_BAD_STATUS 0xe47f0000
90 #define ALCATEL_MULTICAST_PKT 0x01000000
91 #define ALCATEL_BROADCAST_PKT 0x02000000
93 /* typedefs for Free Buffer Descriptors */
98 u32 word2; /* Bits 10-31 reserved, 0-9 descriptor */
101 /* Typedefs for Packet Status Ring Descriptors */
102 typedef union _PKT_STAT_DESC_WORD0_t {
105 #ifdef _BIT_FIELDS_HTOL
106 /* top 16 bits are from the Alcatel Status Word as enumerated in */
107 /* PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2) */
109 u32 asw_trunc:1; /* bit 31(Rx frame truncated) */
111 u32 asw_long_evt:1; /* bit 31(Rx long event) */
112 u32 asw_VLAN_tag:1; /* bit 30(VLAN tag detected) */
113 u32 asw_unsupported_op:1; /* bit 29(unsupported OP code) */
114 u32 asw_pause_frame:1; /* bit 28(is a pause frame) */
115 u32 asw_control_frame:1; /* bit 27(is a control frame) */
116 u32 asw_dribble_nibble:1; /* bit 26(spurious bits after EOP) */
117 u32 asw_broadcast:1; /* bit 25(has a broadcast address) */
118 u32 asw_multicast:1; /* bit 24(has a multicast address) */
119 u32 asw_OK:1; /* bit 23(valid CRC + no code error) */
120 u32 asw_too_long:1; /* bit 22(frame length > 1518 bytes) */
121 u32 asw_len_chk_err:1; /* bit 21(frame length field incorrect) */
122 u32 asw_CRC_err:1; /* bit 20(CRC error) */
123 u32 asw_code_err:1; /* bit 19(one or more nibbles signalled as errors) */
124 u32 asw_false_carrier_event:1; /* bit 18(bad carrier since last good packet) */
125 u32 asw_RX_DV_event:1; /* bit 17(short receive event detected) */
126 u32 asw_prev_pkt_dropped:1;/* bit 16(e.g. IFG too small on previous) */
127 u32 unused:5; /* bits 11-15 */
128 u32 vp:1; /* bit 10(VLAN Packet) */
129 u32 jp:1; /* bit 9(Jumbo Packet) */
130 u32 ft:1; /* bit 8(Frame Truncated) */
131 u32 drop:1; /* bit 7(Drop packet) */
132 u32 rxmac_error:1; /* bit 6(RXMAC Error Indicator) */
133 u32 wol:1; /* bit 5(WOL Event) */
134 u32 tcpp:1; /* bit 4(TCP checksum pass) */
135 u32 tcpa:1; /* bit 3(TCP checksum assist) */
136 u32 ipp:1; /* bit 2(IP checksum pass) */
137 u32 ipa:1; /* bit 1(IP checksum assist) */
138 u32 hp:1; /* bit 0(hash pass) */
140 u32 hp:1; /* bit 0(hash pass) */
141 u32 ipa:1; /* bit 1(IP checksum assist) */
142 u32 ipp:1; /* bit 2(IP checksum pass) */
143 u32 tcpa:1; /* bit 3(TCP checksum assist) */
144 u32 tcpp:1; /* bit 4(TCP checksum pass) */
145 u32 wol:1; /* bit 5(WOL Event) */
146 u32 rxmac_error:1; /* bit 6(RXMAC Error Indicator) */
147 u32 drop:1; /* bit 7(Drop packet) */
148 u32 ft:1; /* bit 8(Frame Truncated) */
149 u32 jp:1; /* bit 9(Jumbo Packet) */
150 u32 vp:1; /* bit 10(VLAN Packet) */
151 u32 unused:5; /* bits 11-15 */
152 u32 asw_prev_pkt_dropped:1;/* bit 16(e.g. IFG too small on previous) */
153 u32 asw_RX_DV_event:1; /* bit 17(short receive event detected) */
154 u32 asw_false_carrier_event:1; /* bit 18(bad carrier since last good packet) */
155 u32 asw_code_err:1; /* bit 19(one or more nibbles signalled as errors) */
156 u32 asw_CRC_err:1; /* bit 20(CRC error) */
157 u32 asw_len_chk_err:1; /* bit 21(frame length field incorrect) */
158 u32 asw_too_long:1; /* bit 22(frame length > 1518 bytes) */
159 u32 asw_OK:1; /* bit 23(valid CRC + no code error) */
160 u32 asw_multicast:1; /* bit 24(has a multicast address) */
161 u32 asw_broadcast:1; /* bit 25(has a broadcast address) */
162 u32 asw_dribble_nibble:1; /* bit 26(spurious bits after EOP) */
163 u32 asw_control_frame:1; /* bit 27(is a control frame) */
164 u32 asw_pause_frame:1; /* bit 28(is a pause frame) */
165 u32 asw_unsupported_op:1; /* bit 29(unsupported OP code) */
166 u32 asw_VLAN_tag:1; /* bit 30(VLAN tag detected) */
167 u32 asw_long_evt:1; /* bit 31(Rx long event) */
169 u32 asw_trunc:1; /* bit 31(Rx frame truncated) */
173 } PKT_STAT_DESC_WORD0_t, *PPKT_STAT_WORD0_t;
175 typedef union _PKT_STAT_DESC_WORD1_t {
178 #ifdef _BIT_FIELDS_HTOL
179 u32 unused:4; /* bits 28-31 */
180 u32 ri:2; /* bits 26-27(Ring Index) */
181 u32 bi:10; /* bits 16-25(Buffer Index) */
182 u32 length:16; /* bit 0-15(length in bytes) */
184 u32 length:16; /* bit 0-15(length in bytes) */
185 u32 bi:10; /* bits 16-25(Buffer Index) */
186 u32 ri:2; /* bits 26-27(Ring Index) */
187 u32 unused:4; /* bits 28-31 */
190 } PKT_STAT_DESC_WORD1_t, *PPKT_STAT_WORD1_t;
192 typedef struct _PKT_STAT_DESC_t {
193 PKT_STAT_DESC_WORD0_t word0;
194 PKT_STAT_DESC_WORD1_t word1;
195 } PKT_STAT_DESC_t, *PPKT_STAT_DESC_t;
197 /* Typedefs for the RX DMA status word */
200 * rx status word 0 holds part of the status bits of the Rx DMA engine
201 * that get copied out to memory by the ET-1310. Word 0 is a 32 bit word
202 * which contains the Free Buffer ring 0 and 1 available offset.
204 * bit 0-9 FBR1 offset
205 * bit 10 Wrap flag for FBR1
206 * bit 16-25 FBR0 offset
207 * bit 26 Wrap flag for FBR0
211 * RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine
212 * that get copied out to memory by the ET-1310. Word 3 is a 32 bit word
213 * which contains the Packet Status Ring available offset.
216 #define RXSTAT1_OFFSET 16
217 #define RXSTAT1_MASK 0xFFF
218 #define RXSTAT1_WRAP 0x10000000
220 typedef union _rxstat_word1_t {
223 #ifdef _BIT_FIELDS_HTOL
224 u32 PSRunused:3; /* bits 29-31 */
225 u32 PSRwrap:1; /* bit 28 */
226 u32 PSRoffset:12; /* bits 16-27 */
227 u32 reserved:16; /* bits 0-15 */
229 u32 reserved:16; /* bits 0-15 */
230 u32 PSRoffset:12; /* bits 16-27 */
231 u32 PSRwrap:1; /* bit 28 */
232 u32 PSRunused:3; /* bits 29-31 */
235 } RXSTAT_WORD1_t, *PRXSTAT_WORD1_t;
238 * RX_STATUS_BLOCK_t is sructure representing the status of the Rx DMA engine
239 * it sits in free memory, and is pointed to by 0x101c / 0x1020
241 typedef struct _rx_status_block_t {
243 RXSTAT_WORD1_t Word1;
244 } RX_STATUS_BLOCK_t, *PRX_STATUS_BLOCK_t;
247 * Structure for look-up table holding free buffer ring pointers
249 typedef struct _FbrLookupTable {
250 void *Va[MAX_DESC_PER_RING_RX];
251 void *Buffer1[MAX_DESC_PER_RING_RX];
252 void *Buffer2[MAX_DESC_PER_RING_RX];
253 u32 PAHigh[MAX_DESC_PER_RING_RX];
254 u32 PALow[MAX_DESC_PER_RING_RX];
255 } FBRLOOKUPTABLE, *PFBRLOOKUPTABLE;
258 ONE_PACKET_INTERRUPT,
259 FOUR_PACKET_INTERRUPT
260 } eRX_INTERRUPT_STATE_t, *PeRX_INTERRUPT_STATE_t;
263 * RX_RING_t is sructure representing the adaptor's local reference(s) to the
266 typedef struct _rx_ring_t {
269 dma_addr_t pFbr0RingPa;
270 void *Fbr0MemVa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
271 dma_addr_t Fbr0MemPa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
279 dma_addr_t pFbr1RingPa;
280 void *Fbr1MemVa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
281 dma_addr_t Fbr1MemPa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
284 FBRLOOKUPTABLE *Fbr[2];
290 dma_addr_t pPSRingPa;
295 dma_addr_t pRxStatusPa;
297 struct list_head RecvBufferPool;
300 struct list_head RecvList;
305 bool UnfinishedReceives;
307 struct list_head RecvPacketPool;
309 /* lookaside lists */
310 struct kmem_cache *RecvLookaside;
311 } RX_RING_t, *PRX_RING_t;
313 /* Forward reference of RFD */
316 /* Forward declaration of the private adapter structure */
317 struct et131x_adapter;
319 /* PROTOTYPES for Initialization */
320 int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter);
321 void et131x_rx_dma_memory_free(struct et131x_adapter *adapter);
322 int et131x_rfd_resources_alloc(struct et131x_adapter *adapter,
323 struct _MP_RFD *pMpRfd);
324 void et131x_rfd_resources_free(struct et131x_adapter *adapter,
325 struct _MP_RFD *pMpRfd);
326 int et131x_init_recv(struct et131x_adapter *adapter);
328 void ConfigRxDmaRegs(struct et131x_adapter *adapter);
329 void SetRxDmaTimer(struct et131x_adapter *adapter);
330 void et131x_rx_dma_disable(struct et131x_adapter *adapter);
331 void et131x_rx_dma_enable(struct et131x_adapter *adapter);
333 void et131x_reset_recv(struct et131x_adapter *adapter);
335 void et131x_handle_recv_interrupt(struct et131x_adapter *adapter);
337 #endif /* __ET1310_RX_H__ */