3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et1310_rx.c - Routines used to perform data reception
13 *------------------------------------------------------------------------------
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
19 * software indicates your acceptance of these terms and conditions. If you do
20 * not agree with these terms and conditions, do not use the software.
22 * Copyright © 2005 Agere Systems Inc.
23 * All rights reserved.
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
28 * . Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following Disclaimer as comments in the code as
30 * well as in the documentation and/or other materials provided with the
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
35 * and/or other materials provided with the distribution.
37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
43 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
47 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
48 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
49 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
51 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
58 #include "et131x_version.h"
59 #include "et131x_debug.h"
60 #include "et131x_defs.h"
62 #include <linux/pci.h>
63 #include <linux/init.h>
64 #include <linux/module.h>
65 #include <linux/types.h>
66 #include <linux/kernel.h>
68 #include <linux/sched.h>
69 #include <linux/ptrace.h>
70 #include <linux/slab.h>
71 #include <linux/ctype.h>
72 #include <linux/string.h>
73 #include <linux/timer.h>
74 #include <linux/interrupt.h>
76 #include <linux/delay.h>
78 #include <linux/bitops.h>
79 #include <asm/system.h>
81 #include <linux/netdevice.h>
82 #include <linux/etherdevice.h>
83 #include <linux/skbuff.h>
84 #include <linux/if_arp.h>
85 #include <linux/ioport.h>
87 #include "et1310_phy.h"
88 #include "et1310_pm.h"
89 #include "et1310_jagcore.h"
91 #include "et131x_adapter.h"
92 #include "et131x_initpci.h"
94 #include "et1310_rx.h"
96 /* Data for debugging facilities */
97 #ifdef CONFIG_ET131X_DEBUG
98 extern dbg_info_t *et131x_dbginfo;
99 #endif /* CONFIG_ET131X_DEBUG */
102 void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD pMpRfd);
105 * et131x_rx_dma_memory_alloc
106 * @adapter: pointer to our private adapter structure
108 * Returns 0 on success and errno on failure (as defined in errno.h)
110 * Allocates Free buffer ring 1 for sure, free buffer ring 0 if required,
111 * and the Packet Status Ring.
113 int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
115 uint32_t OuterLoop, InnerLoop;
117 uint32_t pktStatRingSize, FBRChunkSize;
120 DBG_ENTER(et131x_dbginfo);
122 /* Setup some convenience pointers */
123 rx_ring = (RX_RING_t *) &adapter->RxRing;
125 /* Alloc memory for the lookup table */
127 rx_ring->Fbr[0] = kmalloc(sizeof(FBRLOOKUPTABLE), GFP_KERNEL);
130 rx_ring->Fbr[1] = kmalloc(sizeof(FBRLOOKUPTABLE), GFP_KERNEL);
132 /* The first thing we will do is configure the sizes of the buffer
133 * rings. These will change based on jumbo packet support. Larger
134 * jumbo packets increases the size of each entry in FBR0, and the
135 * number of entries in FBR0, while at the same time decreasing the
136 * number of entries in FBR1.
138 * FBR1 holds "large" frames, FBR0 holds "small" frames. If FBR1
139 * entries are huge in order to accomodate a "jumbo" frame, then it
140 * will have less entries. Conversely, FBR1 will now be relied upon
141 * to carry more "normal" frames, thus it's entry size also increases
142 * and the number of entries goes up too (since it now carries
143 * "small" + "regular" packets.
145 * In this scheme, we try to maintain 512 entries between the two
146 * rings. Also, FBR1 remains a constant size - when it's size doubles
147 * the number of entries halves. FBR0 increases in size, however.
150 if (adapter->RegistryJumboPacket < 2048) {
152 rx_ring->Fbr0BufferSize = 256;
153 rx_ring->Fbr0NumEntries = 512;
155 rx_ring->Fbr1BufferSize = 2048;
156 rx_ring->Fbr1NumEntries = 512;
157 } else if (adapter->RegistryJumboPacket < 4096) {
159 rx_ring->Fbr0BufferSize = 512;
160 rx_ring->Fbr0NumEntries = 1024;
162 rx_ring->Fbr1BufferSize = 4096;
163 rx_ring->Fbr1NumEntries = 512;
166 rx_ring->Fbr0BufferSize = 1024;
167 rx_ring->Fbr0NumEntries = 768;
169 rx_ring->Fbr1BufferSize = 16384;
170 rx_ring->Fbr1NumEntries = 128;
174 adapter->RxRing.PsrNumEntries = adapter->RxRing.Fbr0NumEntries +
175 adapter->RxRing.Fbr1NumEntries;
177 adapter->RxRing.PsrNumEntries = adapter->RxRing.Fbr1NumEntries;
180 /* Allocate an area of memory for Free Buffer Ring 1 */
181 bufsize = (sizeof(FBR_DESC_t) * rx_ring->Fbr1NumEntries) + 0xfff;
182 rx_ring->pFbr1RingVa = pci_alloc_consistent(adapter->pdev,
184 &rx_ring->pFbr1RingPa);
185 if (!rx_ring->pFbr1RingVa) {
186 DBG_ERROR(et131x_dbginfo,
187 "Cannot alloc memory for Free Buffer Ring 1\n");
188 DBG_LEAVE(et131x_dbginfo);
192 /* Save physical address
194 * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
195 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
196 * are ever returned, make sure the high part is retrieved here
197 * before storing the adjusted address.
199 rx_ring->Fbr1Realpa = rx_ring->pFbr1RingPa;
201 /* Align Free Buffer Ring 1 on a 4K boundary */
202 et131x_align_allocated_memory(adapter,
203 &rx_ring->Fbr1Realpa,
204 &rx_ring->Fbr1offset, 0x0FFF);
206 rx_ring->pFbr1RingVa = (void *)((uint8_t *) rx_ring->pFbr1RingVa +
207 rx_ring->Fbr1offset);
210 /* Allocate an area of memory for Free Buffer Ring 0 */
211 bufsize = (sizeof(FBR_DESC_t) * rx_ring->Fbr0NumEntries) + 0xfff;
212 rx_ring->pFbr0RingVa = pci_alloc_consistent(adapter->pdev,
214 &rx_ring->pFbr0RingPa);
215 if (!rx_ring->pFbr0RingVa) {
216 DBG_ERROR(et131x_dbginfo,
217 "Cannot alloc memory for Free Buffer Ring 0\n");
218 DBG_LEAVE(et131x_dbginfo);
222 /* Save physical address
224 * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
225 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
226 * are ever returned, make sure the high part is retrieved here before
227 * storing the adjusted address.
229 rx_ring->Fbr0Realpa = rx_ring->pFbr0RingPa;
231 /* Align Free Buffer Ring 0 on a 4K boundary */
232 et131x_align_allocated_memory(adapter,
233 &rx_ring->Fbr0Realpa,
234 &rx_ring->Fbr0offset, 0x0FFF);
236 rx_ring->pFbr0RingVa = (void *)((uint8_t *) rx_ring->pFbr0RingVa +
237 rx_ring->Fbr0offset);
240 for (OuterLoop = 0; OuterLoop < (rx_ring->Fbr1NumEntries / FBR_CHUNKS);
246 /* This code allocates an area of memory big enough for N
247 * free buffers + (buffer_size - 1) so that the buffers can
248 * be aligned on 4k boundaries. If each buffer were aligned
249 * to a buffer_size boundary, the effect would be to double
250 * the size of FBR0. By allocating N buffers at once, we
251 * reduce this overhead.
253 if (rx_ring->Fbr1BufferSize > 4096)
256 Fbr1Align = rx_ring->Fbr1BufferSize;
259 (FBR_CHUNKS * rx_ring->Fbr1BufferSize) + Fbr1Align - 1;
260 rx_ring->Fbr1MemVa[OuterLoop] =
261 pci_alloc_consistent(adapter->pdev, FBRChunkSize,
262 &rx_ring->Fbr1MemPa[OuterLoop]);
264 if (!rx_ring->Fbr1MemVa[OuterLoop]) {
265 DBG_ERROR(et131x_dbginfo, "Could not alloc memory\n");
266 DBG_LEAVE(et131x_dbginfo);
270 /* See NOTE in "Save Physical Address" comment above */
271 Fbr1TempPa = rx_ring->Fbr1MemPa[OuterLoop];
273 et131x_align_allocated_memory(adapter,
275 &Fbr1Offset, (Fbr1Align - 1));
277 for (InnerLoop = 0; InnerLoop < FBR_CHUNKS; InnerLoop++) {
278 uint32_t index = (OuterLoop * FBR_CHUNKS) + InnerLoop;
280 /* Save the Virtual address of this index for quick
283 rx_ring->Fbr[1]->Va[index] =
284 (uint8_t *) rx_ring->Fbr1MemVa[OuterLoop] +
285 (InnerLoop * rx_ring->Fbr1BufferSize) + Fbr1Offset;
287 /* now store the physical address in the descriptor
288 * so the device can access it
290 rx_ring->Fbr[1]->PAHigh[index] =
291 (uint32_t) (Fbr1TempPa >> 32);
292 rx_ring->Fbr[1]->PALow[index] = (uint32_t) Fbr1TempPa;
294 Fbr1TempPa += rx_ring->Fbr1BufferSize;
296 rx_ring->Fbr[1]->Buffer1[index] =
297 rx_ring->Fbr[1]->Va[index];
298 rx_ring->Fbr[1]->Buffer2[index] =
299 rx_ring->Fbr[1]->Va[index] - 4;
304 /* Same for FBR0 (if in use) */
305 for (OuterLoop = 0; OuterLoop < (rx_ring->Fbr0NumEntries / FBR_CHUNKS);
310 FBRChunkSize = ((FBR_CHUNKS + 1) * rx_ring->Fbr0BufferSize) - 1;
311 rx_ring->Fbr0MemVa[OuterLoop] =
312 pci_alloc_consistent(adapter->pdev, FBRChunkSize,
313 &rx_ring->Fbr0MemPa[OuterLoop]);
315 if (!rx_ring->Fbr0MemVa[OuterLoop]) {
316 DBG_ERROR(et131x_dbginfo, "Could not alloc memory\n");
317 DBG_LEAVE(et131x_dbginfo);
321 /* See NOTE in "Save Physical Address" comment above */
322 Fbr0TempPa = rx_ring->Fbr0MemPa[OuterLoop];
324 et131x_align_allocated_memory(adapter,
327 rx_ring->Fbr0BufferSize - 1);
329 for (InnerLoop = 0; InnerLoop < FBR_CHUNKS; InnerLoop++) {
330 uint32_t index = (OuterLoop * FBR_CHUNKS) + InnerLoop;
332 rx_ring->Fbr[0]->Va[index] =
333 (uint8_t *) rx_ring->Fbr0MemVa[OuterLoop] +
334 (InnerLoop * rx_ring->Fbr0BufferSize) + Fbr0Offset;
336 rx_ring->Fbr[0]->PAHigh[index] =
337 (uint32_t) (Fbr0TempPa >> 32);
338 rx_ring->Fbr[0]->PALow[index] = (uint32_t) Fbr0TempPa;
340 Fbr0TempPa += rx_ring->Fbr0BufferSize;
342 rx_ring->Fbr[0]->Buffer1[index] =
343 rx_ring->Fbr[0]->Va[index];
344 rx_ring->Fbr[0]->Buffer2[index] =
345 rx_ring->Fbr[0]->Va[index] - 4;
350 /* Allocate an area of memory for FIFO of Packet Status ring entries */
352 sizeof(PKT_STAT_DESC_t) * adapter->RxRing.PsrNumEntries;
354 rx_ring->pPSRingVa = pci_alloc_consistent(adapter->pdev,
355 pktStatRingSize + 0x0fff,
356 &rx_ring->pPSRingPa);
358 if (!rx_ring->pPSRingVa) {
359 DBG_ERROR(et131x_dbginfo,
360 "Cannot alloc memory for Packet Status Ring\n");
361 DBG_LEAVE(et131x_dbginfo);
365 /* Save physical address
367 * NOTE : pci_alloc_consistent(), used above to alloc DMA regions,
368 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
369 * are ever returned, make sure the high part is retrieved here before
370 * storing the adjusted address.
372 rx_ring->pPSRingRealPa = rx_ring->pPSRingPa;
374 /* Align Packet Status Ring on a 4K boundary */
375 et131x_align_allocated_memory(adapter,
376 &rx_ring->pPSRingRealPa,
377 &rx_ring->pPSRingOffset, 0x0FFF);
379 rx_ring->pPSRingVa = (void *)((uint8_t *) rx_ring->pPSRingVa +
380 rx_ring->pPSRingOffset);
382 /* Allocate an area of memory for writeback of status information */
383 rx_ring->pRxStatusVa = pci_alloc_consistent(adapter->pdev,
384 sizeof(RX_STATUS_BLOCK_t) +
385 0x7, &rx_ring->pRxStatusPa);
386 if (!rx_ring->pRxStatusVa) {
387 DBG_ERROR(et131x_dbginfo,
388 "Cannot alloc memory for Status Block\n");
389 DBG_LEAVE(et131x_dbginfo);
393 /* Save physical address */
394 rx_ring->RxStatusRealPA = rx_ring->pRxStatusPa;
396 /* Align write back on an 8 byte boundary */
397 et131x_align_allocated_memory(adapter,
398 &rx_ring->RxStatusRealPA,
399 &rx_ring->RxStatusOffset, 0x07);
401 rx_ring->pRxStatusVa = (void *)((uint8_t *) rx_ring->pRxStatusVa +
402 rx_ring->RxStatusOffset);
403 rx_ring->NumRfd = NIC_DEFAULT_NUM_RFD;
406 * pci_pool_create initializes a lookaside list. After successful
407 * creation, nonpaged fixed-size blocks can be allocated from and
408 * freed to the lookaside list.
409 * RFDs will be allocated from this pool.
411 rx_ring->RecvLookaside = kmem_cache_create(adapter->netdev->name,
418 MP_SET_FLAG(adapter, fMP_ADAPTER_RECV_LOOKASIDE);
420 /* The RFDs are going to be put on lists later on, so initialize the
423 INIT_LIST_HEAD(&rx_ring->RecvList);
424 INIT_LIST_HEAD(&rx_ring->RecvPendingList);
426 DBG_LEAVE(et131x_dbginfo);
431 * et131x_rx_dma_memory_free - Free all memory allocated within this module.
432 * @adapter: pointer to our private adapter structure
434 void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
438 uint32_t pktStatRingSize;
442 DBG_ENTER(et131x_dbginfo);
444 /* Setup some convenience pointers */
445 rx_ring = (RX_RING_t *) &adapter->RxRing;
447 /* Free RFDs and associated packet descriptors */
448 DBG_ASSERT(rx_ring->nReadyRecv == rx_ring->NumRfd);
450 while (!list_empty(&rx_ring->RecvList)) {
451 pMpRfd = (MP_RFD *) list_entry(rx_ring->RecvList.next,
454 list_del(&pMpRfd->list_node);
455 et131x_rfd_resources_free(adapter, pMpRfd);
458 while (!list_empty(&rx_ring->RecvPendingList)) {
459 pMpRfd = (MP_RFD *) list_entry(rx_ring->RecvPendingList.next,
461 list_del(&pMpRfd->list_node);
462 et131x_rfd_resources_free(adapter, pMpRfd);
465 /* Free Free Buffer Ring 1 */
466 if (rx_ring->pFbr1RingVa) {
467 /* First the packet memory */
468 for (index = 0; index <
469 (rx_ring->Fbr1NumEntries / FBR_CHUNKS); index++) {
470 if (rx_ring->Fbr1MemVa[index]) {
473 if (rx_ring->Fbr1BufferSize > 4096)
476 Fbr1Align = rx_ring->Fbr1BufferSize;
479 (rx_ring->Fbr1BufferSize * FBR_CHUNKS) +
482 pci_free_consistent(adapter->pdev,
484 rx_ring->Fbr1MemVa[index],
485 rx_ring->Fbr1MemPa[index]);
487 rx_ring->Fbr1MemVa[index] = NULL;
491 /* Now the FIFO itself */
492 rx_ring->pFbr1RingVa = (void *)((uint8_t *)
493 rx_ring->pFbr1RingVa - rx_ring->Fbr1offset);
496 (sizeof(FBR_DESC_t) * rx_ring->Fbr1NumEntries) + 0xfff;
498 pci_free_consistent(adapter->pdev,
500 rx_ring->pFbr1RingVa, rx_ring->pFbr1RingPa);
502 rx_ring->pFbr1RingVa = NULL;
506 /* Now the same for Free Buffer Ring 0 */
507 if (rx_ring->pFbr0RingVa) {
508 /* First the packet memory */
509 for (index = 0; index <
510 (rx_ring->Fbr0NumEntries / FBR_CHUNKS); index++) {
511 if (rx_ring->Fbr0MemVa[index]) {
513 (rx_ring->Fbr0BufferSize *
514 (FBR_CHUNKS + 1)) - 1;
516 pci_free_consistent(adapter->pdev,
518 rx_ring->Fbr0MemVa[index],
519 rx_ring->Fbr0MemPa[index]);
521 rx_ring->Fbr0MemVa[index] = NULL;
525 /* Now the FIFO itself */
526 rx_ring->pFbr0RingVa = (void *)((uint8_t *)
527 rx_ring->pFbr0RingVa - rx_ring->Fbr0offset);
530 (sizeof(FBR_DESC_t) * rx_ring->Fbr0NumEntries) + 0xfff;
532 pci_free_consistent(adapter->pdev,
534 rx_ring->pFbr0RingVa, rx_ring->pFbr0RingPa);
536 rx_ring->pFbr0RingVa = NULL;
540 /* Free Packet Status Ring */
541 if (rx_ring->pPSRingVa) {
542 rx_ring->pPSRingVa = (void *)((uint8_t *) rx_ring->pPSRingVa -
543 rx_ring->pPSRingOffset);
546 sizeof(PKT_STAT_DESC_t) * adapter->RxRing.PsrNumEntries;
548 pci_free_consistent(adapter->pdev,
549 pktStatRingSize + 0x0fff,
550 rx_ring->pPSRingVa, rx_ring->pPSRingPa);
552 rx_ring->pPSRingVa = NULL;
555 /* Free area of memory for the writeback of status information */
556 if (rx_ring->pRxStatusVa) {
557 rx_ring->pRxStatusVa = (void *)((uint8_t *)
558 rx_ring->pRxStatusVa - rx_ring->RxStatusOffset);
560 pci_free_consistent(adapter->pdev,
561 sizeof(RX_STATUS_BLOCK_t) + 0x7,
562 rx_ring->pRxStatusVa, rx_ring->pRxStatusPa);
564 rx_ring->pRxStatusVa = NULL;
567 /* Free receive buffer pool */
569 /* Free receive packet pool */
571 /* Destroy the lookaside (RFD) pool */
572 if (MP_TEST_FLAG(adapter, fMP_ADAPTER_RECV_LOOKASIDE)) {
573 kmem_cache_destroy(rx_ring->RecvLookaside);
574 MP_CLEAR_FLAG(adapter, fMP_ADAPTER_RECV_LOOKASIDE);
577 /* Free the FBR Lookup Table */
579 kfree(rx_ring->Fbr[0]);
582 kfree(rx_ring->Fbr[1]);
585 rx_ring->nReadyRecv = 0;
587 DBG_LEAVE(et131x_dbginfo);
591 * et131x_init_recv - Initialize receive data structures.
592 * @adapter: pointer to our private adapter structure
594 * Returns 0 on success and errno on failure (as defined in errno.h)
596 int et131x_init_recv(struct et131x_adapter *adapter)
598 int status = -ENOMEM;
599 PMP_RFD pMpRfd = NULL;
601 uint32_t TotalNumRfd = 0;
602 RX_RING_t *rx_ring = NULL;
604 DBG_ENTER(et131x_dbginfo);
606 /* Setup some convenience pointers */
607 rx_ring = (RX_RING_t *) &adapter->RxRing;
610 for (RfdCount = 0; RfdCount < rx_ring->NumRfd; RfdCount++) {
611 pMpRfd = (MP_RFD *) kmem_cache_alloc(rx_ring->RecvLookaside,
612 GFP_ATOMIC | GFP_DMA);
615 DBG_ERROR(et131x_dbginfo,
616 "Couldn't alloc RFD out of kmem_cache\n");
621 status = et131x_rfd_resources_alloc(adapter, pMpRfd);
623 DBG_ERROR(et131x_dbginfo,
624 "Couldn't alloc packet for RFD\n");
625 kmem_cache_free(rx_ring->RecvLookaside, pMpRfd);
629 /* Add this RFD to the RecvList */
630 list_add_tail(&pMpRfd->list_node, &rx_ring->RecvList);
632 /* Increment both the available RFD's, and the total RFD's. */
633 rx_ring->nReadyRecv++;
637 if (TotalNumRfd > NIC_MIN_NUM_RFD)
640 rx_ring->NumRfd = TotalNumRfd;
643 kmem_cache_free(rx_ring->RecvLookaside, pMpRfd);
644 DBG_ERROR(et131x_dbginfo,
645 "Allocation problems in et131x_init_recv\n");
648 DBG_LEAVE(et131x_dbginfo);
653 * et131x_rfd_resources_alloc
654 * @adapter: pointer to our private adapter structure
655 * @pMpRfd: pointer to a RFD
657 * Returns 0 on success and errno on failure (as defined in errno.h)
659 int et131x_rfd_resources_alloc(struct et131x_adapter *adapter, MP_RFD *pMpRfd)
661 pMpRfd->Packet = NULL;
667 * et131x_rfd_resources_free - Free the packet allocated for the given RFD
668 * @adapter: pointer to our private adapter structure
669 * @pMpRfd: pointer to a RFD
671 void et131x_rfd_resources_free(struct et131x_adapter *adapter, MP_RFD *pMpRfd)
673 pMpRfd->Packet = NULL;
674 kmem_cache_free(adapter->RxRing.RecvLookaside, pMpRfd);
678 * ConfigRxDmaRegs - Start of Rx_DMA init sequence
679 * @etdev: pointer to our adapter structure
681 void ConfigRxDmaRegs(struct et131x_adapter *etdev)
683 struct _RXDMA_t __iomem *pRxDma = &etdev->regs->rxdma;
684 struct _rx_ring_t *pRxLocal = &etdev->RxRing;
685 PFBR_DESC_t pFbrEntry;
687 RXDMA_PSR_NUM_DES_t psr_num_des;
690 DBG_ENTER(et131x_dbginfo);
692 /* Halt RXDMA to perform the reconfigure. */
693 et131x_rx_dma_disable(etdev);
695 /* Load the completion writeback physical address
697 * NOTE : pci_alloc_consistent(), used above to alloc DMA regions,
698 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
699 * are ever returned, make sure the high part is retrieved here
700 * before storing the adjusted address.
702 writel((uint32_t) (pRxLocal->RxStatusRealPA >> 32),
703 &pRxDma->dma_wb_base_hi);
704 writel((uint32_t) pRxLocal->RxStatusRealPA, &pRxDma->dma_wb_base_lo);
706 memset(pRxLocal->pRxStatusVa, 0, sizeof(RX_STATUS_BLOCK_t));
708 /* Set the address and parameters of the packet status ring into the
711 writel((uint32_t) (pRxLocal->pPSRingRealPa >> 32),
712 &pRxDma->psr_base_hi);
713 writel((uint32_t) pRxLocal->pPSRingRealPa, &pRxDma->psr_base_lo);
714 writel(pRxLocal->PsrNumEntries - 1, &pRxDma->psr_num_des.value);
715 writel(0, &pRxDma->psr_full_offset.value);
717 psr_num_des.value = readl(&pRxDma->psr_num_des.value);
718 writel((psr_num_des.bits.psr_ndes * LO_MARK_PERCENT_FOR_PSR) / 100,
719 &pRxDma->psr_min_des.value);
721 spin_lock_irqsave(&etdev->RcvLock, flags);
723 /* These local variables track the PSR in the adapter structure */
724 pRxLocal->local_psr_full.bits.psr_full = 0;
725 pRxLocal->local_psr_full.bits.psr_full_wrap = 0;
727 /* Now's the best time to initialize FBR1 contents */
728 pFbrEntry = (PFBR_DESC_t) pRxLocal->pFbr1RingVa;
729 for (iEntry = 0; iEntry < pRxLocal->Fbr1NumEntries; iEntry++) {
730 pFbrEntry->addr_hi = pRxLocal->Fbr[1]->PAHigh[iEntry];
731 pFbrEntry->addr_lo = pRxLocal->Fbr[1]->PALow[iEntry];
732 pFbrEntry->word2.bits.bi = iEntry;
736 /* Set the address and parameters of Free buffer ring 1 (and 0 if
737 * required) into the 1310's registers
739 writel((uint32_t) (pRxLocal->Fbr1Realpa >> 32), &pRxDma->fbr1_base_hi);
740 writel((uint32_t) pRxLocal->Fbr1Realpa, &pRxDma->fbr1_base_lo);
741 writel(pRxLocal->Fbr1NumEntries - 1, &pRxDma->fbr1_num_des.value);
744 DMA10W_t fbr1_full = { 0 };
746 fbr1_full.bits.val = 0;
747 fbr1_full.bits.wrap = 1;
748 writel(fbr1_full.value, &pRxDma->fbr1_full_offset.value);
751 /* This variable tracks the free buffer ring 1 full position, so it
752 * has to match the above.
754 pRxLocal->local_Fbr1_full.bits.val = 0;
755 pRxLocal->local_Fbr1_full.bits.wrap = 1;
756 writel(((pRxLocal->Fbr1NumEntries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
757 &pRxDma->fbr1_min_des.value);
760 /* Now's the best time to initialize FBR0 contents */
761 pFbrEntry = (PFBR_DESC_t) pRxLocal->pFbr0RingVa;
762 for (iEntry = 0; iEntry < pRxLocal->Fbr0NumEntries; iEntry++) {
763 pFbrEntry->addr_hi = pRxLocal->Fbr[0]->PAHigh[iEntry];
764 pFbrEntry->addr_lo = pRxLocal->Fbr[0]->PALow[iEntry];
765 pFbrEntry->word2.bits.bi = iEntry;
769 writel((uint32_t) (pRxLocal->Fbr0Realpa >> 32), &pRxDma->fbr0_base_hi);
770 writel((uint32_t) pRxLocal->Fbr0Realpa, &pRxDma->fbr0_base_lo);
771 writel(pRxLocal->Fbr0NumEntries - 1, &pRxDma->fbr0_num_des.value);
774 DMA10W_t fbr0_full = { 0 };
776 fbr0_full.bits.val = 0;
777 fbr0_full.bits.wrap = 1;
778 writel(fbr0_full.value, &pRxDma->fbr0_full_offset.value);
781 /* This variable tracks the free buffer ring 0 full position, so it
782 * has to match the above.
784 pRxLocal->local_Fbr0_full.bits.val = 0;
785 pRxLocal->local_Fbr0_full.bits.wrap = 1;
786 writel(((pRxLocal->Fbr0NumEntries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
787 &pRxDma->fbr0_min_des.value);
790 /* Program the number of packets we will receive before generating an
792 * For version B silicon, this value gets updated once autoneg is
795 writel(etdev->RegistryRxNumBuffers, &pRxDma->num_pkt_done.value);
797 /* The "time_done" is not working correctly to coalesce interrupts
798 * after a given time period, but rather is giving us an interrupt
799 * regardless of whether we have received packets.
800 * This value gets updated once autoneg is complete.
802 writel(etdev->RegistryRxTimeInterval, &pRxDma->max_pkt_time.value);
804 spin_unlock_irqrestore(&etdev->RcvLock, flags);
806 DBG_LEAVE(et131x_dbginfo);
810 * SetRxDmaTimer - Set the heartbeat timer according to line rate.
811 * @etdev: pointer to our adapter structure
813 void SetRxDmaTimer(struct et131x_adapter *etdev)
815 /* For version B silicon, we do not use the RxDMA timer for 10 and 100
816 * Mbits/s line rates. We do not enable and RxDMA interrupt coalescing.
818 if ((etdev->uiLinkSpeed == TRUEPHY_SPEED_100MBPS) ||
819 (etdev->uiLinkSpeed == TRUEPHY_SPEED_10MBPS)) {
820 writel(0, &etdev->regs->rxdma.max_pkt_time.value);
821 writel(1, &etdev->regs->rxdma.num_pkt_done.value);
826 * et131x_rx_dma_disable - Stop of Rx_DMA on the ET1310
827 * @etdev: pointer to our adapter structure
829 void et131x_rx_dma_disable(struct et131x_adapter *etdev)
833 DBG_ENTER(et131x_dbginfo);
835 /* Setup the receive dma configuration register */
836 writel(0x00002001, &etdev->regs->rxdma.csr.value);
837 csr.value = readl(&etdev->regs->rxdma.csr.value);
838 if (csr.bits.halt_status != 1) {
840 csr.value = readl(&etdev->regs->rxdma.csr.value);
841 if (csr.bits.halt_status != 1)
842 DBG_ERROR(et131x_dbginfo,
843 "RX Dma failed to enter halt state. CSR 0x%08x\n",
847 DBG_LEAVE(et131x_dbginfo);
851 * et131x_rx_dma_enable - re-start of Rx_DMA on the ET1310.
852 * @etdev: pointer to our adapter structure
854 void et131x_rx_dma_enable(struct et131x_adapter *etdev)
856 DBG_RX_ENTER(et131x_dbginfo);
858 if (etdev->RegistryPhyLoopbk)
859 /* RxDMA is disabled for loopback operation. */
860 writel(0x1, &etdev->regs->rxdma.csr.value);
862 /* Setup the receive dma configuration register for normal operation */
863 RXDMA_CSR_t csr = { 0 };
865 csr.bits.fbr1_enable = 1;
866 if (etdev->RxRing.Fbr1BufferSize == 4096)
867 csr.bits.fbr1_size = 1;
868 else if (etdev->RxRing.Fbr1BufferSize == 8192)
869 csr.bits.fbr1_size = 2;
870 else if (etdev->RxRing.Fbr1BufferSize == 16384)
871 csr.bits.fbr1_size = 3;
873 csr.bits.fbr0_enable = 1;
874 if (etdev->RxRing.Fbr0BufferSize == 256)
875 csr.bits.fbr0_size = 1;
876 else if (etdev->RxRing.Fbr0BufferSize == 512)
877 csr.bits.fbr0_size = 2;
878 else if (etdev->RxRing.Fbr0BufferSize == 1024)
879 csr.bits.fbr0_size = 3;
881 writel(csr.value, &etdev->regs->rxdma.csr.value);
883 csr.value = readl(&etdev->regs->rxdma.csr.value);
884 if (csr.bits.halt_status != 0) {
886 csr.value = readl(&etdev->regs->rxdma.csr.value);
887 if (csr.bits.halt_status != 0) {
888 DBG_ERROR(et131x_dbginfo,
889 "RX Dma failed to exit halt state. CSR 0x%08x\n",
895 DBG_RX_LEAVE(et131x_dbginfo);
899 * nic_rx_pkts - Checks the hardware for available packets
900 * @etdev: pointer to our adapter
902 * Returns pMpRfd, a pointer to our MPRFD.
904 * Checks the hardware for available packets, using completion ring
905 * If packets are available, it gets an RFD from the RecvList, attaches
906 * the packet to it, puts the RFD in the RecvPendList, and also returns
907 * the pointer to the RFD.
909 PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev)
911 struct _rx_ring_t *pRxLocal = &etdev->RxRing;
912 PRX_STATUS_BLOCK_t pRxStatusBlock;
913 PPKT_STAT_DESC_t pPSREntry;
918 struct list_head *element;
920 uint16_t bufferIndex;
922 PKT_STAT_DESC_WORD0_t Word0;
925 DBG_RX_ENTER(et131x_dbginfo);
927 /* RX Status block is written by the DMA engine prior to every
928 * interrupt. It contains the next to be used entry in the Packet
929 * Status Ring, and also the two Free Buffer rings.
931 pRxStatusBlock = (PRX_STATUS_BLOCK_t) pRxLocal->pRxStatusVa;
933 if (pRxStatusBlock->Word1.bits.PSRoffset ==
934 pRxLocal->local_psr_full.bits.psr_full &&
935 pRxStatusBlock->Word1.bits.PSRwrap ==
936 pRxLocal->local_psr_full.bits.psr_full_wrap) {
937 /* Looks like this ring is not updated yet */
938 DBG_RX(et131x_dbginfo, "(0)\n");
939 DBG_RX_LEAVE(et131x_dbginfo);
943 /* The packet status ring indicates that data is available. */
944 pPSREntry = (PPKT_STAT_DESC_t) (pRxLocal->pPSRingVa) +
945 pRxLocal->local_psr_full.bits.psr_full;
947 /* Grab any information that is required once the PSR is
948 * advanced, since we can no longer rely on the memory being
951 localLen = pPSREntry->word1.bits.length;
952 ringIndex = (uint8_t) pPSREntry->word1.bits.ri;
953 bufferIndex = (uint16_t) pPSREntry->word1.bits.bi;
954 Word0 = pPSREntry->word0;
956 DBG_RX(et131x_dbginfo, "RX PACKET STATUS\n");
957 DBG_RX(et131x_dbginfo, "\tlength : %d\n", localLen);
958 DBG_RX(et131x_dbginfo, "\tringIndex : %d\n", ringIndex);
959 DBG_RX(et131x_dbginfo, "\tbufferIndex : %d\n", bufferIndex);
960 DBG_RX(et131x_dbginfo, "\tword0 : 0x%08x\n", Word0.value);
963 /* Check the Status Word that the MAC has appended to the PSR
964 * entry in case the MAC has detected errors.
966 if (Word0.value & ALCATEL_BAD_STATUS) {
967 DBG_ERROR(et131x_dbginfo,
968 "NICRxPkts >> Alcatel Status Word error."
969 "Value 0x%08x\n", pPSREntry->word0.value);
973 /* Indicate that we have used this PSR entry. */
974 if (++pRxLocal->local_psr_full.bits.psr_full >
975 pRxLocal->PsrNumEntries - 1) {
976 pRxLocal->local_psr_full.bits.psr_full = 0;
977 pRxLocal->local_psr_full.bits.psr_full_wrap ^= 1;
980 writel(pRxLocal->local_psr_full.value,
981 &etdev->regs->rxdma.psr_full_offset.value);
984 if (ringIndex != 1) {
985 DBG_ERROR(et131x_dbginfo,
986 "NICRxPkts PSR Entry %d indicates "
987 "Buffer Ring 0 in use\n",
988 pRxLocal->local_psr_full.bits.psr_full);
989 DBG_RX_LEAVE(et131x_dbginfo);
997 bufferIndex > pRxLocal->Fbr0NumEntries - 1) ||
999 bufferIndex > pRxLocal->Fbr1NumEntries - 1))
1001 if (ringIndex != 1 ||
1002 bufferIndex > pRxLocal->Fbr1NumEntries - 1)
1005 /* Illegal buffer or ring index cannot be used by S/W*/
1006 DBG_ERROR(et131x_dbginfo,
1007 "NICRxPkts PSR Entry %d indicates "
1008 "length of %d and/or bad bi(%d)\n",
1009 pRxLocal->local_psr_full.bits.psr_full,
1010 localLen, bufferIndex);
1011 DBG_RX_LEAVE(et131x_dbginfo);
1015 /* Get and fill the RFD. */
1016 spin_lock_irqsave(&etdev->RcvLock, flags);
1019 element = pRxLocal->RecvList.next;
1020 pMpRfd = (PMP_RFD) list_entry(element, MP_RFD, list_node);
1022 if (pMpRfd == NULL) {
1023 DBG_RX(et131x_dbginfo,
1024 "NULL RFD returned from RecvList via list_entry()\n");
1025 DBG_RX_LEAVE(et131x_dbginfo);
1026 spin_unlock_irqrestore(&etdev->RcvLock, flags);
1030 list_del(&pMpRfd->list_node);
1031 pRxLocal->nReadyRecv--;
1033 spin_unlock_irqrestore(&etdev->RcvLock, flags);
1035 pMpRfd->iBufferIndex = bufferIndex;
1036 pMpRfd->iRingIndex = ringIndex;
1038 /* In V1 silicon, there is a bug which screws up filtering of
1039 * runt packets. Therefore runt packet filtering is disabled
1040 * in the MAC and the packets are dropped here. They are
1041 * also counted here.
1043 if (localLen < (NIC_MIN_PACKET_SIZE + 4)) {
1044 etdev->Stats.other_errors++;
1049 if (etdev->ReplicaPhyLoopbk == 1) {
1050 pBufVa = pRxLocal->Fbr[ringIndex]->Va[bufferIndex];
1052 if (memcmp(&pBufVa[6], &etdev->CurrentAddress[0],
1054 if (memcmp(&pBufVa[42], "Replica packet",
1056 etdev->ReplicaPhyLoopbkPF = 1;
1059 DBG_WARNING(et131x_dbginfo,
1060 "pBufVa:\t%02x:%02x:%02x:%02x:%02x:%02x\n",
1061 pBufVa[6], pBufVa[7], pBufVa[8],
1062 pBufVa[9], pBufVa[10], pBufVa[11]);
1064 DBG_WARNING(et131x_dbginfo,
1065 "CurrentAddr:\t%02x:%02x:%02x:%02x:%02x:%02x\n",
1066 etdev->CurrentAddress[0],
1067 etdev->CurrentAddress[1],
1068 etdev->CurrentAddress[2],
1069 etdev->CurrentAddress[3],
1070 etdev->CurrentAddress[4],
1071 etdev->CurrentAddress[5]);
1074 /* Determine if this is a multicast packet coming in */
1075 if ((Word0.value & ALCATEL_MULTICAST_PKT) &&
1076 !(Word0.value & ALCATEL_BROADCAST_PKT)) {
1077 /* Promiscuous mode and Multicast mode are
1078 * not mutually exclusive as was first
1079 * thought. I guess Promiscuous is just
1080 * considered a super-set of the other
1081 * filters. Generally filter is 0x2b when in
1084 if ((etdev->PacketFilter & ET131X_PACKET_TYPE_MULTICAST)
1085 && !(etdev->PacketFilter & ET131X_PACKET_TYPE_PROMISCUOUS)
1086 && !(etdev->PacketFilter & ET131X_PACKET_TYPE_ALL_MULTICAST)) {
1087 pBufVa = pRxLocal->Fbr[ringIndex]->
1090 /* Loop through our list to see if the
1091 * destination address of this packet
1092 * matches one in our list.
1095 nIndex < etdev->MCAddressCount;
1098 etdev->MCList[nIndex][0]
1100 etdev->MCList[nIndex][1]
1102 etdev->MCList[nIndex][2]
1104 etdev->MCList[nIndex][3]
1106 etdev->MCList[nIndex][4]
1108 etdev->MCList[nIndex][5]) {
1113 /* If our index is equal to the number
1114 * of Multicast address we have, then
1115 * this means we did not find this
1116 * packet's matching address in our
1117 * list. Set the PacketSize to zero,
1118 * so we free our RFD when we return
1119 * from this function.
1121 if (nIndex == etdev->MCAddressCount)
1126 etdev->Stats.multircv++;
1127 } else if (Word0.value & ALCATEL_BROADCAST_PKT)
1128 etdev->Stats.brdcstrcv++;
1130 /* Not sure what this counter measures in
1131 * promiscuous mode. Perhaps we should check
1132 * the MAC address to see if it is directed
1133 * to us in promiscuous mode.
1135 etdev->Stats.unircv++;
1139 struct sk_buff *skb = NULL;
1141 /* pMpRfd->PacketSize = localLen - 4; */
1142 pMpRfd->PacketSize = localLen;
1144 skb = dev_alloc_skb(pMpRfd->PacketSize + 2);
1146 DBG_ERROR(et131x_dbginfo,
1147 "Couldn't alloc an SKB for Rx\n");
1148 DBG_RX_LEAVE(et131x_dbginfo);
1152 etdev->net_stats.rx_bytes += pMpRfd->PacketSize;
1154 memcpy(skb_put(skb, pMpRfd->PacketSize),
1155 pRxLocal->Fbr[ringIndex]->Va[bufferIndex],
1156 pMpRfd->PacketSize);
1158 skb->dev = etdev->netdev;
1159 skb->protocol = eth_type_trans(skb, etdev->netdev);
1160 skb->ip_summed = CHECKSUM_NONE;
1164 pMpRfd->PacketSize = 0;
1167 nic_return_rfd(etdev, pMpRfd);
1169 DBG_RX(et131x_dbginfo, "(1)\n");
1170 DBG_RX_LEAVE(et131x_dbginfo);
1175 * et131x_reset_recv - Reset the receive list
1176 * @etdev: pointer to our adapter
1178 * Assumption, Rcv spinlock has been acquired.
1180 void et131x_reset_recv(struct et131x_adapter *etdev)
1183 struct list_head *element;
1185 DBG_ENTER(et131x_dbginfo);
1187 DBG_ASSERT(!list_empty(&etdev->RxRing.RecvList));
1189 /* Take all the RFD's from the pending list, and stick them on the
1192 while (!list_empty(&etdev->RxRing.RecvPendingList)) {
1193 element = etdev->RxRing.RecvPendingList.next;
1195 pMpRfd = (PMP_RFD) list_entry(element, MP_RFD, list_node);
1197 list_move_tail(&pMpRfd->list_node, &etdev->RxRing.RecvList);
1200 DBG_LEAVE(et131x_dbginfo);
1204 * et131x_handle_recv_interrupt - Interrupt handler for receive processing
1205 * @etdev: pointer to our adapter
1207 * Assumption, Rcv spinlock has been acquired.
1209 void et131x_handle_recv_interrupt(struct et131x_adapter *etdev)
1211 PMP_RFD pMpRfd = NULL;
1212 struct sk_buff *PacketArray[NUM_PACKETS_HANDLED];
1213 PMP_RFD RFDFreeArray[NUM_PACKETS_HANDLED];
1214 uint32_t PacketArrayCount = 0;
1215 uint32_t PacketsToHandle;
1216 uint32_t PacketFreeCount = 0;
1217 bool TempUnfinishedRec = false;
1219 DBG_RX_ENTER(et131x_dbginfo);
1221 PacketsToHandle = NUM_PACKETS_HANDLED;
1223 /* Process up to available RFD's */
1224 while (PacketArrayCount < PacketsToHandle) {
1225 if (list_empty(&etdev->RxRing.RecvList)) {
1226 DBG_ASSERT(etdev->RxRing.nReadyRecv == 0);
1227 DBG_ERROR(et131x_dbginfo, "NO RFD's !!!!!!!!!!!!!\n");
1228 TempUnfinishedRec = true;
1232 pMpRfd = nic_rx_pkts(etdev);
1237 /* Do not receive any packets until a filter has been set.
1238 * Do not receive any packets until we have link.
1239 * If length is zero, return the RFD in order to advance the
1242 if ((!etdev->PacketFilter) ||
1243 (!MP_LINK_DETECTED(etdev)) ||
1244 (pMpRfd->PacketSize == 0)) {
1248 /* Increment the number of packets we received */
1249 etdev->Stats.ipackets++;
1251 /* Set the status on the packet, either resources or success */
1252 if (etdev->RxRing.nReadyRecv >= RFD_LOW_WATER_MARK) {
1253 /* Put this RFD on the pending list
1255 * NOTE: nic_rx_pkts() above is already returning the
1256 * RFD to the RecvList, so don't additionally do that
1258 * Besides, we don't really need (at this point) the
1259 * pending list anyway.
1262 RFDFreeArray[PacketFreeCount] = pMpRfd;
1265 DBG_WARNING(et131x_dbginfo,
1266 "RFD's are running out !!!!!!!!!!!!!\n");
1269 PacketArray[PacketArrayCount] = pMpRfd->Packet;
1273 if ((PacketArrayCount == NUM_PACKETS_HANDLED) || TempUnfinishedRec) {
1274 etdev->RxRing.UnfinishedReceives = true;
1275 writel(etdev->RegistryTxTimeInterval * NANO_IN_A_MICRO,
1276 &etdev->regs->global.watchdog_timer);
1278 /* Watchdog timer will disable itself if appropriate. */
1279 etdev->RxRing.UnfinishedReceives = false;
1282 DBG_RX_LEAVE(et131x_dbginfo);
1286 * NICReturnRFD - Recycle a RFD and put it back onto the receive list
1287 * @etdev: pointer to our adapter
1288 * @pMpRfd: pointer to the RFD
1290 void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD pMpRfd)
1292 struct _rx_ring_t *pRxLocal = &etdev->RxRing;
1293 struct _RXDMA_t __iomem *pRxDma = &etdev->regs->rxdma;
1294 uint16_t bi = pMpRfd->iBufferIndex;
1295 uint8_t ri = pMpRfd->iRingIndex;
1296 unsigned long flags;
1298 DBG_RX_ENTER(et131x_dbginfo);
1300 /* We don't use any of the OOB data besides status. Otherwise, we
1301 * need to clean up OOB data
1305 (ri == 0 && bi < pRxLocal->Fbr0NumEntries) ||
1307 (ri == 1 && bi < pRxLocal->Fbr1NumEntries)) {
1308 spin_lock_irqsave(&etdev->FbrLock, flags);
1311 PFBR_DESC_t pNextDesc =
1312 (PFBR_DESC_t) (pRxLocal->pFbr1RingVa) +
1313 pRxLocal->local_Fbr1_full.bits.val;
1315 /* Handle the Free Buffer Ring advancement here. Write
1316 * the PA / Buffer Index for the returned buffer into
1317 * the oldest (next to be freed)FBR entry
1319 pNextDesc->addr_hi = pRxLocal->Fbr[1]->PAHigh[bi];
1320 pNextDesc->addr_lo = pRxLocal->Fbr[1]->PALow[bi];
1321 pNextDesc->word2.value = bi;
1323 if (++pRxLocal->local_Fbr1_full.bits.val >
1324 (pRxLocal->Fbr1NumEntries - 1)) {
1325 pRxLocal->local_Fbr1_full.bits.val = 0;
1326 pRxLocal->local_Fbr1_full.bits.wrap ^= 1;
1329 writel(pRxLocal->local_Fbr1_full.value,
1330 &pRxDma->fbr1_full_offset.value);
1334 PFBR_DESC_t pNextDesc =
1335 (PFBR_DESC_t) pRxLocal->pFbr0RingVa +
1336 pRxLocal->local_Fbr0_full.bits.val;
1338 /* Handle the Free Buffer Ring advancement here. Write
1339 * the PA / Buffer Index for the returned buffer into
1340 * the oldest (next to be freed) FBR entry
1342 pNextDesc->addr_hi = pRxLocal->Fbr[0]->PAHigh[bi];
1343 pNextDesc->addr_lo = pRxLocal->Fbr[0]->PALow[bi];
1344 pNextDesc->word2.value = bi;
1346 if (++pRxLocal->local_Fbr0_full.bits.val >
1347 (pRxLocal->Fbr0NumEntries - 1)) {
1348 pRxLocal->local_Fbr0_full.bits.val = 0;
1349 pRxLocal->local_Fbr0_full.bits.wrap ^= 1;
1352 writel(pRxLocal->local_Fbr0_full.value,
1353 &pRxDma->fbr0_full_offset.value);
1356 spin_unlock_irqrestore(&etdev->FbrLock, flags);
1358 DBG_ERROR(et131x_dbginfo,
1359 "NICReturnRFD illegal Buffer Index returned\n");
1362 /* The processing on this RFD is done, so put it back on the tail of
1365 spin_lock_irqsave(&etdev->RcvLock, flags);
1366 list_add_tail(&pMpRfd->list_node, &pRxLocal->RecvList);
1367 pRxLocal->nReadyRecv++;
1368 spin_unlock_irqrestore(&etdev->RcvLock, flags);
1370 DBG_ASSERT(pRxLocal->nReadyRecv <= pRxLocal->NumRfd);
1371 DBG_RX_LEAVE(et131x_dbginfo);