3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright * 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et1310_phy.c - Routines for configuring and accessing the PHY
13 *------------------------------------------------------------------------------
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
19 * software indicates your acceptance of these terms and conditions. If you do
20 * not agree with these terms and conditions, do not use the software.
22 * Copyright * 2005 Agere Systems Inc.
23 * All rights reserved.
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
28 * . Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following Disclaimer as comments in the code as
30 * well as in the documentation and/or other materials provided with the
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
35 * and/or other materials provided with the distribution.
37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
43 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
47 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
48 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
49 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
51 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
58 #include "et131x_version.h"
59 #include "et131x_defs.h"
61 #include <linux/pci.h>
62 #include <linux/init.h>
63 #include <linux/module.h>
64 #include <linux/types.h>
65 #include <linux/kernel.h>
67 #include <linux/sched.h>
68 #include <linux/ptrace.h>
69 #include <linux/slab.h>
70 #include <linux/ctype.h>
71 #include <linux/string.h>
72 #include <linux/timer.h>
73 #include <linux/interrupt.h>
75 #include <linux/delay.h>
77 #include <linux/bitops.h>
78 #include <asm/system.h>
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/skbuff.h>
83 #include <linux/if_arp.h>
84 #include <linux/ioport.h>
85 #include <linux/random.h>
87 #include "et1310_phy.h"
89 #include "et131x_adapter.h"
91 #include "et1310_address_map.h"
92 #include "et1310_tx.h"
93 #include "et1310_rx.h"
97 /* Prototypes for functions with local scope */
98 static void et131x_xcvr_init(struct et131x_adapter *etdev);
101 * PhyMiRead - Read from the PHY through the MII Interface on the MAC
102 * @etdev: pointer to our private adapter structure
103 * @xcvrAddr: the address of the transciever
104 * @xcvrReg: the register to read
105 * @value: pointer to a 16-bit value in which the value will be stored
107 * Returns 0 on success, errno on failure (as defined in errno.h)
109 int PhyMiRead(struct et131x_adapter *etdev, u8 xcvrAddr,
110 u8 xcvrReg, u16 *value)
112 struct _MAC_t __iomem *mac = &etdev->regs->mac;
119 /* Save a local copy of the registers we are dealing with so we can
122 miiAddr = readl(&mac->mii_mgmt_addr);
123 miiCmd = readl(&mac->mii_mgmt_cmd);
125 /* Stop the current operation */
126 writel(0, &mac->mii_mgmt_cmd);
128 /* Set up the register we need to read from on the correct PHY */
129 writel(MII_ADDR(xcvrAddr, xcvrReg), &mac->mii_mgmt_addr);
131 /* Kick the read cycle off */
134 writel(0x1, &mac->mii_mgmt_cmd);
139 miiIndicator = readl(&mac->mii_mgmt_indicator);
140 } while ((miiIndicator & MGMT_WAIT) && delay < 50);
142 /* If we hit the max delay, we could not read the register */
144 dev_warn(&etdev->pdev->dev,
145 "xcvrReg 0x%08x could not be read\n", xcvrReg);
146 dev_warn(&etdev->pdev->dev, "status is 0x%08x\n",
152 /* If we hit here we were able to read the register and we need to
153 * return the value to the caller */
154 *value = readl(&mac->mii_mgmt_stat) & 0xFFFF;
156 /* Stop the read operation */
157 writel(0, &mac->mii_mgmt_cmd);
159 /* set the registers we touched back to the state at which we entered
162 writel(miiAddr, &mac->mii_mgmt_addr);
163 writel(miiCmd, &mac->mii_mgmt_cmd);
169 * MiWrite - Write to a PHY register through the MII interface of the MAC
170 * @etdev: pointer to our private adapter structure
171 * @xcvrReg: the register to read
172 * @value: 16-bit value to write
174 * FIXME: one caller in netdev still
176 * Return 0 on success, errno on failure (as defined in errno.h)
178 int MiWrite(struct et131x_adapter *etdev, u8 xcvrReg, u16 value)
180 struct _MAC_t __iomem *mac = &etdev->regs->mac;
182 u8 xcvrAddr = etdev->Stats.xcvr_addr;
188 /* Save a local copy of the registers we are dealing with so we can
191 miiAddr = readl(&mac->mii_mgmt_addr);
192 miiCmd = readl(&mac->mii_mgmt_cmd);
194 /* Stop the current operation */
195 writel(0, &mac->mii_mgmt_cmd);
197 /* Set up the register we need to write to on the correct PHY */
198 writel(MII_ADDR(xcvrAddr, xcvrReg), &mac->mii_mgmt_addr);
200 /* Add the value to write to the registers to the mac */
201 writel(value, &mac->mii_mgmt_ctrl);
207 miiIndicator = readl(&mac->mii_mgmt_indicator);
208 } while ((miiIndicator & MGMT_BUSY) && delay < 100);
210 /* If we hit the max delay, we could not write the register */
214 dev_warn(&etdev->pdev->dev,
215 "xcvrReg 0x%08x could not be written", xcvrReg);
216 dev_warn(&etdev->pdev->dev, "status is 0x%08x\n",
218 dev_warn(&etdev->pdev->dev, "command is 0x%08x\n",
219 readl(&mac->mii_mgmt_cmd));
221 MiRead(etdev, xcvrReg, &TempValue);
225 /* Stop the write operation */
226 writel(0, &mac->mii_mgmt_cmd);
228 /* set the registers we touched back to the state at which we entered
231 writel(miiAddr, &mac->mii_mgmt_addr);
232 writel(miiCmd, &mac->mii_mgmt_cmd);
238 * et131x_xcvr_find - Find the PHY ID
239 * @etdev: pointer to our private adapter structure
241 * Returns 0 on success, errno on failure (as defined in errno.h)
243 int et131x_xcvr_find(struct et131x_adapter *etdev)
250 /* We need to get xcvr id and address we just get the first one */
251 for (xcvr_addr = 0; xcvr_addr < 32; xcvr_addr++) {
252 /* Read the ID from the PHY */
253 PhyMiRead(etdev, xcvr_addr,
254 (u8) offsetof(MI_REGS_t, idr1),
256 PhyMiRead(etdev, xcvr_addr,
257 (u8) offsetof(MI_REGS_t, idr2),
260 xcvr_id = (u32) ((idr1.value << 16) | idr2.value);
262 if (idr1.value != 0 && idr1.value != 0xffff) {
263 etdev->Stats.xcvr_id = xcvr_id;
264 etdev->Stats.xcvr_addr = xcvr_addr;
271 void ET1310_PhyReset(struct et131x_adapter *etdev)
273 MiWrite(etdev, PHY_CONTROL, 0x8000);
277 * ET1310_PhyPowerDown - PHY power control
278 * @etdev: device to control
279 * @down: true for off/false for back on
281 * one hundred, ten, one thousand megs
282 * How would you like to have your LAN accessed
283 * Can't you see that this code processed
284 * Phy power, phy power..
287 void ET1310_PhyPowerDown(struct et131x_adapter *etdev, bool down)
291 MiRead(etdev, PHY_CONTROL, &data);
292 data &= ~0x0800; /* Power UP */
293 if (down) /* Power DOWN */
295 MiWrite(etdev, PHY_CONTROL, data);
299 * ET130_PhyAutoNEg - autonegotiate control
300 * @etdev: device to control
301 * @enabe: autoneg on/off
303 * Set up the autonegotiation state according to whether we will be
304 * negotiating the state or forcing a speed.
307 static void ET1310_PhyAutoNeg(struct et131x_adapter *etdev, bool enable)
311 MiRead(etdev, PHY_CONTROL, &data);
312 data &= ~0x1000; /* Autonegotiation OFF */
314 data |= 0x1000; /* Autonegotiation ON */
315 MiWrite(etdev, PHY_CONTROL, data);
319 * ET130_PhyDuplexMode - duplex control
320 * @etdev: device to control
321 * @duplex: duplex on/off
323 * Set up the duplex state on the PHY
326 static void ET1310_PhyDuplexMode(struct et131x_adapter *etdev, u16 duplex)
330 MiRead(etdev, PHY_CONTROL, &data);
331 data &= ~0x100; /* Set Half Duplex */
332 if (duplex == TRUEPHY_DUPLEX_FULL)
333 data |= 0x100; /* Set Full Duplex */
334 MiWrite(etdev, PHY_CONTROL, data);
338 * ET130_PhySpeedSelect - speed control
339 * @etdev: device to control
340 * @duplex: duplex on/off
342 * Set the speed of our PHY.
345 static void ET1310_PhySpeedSelect(struct et131x_adapter *etdev, u16 speed)
348 static const u16 bits[3]={0x0000, 0x2000, 0x0040};
350 /* Read the PHY control register */
351 MiRead(etdev, PHY_CONTROL, &data);
352 /* Clear all Speed settings (Bits 6, 13) */
354 /* Write back the new speed */
355 MiWrite(etdev, PHY_CONTROL, data | bits[speed]);
359 * ET1310_PhyLinkStatus - read link state
360 * @etdev: device to read
361 * @link_status: reported link state
362 * @autoneg: reported autonegotiation state (complete/incomplete/disabled)
363 * @linkspeed: returnedlink speed in use
364 * @duplex_mode: reported half/full duplex state
365 * @mdi_mdix: not yet working
366 * @masterslave: report whether we are master or slave
367 * @polarity: link polarity
369 * I can read your lan like a magazine
371 * I know your link speed
372 * I see all the setting that you'd rather keep
375 static void ET1310_PhyLinkStatus(struct et131x_adapter *etdev,
381 u32 *masterslave, u32 *polarity)
385 u16 vmi_phystatus = 0;
388 MiRead(etdev, PHY_STATUS, &mistatus);
389 MiRead(etdev, PHY_1000_STATUS, &is1000BaseT);
390 MiRead(etdev, PHY_PHY_STATUS, &vmi_phystatus);
391 MiRead(etdev, PHY_CONTROL, &control);
393 *link_status = (vmi_phystatus & 0x0040) ? 1 : 0;
394 *autoneg = (control & 0x1000) ? ((vmi_phystatus & 0x0020) ?
395 TRUEPHY_ANEG_COMPLETE :
396 TRUEPHY_ANEG_NOT_COMPLETE) :
397 TRUEPHY_ANEG_DISABLED;
398 *linkspeed = (vmi_phystatus & 0x0300) >> 8;
399 *duplex_mode = (vmi_phystatus & 0x0080) >> 7;
400 /* NOTE: Need to complete this */
403 *masterslave = (is1000BaseT & 0x4000) ?
404 TRUEPHY_CFG_MASTER : TRUEPHY_CFG_SLAVE;
405 *polarity = (vmi_phystatus & 0x0400) ?
406 TRUEPHY_POLARITY_INVERTED : TRUEPHY_POLARITY_NORMAL;
409 static void ET1310_PhyAndOrReg(struct et131x_adapter *etdev,
410 u16 regnum, u16 andMask, u16 orMask)
414 MiRead(etdev, regnum, ®);
417 MiWrite(etdev, regnum, reg);
420 /* Still used from _mac for BIT_READ */
421 void ET1310_PhyAccessMiBit(struct et131x_adapter *etdev, u16 action,
422 u16 regnum, u16 bitnum, u8 *value)
425 u16 mask = 0x0001 << bitnum;
427 /* Read the requested register */
428 MiRead(etdev, regnum, ®);
431 case TRUEPHY_BIT_READ:
432 *value = (reg & mask) >> bitnum;
435 case TRUEPHY_BIT_SET:
436 MiWrite(etdev, regnum, reg | mask);
439 case TRUEPHY_BIT_CLEAR:
440 MiWrite(etdev, regnum, reg & ~mask);
448 void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *etdev,
453 /* Read the PHY 1000 Base-T Control Register */
454 MiRead(etdev, PHY_1000_CONTROL, &data);
460 case TRUEPHY_ADV_DUPLEX_NONE:
461 /* Duplex already cleared, do nothing */
464 case TRUEPHY_ADV_DUPLEX_FULL:
469 case TRUEPHY_ADV_DUPLEX_HALF:
474 case TRUEPHY_ADV_DUPLEX_BOTH:
480 /* Write back advertisement */
481 MiWrite(etdev, PHY_1000_CONTROL, data);
484 static void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *etdev,
489 /* Read the Autonegotiation Register (10/100) */
490 MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data);
496 case TRUEPHY_ADV_DUPLEX_NONE:
497 /* Duplex already cleared, do nothing */
500 case TRUEPHY_ADV_DUPLEX_FULL:
505 case TRUEPHY_ADV_DUPLEX_HALF:
510 case TRUEPHY_ADV_DUPLEX_BOTH:
517 /* Write back advertisement */
518 MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data);
521 static void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *etdev,
526 /* Read the Autonegotiation Register (10/100) */
527 MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data);
533 case TRUEPHY_ADV_DUPLEX_NONE:
534 /* Duplex already cleared, do nothing */
537 case TRUEPHY_ADV_DUPLEX_FULL:
542 case TRUEPHY_ADV_DUPLEX_HALF:
547 case TRUEPHY_ADV_DUPLEX_BOTH:
554 /* Write back advertisement */
555 MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data);
559 * et131x_setphy_normal - Set PHY for normal operation.
560 * @etdev: pointer to our private adapter structure
562 * Used by Power Management to force the PHY into 10 Base T half-duplex mode,
563 * when going to D3 in WOL mode. Also used during initialization to set the
564 * PHY for normal operation.
566 void et131x_setphy_normal(struct et131x_adapter *etdev)
568 /* Make sure the PHY is powered up */
569 ET1310_PhyPowerDown(etdev, 0);
570 et131x_xcvr_init(etdev);
575 * et131x_xcvr_init - Init the phy if we are setting it into force mode
576 * @etdev: pointer to our private adapter structure
579 static void et131x_xcvr_init(struct et131x_adapter *etdev)
585 /* Zero out the adapter structure variable representing BMSR */
586 etdev->Bmsr.value = 0;
588 MiRead(etdev, (u8) offsetof(MI_REGS_t, isr), &isr.value);
589 MiRead(etdev, (u8) offsetof(MI_REGS_t, imr), &imr.value);
591 /* Set the link status interrupt only. Bad behavior when link status
592 * and auto neg are set, we run into a nested interrupt problem
594 imr.bits.int_en = 0x1;
595 imr.bits.link_status = 0x1;
596 imr.bits.autoneg_status = 0x1;
598 MiWrite(etdev, (u8) offsetof(MI_REGS_t, imr), imr.value);
600 /* Set the LED behavior such that LED 1 indicates speed (off =
601 * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
602 * link and activity (on for link, blink off for activity).
604 * NOTE: Some customizations have been added here for specific
605 * vendors; The LED behavior is now determined by vendor data in the
606 * EEPROM. However, the above description is the default.
608 if ((etdev->eepromData[1] & 0x4) == 0) {
609 MiRead(etdev, (u8) offsetof(MI_REGS_t, lcr2),
611 if ((etdev->eepromData[1] & 0x8) == 0)
612 lcr2.bits.led_tx_rx = 0x3;
614 lcr2.bits.led_tx_rx = 0x4;
615 lcr2.bits.led_link = 0xa;
616 MiWrite(etdev, (u8) offsetof(MI_REGS_t, lcr2),
620 /* Determine if we need to go into a force mode and set it */
621 if (etdev->AiForceSpeed == 0 && etdev->AiForceDpx == 0) {
622 if (etdev->RegistryFlowControl == TxOnly ||
623 etdev->RegistryFlowControl == Both)
624 ET1310_PhyAccessMiBit(etdev,
625 TRUEPHY_BIT_SET, 4, 11, NULL);
627 ET1310_PhyAccessMiBit(etdev,
628 TRUEPHY_BIT_CLEAR, 4, 11, NULL);
630 if (etdev->RegistryFlowControl == Both)
631 ET1310_PhyAccessMiBit(etdev,
632 TRUEPHY_BIT_SET, 4, 10, NULL);
634 ET1310_PhyAccessMiBit(etdev,
635 TRUEPHY_BIT_CLEAR, 4, 10, NULL);
637 /* Set the phy to autonegotiation */
638 ET1310_PhyAutoNeg(etdev, true);
640 /* NOTE - Do we need this? */
641 ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_SET, 0, 9, NULL);
645 ET1310_PhyAutoNeg(etdev, false);
647 /* Set to the correct force mode. */
648 if (etdev->AiForceDpx != 1) {
649 if (etdev->RegistryFlowControl == TxOnly ||
650 etdev->RegistryFlowControl == Both)
651 ET1310_PhyAccessMiBit(etdev,
652 TRUEPHY_BIT_SET, 4, 11, NULL);
654 ET1310_PhyAccessMiBit(etdev,
655 TRUEPHY_BIT_CLEAR, 4, 11, NULL);
657 if (etdev->RegistryFlowControl == Both)
658 ET1310_PhyAccessMiBit(etdev,
659 TRUEPHY_BIT_SET, 4, 10, NULL);
661 ET1310_PhyAccessMiBit(etdev,
662 TRUEPHY_BIT_CLEAR, 4, 10, NULL);
664 ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_CLEAR, 4, 10, NULL);
665 ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_CLEAR, 4, 11, NULL);
667 ET1310_PhyPowerDown(etdev, 1);
668 switch (etdev->AiForceSpeed) {
670 /* First we need to turn off all other advertisement */
671 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
672 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
673 if (etdev->AiForceDpx == 1) {
674 /* Set our advertise values accordingly */
675 ET1310_PhyAdvertise10BaseT(etdev,
676 TRUEPHY_ADV_DUPLEX_HALF);
677 } else if (etdev->AiForceDpx == 2) {
678 /* Set our advertise values accordingly */
679 ET1310_PhyAdvertise10BaseT(etdev,
680 TRUEPHY_ADV_DUPLEX_FULL);
682 /* Disable autoneg */
683 ET1310_PhyAutoNeg(etdev, false);
684 /* Disable rest of the advertisements */
685 ET1310_PhyAdvertise10BaseT(etdev,
686 TRUEPHY_ADV_DUPLEX_NONE);
688 ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_10MBPS);
689 /* Force Full duplex */
690 ET1310_PhyDuplexMode(etdev, TRUEPHY_DUPLEX_FULL);
694 /* first we need to turn off all other advertisement */
695 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
696 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
697 if (etdev->AiForceDpx == 1) {
698 /* Set our advertise values accordingly */
699 ET1310_PhyAdvertise100BaseT(etdev,
700 TRUEPHY_ADV_DUPLEX_HALF);
702 ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_100MBPS);
703 } else if (etdev->AiForceDpx == 2) {
704 /* Set our advertise values accordingly */
705 ET1310_PhyAdvertise100BaseT(etdev,
706 TRUEPHY_ADV_DUPLEX_FULL);
708 /* Disable autoneg */
709 ET1310_PhyAutoNeg(etdev, false);
710 /* Disable other advertisement */
711 ET1310_PhyAdvertise100BaseT(etdev,
712 TRUEPHY_ADV_DUPLEX_NONE);
714 ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_100MBPS);
715 /* Force Full duplex */
716 ET1310_PhyDuplexMode(etdev, TRUEPHY_DUPLEX_FULL);
720 /* first we need to turn off all other advertisement */
721 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
722 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
723 /* set our advertise values accordingly */
724 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL);
727 ET1310_PhyPowerDown(etdev, 0);
730 void et131x_Mii_check(struct et131x_adapter *etdev,
731 MI_BMSR_t bmsr, MI_BMSR_t bmsr_ints)
742 if (bmsr_ints.bits.link_status) {
743 if (bmsr.bits.link_status) {
744 etdev->PoMgmt.TransPhyComaModeOnBoot = 20;
746 /* Update our state variables and indicate the
749 spin_lock_irqsave(&etdev->Lock, flags);
751 etdev->MediaState = NETIF_STATUS_MEDIA_CONNECT;
752 etdev->Flags &= ~fMP_ADAPTER_LINK_DETECTION;
754 spin_unlock_irqrestore(&etdev->Lock, flags);
756 netif_carrier_on(etdev->netdev);
758 dev_warn(&etdev->pdev->dev,
759 "Link down - cable problem ?\n");
761 if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) {
762 /* NOTE - Is there a way to query this without
764 * && TRU_QueryCoreType(etdev->hTruePhy, 0) == EMI_TRUEPHY_A13O) {
768 MiRead(etdev, 0x12, &Register18);
769 MiWrite(etdev, 0x12, Register18 | 0x4);
770 MiWrite(etdev, 0x10, Register18 | 0x8402);
771 MiWrite(etdev, 0x11, Register18 | 511);
772 MiWrite(etdev, 0x12, Register18);
775 /* For the first N seconds of life, we are in "link
776 * detection" When we are in this state, we should
777 * only report "connected". When the LinkDetection
778 * Timer expires, we can report disconnected (handled
779 * in the LinkDetectionDPC).
781 if (!(etdev->Flags & fMP_ADAPTER_LINK_DETECTION) ||
782 (etdev->MediaState == NETIF_STATUS_MEDIA_DISCONNECT)) {
783 spin_lock_irqsave(&etdev->Lock, flags);
785 NETIF_STATUS_MEDIA_DISCONNECT;
786 spin_unlock_irqrestore(&etdev->Lock,
789 netif_carrier_off(etdev->netdev);
792 etdev->linkspeed = 0;
793 etdev->duplex_mode = 0;
795 /* Free the packets being actively sent & stopped */
796 et131x_free_busy_send_packets(etdev);
798 /* Re-initialize the send structures */
799 et131x_init_send(etdev);
801 /* Reset the RFD list and re-start RU */
802 et131x_reset_recv(etdev);
805 * Bring the device back to the state it was during
806 * init prior to autonegotiation being complete. This
807 * way, when we get the auto-neg complete interrupt,
808 * we can complete init by calling ConfigMacREGS2.
810 et131x_soft_reset(etdev);
812 /* Setup ET1310 as per the documentation */
813 et131x_adapter_setup(etdev);
815 /* Setup the PHY into coma mode until the cable is
818 if (etdev->RegistryPhyComa == 1)
819 EnablePhyComa(etdev);
823 if (bmsr_ints.bits.auto_neg_complete ||
824 (etdev->AiForceDpx == 3 && bmsr_ints.bits.link_status)) {
825 if (bmsr.bits.auto_neg_complete || etdev->AiForceDpx == 3) {
826 ET1310_PhyLinkStatus(etdev,
827 &link_status, &autoneg_status,
828 &speed, &duplex, &mdi_mdix,
829 &masterslave, &polarity);
831 etdev->linkspeed = speed;
832 etdev->duplex_mode = duplex;
834 etdev->PoMgmt.TransPhyComaModeOnBoot = 20;
836 if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) {
838 * NOTE - Is there a way to query this without
840 * && TRU_QueryCoreType(etdev->hTruePhy, 0)== EMI_TRUEPHY_A13O) {
844 MiRead(etdev, 0x12, &Register18);
845 MiWrite(etdev, 0x12, Register18 | 0x4);
846 MiWrite(etdev, 0x10, Register18 | 0x8402);
847 MiWrite(etdev, 0x11, Register18 | 511);
848 MiWrite(etdev, 0x12, Register18);
851 ConfigFlowControl(etdev);
853 if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS &&
854 etdev->RegistryJumboPacket > 2048)
855 ET1310_PhyAndOrReg(etdev, 0x16, 0xcfff,
858 SetRxDmaTimer(etdev);
859 ConfigMACRegs2(etdev);
865 * The routines which follow provide low-level access to the PHY, and are used
866 * primarily by the routines above (although there are a few places elsewhere
867 * in the driver where this level of access is required).
870 static const u16 ConfigPhy[25][2] = {
871 /* Reg Value Register */
873 {0x880B, 0x0926}, /* AfeIfCreg4B1000Msbs */
874 {0x880C, 0x0926}, /* AfeIfCreg4B100Msbs */
875 {0x880D, 0x0926}, /* AfeIfCreg4B10Msbs */
877 {0x880E, 0xB4D3}, /* AfeIfCreg4B1000Lsbs */
878 {0x880F, 0xB4D3}, /* AfeIfCreg4B100Lsbs */
879 {0x8810, 0xB4D3}, /* AfeIfCreg4B10Lsbs */
881 {0x8805, 0xB03E}, /* AfeIfCreg3B1000Msbs */
882 {0x8806, 0xB03E}, /* AfeIfCreg3B100Msbs */
883 {0x8807, 0xFF00}, /* AfeIfCreg3B10Msbs */
885 {0x8808, 0xE090}, /* AfeIfCreg3B1000Lsbs */
886 {0x8809, 0xE110}, /* AfeIfCreg3B100Lsbs */
887 {0x880A, 0x0000}, /* AfeIfCreg3B10Lsbs */
889 {0x300D, 1}, /* DisableNorm */
891 {0x280C, 0x0180}, /* LinkHoldEnd */
893 {0x1C21, 0x0002}, /* AlphaM */
895 {0x3821, 6}, /* FfeLkgTx0 */
896 {0x381D, 1}, /* FfeLkg1g4 */
897 {0x381E, 1}, /* FfeLkg1g5 */
898 {0x381F, 1}, /* FfeLkg1g6 */
899 {0x3820, 1}, /* FfeLkg1g7 */
901 {0x8402, 0x01F0}, /* Btinact */
902 {0x800E, 20}, /* LftrainTime */
903 {0x800F, 24}, /* DvguardTime */
904 {0x8010, 46}, /* IdlguardTime */
910 /* condensed version of the phy initialization routine */
911 void ET1310_PhyInit(struct et131x_adapter *etdev)
918 /* get the identity (again ?) */
919 MiRead(etdev, PHY_ID_1, &data);
920 MiRead(etdev, PHY_ID_2, &data);
922 /* what does this do/achieve ? */
923 MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
924 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0006);
926 /* read modem register 0402, should I do something with the return
928 MiWrite(etdev, PHY_INDEX_REG, 0x0402);
929 MiRead(etdev, PHY_DATA_REG, &data);
931 /* what does this do/achieve ? */
932 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
934 /* get the identity (again ?) */
935 MiRead(etdev, PHY_ID_1, &data);
936 MiRead(etdev, PHY_ID_2, &data);
938 /* what does this achieve ? */
939 MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
940 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0006);
942 /* read modem register 0402, should I do something with
944 MiWrite(etdev, PHY_INDEX_REG, 0x0402);
945 MiRead(etdev, PHY_DATA_REG, &data);
947 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
949 /* what does this achieve (should return 0x1040) */
950 MiRead(etdev, PHY_CONTROL, &data);
951 MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
952 MiWrite(etdev, PHY_CONTROL, 0x1840);
954 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0007);
956 /* here the writing of the array starts.... */
958 while (ConfigPhy[index][0] != 0x0000) {
960 MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[index][0]);
961 MiWrite(etdev, PHY_DATA_REG, ConfigPhy[index][1]);
964 MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[index][0]);
965 MiRead(etdev, PHY_DATA_REG, &data);
967 /* do a check on the value read back ? */
970 /* here the writing of the array ends... */
972 MiRead(etdev, PHY_CONTROL, &data); /* 0x1840 */
973 MiRead(etdev, PHY_MPHY_CONTROL_REG, &data);/* should read 0007 */
974 MiWrite(etdev, PHY_CONTROL, 0x1040);
975 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);