3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et1310_eeprom.c - Code used to access the device's EEPROM
13 *------------------------------------------------------------------------------
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
19 * software indicates your acceptance of these terms and conditions. If you do
20 * not agree with these terms and conditions, do not use the software.
22 * Copyright © 2005 Agere Systems Inc.
23 * All rights reserved.
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
28 * . Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following Disclaimer as comments in the code as
30 * well as in the documentation and/or other materials provided with the
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
35 * and/or other materials provided with the distribution.
37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
43 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
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46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
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58 #include "et131x_version.h"
59 #include "et131x_defs.h"
61 #include <linux/pci.h>
62 #include <linux/init.h>
63 #include <linux/module.h>
64 #include <linux/types.h>
65 #include <linux/kernel.h>
67 #include <linux/sched.h>
68 #include <linux/ptrace.h>
69 #include <linux/slab.h>
70 #include <linux/ctype.h>
71 #include <linux/string.h>
72 #include <linux/timer.h>
73 #include <linux/interrupt.h>
75 #include <linux/delay.h>
76 #include <linux/bitops.h>
78 #include <asm/system.h>
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/skbuff.h>
83 #include <linux/if_arp.h>
84 #include <linux/ioport.h>
86 #include "et1310_phy.h"
87 #include "et131x_adapter.h"
94 /* LBCIF Register Groups (addressed via 32-bit offsets) */
95 #define LBCIF_DWORD0_GROUP 0xAC
96 #define LBCIF_DWORD1_GROUP 0xB0
98 /* LBCIF Registers (addressed via 8-bit offsets) */
99 #define LBCIF_ADDRESS_REGISTER 0xAC
100 #define LBCIF_DATA_REGISTER 0xB0
101 #define LBCIF_CONTROL_REGISTER 0xB1
102 #define LBCIF_STATUS_REGISTER 0xB2
104 /* LBCIF Control Register Bits */
105 #define LBCIF_CONTROL_SEQUENTIAL_READ 0x01
106 #define LBCIF_CONTROL_PAGE_WRITE 0x02
107 #define LBCIF_CONTROL_EEPROM_RELOAD 0x08
108 #define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20
109 #define LBCIF_CONTROL_I2C_WRITE 0x40
110 #define LBCIF_CONTROL_LBCIF_ENABLE 0x80
112 /* LBCIF Status Register Bits */
113 #define LBCIF_STATUS_PHY_QUEUE_AVAIL 0x01
114 #define LBCIF_STATUS_I2C_IDLE 0x02
115 #define LBCIF_STATUS_ACK_ERROR 0x04
116 #define LBCIF_STATUS_GENERAL_ERROR 0x08
117 #define LBCIF_STATUS_CHECKSUM_ERROR 0x40
118 #define LBCIF_STATUS_EEPROM_PRESENT 0x80
120 /* Miscellaneous Constraints */
121 #define MAX_NUM_REGISTER_POLLS 1000
122 #define MAX_NUM_WRITE_RETRIES 2
124 static int eeprom_wait_ready(struct pci_dev *pdev, u32 *status)
130 * 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
131 * bits 7,1:0 both equal to 1, at least once after reset.
132 * Subsequent operations need only to check that bits 1:0 are equal
133 * to 1 prior to starting a single byte read/write
136 for (i = 0; i < MAX_NUM_REGISTER_POLLS; i++) {
137 /* Read registers grouped in DWORD1 */
138 if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP, ®))
141 /* I2C idle and Phy Queue Avail both true */
142 if ((reg & 0x3000) == 0x3000) {
153 * eeprom_write - Write a byte to the ET1310's EEPROM
154 * @etdev: pointer to our private adapter structure
155 * @addr: the address to write
156 * @data: the value to write
158 * Returns 1 for a successful write.
160 static int eeprom_write(struct et131x_adapter *etdev, u32 addr, u8 data)
162 struct pci_dev *pdev = etdev->pdev;
172 * For an EEPROM, an I2C single byte write is defined as a START
173 * condition followed by the device address, EEPROM address, one byte
174 * of data and a STOP condition. The STOP condition will trigger the
175 * EEPROM's internally timed write cycle to the nonvolatile memory.
176 * All inputs are disabled during this write cycle and the EEPROM will
177 * not respond to any access until the internal write is complete.
180 err = eeprom_wait_ready(pdev, NULL);
185 * 2. Write to the LBCIF Control Register: bit 7=1, bit 6=1, bit 3=0,
186 * and bits 1:0 both =0. Bit 5 should be set according to the
187 * type of EEPROM being accessed (1=two byte addressing, 0=one
190 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
191 LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE))
196 /* Prepare EEPROM address for Step 3 */
198 for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) {
199 /* Write the address to the LBCIF Address Register */
200 if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
203 * Write the data to the LBCIF Data Register (the I2C write
206 if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER, data))
209 * Monitor bit 1:0 of the LBCIF Status Register. When bits
210 * 1:0 are both equal to 1, the I2C write has completed and the
211 * internal write cycle of the EEPROM is about to start.
212 * (bits 1:0 = 01 is a legal state while waiting from both
213 * equal to 1, but bits 1:0 = 10 is invalid and implies that
214 * something is broken).
216 err = eeprom_wait_ready(pdev, &status);
221 * Check bit 3 of the LBCIF Status Register. If equal to 1,
222 * an error has occurred.Don't break here if we are revision
223 * 1, this is so we do a blind write for load bug.
225 if ((status & LBCIF_STATUS_GENERAL_ERROR)
226 && etdev->pdev->revision == 0)
230 * Check bit 2 of the LBCIF Status Register. If equal to 1 an
231 * ACK error has occurred on the address phase of the write.
232 * This could be due to an actual hardware failure or the
233 * EEPROM may still be in its internal write cycle from a
234 * previous write. This write operation was ignored and must be
237 if (status & LBCIF_STATUS_ACK_ERROR) {
239 * This could be due to an actual hardware failure
240 * or the EEPROM may still be in its internal write
241 * cycle from a previous write. This write operation
242 * was ignored and must be repeated later.
253 * Set bit 6 of the LBCIF Control Register = 0.
258 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
259 LBCIF_CONTROL_LBCIF_ENABLE))
262 /* Do read until internal ACK_ERROR goes away meaning write
266 pci_write_config_dword(pdev,
267 LBCIF_ADDRESS_REGISTER,
270 pci_read_config_dword(pdev,
271 LBCIF_DATA_REGISTER, &val);
272 } while ((val & 0x00010000) == 0);
273 } while (val & 0x00040000);
275 if ((val & 0xFF00) != 0xC000 || index == 10000)
279 return writeok ? 0 : -EIO;
283 * eeprom_read - Read a byte from the ET1310's EEPROM
284 * @etdev: pointer to our private adapter structure
285 * @addr: the address from which to read
286 * @pdata: a pointer to a byte in which to store the value of the read
287 * @eeprom_id: the ID of the EEPROM
288 * @addrmode: how the EEPROM is to be accessed
290 * Returns 1 for a successful read
292 static int eeprom_read(struct et131x_adapter *etdev, u32 addr, u8 *pdata)
294 struct pci_dev *pdev = etdev->pdev;
299 * A single byte read is similar to the single byte write, with the
300 * exception of the data flow:
303 err = eeprom_wait_ready(pdev, NULL);
307 * Write to the LBCIF Control Register: bit 7=1, bit 6=0, bit 3=0,
308 * and bits 1:0 both =0. Bit 5 should be set according to the type
309 * of EEPROM being accessed (1=two byte addressing, 0=one byte
312 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
313 LBCIF_CONTROL_LBCIF_ENABLE))
316 * Write the address to the LBCIF Address Register (I2C read will
319 if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
322 * Monitor bit 0 of the LBCIF Status Register. When = 1, I2C read
323 * is complete. (if bit 1 =1 and bit 0 stays = 0, a hardware failure
326 err = eeprom_wait_ready(pdev, &status);
330 * Regardless of error status, read data byte from LBCIF Data
335 * Check bit 2 of the LBCIF Status Register. If = 1,
336 * then an error has occurred.
338 return (status & LBCIF_STATUS_ACK_ERROR) ? -EIO : 0;
341 int et131x_init_eeprom(struct et131x_adapter *etdev)
343 struct pci_dev *pdev = etdev->pdev;
346 /* We first need to check the EEPROM Status code located at offset
347 * 0xB2 of config space
349 pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS,
352 /* THIS IS A WORKAROUND:
353 * I need to call this function twice to get my card in a
354 * LG M1 Express Dual running. I tried also a msleep before this
355 * function, because I thougth there could be some time condidions
356 * but it didn't work. Call the whole function twice also work.
358 if (pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus)) {
360 "Could not read PCI config space for EEPROM Status\n");
364 /* Determine if the error(s) we care about are present. If they are
365 * present we need to fail.
367 if (eestatus & 0x4C) {
368 int write_failed = 0;
369 if (pdev->revision == 0x01) {
371 static const u8 eedata[4] = { 0xFE, 0x13, 0x10, 0xFF };
373 /* Re-write the first 4 bytes if we have an eeprom
374 * present and the revision id is 1, this fixes the
375 * corruption seen with 1310 B Silicon
377 for (i = 0; i < 3; i++)
378 if (eeprom_write(etdev, i, eedata[i]) < 0)
381 if (pdev->revision != 0x01 || write_failed) {
383 "Fatal EEPROM Status Error - 0x%04x\n", eestatus);
385 /* This error could mean that there was an error
386 * reading the eeprom or that the eeprom doesn't exist.
387 * We will treat each case the same and not try to gather
388 * additional information that normally would come from the
389 * eeprom, like MAC Address
391 etdev->has_eeprom = 0;
395 etdev->has_eeprom = 1;
397 /* Read the EEPROM for information regarding LED behavior. Refer to
398 * ET1310_phy.c, et131x_xcvr_init(), for its use.
400 eeprom_read(etdev, 0x70, &etdev->eepromData[0]);
401 eeprom_read(etdev, 0x71, &etdev->eepromData[1]);
403 if (etdev->eepromData[0] != 0xcd)
404 /* Disable all optional features */
405 etdev->eepromData[1] = 0x00;