4 * Xilinx SPI controller driver (master mode only)
6 * Author: MontaVista Software, Inc.
9 * 2002-2007 (c) MontaVista Software, Inc. This file is licensed under the
10 * terms of the GNU General Public License version 2. This program is licensed
11 * "as is" without any warranty of any kind, whether express or implied.
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
18 #include <linux/spi/spi.h>
19 #include <linux/spi/spi_bitbang.h>
22 #include "xilinx_spi.h"
23 #include <linux/spi/xilinx_spi.h>
25 #define XILINX_SPI_NAME "xilinx_spi"
27 /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
28 * Product Specification", DS464
30 #define XSPI_CR_OFFSET 0x62 /* 16-bit Control Register */
32 #define XSPI_CR_ENABLE 0x02
33 #define XSPI_CR_MASTER_MODE 0x04
34 #define XSPI_CR_CPOL 0x08
35 #define XSPI_CR_CPHA 0x10
36 #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL)
37 #define XSPI_CR_TXFIFO_RESET 0x20
38 #define XSPI_CR_RXFIFO_RESET 0x40
39 #define XSPI_CR_MANUAL_SSELECT 0x80
40 #define XSPI_CR_TRANS_INHIBIT 0x100
42 #define XSPI_SR_OFFSET 0x67 /* 8-bit Status Register */
44 #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
45 #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
46 #define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */
47 #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
48 #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
50 #define XSPI_TXD_OFFSET 0x6b /* 8-bit Data Transmit Register */
51 #define XSPI_RXD_OFFSET 0x6f /* 8-bit Data Receive Register */
53 #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
55 /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
56 * IPIF registers are 32 bit
58 #define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */
59 #define XIPIF_V123B_GINTR_ENABLE 0x80000000
61 #define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */
62 #define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */
64 #define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */
65 #define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while
67 #define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */
68 #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */
69 #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */
70 #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */
72 #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
73 #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
76 /* bitbang has to be first */
77 struct spi_bitbang bitbang;
78 struct completion done;
79 struct resource mem; /* phys mem */
80 void __iomem *regs; /* virt. address of the control registers */
84 u32 speed_hz; /* SCK has a fixed frequency of speed_hz Hz */
86 u8 *rx_ptr; /* pointer in the Tx buffer */
87 const u8 *tx_ptr; /* pointer in the Rx buffer */
88 int remaining_bytes; /* the number of bytes left to transfer */
91 static void xspi_init_hw(void __iomem *regs_base)
93 /* Reset the SPI device */
94 out_be32(regs_base + XIPIF_V123B_RESETR_OFFSET,
95 XIPIF_V123B_RESET_MASK);
96 /* Disable all the interrupts just in case */
97 out_be32(regs_base + XIPIF_V123B_IIER_OFFSET, 0);
98 /* Enable the global IPIF interrupt */
99 out_be32(regs_base + XIPIF_V123B_DGIER_OFFSET,
100 XIPIF_V123B_GINTR_ENABLE);
101 /* Deselect the slave on the SPI bus */
102 out_be32(regs_base + XSPI_SSR_OFFSET, 0xffff);
103 /* Disable the transmitter, enable Manual Slave Select Assertion,
104 * put SPI controller into master mode, and enable it */
105 out_be16(regs_base + XSPI_CR_OFFSET,
106 XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT
107 | XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE);
110 static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
112 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
114 if (is_on == BITBANG_CS_INACTIVE) {
115 /* Deselect the slave on the SPI bus */
116 out_be32(xspi->regs + XSPI_SSR_OFFSET, 0xffff);
117 } else if (is_on == BITBANG_CS_ACTIVE) {
118 /* Set the SPI clock phase and polarity */
119 u16 cr = in_be16(xspi->regs + XSPI_CR_OFFSET)
120 & ~XSPI_CR_MODE_MASK;
121 if (spi->mode & SPI_CPHA)
123 if (spi->mode & SPI_CPOL)
125 out_be16(xspi->regs + XSPI_CR_OFFSET, cr);
127 /* We do not check spi->max_speed_hz here as the SPI clock
128 * frequency is not software programmable (the IP block design
132 /* Activate the chip select */
133 out_be32(xspi->regs + XSPI_SSR_OFFSET,
134 ~(0x0001 << spi->chip_select));
138 /* spi_bitbang requires custom setup_transfer() to be defined if there is a
139 * custom txrx_bufs(). We have nothing to setup here as the SPI IP block
140 * supports just 8 bits per word, and SPI clock can't be changed in software.
141 * Check for 8 bits per word. Chip select delay calculations could be
142 * added here as soon as bitbang_work() can be made aware of the delay value.
144 static int xilinx_spi_setup_transfer(struct spi_device *spi,
145 struct spi_transfer *t)
149 bits_per_word = (t && t->bits_per_word)
150 ? t->bits_per_word : spi->bits_per_word;
151 if (bits_per_word != 8) {
152 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
153 __func__, bits_per_word);
160 static int xilinx_spi_setup(struct spi_device *spi)
162 struct spi_bitbang *bitbang;
163 struct xilinx_spi *xspi;
166 xspi = spi_master_get_devdata(spi->master);
167 bitbang = &xspi->bitbang;
169 retval = xilinx_spi_setup_transfer(spi, NULL);
176 static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi)
180 /* Fill the Tx FIFO with as many bytes as possible */
181 sr = in_8(xspi->regs + XSPI_SR_OFFSET);
182 while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) {
184 out_8(xspi->regs + XSPI_TXD_OFFSET, *xspi->tx_ptr++);
186 out_8(xspi->regs + XSPI_TXD_OFFSET, 0);
188 xspi->remaining_bytes--;
189 sr = in_8(xspi->regs + XSPI_SR_OFFSET);
193 static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
195 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
199 /* We get here with transmitter inhibited */
201 xspi->tx_ptr = t->tx_buf;
202 xspi->rx_ptr = t->rx_buf;
203 xspi->remaining_bytes = t->len;
204 INIT_COMPLETION(xspi->done);
206 xilinx_spi_fill_tx_fifo(xspi);
208 /* Enable the transmit empty interrupt, which we use to determine
209 * progress on the transmission.
211 ipif_ier = in_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET);
212 out_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET,
213 ipif_ier | XSPI_INTR_TX_EMPTY);
215 /* Start the transfer by not inhibiting the transmitter any longer */
216 cr = in_be16(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_TRANS_INHIBIT;
217 out_be16(xspi->regs + XSPI_CR_OFFSET, cr);
219 wait_for_completion(&xspi->done);
221 /* Disable the transmit empty interrupt */
222 out_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET, ipif_ier);
224 return t->len - xspi->remaining_bytes;
228 /* This driver supports single master mode only. Hence Tx FIFO Empty
229 * is the only interrupt we care about.
230 * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
231 * Fault are not to happen.
233 static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
235 struct xilinx_spi *xspi = dev_id;
238 /* Get the IPIF interrupts, and clear them immediately */
239 ipif_isr = in_be32(xspi->regs + XIPIF_V123B_IISR_OFFSET);
240 out_be32(xspi->regs + XIPIF_V123B_IISR_OFFSET, ipif_isr);
242 if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
246 /* A transmit has just completed. Process received data and
247 * check for more data to transmit. Always inhibit the
248 * transmitter while the Isr refills the transmit register/FIFO,
249 * or make sure it is stopped if we're done.
251 cr = in_be16(xspi->regs + XSPI_CR_OFFSET);
252 out_be16(xspi->regs + XSPI_CR_OFFSET,
253 cr | XSPI_CR_TRANS_INHIBIT);
255 /* Read out all the data from the Rx FIFO */
256 sr = in_8(xspi->regs + XSPI_SR_OFFSET);
257 while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
260 data = in_8(xspi->regs + XSPI_RXD_OFFSET);
262 *xspi->rx_ptr++ = data;
264 sr = in_8(xspi->regs + XSPI_SR_OFFSET);
267 /* See if there is more data to send */
268 if (xspi->remaining_bytes > 0) {
269 xilinx_spi_fill_tx_fifo(xspi);
270 /* Start the transfer by not inhibiting the
271 * transmitter any longer
273 out_be16(xspi->regs + XSPI_CR_OFFSET, cr);
275 /* No more data to send.
276 * Indicate the transfer is completed.
278 complete(&xspi->done);
285 struct spi_master *xilinx_spi_init(struct device *dev, struct resource *mem,
286 u32 irq, s16 bus_num)
288 struct spi_master *master;
289 struct xilinx_spi *xspi;
290 struct xspi_platform_data *pdata = dev->platform_data;
294 dev_err(dev, "No platform data attached\n");
298 master = spi_alloc_master(dev, sizeof(struct xilinx_spi));
302 /* the spi->mode bits understood by this driver: */
303 master->mode_bits = SPI_CPOL | SPI_CPHA;
305 xspi = spi_master_get_devdata(master);
306 xspi->bitbang.master = spi_master_get(master);
307 xspi->bitbang.chipselect = xilinx_spi_chipselect;
308 xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
309 xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
310 xspi->bitbang.master->setup = xilinx_spi_setup;
311 init_completion(&xspi->done);
313 if (!request_mem_region(mem->start, resource_size(mem),
317 xspi->regs = ioremap(mem->start, resource_size(mem));
318 if (xspi->regs == NULL) {
319 dev_warn(dev, "ioremap failure\n");
323 master->bus_num = bus_num;
324 master->num_chipselect = pdata->num_chipselect;
329 /* SPI controller initializations */
330 xspi_init_hw(xspi->regs);
332 /* Register for SPI Interrupt */
333 ret = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi);
337 ret = spi_bitbang_start(&xspi->bitbang);
339 dev_err(dev, "spi_bitbang_start FAILED\n");
343 dev_info(dev, "at 0x%08X mapped to 0x%08X, irq=%d\n",
344 (u32)mem->start, (u32)xspi->regs, xspi->irq);
348 free_irq(xspi->irq, xspi);
352 release_mem_region(mem->start, resource_size(mem));
354 spi_master_put(master);
357 EXPORT_SYMBOL(xilinx_spi_init);
359 void xilinx_spi_deinit(struct spi_master *master)
361 struct xilinx_spi *xspi;
363 xspi = spi_master_get_devdata(master);
365 spi_bitbang_stop(&xspi->bitbang);
366 free_irq(xspi->irq, xspi);
369 release_mem_region(xspi->mem.start, resource_size(&xspi->mem));
370 spi_master_put(xspi->bitbang.master);
372 EXPORT_SYMBOL(xilinx_spi_deinit);
374 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
375 MODULE_DESCRIPTION("Xilinx SPI driver");
376 MODULE_LICENSE("GPL");