SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/spi/spi_mpc8xxx.c

   1 /*
   2  * MPC8xxx SPI controller driver.
   3  *
   4  * Maintainer: Kumar Gala
   5  *
   6  * Copyright (C) 2006 Polycom, Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/types.h>
  16 #include <linux/kernel.h>
  17 #include <linux/bug.h>
  18 #include <linux/errno.h>
  19 #include <linux/err.h>
  20 #include <linux/io.h>
  21 #include <linux/completion.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/delay.h>
  24 #include <linux/irq.h>
  25 #include <linux/device.h>
  26 #include <linux/spi/spi.h>
  27 #include <linux/spi/spi_bitbang.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/fsl_devices.h>
  30 #include <linux/of.h>
  31 #include <linux/of_platform.h>
  32 #include <linux/gpio.h>
  33 #include <linux/of_gpio.h>
  34 #include <linux/of_spi.h>
  35
  36 #include <sysdev/fsl_soc.h>
  37 #include <asm/irq.h>
  38
  39 /* SPI Controller registers */
  40 struct mpc8xxx_spi_reg {
  41         u8 res1[0x20];
  42         __be32 mode;
  43         __be32 event;
  44         __be32 mask;
  45         __be32 command;
  46         __be32 transmit;
  47         __be32 receive;
  48 };
  49
  50 /* SPI Controller mode register definitions */
  51 #define SPMODE_LOOP             (1 << 30)
  52 #define SPMODE_CI_INACTIVEHIGH  (1 << 29)
  53 #define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
  54 #define SPMODE_DIV16            (1 << 27)
  55 #define SPMODE_REV              (1 << 26)
  56 #define SPMODE_MS               (1 << 25)
  57 #define SPMODE_ENABLE           (1 << 24)
  58 #define SPMODE_LEN(x)           ((x) << 20)
  59 #define SPMODE_PM(x)            ((x) << 16)
  60 #define SPMODE_OP               (1 << 14)
  61 #define SPMODE_CG(x)            ((x) << 7)
  62
  63 /*
  64  * Default for SPI Mode:
  65  *      SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
  66  */
  67 #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
  68                          SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
  69
  70 /* SPIE register values */
  71 #define SPIE_NE         0x00000200      /* Not empty */
  72 #define SPIE_NF         0x00000100      /* Not full */
  73
  74 /* SPIM register values */
  75 #define SPIM_NE         0x00000200      /* Not empty */
  76 #define SPIM_NF         0x00000100      /* Not full */
  77
  78 /* SPI Controller driver's private data. */
  79 struct mpc8xxx_spi {
  80         struct mpc8xxx_spi_reg __iomem *base;
  81
  82         /* rx & tx bufs from the spi_transfer */
  83         const void *tx;
  84         void *rx;
  85
  86         /* functions to deal with different sized buffers */
  87         void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
  88         u32(*get_tx) (struct mpc8xxx_spi *);
  89
  90         unsigned int count;
  91         unsigned int irq;
  92
  93         unsigned nsecs;         /* (clock cycle time)/2 */
  94
  95         u32 spibrg;             /* SPIBRG input clock */
  96         u32 rx_shift;           /* RX data reg shift when in qe mode */
  97         u32 tx_shift;           /* TX data reg shift when in qe mode */
  98
  99         unsigned int flags;
 100 #define SPI_QE_CPU_MODE         (1 << 0) /* QE CPU ("PIO") mode */
 101
 102         struct workqueue_struct *workqueue;
 103         struct work_struct work;
 104
 105         struct list_head queue;
 106         spinlock_t lock;
 107
 108         struct completion done;
 109 };
 110
 111 struct spi_mpc8xxx_cs {
 112         /* functions to deal with different sized buffers */
 113         void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
 114         u32 (*get_tx) (struct mpc8xxx_spi *);
 115         u32 rx_shift;           /* RX data reg shift when in qe mode */
 116         u32 tx_shift;           /* TX data reg shift when in qe mode */
 117         u32 hw_mode;            /* Holds HW mode register settings */
 118 };
 119
 120 static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
 121 {
 122         out_be32(reg, val);
 123 }
 124
 125 static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
 126 {
 127         return in_be32(reg);
 128 }
 129
 130 #define MPC83XX_SPI_RX_BUF(type)                                          \
 131 static                                                                    \
 132 void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
 133 {                                                                         \
 134         type *rx = mpc8xxx_spi->rx;                                       \
 135         *rx++ = (type)(data >> mpc8xxx_spi->rx_shift);                    \
 136         mpc8xxx_spi->rx = rx;                                             \
 137 }
 138
 139 #define MPC83XX_SPI_TX_BUF(type)                                \
 140 static                                                          \
 141 u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi)  \
 142 {                                                               \
 143         u32 data;                                               \
 144         const type *tx = mpc8xxx_spi->tx;                       \
 145         if (!tx)                                                \
 146                 return 0;                                       \
 147         data = *tx++ << mpc8xxx_spi->tx_shift;                  \
 148         mpc8xxx_spi->tx = tx;                                   \
 149         return data;                                            \
 150 }
 151
 152 MPC83XX_SPI_RX_BUF(u8)
 153 MPC83XX_SPI_RX_BUF(u16)
 154 MPC83XX_SPI_RX_BUF(u32)
 155 MPC83XX_SPI_TX_BUF(u8)
 156 MPC83XX_SPI_TX_BUF(u16)
 157 MPC83XX_SPI_TX_BUF(u32)
 158
 159 static void mpc8xxx_spi_change_mode(struct spi_device *spi)
 160 {
 161         struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
 162         struct spi_mpc8xxx_cs *cs = spi->controller_state;
 163         __be32 __iomem *mode = &mspi->base->mode;
 164         unsigned long flags;
 165
 166         if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
 167                 return;
 168
 169         /* Turn off IRQs locally to minimize time that SPI is disabled. */
 170         local_irq_save(flags);
 171
 172         /* Turn off SPI unit prior changing mode */
 173         mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
 174         mpc8xxx_spi_write_reg(mode, cs->hw_mode);
 175
 176         local_irq_restore(flags);
 177 }
 178
 179 static void mpc8xxx_spi_chipselect(struct spi_device *spi, int value)
 180 {
 181         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 182         struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data;
 183         bool pol = spi->mode & SPI_CS_HIGH;
 184         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
 185
 186         if (value == BITBANG_CS_INACTIVE) {
 187                 if (pdata->cs_control)
 188                         pdata->cs_control(spi, !pol);
 189         }
 190
 191         if (value == BITBANG_CS_ACTIVE) {
 192                 mpc8xxx_spi->rx_shift = cs->rx_shift;
 193                 mpc8xxx_spi->tx_shift = cs->tx_shift;
 194                 mpc8xxx_spi->get_rx = cs->get_rx;
 195                 mpc8xxx_spi->get_tx = cs->get_tx;
 196
 197                 mpc8xxx_spi_change_mode(spi);
 198
 199                 if (pdata->cs_control)
 200                         pdata->cs_control(spi, pol);
 201         }
 202 }
 203
 204 static
 205 int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 206 {
 207         struct mpc8xxx_spi *mpc8xxx_spi;
 208         u8 bits_per_word, pm;
 209         u32 hz;
 210         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
 211
 212         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 213
 214         if (t) {
 215                 bits_per_word = t->bits_per_word;
 216                 hz = t->speed_hz;
 217         } else {
 218                 bits_per_word = 0;
 219                 hz = 0;
 220         }
 221
 222         /* spi_transfer level calls that work per-word */
 223         if (!bits_per_word)
 224                 bits_per_word = spi->bits_per_word;
 225
 226         /* Make sure its a bit width we support [4..16, 32] */
 227         if ((bits_per_word < 4)
 228             || ((bits_per_word > 16) && (bits_per_word != 32)))
 229                 return -EINVAL;
 230
 231         if (!hz)
 232                 hz = spi->max_speed_hz;
 233
 234         cs->rx_shift = 0;
 235         cs->tx_shift = 0;
 236         if (bits_per_word <= 8) {
 237                 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
 238                 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
 239                 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
 240                         cs->rx_shift = 16;
 241                         cs->tx_shift = 24;
 242                 }
 243         } else if (bits_per_word <= 16) {
 244                 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
 245                 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
 246                 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
 247                         cs->rx_shift = 16;
 248                         cs->tx_shift = 16;
 249                 }
 250         } else if (bits_per_word <= 32) {
 251                 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
 252                 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
 253         } else
 254                 return -EINVAL;
 255
 256         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE &&
 257                         spi->mode & SPI_LSB_FIRST) {
 258                 cs->tx_shift = 0;
 259                 if (bits_per_word <= 8)
 260                         cs->rx_shift = 8;
 261                 else
 262                         cs->rx_shift = 0;
 263         }
 264
 265         mpc8xxx_spi->rx_shift = cs->rx_shift;
 266         mpc8xxx_spi->tx_shift = cs->tx_shift;
 267         mpc8xxx_spi->get_rx = cs->get_rx;
 268         mpc8xxx_spi->get_tx = cs->get_tx;
 269
 270         if (bits_per_word == 32)
 271                 bits_per_word = 0;
 272         else
 273                 bits_per_word = bits_per_word - 1;
 274
 275         /* mask out bits we are going to set */
 276         cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
 277                                   | SPMODE_PM(0xF));
 278
 279         cs->hw_mode |= SPMODE_LEN(bits_per_word);
 280
 281         if ((mpc8xxx_spi->spibrg / hz) > 64) {
 282                 cs->hw_mode |= SPMODE_DIV16;
 283                 pm = mpc8xxx_spi->spibrg / (hz * 64);
 284
 285                 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
 286                           "Will use %d Hz instead.\n", dev_name(&spi->dev),
 287                           hz, mpc8xxx_spi->spibrg / 1024);
 288                 if (pm > 16)
 289                         pm = 16;
 290         } else
 291                 pm = mpc8xxx_spi->spibrg / (hz * 4);
 292         if (pm)
 293                 pm--;
 294
 295         cs->hw_mode |= SPMODE_PM(pm);
 296
 297         mpc8xxx_spi_change_mode(spi);
 298         return 0;
 299 }
 300
 301 static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
 302 {
 303         struct mpc8xxx_spi *mpc8xxx_spi;
 304         u32 word, len, bits_per_word;
 305
 306         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 307
 308         mpc8xxx_spi->tx = t->tx_buf;
 309         mpc8xxx_spi->rx = t->rx_buf;
 310         bits_per_word = spi->bits_per_word;
 311         if (t->bits_per_word)
 312                 bits_per_word = t->bits_per_word;
 313         len = t->len;
 314         if (bits_per_word > 8) {
 315                 /* invalid length? */
 316                 if (len & 1)
 317                         return -EINVAL;
 318                 len /= 2;
 319         }
 320         if (bits_per_word > 16) {
 321                 /* invalid length? */
 322                 if (len & 1)
 323                         return -EINVAL;
 324                 len /= 2;
 325         }
 326         mpc8xxx_spi->count = len;
 327
 328         INIT_COMPLETION(mpc8xxx_spi->done);
 329
 330         /* enable rx ints */
 331         mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, SPIM_NE);
 332
 333         /* transmit word */
 334         word = mpc8xxx_spi->get_tx(mpc8xxx_spi);
 335         mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->transmit, word);
 336
 337         wait_for_completion(&mpc8xxx_spi->done);
 338
 339         /* disable rx ints */
 340         mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
 341
 342         return mpc8xxx_spi->count;
 343 }
 344
 345 static void mpc8xxx_spi_do_one_msg(struct spi_message *m)
 346 {
 347         struct spi_device *spi = m->spi;
 348         struct spi_transfer *t;
 349         unsigned int cs_change;
 350         const int nsecs = 50;
 351         int status;
 352
 353         cs_change = 1;
 354         status = 0;
 355         list_for_each_entry(t, &m->transfers, transfer_list) {
 356                 if (t->bits_per_word || t->speed_hz) {
 357                         /* Don't allow changes if CS is active */
 358                         status = -EINVAL;
 359
 360                         if (cs_change)
 361                                 status = mpc8xxx_spi_setup_transfer(spi, t);
 362                         if (status < 0)
 363                                 break;
 364                 }
 365
 366                 if (cs_change) {
 367                         mpc8xxx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
 368                         ndelay(nsecs);
 369                 }
 370                 cs_change = t->cs_change;
 371                 if (t->len)
 372                         status = mpc8xxx_spi_bufs(spi, t);
 373                 if (status) {
 374                         status = -EMSGSIZE;
 375                         break;
 376                 }
 377                 m->actual_length += t->len;
 378
 379                 if (t->delay_usecs)
 380                         udelay(t->delay_usecs);
 381
 382                 if (cs_change) {
 383                         ndelay(nsecs);
 384                         mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 385                         ndelay(nsecs);
 386                 }
 387         }
 388
 389         m->status = status;
 390         m->complete(m->context);
 391
 392         if (status || !cs_change) {
 393                 ndelay(nsecs);
 394                 mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 395         }
 396
 397         mpc8xxx_spi_setup_transfer(spi, NULL);
 398 }
 399
 400 static void mpc8xxx_spi_work(struct work_struct *work)
 401 {
 402         struct mpc8xxx_spi *mpc8xxx_spi = container_of(work, struct mpc8xxx_spi,
 403                                                        work);
 404
 405         spin_lock_irq(&mpc8xxx_spi->lock);
 406         while (!list_empty(&mpc8xxx_spi->queue)) {
 407                 struct spi_message *m = container_of(mpc8xxx_spi->queue.next,
 408                                                    struct spi_message, queue);
 409
 410                 list_del_init(&m->queue);
 411                 spin_unlock_irq(&mpc8xxx_spi->lock);
 412
 413                 mpc8xxx_spi_do_one_msg(m);
 414
 415                 spin_lock_irq(&mpc8xxx_spi->lock);
 416         }
 417         spin_unlock_irq(&mpc8xxx_spi->lock);
 418 }
 419
 420 static int mpc8xxx_spi_setup(struct spi_device *spi)
 421 {
 422         struct mpc8xxx_spi *mpc8xxx_spi;
 423         int retval;
 424         u32 hw_mode;
 425         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
 426
 427         if (!spi->max_speed_hz)
 428                 return -EINVAL;
 429
 430         if (!cs) {
 431                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 432                 if (!cs)
 433                         return -ENOMEM;
 434                 spi->controller_state = cs;
 435         }
 436         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 437
 438         hw_mode = cs->hw_mode; /* Save orginal settings */
 439         cs->hw_mode = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode);
 440         /* mask out bits we are going to set */
 441         cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
 442                          | SPMODE_REV | SPMODE_LOOP);
 443
 444         if (spi->mode & SPI_CPHA)
 445                 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
 446         if (spi->mode & SPI_CPOL)
 447                 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
 448         if (!(spi->mode & SPI_LSB_FIRST))
 449                 cs->hw_mode |= SPMODE_REV;
 450         if (spi->mode & SPI_LOOP)
 451                 cs->hw_mode |= SPMODE_LOOP;
 452
 453         retval = mpc8xxx_spi_setup_transfer(spi, NULL);
 454         if (retval < 0) {
 455                 cs->hw_mode = hw_mode; /* Restore settings */
 456                 return retval;
 457         }
 458         return 0;
 459 }
 460
 461 static irqreturn_t mpc8xxx_spi_irq(s32 irq, void *context_data)
 462 {
 463         struct mpc8xxx_spi *mpc8xxx_spi = context_data;
 464         u32 event;
 465         irqreturn_t ret = IRQ_NONE;
 466
 467         /* Get interrupt events(tx/rx) */
 468         event = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->event);
 469
 470         /* We need handle RX first */
 471         if (event & SPIE_NE) {
 472                 u32 rx_data = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->receive);
 473
 474                 if (mpc8xxx_spi->rx)
 475                         mpc8xxx_spi->get_rx(rx_data, mpc8xxx_spi);
 476
 477                 ret = IRQ_HANDLED;
 478         }
 479
 480         if ((event & SPIE_NF) == 0)
 481                 /* spin until TX is done */
 482                 while (((event =
 483                          mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->event)) &
 484                                                 SPIE_NF) == 0)
 485                         cpu_relax();
 486
 487         mpc8xxx_spi->count -= 1;
 488         if (mpc8xxx_spi->count) {
 489                 u32 word = mpc8xxx_spi->get_tx(mpc8xxx_spi);
 490                 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->transmit, word);
 491         } else {
 492                 complete(&mpc8xxx_spi->done);
 493         }
 494
 495         /* Clear the events */
 496         mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, event);
 497
 498         return ret;
 499 }
 500 static int mpc8xxx_spi_transfer(struct spi_device *spi,
 501                                 struct spi_message *m)
 502 {
 503         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 504         unsigned long flags;
 505
 506         m->actual_length = 0;
 507         m->status = -EINPROGRESS;
 508
 509         spin_lock_irqsave(&mpc8xxx_spi->lock, flags);
 510         list_add_tail(&m->queue, &mpc8xxx_spi->queue);
 511         queue_work(mpc8xxx_spi->workqueue, &mpc8xxx_spi->work);
 512         spin_unlock_irqrestore(&mpc8xxx_spi->lock, flags);
 513
 514         return 0;
 515 }
 516
 517
 518 static void mpc8xxx_spi_cleanup(struct spi_device *spi)
 519 {
 520         kfree(spi->controller_state);
 521 }
 522
 523 static const char *mpc8xxx_spi_strmode(unsigned int flags)
 524 {
 525         if (flags & SPI_QE_CPU_MODE)
 526                 return "QE CPU";
 527         return "CPU";
 528 }
 529
 530 static struct spi_master * __devinit
 531 mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq)
 532 {
 533         struct fsl_spi_platform_data *pdata = dev->platform_data;
 534         struct spi_master *master;
 535         struct mpc8xxx_spi *mpc8xxx_spi;
 536         u32 regval;
 537         int ret = 0;
 538
 539         master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
 540         if (master == NULL) {
 541                 ret = -ENOMEM;
 542                 goto err;
 543         }
 544
 545         dev_set_drvdata(dev, master);
 546
 547         /* the spi->mode bits understood by this driver: */
 548         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
 549                         | SPI_LSB_FIRST | SPI_LOOP;
 550
 551         master->setup = mpc8xxx_spi_setup;
 552         master->transfer = mpc8xxx_spi_transfer;
 553         master->cleanup = mpc8xxx_spi_cleanup;
 554
 555         mpc8xxx_spi = spi_master_get_devdata(master);
 556         mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8;
 557         mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8;
 558         mpc8xxx_spi->flags = pdata->flags;
 559         mpc8xxx_spi->spibrg = pdata->sysclk;
 560
 561         mpc8xxx_spi->rx_shift = 0;
 562         mpc8xxx_spi->tx_shift = 0;
 563         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
 564                 mpc8xxx_spi->rx_shift = 16;
 565                 mpc8xxx_spi->tx_shift = 24;
 566         }
 567
 568         init_completion(&mpc8xxx_spi->done);
 569
 570         mpc8xxx_spi->base = ioremap(mem->start, mem->end - mem->start + 1);
 571         if (mpc8xxx_spi->base == NULL) {
 572                 ret = -ENOMEM;
 573                 goto put_master;
 574         }
 575
 576         mpc8xxx_spi->irq = irq;
 577
 578         /* Register for SPI Interrupt */
 579         ret = request_irq(mpc8xxx_spi->irq, mpc8xxx_spi_irq,
 580                           0, "mpc8xxx_spi", mpc8xxx_spi);
 581
 582         if (ret != 0)
 583                 goto unmap_io;
 584
 585         master->bus_num = pdata->bus_num;
 586         master->num_chipselect = pdata->max_chipselect;
 587
 588         /* SPI controller initializations */
 589         mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, 0);
 590         mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
 591         mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->command, 0);
 592         mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, 0xffffffff);
 593
 594         /* Enable SPI interface */
 595         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
 596         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
 597                 regval |= SPMODE_OP;
 598
 599         mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, regval);
 600         spin_lock_init(&mpc8xxx_spi->lock);
 601         init_completion(&mpc8xxx_spi->done);
 602         INIT_WORK(&mpc8xxx_spi->work, mpc8xxx_spi_work);
 603         INIT_LIST_HEAD(&mpc8xxx_spi->queue);
 604
 605         mpc8xxx_spi->workqueue = create_singlethread_workqueue(
 606                 dev_name(master->dev.parent));
 607         if (mpc8xxx_spi->workqueue == NULL) {
 608                 ret = -EBUSY;
 609                 goto free_irq;
 610         }
 611
 612         ret = spi_register_master(master);
 613         if (ret < 0)
 614                 goto unreg_master;
 615
 616         dev_info(dev, "at 0x%p (irq = %d), %s mode\n", mpc8xxx_spi->base,
 617                  mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
 618
 619         return master;
 620
 621 unreg_master:
 622         destroy_workqueue(mpc8xxx_spi->workqueue);
 623 free_irq:
 624         free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
 625 unmap_io:
 626         iounmap(mpc8xxx_spi->base);
 627 put_master:
 628         spi_master_put(master);
 629 err:
 630         return ERR_PTR(ret);
 631 }
 632
 633 static int __devexit mpc8xxx_spi_remove(struct device *dev)
 634 {
 635         struct mpc8xxx_spi *mpc8xxx_spi;
 636         struct spi_master *master;
 637
 638         master = dev_get_drvdata(dev);
 639         mpc8xxx_spi = spi_master_get_devdata(master);
 640
 641         flush_workqueue(mpc8xxx_spi->workqueue);
 642         destroy_workqueue(mpc8xxx_spi->workqueue);
 643         spi_unregister_master(master);
 644
 645         free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
 646         iounmap(mpc8xxx_spi->base);
 647
 648         return 0;
 649 }
 650
 651 struct mpc8xxx_spi_probe_info {
 652         struct fsl_spi_platform_data pdata;
 653         int *gpios;
 654         bool *alow_flags;
 655 };
 656
 657 static struct mpc8xxx_spi_probe_info *
 658 to_of_pinfo(struct fsl_spi_platform_data *pdata)
 659 {
 660         return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
 661 }
 662
 663 static void mpc8xxx_spi_cs_control(struct spi_device *spi, bool on)
 664 {
 665         struct device *dev = spi->dev.parent;
 666         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data);
 667         u16 cs = spi->chip_select;
 668         int gpio = pinfo->gpios[cs];
 669         bool alow = pinfo->alow_flags[cs];
 670
 671         gpio_set_value(gpio, on ^ alow);
 672 }
 673
 674 static int of_mpc8xxx_spi_get_chipselects(struct device *dev)
 675 {
 676         struct device_node *np = dev_archdata_get_node(&dev->archdata);
 677         struct fsl_spi_platform_data *pdata = dev->platform_data;
 678         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 679         unsigned int ngpios;
 680         int i = 0;
 681         int ret;
 682
 683         ngpios = of_gpio_count(np);
 684         if (!ngpios) {
 685                 /*
 686                  * SPI w/o chip-select line. One SPI device is still permitted
 687                  * though.
 688                  */
 689                 pdata->max_chipselect = 1;
 690                 return 0;
 691         }
 692
 693         pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
 694         if (!pinfo->gpios)
 695                 return -ENOMEM;
 696         memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
 697
 698         pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
 699                                     GFP_KERNEL);
 700         if (!pinfo->alow_flags) {
 701                 ret = -ENOMEM;
 702                 goto err_alloc_flags;
 703         }
 704
 705         for (; i < ngpios; i++) {
 706                 int gpio;
 707                 enum of_gpio_flags flags;
 708
 709                 gpio = of_get_gpio_flags(np, i, &flags);
 710                 if (!gpio_is_valid(gpio)) {
 711                         dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
 712                         ret = gpio;
 713                         goto err_loop;
 714                 }
 715
 716                 ret = gpio_request(gpio, dev_name(dev));
 717                 if (ret) {
 718                         dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
 719                         goto err_loop;
 720                 }
 721
 722                 pinfo->gpios[i] = gpio;
 723                 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
 724
 725                 ret = gpio_direction_output(pinfo->gpios[i],
 726                                             pinfo->alow_flags[i]);
 727                 if (ret) {
 728                         dev_err(dev, "can't set output direction for gpio "
 729                                 "#%d: %d\n", i, ret);
 730                         goto err_loop;
 731                 }
 732         }
 733
 734         pdata->max_chipselect = ngpios;
 735         pdata->cs_control = mpc8xxx_spi_cs_control;
 736
 737         return 0;
 738
 739 err_loop:
 740         while (i >= 0) {
 741                 if (gpio_is_valid(pinfo->gpios[i]))
 742                         gpio_free(pinfo->gpios[i]);
 743                 i--;
 744         }
 745
 746         kfree(pinfo->alow_flags);
 747         pinfo->alow_flags = NULL;
 748 err_alloc_flags:
 749         kfree(pinfo->gpios);
 750         pinfo->gpios = NULL;
 751         return ret;
 752 }
 753
 754 static int of_mpc8xxx_spi_free_chipselects(struct device *dev)
 755 {
 756         struct fsl_spi_platform_data *pdata = dev->platform_data;
 757         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 758         int i;
 759
 760         if (!pinfo->gpios)
 761                 return 0;
 762
 763         for (i = 0; i < pdata->max_chipselect; i++) {
 764                 if (gpio_is_valid(pinfo->gpios[i]))
 765                         gpio_free(pinfo->gpios[i]);
 766         }
 767
 768         kfree(pinfo->gpios);
 769         kfree(pinfo->alow_flags);
 770         return 0;
 771 }
 772
 773 static int __devinit of_mpc8xxx_spi_probe(struct of_device *ofdev,
 774                                           const struct of_device_id *ofid)
 775 {
 776         struct device *dev = &ofdev->dev;
 777         struct device_node *np = ofdev->node;
 778         struct mpc8xxx_spi_probe_info *pinfo;
 779         struct fsl_spi_platform_data *pdata;
 780         struct spi_master *master;
 781         struct resource mem;
 782         struct resource irq;
 783         const void *prop;
 784         int ret = -ENOMEM;
 785
 786         pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL);
 787         if (!pinfo)
 788                 return -ENOMEM;
 789
 790         pdata = &pinfo->pdata;
 791         dev->platform_data = pdata;
 792
 793         /* Allocate bus num dynamically. */
 794         pdata->bus_num = -1;
 795
 796         /* SPI controller is either clocked from QE or SoC clock. */
 797         pdata->sysclk = get_brgfreq();
 798         if (pdata->sysclk == -1) {
 799                 pdata->sysclk = fsl_get_sys_freq();
 800                 if (pdata->sysclk == -1) {
 801                         ret = -ENODEV;
 802                         goto err_clk;
 803                 }
 804         }
 805
 806         prop = of_get_property(np, "mode", NULL);
 807         if (prop && !strcmp(prop, "cpu-qe"))
 808                 pdata->flags = SPI_QE_CPU_MODE;
 809
 810         ret = of_mpc8xxx_spi_get_chipselects(dev);
 811         if (ret)
 812                 goto err;
 813
 814         ret = of_address_to_resource(np, 0, &mem);
 815         if (ret)
 816                 goto err;
 817
 818         ret = of_irq_to_resource(np, 0, &irq);
 819         if (!ret) {
 820                 ret = -EINVAL;
 821                 goto err;
 822         }
 823
 824         master = mpc8xxx_spi_probe(dev, &mem, irq.start);
 825         if (IS_ERR(master)) {
 826                 ret = PTR_ERR(master);
 827                 goto err;
 828         }
 829
 830         of_register_spi_devices(master, np);
 831
 832         return 0;
 833
 834 err:
 835         of_mpc8xxx_spi_free_chipselects(dev);
 836 err_clk:
 837         kfree(pinfo);
 838         return ret;
 839 }
 840
 841 static int __devexit of_mpc8xxx_spi_remove(struct of_device *ofdev)
 842 {
 843         int ret;
 844
 845         ret = mpc8xxx_spi_remove(&ofdev->dev);
 846         if (ret)
 847                 return ret;
 848         of_mpc8xxx_spi_free_chipselects(&ofdev->dev);
 849         return 0;
 850 }
 851
 852 static const struct of_device_id of_mpc8xxx_spi_match[] = {
 853         { .compatible = "fsl,spi" },
 854         {},
 855 };
 856 MODULE_DEVICE_TABLE(of, of_mpc8xxx_spi_match);
 857
 858 static struct of_platform_driver of_mpc8xxx_spi_driver = {
 859         .name           = "mpc8xxx_spi",
 860         .match_table    = of_mpc8xxx_spi_match,
 861         .probe          = of_mpc8xxx_spi_probe,
 862         .remove         = __devexit_p(of_mpc8xxx_spi_remove),
 863 };
 864
 865 #ifdef CONFIG_MPC832x_RDB
 866 /*
 867  *                              XXX XXX XXX
 868  * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
 869  * only. The driver should go away soon, since newer MPC8323E-RDB's device
 870  * tree can work with OpenFirmware driver. But for now we support old trees
 871  * as well.
 872  */
 873 static int __devinit plat_mpc8xxx_spi_probe(struct platform_device *pdev)
 874 {
 875         struct resource *mem;
 876         unsigned int irq;
 877         struct spi_master *master;
 878
 879         if (!pdev->dev.platform_data)
 880                 return -EINVAL;
 881
 882         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 883         if (!mem)
 884                 return -EINVAL;
 885
 886         irq = platform_get_irq(pdev, 0);
 887         if (!irq)
 888                 return -EINVAL;
 889
 890         master = mpc8xxx_spi_probe(&pdev->dev, mem, irq);
 891         if (IS_ERR(master))
 892                 return PTR_ERR(master);
 893         return 0;
 894 }
 895
 896 static int __devexit plat_mpc8xxx_spi_remove(struct platform_device *pdev)
 897 {
 898         return mpc8xxx_spi_remove(&pdev->dev);
 899 }
 900
 901 MODULE_ALIAS("platform:mpc8xxx_spi");
 902 static struct platform_driver mpc8xxx_spi_driver = {
 903         .probe = plat_mpc8xxx_spi_probe,
 904         .remove = __exit_p(plat_mpc8xxx_spi_remove),
 905         .driver = {
 906                 .name = "mpc8xxx_spi",
 907                 .owner = THIS_MODULE,
 908         },
 909 };
 910
 911 static bool legacy_driver_failed;
 912
 913 static void __init legacy_driver_register(void)
 914 {
 915         legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
 916 }
 917
 918 static void __exit legacy_driver_unregister(void)
 919 {
 920         if (legacy_driver_failed)
 921                 return;
 922         platform_driver_unregister(&mpc8xxx_spi_driver);
 923 }
 924 #else
 925 static void __init legacy_driver_register(void) {}
 926 static void __exit legacy_driver_unregister(void) {}
 927 #endif /* CONFIG_MPC832x_RDB */
 928
 929 static int __init mpc8xxx_spi_init(void)
 930 {
 931         legacy_driver_register();
 932         return of_register_platform_driver(&of_mpc8xxx_spi_driver);
 933 }
 934
 935 static void __exit mpc8xxx_spi_exit(void)
 936 {
 937         of_unregister_platform_driver(&of_mpc8xxx_spi_driver);
 938         legacy_driver_unregister();
 939 }
 940
 941 module_init(mpc8xxx_spi_init);
 942 module_exit(mpc8xxx_spi_exit);
 943
 944 MODULE_AUTHOR("Kumar Gala");
 945 MODULE_DESCRIPTION("Simple MPC8xxx SPI Driver");
 946 MODULE_LICENSE("GPL");