SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/spi/spi_bfin5xx.c

   1 /*
   2  * File:        drivers/spi/bfin5xx_spi.c
   3  * Maintainer:
   4  *              Bryan Wu <bryan.wu@analog.com>
   5  * Original Author:
   6  *              Luke Yang (Analog Devices Inc.)
   7  *
   8  * Created:     March. 10th 2006
   9  * Description: SPI controller driver for Blackfin BF5xx
  10  * Bugs:        Enter bugs at http://blackfin.uclinux.org/
  11  *
  12  * Modified:
  13  *      March 10, 2006  bfin5xx_spi.c Created. (Luke Yang)
  14  *      August 7, 2006  added full duplex mode (Axel Weiss & Luke Yang)
  15  *      July  17, 2007  add support for BF54x SPI0 controller (Bryan Wu)
  16  *      July  30, 2007  add platfrom_resource interface to support multi-port
  17  *                      SPI controller (Bryan Wu)
  18  *
  19  * Copyright 2004-2007 Analog Devices Inc.
  20  *
  21  * This program is free software ;  you can redistribute it and/or modify
  22  * it under the terms of the GNU General Public License as published by
  23  * the Free Software Foundation ;  either version 2, or (at your option)
  24  * any later version.
  25  *
  26  * This program is distributed in the hope that it will be useful,
  27  * but WITHOUT ANY WARRANTY ;  without even the implied warranty of
  28  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  29  * GNU General Public License for more details.
  30  *
  31  * You should have received a copy of the GNU General Public License
  32  * along with this program ;  see the file COPYING.
  33  * If not, write to the Free Software Foundation,
  34  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  35  */
  36
  37 #include <linux/init.h>
  38 #include <linux/module.h>
  39 #include <linux/delay.h>
  40 #include <linux/device.h>
  41 #include <linux/io.h>
  42 #include <linux/ioport.h>
  43 #include <linux/irq.h>
  44 #include <linux/errno.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/platform_device.h>
  47 #include <linux/dma-mapping.h>
  48 #include <linux/spi/spi.h>
  49 #include <linux/workqueue.h>
  50
  51 #include <asm/dma.h>
  52 #include <asm/portmux.h>
  53 #include <asm/bfin5xx_spi.h>
  54
  55 #define DRV_NAME        "bfin-spi"
  56 #define DRV_AUTHOR      "Bryan Wu, Luke Yang"
  57 #define DRV_DESC        "Blackfin BF5xx on-chip SPI Contoller Driver"
  58 #define DRV_VERSION     "1.0"
  59
  60 MODULE_AUTHOR(DRV_AUTHOR);
  61 MODULE_DESCRIPTION(DRV_DESC);
  62 MODULE_LICENSE("GPL");
  63
  64 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)
  65
  66 static u32 spi_dma_ch;
  67 static u32 spi_regs_base;
  68
  69 #define DEFINE_SPI_REG(reg, off) \
  70 static inline u16 read_##reg(void) \
  71         { return bfin_read16(spi_regs_base + off); } \
  72 static inline void write_##reg(u16 v) \
  73         {bfin_write16(spi_regs_base + off, v); }
  74
  75 DEFINE_SPI_REG(CTRL, 0x00)
  76 DEFINE_SPI_REG(FLAG, 0x04)
  77 DEFINE_SPI_REG(STAT, 0x08)
  78 DEFINE_SPI_REG(TDBR, 0x0C)
  79 DEFINE_SPI_REG(RDBR, 0x10)
  80 DEFINE_SPI_REG(BAUD, 0x14)
  81 DEFINE_SPI_REG(SHAW, 0x18)
  82 #define START_STATE ((void*)0)
  83 #define RUNNING_STATE ((void*)1)
  84 #define DONE_STATE ((void*)2)
  85 #define ERROR_STATE ((void*)-1)
  86 #define QUEUE_RUNNING 0
  87 #define QUEUE_STOPPED 1
  88 int dma_requested;
  89
  90 struct driver_data {
  91         /* Driver model hookup */
  92         struct platform_device *pdev;
  93
  94         /* SPI framework hookup */
  95         struct spi_master *master;
  96
  97         /* BFIN hookup */
  98         struct bfin5xx_spi_master *master_info;
  99
 100         /* Driver message queue */
 101         struct workqueue_struct *workqueue;
 102         struct work_struct pump_messages;
 103         spinlock_t lock;
 104         struct list_head queue;
 105         int busy;
 106         int run;
 107
 108         /* Message Transfer pump */
 109         struct tasklet_struct pump_transfers;
 110
 111         /* Current message transfer state info */
 112         struct spi_message *cur_msg;
 113         struct spi_transfer *cur_transfer;
 114         struct chip_data *cur_chip;
 115         size_t len_in_bytes;
 116         size_t len;
 117         void *tx;
 118         void *tx_end;
 119         void *rx;
 120         void *rx_end;
 121         int dma_mapped;
 122         dma_addr_t rx_dma;
 123         dma_addr_t tx_dma;
 124         size_t rx_map_len;
 125         size_t tx_map_len;
 126         u8 n_bytes;
 127         int cs_change;
 128         void (*write) (struct driver_data *);
 129         void (*read) (struct driver_data *);
 130         void (*duplex) (struct driver_data *);
 131 };
 132
 133 struct chip_data {
 134         u16 ctl_reg;
 135         u16 baud;
 136         u16 flag;
 137
 138         u8 chip_select_num;
 139         u8 chip_select_requested;
 140         u8 n_bytes;
 141         u8 width;               /* 0 or 1 */
 142         u8 enable_dma;
 143         u8 bits_per_word;       /* 8 or 16 */
 144         u8 cs_change_per_word;
 145         u8 cs_chg_udelay;
 146         void (*write) (struct driver_data *);
 147         void (*read) (struct driver_data *);
 148         void (*duplex) (struct driver_data *);
 149 };
 150
 151 static void bfin_spi_enable(struct driver_data *drv_data)
 152 {
 153         u16 cr;
 154
 155         cr = read_CTRL();
 156         write_CTRL(cr | BIT_CTL_ENABLE);
 157 }
 158
 159 static void bfin_spi_disable(struct driver_data *drv_data)
 160 {
 161         u16 cr;
 162
 163         cr = read_CTRL();
 164         write_CTRL(cr & (~BIT_CTL_ENABLE));
 165 }
 166
 167 /* Caculate the SPI_BAUD register value based on input HZ */
 168 static u16 hz_to_spi_baud(u32 speed_hz)
 169 {
 170         u_long sclk = get_sclk();
 171         u16 spi_baud = (sclk / (2 * speed_hz));
 172
 173         if ((sclk % (2 * speed_hz)) > 0)
 174                 spi_baud++;
 175
 176         return spi_baud;
 177 }
 178
 179 static int flush(struct driver_data *drv_data)
 180 {
 181         unsigned long limit = loops_per_jiffy << 1;
 182
 183         /* wait for stop and clear stat */
 184         while (!(read_STAT() & BIT_STAT_SPIF) && limit--)
 185                 continue;
 186
 187         write_STAT(BIT_STAT_CLR);
 188
 189         return limit;
 190 }
 191
 192 /* Chip select operation functions for cs_change flag */
 193 static void cs_active(struct chip_data *chip)
 194 {
 195         u16 flag = read_FLAG();
 196
 197         flag |= chip->flag;
 198         flag &= ~(chip->flag << 8);
 199
 200         write_FLAG(flag);
 201 }
 202
 203 static void cs_deactive(struct chip_data *chip)
 204 {
 205         u16 flag = read_FLAG();
 206
 207         flag |= (chip->flag << 8);
 208
 209         write_FLAG(flag);
 210 }
 211
 212 #define MAX_SPI_SSEL    7
 213
 214 /* stop controller and re-config current chip*/
 215 static int restore_state(struct driver_data *drv_data)
 216 {
 217         struct chip_data *chip = drv_data->cur_chip;
 218         int ret = 0;
 219         u16 ssel[3][MAX_SPI_SSEL] = {
 220                 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
 221                 P_SPI0_SSEL4, P_SPI0_SSEL5,
 222                 P_SPI0_SSEL6, P_SPI0_SSEL7},
 223
 224                 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
 225                 P_SPI1_SSEL4, P_SPI1_SSEL5,
 226                 P_SPI1_SSEL6, P_SPI1_SSEL7},
 227
 228                 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
 229                 P_SPI2_SSEL4, P_SPI2_SSEL5,
 230                 P_SPI2_SSEL6, P_SPI2_SSEL7},
 231         };
 232         /* Clear status and disable clock */
 233         write_STAT(BIT_STAT_CLR);
 234         bfin_spi_disable(drv_data);
 235         dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
 236
 237         /* Load the registers */
 238         write_CTRL(chip->ctl_reg);
 239         write_BAUD(chip->baud);
 240         cs_active(chip);
 241
 242         if (!chip->chip_select_requested) {
 243                 int i = chip->chip_select_num;
 244
 245                 dev_dbg(&drv_data->pdev->dev, "chip select number is %d\n", i);
 246                 if ((i > 0) && (i <= MAX_SPI_SSEL))
 247                         ret = peripheral_request(
 248                                 ssel[drv_data->master->bus_num][i-1], DRV_NAME);
 249
 250                 chip->chip_select_requested = 1;
 251         }
 252
 253         if (ret)
 254                 dev_dbg(&drv_data->pdev->dev,
 255                         ": request chip select number %d failed\n",
 256                         chip->chip_select_num);
 257
 258         return ret;
 259 }
 260
 261 /* used to kick off transfer in rx mode */
 262 static unsigned short dummy_read(void)
 263 {
 264         unsigned short tmp;
 265         tmp = read_RDBR();
 266         return tmp;
 267 }
 268
 269 static void null_writer(struct driver_data *drv_data)
 270 {
 271         u8 n_bytes = drv_data->n_bytes;
 272
 273         while (drv_data->tx < drv_data->tx_end) {
 274                 write_TDBR(0);
 275                 while ((read_STAT() & BIT_STAT_TXS))
 276                         continue;
 277                 drv_data->tx += n_bytes;
 278         }
 279 }
 280
 281 static void null_reader(struct driver_data *drv_data)
 282 {
 283         u8 n_bytes = drv_data->n_bytes;
 284         dummy_read();
 285
 286         while (drv_data->rx < drv_data->rx_end) {
 287                 while (!(read_STAT() & BIT_STAT_RXS))
 288                         continue;
 289                 dummy_read();
 290                 drv_data->rx += n_bytes;
 291         }
 292 }
 293
 294 static void u8_writer(struct driver_data *drv_data)
 295 {
 296         dev_dbg(&drv_data->pdev->dev,
 297                 "cr8-s is 0x%x\n", read_STAT());
 298         while (drv_data->tx < drv_data->tx_end) {
 299                 write_TDBR(*(u8 *) (drv_data->tx));
 300                 while (read_STAT() & BIT_STAT_TXS)
 301                         continue;
 302                 ++drv_data->tx;
 303         }
 304
 305         /* poll for SPI completion before returning */
 306         while (!(read_STAT() & BIT_STAT_SPIF))
 307                 continue;
 308 }
 309
 310 static void u8_cs_chg_writer(struct driver_data *drv_data)
 311 {
 312         struct chip_data *chip = drv_data->cur_chip;
 313
 314         while (drv_data->tx < drv_data->tx_end) {
 315                 cs_active(chip);
 316
 317                 write_TDBR(*(u8 *) (drv_data->tx));
 318                 while (read_STAT() & BIT_STAT_TXS)
 319                         continue;
 320                 while (!(read_STAT() & BIT_STAT_SPIF))
 321                         continue;
 322                 cs_deactive(chip);
 323
 324                 if (chip->cs_chg_udelay)
 325                         udelay(chip->cs_chg_udelay);
 326                 ++drv_data->tx;
 327         }
 328         cs_deactive(chip);
 329
 330 }
 331
 332 static void u8_reader(struct driver_data *drv_data)
 333 {
 334         dev_dbg(&drv_data->pdev->dev,
 335                 "cr-8 is 0x%x\n", read_STAT());
 336
 337         /* clear TDBR buffer before read(else it will be shifted out) */
 338         write_TDBR(0xFFFF);
 339
 340         dummy_read();
 341         while (drv_data->rx < drv_data->rx_end - 1) {
 342                 while (!(read_STAT() & BIT_STAT_RXS))
 343                         continue;
 344                 *(u8 *) (drv_data->rx) = read_RDBR();
 345                 ++drv_data->rx;
 346         }
 347
 348         while (!(read_STAT() & BIT_STAT_RXS))
 349                 continue;
 350         *(u8 *) (drv_data->rx) = read_SHAW();
 351         ++drv_data->rx;
 352 }
 353
 354 static void u8_cs_chg_reader(struct driver_data *drv_data)
 355 {
 356         struct chip_data *chip = drv_data->cur_chip;
 357
 358         while (drv_data->rx < drv_data->rx_end) {
 359                 cs_active(chip);
 360
 361                 read_RDBR();    /* kick off */
 362                 while (!(read_STAT() & BIT_STAT_RXS))
 363                         continue;
 364                 while (!(read_STAT() & BIT_STAT_SPIF))
 365                         continue;
 366                 *(u8 *) (drv_data->rx) = read_SHAW();
 367                 cs_deactive(chip);
 368
 369                 if (chip->cs_chg_udelay)
 370                         udelay(chip->cs_chg_udelay);
 371                 ++drv_data->rx;
 372         }
 373         cs_deactive(chip);
 374
 375 }
 376
 377 static void u8_duplex(struct driver_data *drv_data)
 378 {
 379         /* in duplex mode, clk is triggered by writing of TDBR */
 380         while (drv_data->rx < drv_data->rx_end) {
 381                 write_TDBR(*(u8 *) (drv_data->tx));
 382                 while (!(read_STAT() & BIT_STAT_SPIF))
 383                         continue;
 384                 while (!(read_STAT() & BIT_STAT_RXS))
 385                         continue;
 386                 *(u8 *) (drv_data->rx) = read_RDBR();
 387                 ++drv_data->rx;
 388                 ++drv_data->tx;
 389         }
 390 }
 391
 392 static void u8_cs_chg_duplex(struct driver_data *drv_data)
 393 {
 394         struct chip_data *chip = drv_data->cur_chip;
 395
 396         while (drv_data->rx < drv_data->rx_end) {
 397                 cs_active(chip);
 398
 399
 400                 write_TDBR(*(u8 *) (drv_data->tx));
 401                 while (!(read_STAT() & BIT_STAT_SPIF))
 402                         continue;
 403                 while (!(read_STAT() & BIT_STAT_RXS))
 404                         continue;
 405                 *(u8 *) (drv_data->rx) = read_RDBR();
 406                 cs_deactive(chip);
 407
 408                 if (chip->cs_chg_udelay)
 409                         udelay(chip->cs_chg_udelay);
 410                 ++drv_data->rx;
 411                 ++drv_data->tx;
 412         }
 413         cs_deactive(chip);
 414 }
 415
 416 static void u16_writer(struct driver_data *drv_data)
 417 {
 418         dev_dbg(&drv_data->pdev->dev,
 419                 "cr16 is 0x%x\n", read_STAT());
 420
 421         while (drv_data->tx < drv_data->tx_end) {
 422                 write_TDBR(*(u16 *) (drv_data->tx));
 423                 while ((read_STAT() & BIT_STAT_TXS))
 424                         continue;
 425                 drv_data->tx += 2;
 426         }
 427
 428         /* poll for SPI completion before returning */
 429         while (!(read_STAT() & BIT_STAT_SPIF))
 430                 continue;
 431 }
 432
 433 static void u16_cs_chg_writer(struct driver_data *drv_data)
 434 {
 435         struct chip_data *chip = drv_data->cur_chip;
 436
 437         while (drv_data->tx < drv_data->tx_end) {
 438                 cs_active(chip);
 439
 440                 write_TDBR(*(u16 *) (drv_data->tx));
 441                 while ((read_STAT() & BIT_STAT_TXS))
 442                         continue;
 443                 while (!(read_STAT() & BIT_STAT_SPIF))
 444                         continue;
 445                 cs_deactive(chip);
 446
 447                 if (chip->cs_chg_udelay)
 448                         udelay(chip->cs_chg_udelay);
 449                 drv_data->tx += 2;
 450         }
 451         cs_deactive(chip);
 452 }
 453
 454 static void u16_reader(struct driver_data *drv_data)
 455 {
 456         dev_dbg(&drv_data->pdev->dev,
 457                 "cr-16 is 0x%x\n", read_STAT());
 458         dummy_read();
 459
 460         while (drv_data->rx < (drv_data->rx_end - 2)) {
 461                 while (!(read_STAT() & BIT_STAT_RXS))
 462                         continue;
 463                 *(u16 *) (drv_data->rx) = read_RDBR();
 464                 drv_data->rx += 2;
 465         }
 466
 467         while (!(read_STAT() & BIT_STAT_RXS))
 468                 continue;
 469         *(u16 *) (drv_data->rx) = read_SHAW();
 470         drv_data->rx += 2;
 471 }
 472
 473 static void u16_cs_chg_reader(struct driver_data *drv_data)
 474 {
 475         struct chip_data *chip = drv_data->cur_chip;
 476
 477         while (drv_data->rx < drv_data->rx_end) {
 478                 cs_active(chip);
 479
 480                 read_RDBR();    /* kick off */
 481                 while (!(read_STAT() & BIT_STAT_RXS))
 482                         continue;
 483                 while (!(read_STAT() & BIT_STAT_SPIF))
 484                         continue;
 485                 *(u16 *) (drv_data->rx) = read_SHAW();
 486                 cs_deactive(chip);
 487
 488                 if (chip->cs_chg_udelay)
 489                         udelay(chip->cs_chg_udelay);
 490                 drv_data->rx += 2;
 491         }
 492         cs_deactive(chip);
 493 }
 494
 495 static void u16_duplex(struct driver_data *drv_data)
 496 {
 497         /* in duplex mode, clk is triggered by writing of TDBR */
 498         while (drv_data->tx < drv_data->tx_end) {
 499                 write_TDBR(*(u16 *) (drv_data->tx));
 500                 while (!(read_STAT() & BIT_STAT_SPIF))
 501                         continue;
 502                 while (!(read_STAT() & BIT_STAT_RXS))
 503                         continue;
 504                 *(u16 *) (drv_data->rx) = read_RDBR();
 505                 drv_data->rx += 2;
 506                 drv_data->tx += 2;
 507         }
 508 }
 509
 510 static void u16_cs_chg_duplex(struct driver_data *drv_data)
 511 {
 512         struct chip_data *chip = drv_data->cur_chip;
 513
 514         while (drv_data->tx < drv_data->tx_end) {
 515                 cs_active(chip);
 516
 517                 write_TDBR(*(u16 *) (drv_data->tx));
 518                 while (!(read_STAT() & BIT_STAT_SPIF))
 519                         continue;
 520                 while (!(read_STAT() & BIT_STAT_RXS))
 521                         continue;
 522                 *(u16 *) (drv_data->rx) = read_RDBR();
 523                 cs_deactive(chip);
 524
 525                 if (chip->cs_chg_udelay)
 526                         udelay(chip->cs_chg_udelay);
 527                 drv_data->rx += 2;
 528                 drv_data->tx += 2;
 529         }
 530         cs_deactive(chip);
 531 }
 532
 533 /* test if ther is more transfer to be done */
 534 static void *next_transfer(struct driver_data *drv_data)
 535 {
 536         struct spi_message *msg = drv_data->cur_msg;
 537         struct spi_transfer *trans = drv_data->cur_transfer;
 538
 539         /* Move to next transfer */
 540         if (trans->transfer_list.next != &msg->transfers) {
 541                 drv_data->cur_transfer =
 542                     list_entry(trans->transfer_list.next,
 543                                struct spi_transfer, transfer_list);
 544                 return RUNNING_STATE;
 545         } else
 546                 return DONE_STATE;
 547 }
 548
 549 /*
 550  * caller already set message->status;
 551  * dma and pio irqs are blocked give finished message back
 552  */
 553 static void giveback(struct driver_data *drv_data)
 554 {
 555         struct chip_data *chip = drv_data->cur_chip;
 556         struct spi_transfer *last_transfer;
 557         unsigned long flags;
 558         struct spi_message *msg;
 559
 560         spin_lock_irqsave(&drv_data->lock, flags);
 561         msg = drv_data->cur_msg;
 562         drv_data->cur_msg = NULL;
 563         drv_data->cur_transfer = NULL;
 564         drv_data->cur_chip = NULL;
 565         queue_work(drv_data->workqueue, &drv_data->pump_messages);
 566         spin_unlock_irqrestore(&drv_data->lock, flags);
 567
 568         last_transfer = list_entry(msg->transfers.prev,
 569                                    struct spi_transfer, transfer_list);
 570
 571         msg->state = NULL;
 572
 573         /* disable chip select signal. And not stop spi in autobuffer mode */
 574         if (drv_data->tx_dma != 0xFFFF) {
 575                 cs_deactive(chip);
 576                 bfin_spi_disable(drv_data);
 577         }
 578
 579         if (!drv_data->cs_change)
 580                 cs_deactive(chip);
 581
 582         if (msg->complete)
 583                 msg->complete(msg->context);
 584 }
 585
 586 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 587 {
 588         struct driver_data *drv_data = (struct driver_data *)dev_id;
 589         struct spi_message *msg = drv_data->cur_msg;
 590         struct chip_data *chip = drv_data->cur_chip;
 591
 592         dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
 593         clear_dma_irqstat(spi_dma_ch);
 594
 595         /* Wait for DMA to complete */
 596         while (get_dma_curr_irqstat(spi_dma_ch) & DMA_RUN)
 597                 continue;
 598
 599         /*
 600          * wait for the last transaction shifted out.  HRM states:
 601          * at this point there may still be data in the SPI DMA FIFO waiting
 602          * to be transmitted ... software needs to poll TXS in the SPI_STAT
 603          * register until it goes low for 2 successive reads
 604          */
 605         if (drv_data->tx != NULL) {
 606                 while ((read_STAT() & TXS) ||
 607                        (read_STAT() & TXS))
 608                         continue;
 609         }
 610
 611         while (!(read_STAT() & SPIF))
 612                 continue;
 613
 614         bfin_spi_disable(drv_data);
 615
 616         msg->actual_length += drv_data->len_in_bytes;
 617
 618         if (drv_data->cs_change)
 619                 cs_deactive(chip);
 620
 621         /* Move to next transfer */
 622         msg->state = next_transfer(drv_data);
 623
 624         /* Schedule transfer tasklet */
 625         tasklet_schedule(&drv_data->pump_transfers);
 626
 627         /* free the irq handler before next transfer */
 628         dev_dbg(&drv_data->pdev->dev,
 629                 "disable dma channel irq%d\n",
 630                 spi_dma_ch);
 631         dma_disable_irq(spi_dma_ch);
 632
 633         return IRQ_HANDLED;
 634 }
 635
 636 static void pump_transfers(unsigned long data)
 637 {
 638         struct driver_data *drv_data = (struct driver_data *)data;
 639         struct spi_message *message = NULL;
 640         struct spi_transfer *transfer = NULL;
 641         struct spi_transfer *previous = NULL;
 642         struct chip_data *chip = NULL;
 643         u8 width;
 644         u16 cr, dma_width, dma_config;
 645         u32 tranf_success = 1;
 646
 647         /* Get current state information */
 648         message = drv_data->cur_msg;
 649         transfer = drv_data->cur_transfer;
 650         chip = drv_data->cur_chip;
 651         /*
 652          * if msg is error or done, report it back using complete() callback
 653          */
 654
 655          /* Handle for abort */
 656         if (message->state == ERROR_STATE) {
 657                 message->status = -EIO;
 658                 giveback(drv_data);
 659                 return;
 660         }
 661
 662         /* Handle end of message */
 663         if (message->state == DONE_STATE) {
 664                 message->status = 0;
 665                 giveback(drv_data);
 666                 return;
 667         }
 668
 669         /* Delay if requested at end of transfer */
 670         if (message->state == RUNNING_STATE) {
 671                 previous = list_entry(transfer->transfer_list.prev,
 672                                       struct spi_transfer, transfer_list);
 673                 if (previous->delay_usecs)
 674                         udelay(previous->delay_usecs);
 675         }
 676
 677         /* Setup the transfer state based on the type of transfer */
 678         if (flush(drv_data) == 0) {
 679                 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
 680                 message->status = -EIO;
 681                 giveback(drv_data);
 682                 return;
 683         }
 684
 685         if (transfer->tx_buf != NULL) {
 686                 drv_data->tx = (void *)transfer->tx_buf;
 687                 drv_data->tx_end = drv_data->tx + transfer->len;
 688                 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
 689                         transfer->tx_buf, drv_data->tx_end);
 690         } else {
 691                 drv_data->tx = NULL;
 692         }
 693
 694         if (transfer->rx_buf != NULL) {
 695                 drv_data->rx = transfer->rx_buf;
 696                 drv_data->rx_end = drv_data->rx + transfer->len;
 697                 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
 698                         transfer->rx_buf, drv_data->rx_end);
 699         } else {
 700                 drv_data->rx = NULL;
 701         }
 702
 703         drv_data->rx_dma = transfer->rx_dma;
 704         drv_data->tx_dma = transfer->tx_dma;
 705         drv_data->len_in_bytes = transfer->len;
 706         drv_data->cs_change = transfer->cs_change;
 707
 708         width = chip->width;
 709         if (width == CFG_SPI_WORDSIZE16) {
 710                 drv_data->len = (transfer->len) >> 1;
 711         } else {
 712                 drv_data->len = transfer->len;
 713         }
 714         drv_data->write = drv_data->tx ? chip->write : null_writer;
 715         drv_data->read = drv_data->rx ? chip->read : null_reader;
 716         drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
 717         dev_dbg(&drv_data->pdev->dev, "transfer: ",
 718                 "drv_data->write is %p, chip->write is %p, null_wr is %p\n",
 719                 drv_data->write, chip->write, null_writer);
 720
 721         /* speed and width has been set on per message */
 722         message->state = RUNNING_STATE;
 723         dma_config = 0;
 724
 725         /* restore spi status for each spi transfer */
 726         if (transfer->speed_hz) {
 727                 write_BAUD(hz_to_spi_baud(transfer->speed_hz));
 728         } else {
 729                 write_BAUD(chip->baud);
 730         }
 731         cs_active(chip);
 732
 733         dev_dbg(&drv_data->pdev->dev,
 734                 "now pumping a transfer: width is %d, len is %d\n",
 735                 width, transfer->len);
 736
 737         /*
 738          * Try to map dma buffer and do a dma transfer if
 739          * successful use different way to r/w according to
 740          * drv_data->cur_chip->enable_dma
 741          */
 742         if (drv_data->cur_chip->enable_dma && drv_data->len > 6) {
 743
 744                 write_STAT(BIT_STAT_CLR);
 745                 disable_dma(spi_dma_ch);
 746                 clear_dma_irqstat(spi_dma_ch);
 747                 bfin_spi_disable(drv_data);
 748
 749                 /* config dma channel */
 750                 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
 751                 if (width == CFG_SPI_WORDSIZE16) {
 752                         set_dma_x_count(spi_dma_ch, drv_data->len);
 753                         set_dma_x_modify(spi_dma_ch, 2);
 754                         dma_width = WDSIZE_16;
 755                 } else {
 756                         set_dma_x_count(spi_dma_ch, drv_data->len);
 757                         set_dma_x_modify(spi_dma_ch, 1);
 758                         dma_width = WDSIZE_8;
 759                 }
 760
 761                 /* set transfer width,direction. And enable spi */
 762                 cr = (read_CTRL() & (~BIT_CTL_TIMOD));
 763
 764                 /* dirty hack for autobuffer DMA mode */
 765                 if (drv_data->tx_dma == 0xFFFF) {
 766                         dev_dbg(&drv_data->pdev->dev,
 767                                 "doing autobuffer DMA out.\n");
 768
 769                         /* no irq in autobuffer mode */
 770                         dma_config =
 771                             (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
 772                         set_dma_config(spi_dma_ch, dma_config);
 773                         set_dma_start_addr(spi_dma_ch,
 774                                         (unsigned long)drv_data->tx);
 775                         enable_dma(spi_dma_ch);
 776                         write_CTRL(cr | CFG_SPI_DMAWRITE | (width << 8) |
 777                                    (CFG_SPI_ENABLE << 14));
 778
 779                         /* just return here, there can only be one transfer in this mode */
 780                         message->status = 0;
 781                         giveback(drv_data);
 782                         return;
 783                 }
 784
 785                 /* In dma mode, rx or tx must be NULL in one transfer */
 786                 if (drv_data->rx != NULL) {
 787                         /* set transfer mode, and enable SPI */
 788                         dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");
 789
 790                         /* disable SPI before write to TDBR */
 791                         write_CTRL(cr & ~BIT_CTL_ENABLE);
 792
 793                         /* clear tx reg soformer data is not shifted out */
 794                         write_TDBR(0xFF);
 795
 796                         set_dma_x_count(spi_dma_ch, drv_data->len);
 797
 798                         /* start dma */
 799                         dma_enable_irq(spi_dma_ch);
 800                         dma_config = (WNR | RESTART | dma_width | DI_EN);
 801                         set_dma_config(spi_dma_ch, dma_config);
 802                         set_dma_start_addr(spi_dma_ch,
 803                                         (unsigned long)drv_data->rx);
 804                         enable_dma(spi_dma_ch);
 805
 806                         cr |=
 807                             CFG_SPI_DMAREAD | (width << 8) | (CFG_SPI_ENABLE <<
 808                                                               14);
 809                         /* set transfer mode, and enable SPI */
 810                         write_CTRL(cr);
 811                 } else if (drv_data->tx != NULL) {
 812                         dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
 813
 814                         /* start dma */
 815                         dma_enable_irq(spi_dma_ch);
 816                         dma_config = (RESTART | dma_width | DI_EN);
 817                         set_dma_config(spi_dma_ch, dma_config);
 818                         set_dma_start_addr(spi_dma_ch,
 819                                         (unsigned long)drv_data->tx);
 820                         enable_dma(spi_dma_ch);
 821
 822                         write_CTRL(cr | CFG_SPI_DMAWRITE | (width << 8) |
 823                                    (CFG_SPI_ENABLE << 14));
 824
 825                 }
 826         } else {
 827                 /* IO mode write then read */
 828                 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
 829
 830                 write_STAT(BIT_STAT_CLR);
 831
 832                 if (drv_data->tx != NULL && drv_data->rx != NULL) {
 833                         /* full duplex mode */
 834                         BUG_ON((drv_data->tx_end - drv_data->tx) !=
 835                                (drv_data->rx_end - drv_data->rx));
 836                         cr = (read_CTRL() & (~BIT_CTL_TIMOD));
 837                         cr |= CFG_SPI_WRITE | (width << 8) |
 838                                 (CFG_SPI_ENABLE << 14);
 839                         dev_dbg(&drv_data->pdev->dev,
 840                                 "IO duplex: cr is 0x%x\n", cr);
 841
 842                         write_CTRL(cr);
 843
 844                         drv_data->duplex(drv_data);
 845
 846                         if (drv_data->tx != drv_data->tx_end)
 847                                 tranf_success = 0;
 848                 } else if (drv_data->tx != NULL) {
 849                         /* write only half duplex */
 850                         cr = (read_CTRL() & (~BIT_CTL_TIMOD));
 851                         cr |= CFG_SPI_WRITE | (width << 8) |
 852                                 (CFG_SPI_ENABLE << 14);
 853                         dev_dbg(&drv_data->pdev->dev,
 854                                 "IO write: cr is 0x%x\n", cr);
 855
 856                         write_CTRL(cr);
 857
 858                         drv_data->write(drv_data);
 859
 860                         if (drv_data->tx != drv_data->tx_end)
 861                                 tranf_success = 0;
 862                 } else if (drv_data->rx != NULL) {
 863                         /* read only half duplex */
 864                         cr = (read_CTRL() & (~BIT_CTL_TIMOD));
 865                         cr |= CFG_SPI_READ | (width << 8) |
 866                                 (CFG_SPI_ENABLE << 14);
 867                         dev_dbg(&drv_data->pdev->dev,
 868                                 "IO read: cr is 0x%x\n", cr);
 869
 870                         write_CTRL(cr);
 871
 872                         drv_data->read(drv_data);
 873                         if (drv_data->rx != drv_data->rx_end)
 874                                 tranf_success = 0;
 875                 }
 876
 877                 if (!tranf_success) {
 878                         dev_dbg(&drv_data->pdev->dev,
 879                                 "IO write error!\n");
 880                         message->state = ERROR_STATE;
 881                 } else {
 882                         /* Update total byte transfered */
 883                         message->actual_length += drv_data->len;
 884
 885                         if (drv_data->cs_change)
 886                                 cs_deactive(chip);
 887
 888                         /* Move to next transfer of this msg */
 889                         message->state = next_transfer(drv_data);
 890                 }
 891
 892                 /* Schedule next transfer tasklet */
 893                 tasklet_schedule(&drv_data->pump_transfers);
 894
 895         }
 896 }
 897
 898 /* pop a msg from queue and kick off real transfer */
 899 static void pump_messages(struct work_struct *work)
 900 {
 901         struct driver_data *drv_data;
 902         unsigned long flags;
 903
 904         drv_data = container_of(work, struct driver_data, pump_messages);
 905
 906         /* Lock queue and check for queue work */
 907         spin_lock_irqsave(&drv_data->lock, flags);
 908         if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
 909                 /* pumper kicked off but no work to do */
 910                 drv_data->busy = 0;
 911                 spin_unlock_irqrestore(&drv_data->lock, flags);
 912                 return;
 913         }
 914
 915         /* Make sure we are not already running a message */
 916         if (drv_data->cur_msg) {
 917                 spin_unlock_irqrestore(&drv_data->lock, flags);
 918                 return;
 919         }
 920
 921         /* Extract head of queue */
 922         drv_data->cur_msg = list_entry(drv_data->queue.next,
 923                                        struct spi_message, queue);
 924
 925         /* Setup the SSP using the per chip configuration */
 926         drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
 927         if (restore_state(drv_data)) {
 928                 spin_unlock_irqrestore(&drv_data->lock, flags);
 929                 return;
 930         };
 931
 932         list_del_init(&drv_data->cur_msg->queue);
 933
 934         /* Initial message state */
 935         drv_data->cur_msg->state = START_STATE;
 936         drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
 937                                             struct spi_transfer, transfer_list);
 938
 939         dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
 940                 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
 941                 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
 942                 drv_data->cur_chip->ctl_reg);
 943
 944         dev_dbg(&drv_data->pdev->dev,
 945                 "the first transfer len is %d\n",
 946                 drv_data->cur_transfer->len);
 947
 948         /* Mark as busy and launch transfers */
 949         tasklet_schedule(&drv_data->pump_transfers);
 950
 951         drv_data->busy = 1;
 952         spin_unlock_irqrestore(&drv_data->lock, flags);
 953 }
 954
 955 /*
 956  * got a msg to transfer, queue it in drv_data->queue.
 957  * And kick off message pumper
 958  */
 959 static int transfer(struct spi_device *spi, struct spi_message *msg)
 960 {
 961         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
 962         unsigned long flags;
 963
 964         spin_lock_irqsave(&drv_data->lock, flags);
 965
 966         if (drv_data->run == QUEUE_STOPPED) {
 967                 spin_unlock_irqrestore(&drv_data->lock, flags);
 968                 return -ESHUTDOWN;
 969         }
 970
 971         msg->actual_length = 0;
 972         msg->status = -EINPROGRESS;
 973         msg->state = START_STATE;
 974
 975         dev_dbg(&spi->dev, "adding an msg in transfer() \n");
 976         list_add_tail(&msg->queue, &drv_data->queue);
 977
 978         if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
 979                 queue_work(drv_data->workqueue, &drv_data->pump_messages);
 980
 981         spin_unlock_irqrestore(&drv_data->lock, flags);
 982
 983         return 0;
 984 }
 985
 986 /* first setup for new devices */
 987 static int setup(struct spi_device *spi)
 988 {
 989         struct bfin5xx_spi_chip *chip_info = NULL;
 990         struct chip_data *chip;
 991         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
 992         u8 spi_flg;
 993
 994         /* Abort device setup if requested features are not supported */
 995         if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
 996                 dev_err(&spi->dev, "requested mode not fully supported\n");
 997                 return -EINVAL;
 998         }
 999
1000         /* Zero (the default) here means 8 bits */
1001         if (!spi->bits_per_word)
1002                 spi->bits_per_word = 8;
1003
1004         if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1005                 return -EINVAL;
1006
1007         /* Only alloc (or use chip_info) on first setup */
1008         chip = spi_get_ctldata(spi);
1009         if (chip == NULL) {
1010                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1011                 if (!chip)
1012                         return -ENOMEM;
1013
1014                 chip->enable_dma = 0;
1015                 chip_info = spi->controller_data;
1016         }
1017
1018         /* chip_info isn't always needed */
1019         if (chip_info) {
1020                 /* Make sure people stop trying to set fields via ctl_reg
1021                  * when they should actually be using common SPI framework.
1022                  * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1023                  * Not sure if a user actually needs/uses any of these,
1024                  * but let's assume (for now) they do.
1025                  */
1026                 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1027                         dev_err(&spi->dev, "do not set bits in ctl_reg "
1028                                 "that the SPI framework manages\n");
1029                         return -EINVAL;
1030                 }
1031
1032                 chip->enable_dma = chip_info->enable_dma != 0
1033                     && drv_data->master_info->enable_dma;
1034                 chip->ctl_reg = chip_info->ctl_reg;
1035                 chip->bits_per_word = chip_info->bits_per_word;
1036                 chip->cs_change_per_word = chip_info->cs_change_per_word;
1037                 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1038         }
1039
1040         /* translate common spi framework into our register */
1041         if (spi->mode & SPI_CPOL)
1042                 chip->ctl_reg |= CPOL;
1043         if (spi->mode & SPI_CPHA)
1044                 chip->ctl_reg |= CPHA;
1045         if (spi->mode & SPI_LSB_FIRST)
1046                 chip->ctl_reg |= LSBF;
1047         /* we dont support running in slave mode (yet?) */
1048         chip->ctl_reg |= MSTR;
1049
1050         /*
1051          * if any one SPI chip is registered and wants DMA, request the
1052          * DMA channel for it
1053          */
1054         if (chip->enable_dma && !dma_requested) {
1055                 /* register dma irq handler */
1056                 if (request_dma(spi_dma_ch, "BF53x_SPI_DMA") < 0) {
1057                         dev_dbg(&spi->dev,
1058                                 "Unable to request BlackFin SPI DMA channel\n");
1059                         return -ENODEV;
1060                 }
1061                 if (set_dma_callback(spi_dma_ch, (void *)dma_irq_handler,
1062                         drv_data) < 0) {
1063                         dev_dbg(&spi->dev, "Unable to set dma callback\n");
1064                         return -EPERM;
1065                 }
1066                 dma_disable_irq(spi_dma_ch);
1067                 dma_requested = 1;
1068         }
1069
1070         /*
1071          * Notice: for blackfin, the speed_hz is the value of register
1072          * SPI_BAUD, not the real baudrate
1073          */
1074         chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1075         spi_flg = ~(1 << (spi->chip_select));
1076         chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1077         chip->chip_select_num = spi->chip_select;
1078
1079         switch (chip->bits_per_word) {
1080         case 8:
1081                 chip->n_bytes = 1;
1082                 chip->width = CFG_SPI_WORDSIZE8;
1083                 chip->read = chip->cs_change_per_word ?
1084                         u8_cs_chg_reader : u8_reader;
1085                 chip->write = chip->cs_change_per_word ?
1086                         u8_cs_chg_writer : u8_writer;
1087                 chip->duplex = chip->cs_change_per_word ?
1088                         u8_cs_chg_duplex : u8_duplex;
1089                 break;
1090
1091         case 16:
1092                 chip->n_bytes = 2;
1093                 chip->width = CFG_SPI_WORDSIZE16;
1094                 chip->read = chip->cs_change_per_word ?
1095                         u16_cs_chg_reader : u16_reader;
1096                 chip->write = chip->cs_change_per_word ?
1097                         u16_cs_chg_writer : u16_writer;
1098                 chip->duplex = chip->cs_change_per_word ?
1099                         u16_cs_chg_duplex : u16_duplex;
1100                 break;
1101
1102         default:
1103                 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1104                                 chip->bits_per_word);
1105                 kfree(chip);
1106                 return -ENODEV;
1107         }
1108
1109         dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1110                         spi->modalias, chip->width, chip->enable_dma);
1111         dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1112                         chip->ctl_reg, chip->flag);
1113
1114         spi_set_ctldata(spi, chip);
1115
1116         return 0;
1117 }
1118
1119 /*
1120  * callback for spi framework.
1121  * clean driver specific data
1122  */
1123 static void cleanup(struct spi_device *spi)
1124 {
1125         struct chip_data *chip = spi_get_ctldata(spi);
1126
1127         kfree(chip);
1128 }
1129
1130 static inline int init_queue(struct driver_data *drv_data)
1131 {
1132         INIT_LIST_HEAD(&drv_data->queue);
1133         spin_lock_init(&drv_data->lock);
1134
1135         drv_data->run = QUEUE_STOPPED;
1136         drv_data->busy = 0;
1137
1138         /* init transfer tasklet */
1139         tasklet_init(&drv_data->pump_transfers,
1140                      pump_transfers, (unsigned long)drv_data);
1141
1142         /* init messages workqueue */
1143         INIT_WORK(&drv_data->pump_messages, pump_messages);
1144         drv_data->workqueue =
1145             create_singlethread_workqueue(drv_data->master->dev.parent->bus_id);
1146         if (drv_data->workqueue == NULL)
1147                 return -EBUSY;
1148
1149         return 0;
1150 }
1151
1152 static inline int start_queue(struct driver_data *drv_data)
1153 {
1154         unsigned long flags;
1155
1156         spin_lock_irqsave(&drv_data->lock, flags);
1157
1158         if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1159                 spin_unlock_irqrestore(&drv_data->lock, flags);
1160                 return -EBUSY;
1161         }
1162
1163         drv_data->run = QUEUE_RUNNING;
1164         drv_data->cur_msg = NULL;
1165         drv_data->cur_transfer = NULL;
1166         drv_data->cur_chip = NULL;
1167         spin_unlock_irqrestore(&drv_data->lock, flags);
1168
1169         queue_work(drv_data->workqueue, &drv_data->pump_messages);
1170
1171         return 0;
1172 }
1173
1174 static inline int stop_queue(struct driver_data *drv_data)
1175 {
1176         unsigned long flags;
1177         unsigned limit = 500;
1178         int status = 0;
1179
1180         spin_lock_irqsave(&drv_data->lock, flags);
1181
1182         /*
1183          * This is a bit lame, but is optimized for the common execution path.
1184          * A wait_queue on the drv_data->busy could be used, but then the common
1185          * execution path (pump_messages) would be required to call wake_up or
1186          * friends on every SPI message. Do this instead
1187          */
1188         drv_data->run = QUEUE_STOPPED;
1189         while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1190                 spin_unlock_irqrestore(&drv_data->lock, flags);
1191                 msleep(10);
1192                 spin_lock_irqsave(&drv_data->lock, flags);
1193         }
1194
1195         if (!list_empty(&drv_data->queue) || drv_data->busy)
1196                 status = -EBUSY;
1197
1198         spin_unlock_irqrestore(&drv_data->lock, flags);
1199
1200         return status;
1201 }
1202
1203 static inline int destroy_queue(struct driver_data *drv_data)
1204 {
1205         int status;
1206
1207         status = stop_queue(drv_data);
1208         if (status != 0)
1209                 return status;
1210
1211         destroy_workqueue(drv_data->workqueue);
1212
1213         return 0;
1214 }
1215
1216 static int setup_pin_mux(int action, int bus_num)
1217 {
1218
1219         u16 pin_req[3][4] = {
1220                 {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1221                 {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
1222                 {P_SPI2_SCK, P_SPI2_MISO, P_SPI2_MOSI, 0},
1223         };
1224
1225         if (action) {
1226                 if (peripheral_request_list(pin_req[bus_num], DRV_NAME))
1227                         return -EFAULT;
1228         } else {
1229                 peripheral_free_list(pin_req[bus_num]);
1230         }
1231
1232         return 0;
1233 }
1234
1235 static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1236 {
1237         struct device *dev = &pdev->dev;
1238         struct bfin5xx_spi_master *platform_info;
1239         struct spi_master *master;
1240         struct driver_data *drv_data = 0;
1241         struct resource *res;
1242         int status = 0;
1243
1244         platform_info = dev->platform_data;
1245
1246         /* Allocate master with space for drv_data */
1247         master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1248         if (!master) {
1249                 dev_err(&pdev->dev, "can not alloc spi_master\n");
1250                 return -ENOMEM;
1251         }
1252
1253         drv_data = spi_master_get_devdata(master);
1254         drv_data->master = master;
1255         drv_data->master_info = platform_info;
1256         drv_data->pdev = pdev;
1257
1258         master->bus_num = pdev->id;
1259         master->num_chipselect = platform_info->num_chipselect;
1260         master->cleanup = cleanup;
1261         master->setup = setup;
1262         master->transfer = transfer;
1263
1264         /* Find and map our resources */
1265         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1266         if (res == NULL) {
1267                 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1268                 status = -ENOENT;
1269                 goto out_error_get_res;
1270         }
1271
1272         spi_regs_base = (u32) ioremap(res->start, (res->end - res->start)+1);
1273         if (!spi_regs_base) {
1274                 dev_err(dev, "Cannot map IO\n");
1275                 status = -ENXIO;
1276                 goto out_error_ioremap;
1277         }
1278
1279         spi_dma_ch = platform_get_irq(pdev, 0);
1280         if (spi_dma_ch < 0) {
1281                 dev_err(dev, "No DMA channel specified\n");
1282                 status = -ENOENT;
1283                 goto out_error_no_dma_ch;
1284         }
1285
1286         /* Initial and start queue */
1287         status = init_queue(drv_data);
1288         if (status != 0) {
1289                 dev_err(dev, "problem initializing queue\n");
1290                 goto out_error_queue_alloc;
1291         }
1292
1293         status = start_queue(drv_data);
1294         if (status != 0) {
1295                 dev_err(dev, "problem starting queue\n");
1296                 goto out_error_queue_alloc;
1297         }
1298
1299         /* Register with the SPI framework */
1300         platform_set_drvdata(pdev, drv_data);
1301         status = spi_register_master(master);
1302         if (status != 0) {
1303                 dev_err(dev, "problem registering spi master\n");
1304                 goto out_error_queue_alloc;
1305         }
1306
1307         if (setup_pin_mux(1, master->bus_num)) {
1308                 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1309                 goto out_error;
1310         }
1311
1312         dev_info(dev, "%s, Version %s, regs_base @ 0x%08x\n",
1313                 DRV_DESC, DRV_VERSION, spi_regs_base);
1314         return status;
1315
1316 out_error_queue_alloc:
1317         destroy_queue(drv_data);
1318 out_error_no_dma_ch:
1319         iounmap((void *) spi_regs_base);
1320 out_error_ioremap:
1321 out_error_get_res:
1322 out_error:
1323         spi_master_put(master);
1324
1325         return status;
1326 }
1327
1328 /* stop hardware and remove the driver */
1329 static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1330 {
1331         struct driver_data *drv_data = platform_get_drvdata(pdev);
1332         int status = 0;
1333
1334         if (!drv_data)
1335                 return 0;
1336
1337         /* Remove the queue */
1338         status = destroy_queue(drv_data);
1339         if (status != 0)
1340                 return status;
1341
1342         /* Disable the SSP at the peripheral and SOC level */
1343         bfin_spi_disable(drv_data);
1344
1345         /* Release DMA */
1346         if (drv_data->master_info->enable_dma) {
1347                 if (dma_channel_active(spi_dma_ch))
1348                         free_dma(spi_dma_ch);
1349         }
1350
1351         /* Disconnect from the SPI framework */
1352         spi_unregister_master(drv_data->master);
1353
1354         setup_pin_mux(0, drv_data->master->bus_num);
1355
1356         /* Prevent double remove */
1357         platform_set_drvdata(pdev, NULL);
1358
1359         return 0;
1360 }
1361
1362 #ifdef CONFIG_PM
1363 static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1364 {
1365         struct driver_data *drv_data = platform_get_drvdata(pdev);
1366         int status = 0;
1367
1368         status = stop_queue(drv_data);
1369         if (status != 0)
1370                 return status;
1371
1372         /* stop hardware */
1373         bfin_spi_disable(drv_data);
1374
1375         return 0;
1376 }
1377
1378 static int bfin5xx_spi_resume(struct platform_device *pdev)
1379 {
1380         struct driver_data *drv_data = platform_get_drvdata(pdev);
1381         int status = 0;
1382
1383         /* Enable the SPI interface */
1384         bfin_spi_enable(drv_data);
1385
1386         /* Start the queue running */
1387         status = start_queue(drv_data);
1388         if (status != 0) {
1389                 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1390                 return status;
1391         }
1392
1393         return 0;
1394 }
1395 #else
1396 #define bfin5xx_spi_suspend NULL
1397 #define bfin5xx_spi_resume NULL
1398 #endif                          /* CONFIG_PM */
1399
1400 MODULE_ALIAS("bfin-spi-master");        /* for platform bus hotplug */
1401 static struct platform_driver bfin5xx_spi_driver = {
1402         .driver = {
1403                 .name   = DRV_NAME,
1404                 .owner  = THIS_MODULE,
1405         },
1406         .suspend        = bfin5xx_spi_suspend,
1407         .resume         = bfin5xx_spi_resume,
1408         .remove         = __devexit_p(bfin5xx_spi_remove),
1409 };
1410
1411 static int __init bfin5xx_spi_init(void)
1412 {
1413         return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
1414 }
1415 module_init(bfin5xx_spi_init);
1416
1417 static void __exit bfin5xx_spi_exit(void)
1418 {
1419         platform_driver_unregister(&bfin5xx_spi_driver);
1420 }
1421 module_exit(bfin5xx_spi_exit);