2 * dw_spi.c - Designware SPI core controller driver (refer pxa2xx_spi.c)
4 * Copyright (c) 2009, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 #include <linux/dma-mapping.h>
21 #include <linux/interrupt.h>
22 #include <linux/highmem.h>
23 #include <linux/delay.h>
25 #include <linux/spi/dw_spi.h>
26 #include <linux/spi/spi.h>
28 #ifdef CONFIG_DEBUG_FS
29 #include <linux/debugfs.h>
32 #define START_STATE ((void *)0)
33 #define RUNNING_STATE ((void *)1)
34 #define DONE_STATE ((void *)2)
35 #define ERROR_STATE ((void *)-1)
37 #define QUEUE_RUNNING 0
38 #define QUEUE_STOPPED 1
40 #define MRST_SPI_DEASSERT 0
41 #define MRST_SPI_ASSERT 1
43 /* Slave spi_dev related */
46 u8 cs; /* chip select pin */
47 u8 n_bytes; /* current is a 1/2/4 byte op */
48 u8 tmode; /* TR/TO/RO/EEPROM */
49 u8 type; /* SPI/SSP/MicroWire */
51 u8 poll_mode; /* 1 means use poll mode */
58 u16 clk_div; /* baud rate divider */
59 u32 speed_hz; /* baud rate */
60 int (*write)(struct dw_spi *dws);
61 int (*read)(struct dw_spi *dws);
62 void (*cs_control)(u32 command);
65 #ifdef CONFIG_DEBUG_FS
66 static int spi_show_regs_open(struct inode *inode, struct file *file)
68 file->private_data = inode->i_private;
72 #define SPI_REGS_BUFSIZE 1024
73 static ssize_t spi_show_regs(struct file *file, char __user *user_buf,
74 size_t count, loff_t *ppos)
81 dws = file->private_data;
83 buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
87 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
88 "MRST SPI0 registers:\n");
89 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
90 "=================================\n");
91 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
92 "CTRL0: \t\t0x%08x\n", dw_readl(dws, ctrl0));
93 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
94 "CTRL1: \t\t0x%08x\n", dw_readl(dws, ctrl1));
95 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
96 "SSIENR: \t0x%08x\n", dw_readl(dws, ssienr));
97 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
98 "SER: \t\t0x%08x\n", dw_readl(dws, ser));
99 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
100 "BAUDR: \t\t0x%08x\n", dw_readl(dws, baudr));
101 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
102 "TXFTLR: \t0x%08x\n", dw_readl(dws, txfltr));
103 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
104 "RXFTLR: \t0x%08x\n", dw_readl(dws, rxfltr));
105 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
106 "TXFLR: \t\t0x%08x\n", dw_readl(dws, txflr));
107 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
108 "RXFLR: \t\t0x%08x\n", dw_readl(dws, rxflr));
109 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
110 "SR: \t\t0x%08x\n", dw_readl(dws, sr));
111 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
112 "IMR: \t\t0x%08x\n", dw_readl(dws, imr));
113 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
114 "ISR: \t\t0x%08x\n", dw_readl(dws, isr));
115 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
116 "DMACR: \t\t0x%08x\n", dw_readl(dws, dmacr));
117 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
118 "DMATDLR: \t0x%08x\n", dw_readl(dws, dmatdlr));
119 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
120 "DMARDLR: \t0x%08x\n", dw_readl(dws, dmardlr));
121 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
122 "=================================\n");
124 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
129 static const struct file_operations mrst_spi_regs_ops = {
130 .owner = THIS_MODULE,
131 .open = spi_show_regs_open,
132 .read = spi_show_regs,
135 static int mrst_spi_debugfs_init(struct dw_spi *dws)
137 dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
141 debugfs_create_file("registers", S_IFREG | S_IRUGO,
142 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
146 static void mrst_spi_debugfs_remove(struct dw_spi *dws)
149 debugfs_remove_recursive(dws->debugfs);
153 static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
157 static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
160 #endif /* CONFIG_DEBUG_FS */
162 static void wait_till_not_busy(struct dw_spi *dws)
164 unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);
166 while (time_before(jiffies, end)) {
167 if (!(dw_readw(dws, sr) & SR_BUSY))
170 dev_err(&dws->master->dev,
171 "DW SPI: Stutus keeps busy for 1000us after a read/write!\n");
174 static void flush(struct dw_spi *dws)
176 while (dw_readw(dws, sr) & SR_RF_NOT_EMPT)
179 wait_till_not_busy(dws);
182 static void null_cs_control(u32 command)
186 static int null_writer(struct dw_spi *dws)
188 u8 n_bytes = dws->n_bytes;
190 if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
191 || (dws->tx == dws->tx_end))
193 dw_writew(dws, dr, 0);
196 wait_till_not_busy(dws);
200 static int null_reader(struct dw_spi *dws)
202 u8 n_bytes = dws->n_bytes;
204 while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
205 && (dws->rx < dws->rx_end)) {
209 wait_till_not_busy(dws);
210 return dws->rx == dws->rx_end;
213 static int u8_writer(struct dw_spi *dws)
215 if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
216 || (dws->tx == dws->tx_end))
219 dw_writew(dws, dr, *(u8 *)(dws->tx));
222 wait_till_not_busy(dws);
226 static int u8_reader(struct dw_spi *dws)
228 while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
229 && (dws->rx < dws->rx_end)) {
230 *(u8 *)(dws->rx) = dw_readw(dws, dr);
234 wait_till_not_busy(dws);
235 return dws->rx == dws->rx_end;
238 static int u16_writer(struct dw_spi *dws)
240 if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
241 || (dws->tx == dws->tx_end))
244 dw_writew(dws, dr, *(u16 *)(dws->tx));
247 wait_till_not_busy(dws);
251 static int u16_reader(struct dw_spi *dws)
255 while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
256 && (dws->rx < dws->rx_end)) {
257 temp = dw_readw(dws, dr);
258 *(u16 *)(dws->rx) = temp;
262 wait_till_not_busy(dws);
263 return dws->rx == dws->rx_end;
266 static void *next_transfer(struct dw_spi *dws)
268 struct spi_message *msg = dws->cur_msg;
269 struct spi_transfer *trans = dws->cur_transfer;
271 /* Move to next transfer */
272 if (trans->transfer_list.next != &msg->transfers) {
274 list_entry(trans->transfer_list.next,
277 return RUNNING_STATE;
283 * Note: first step is the protocol driver prepares
284 * a dma-capable memory, and this func just need translate
285 * the virt addr to physical
287 static int map_dma_buffers(struct dw_spi *dws)
289 if (!dws->cur_msg->is_dma_mapped || !dws->dma_inited
290 || !dws->cur_chip->enable_dma)
293 if (dws->cur_transfer->tx_dma)
294 dws->tx_dma = dws->cur_transfer->tx_dma;
296 if (dws->cur_transfer->rx_dma)
297 dws->rx_dma = dws->cur_transfer->rx_dma;
302 /* Caller already set message->status; dma and pio irqs are blocked */
303 static void giveback(struct dw_spi *dws)
305 struct spi_transfer *last_transfer;
307 struct spi_message *msg;
309 spin_lock_irqsave(&dws->lock, flags);
312 dws->cur_transfer = NULL;
313 dws->prev_chip = dws->cur_chip;
314 dws->cur_chip = NULL;
316 queue_work(dws->workqueue, &dws->pump_messages);
317 spin_unlock_irqrestore(&dws->lock, flags);
319 last_transfer = list_entry(msg->transfers.prev,
323 if (!last_transfer->cs_change)
324 dws->cs_control(MRST_SPI_DEASSERT);
328 msg->complete(msg->context);
331 static void int_error_stop(struct dw_spi *dws, const char *msg)
333 /* Stop and reset hw */
335 spi_enable_chip(dws, 0);
337 dev_err(&dws->master->dev, "%s\n", msg);
338 dws->cur_msg->state = ERROR_STATE;
339 tasklet_schedule(&dws->pump_transfers);
342 static void transfer_complete(struct dw_spi *dws)
344 /* Update total byte transfered return count actual bytes read */
345 dws->cur_msg->actual_length += dws->len;
347 /* Move to next transfer */
348 dws->cur_msg->state = next_transfer(dws);
350 /* Handle end of message */
351 if (dws->cur_msg->state == DONE_STATE) {
352 dws->cur_msg->status = 0;
355 tasklet_schedule(&dws->pump_transfers);
358 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
360 u16 irq_status, irq_mask = 0x3f;
361 u32 int_level = dws->fifo_len / 2;
364 irq_status = dw_readw(dws, isr) & irq_mask;
366 if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
367 dw_readw(dws, txoicr);
368 dw_readw(dws, rxoicr);
369 dw_readw(dws, rxuicr);
370 int_error_stop(dws, "interrupt_transfer: fifo overrun");
374 if (irq_status & SPI_INT_TXEI) {
375 spi_mask_intr(dws, SPI_INT_TXEI);
377 left = (dws->tx_end - dws->tx) / dws->n_bytes;
378 left = (left > int_level) ? int_level : left;
384 /* Re-enable the IRQ if there is still data left to tx */
385 if (dws->tx_end > dws->tx)
386 spi_umask_intr(dws, SPI_INT_TXEI);
388 transfer_complete(dws);
394 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
396 struct dw_spi *dws = dev_id;
399 spi_mask_intr(dws, SPI_INT_TXEI);
404 return dws->transfer_handler(dws);
407 /* Must be called inside pump_transfers() */
408 static void poll_transfer(struct dw_spi *dws)
411 while (dws->write(dws))
416 transfer_complete(dws);
419 static void dma_transfer(struct dw_spi *dws, int cs_change)
423 static void pump_transfers(unsigned long data)
425 struct dw_spi *dws = (struct dw_spi *)data;
426 struct spi_message *message = NULL;
427 struct spi_transfer *transfer = NULL;
428 struct spi_transfer *previous = NULL;
429 struct spi_device *spi = NULL;
430 struct chip_data *chip = NULL;
439 /* Get current state information */
440 message = dws->cur_msg;
441 transfer = dws->cur_transfer;
442 chip = dws->cur_chip;
445 if (unlikely(!chip->clk_div))
446 chip->clk_div = dws->max_freq / chip->speed_hz;
448 if (message->state == ERROR_STATE) {
449 message->status = -EIO;
453 /* Handle end of message */
454 if (message->state == DONE_STATE) {
459 /* Delay if requested at end of transfer*/
460 if (message->state == RUNNING_STATE) {
461 previous = list_entry(transfer->transfer_list.prev,
464 if (previous->delay_usecs)
465 udelay(previous->delay_usecs);
468 dws->n_bytes = chip->n_bytes;
469 dws->dma_width = chip->dma_width;
470 dws->cs_control = chip->cs_control;
472 dws->rx_dma = transfer->rx_dma;
473 dws->tx_dma = transfer->tx_dma;
474 dws->tx = (void *)transfer->tx_buf;
475 dws->tx_end = dws->tx + transfer->len;
476 dws->rx = transfer->rx_buf;
477 dws->rx_end = dws->rx + transfer->len;
478 dws->write = dws->tx ? chip->write : null_writer;
479 dws->read = dws->rx ? chip->read : null_reader;
480 dws->cs_change = transfer->cs_change;
481 dws->len = dws->cur_transfer->len;
482 if (chip != dws->prev_chip)
487 /* Handle per transfer options for bpw and speed */
488 if (transfer->speed_hz) {
489 speed = chip->speed_hz;
491 if (transfer->speed_hz != speed) {
492 speed = transfer->speed_hz;
493 if (speed > dws->max_freq) {
494 printk(KERN_ERR "MRST SPI0: unsupported"
495 "freq: %dHz\n", speed);
496 message->status = -EIO;
500 /* clk_div doesn't support odd number */
501 clk_div = dws->max_freq / speed;
502 clk_div = (clk_div + 1) & 0xfffe;
504 chip->speed_hz = speed;
505 chip->clk_div = clk_div;
508 if (transfer->bits_per_word) {
509 bits = transfer->bits_per_word;
515 dws->read = (dws->read != null_reader) ?
516 u8_reader : null_reader;
517 dws->write = (dws->write != null_writer) ?
518 u8_writer : null_writer;
523 dws->read = (dws->read != null_reader) ?
524 u16_reader : null_reader;
525 dws->write = (dws->write != null_writer) ?
526 u16_writer : null_writer;
529 printk(KERN_ERR "MRST SPI0: unsupported bits:"
531 message->status = -EIO;
536 | (chip->type << SPI_FRF_OFFSET)
537 | (spi->mode << SPI_MODE_OFFSET)
538 | (chip->tmode << SPI_TMOD_OFFSET);
540 message->state = RUNNING_STATE;
542 /* Check if current transfer is a DMA transaction */
543 dws->dma_mapped = map_dma_buffers(dws);
547 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
549 if (!dws->dma_mapped && !chip->poll_mode) {
550 int templen = dws->len / dws->n_bytes;
551 txint_level = dws->fifo_len / 2;
552 txint_level = (templen > txint_level) ? txint_level : templen;
554 imask |= SPI_INT_TXEI;
555 dws->transfer_handler = interrupt_transfer;
559 * Reprogram registers only if
560 * 1. chip select changes
561 * 2. clk_div is changed
562 * 3. control value changes
564 if (dw_readw(dws, ctrl0) != cr0 || cs_change || clk_div || imask) {
565 spi_enable_chip(dws, 0);
567 if (dw_readw(dws, ctrl0) != cr0)
568 dw_writew(dws, ctrl0, cr0);
570 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
571 spi_chip_sel(dws, spi->chip_select);
573 /* Set the interrupt mask, for poll mode just diable all int */
574 spi_mask_intr(dws, 0xff);
576 spi_umask_intr(dws, imask);
578 dw_writew(dws, txfltr, txint_level);
580 spi_enable_chip(dws, 1);
582 dws->prev_chip = chip;
586 dma_transfer(dws, cs_change);
598 static void pump_messages(struct work_struct *work)
601 container_of(work, struct dw_spi, pump_messages);
604 /* Lock queue and check for queue work */
605 spin_lock_irqsave(&dws->lock, flags);
606 if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
608 spin_unlock_irqrestore(&dws->lock, flags);
612 /* Make sure we are not already running a message */
614 spin_unlock_irqrestore(&dws->lock, flags);
618 /* Extract head of queue */
619 dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
620 list_del_init(&dws->cur_msg->queue);
622 /* Initial message state*/
623 dws->cur_msg->state = START_STATE;
624 dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
627 dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
629 /* Mark as busy and launch transfers */
630 tasklet_schedule(&dws->pump_transfers);
633 spin_unlock_irqrestore(&dws->lock, flags);
636 /* spi_device use this to queue in their spi_msg */
637 static int dw_spi_transfer(struct spi_device *spi, struct spi_message *msg)
639 struct dw_spi *dws = spi_master_get_devdata(spi->master);
642 spin_lock_irqsave(&dws->lock, flags);
644 if (dws->run == QUEUE_STOPPED) {
645 spin_unlock_irqrestore(&dws->lock, flags);
649 msg->actual_length = 0;
650 msg->status = -EINPROGRESS;
651 msg->state = START_STATE;
653 list_add_tail(&msg->queue, &dws->queue);
655 if (dws->run == QUEUE_RUNNING && !dws->busy) {
657 if (dws->cur_transfer || dws->cur_msg)
658 queue_work(dws->workqueue,
659 &dws->pump_messages);
661 /* If no other data transaction in air, just go */
662 spin_unlock_irqrestore(&dws->lock, flags);
663 pump_messages(&dws->pump_messages);
668 spin_unlock_irqrestore(&dws->lock, flags);
672 /* This may be called twice for each spi dev */
673 static int dw_spi_setup(struct spi_device *spi)
675 struct dw_spi_chip *chip_info = NULL;
676 struct chip_data *chip;
678 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
681 /* Only alloc on first setup */
682 chip = spi_get_ctldata(spi);
684 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
688 chip->cs_control = null_cs_control;
689 chip->enable_dma = 0;
693 * Protocol drivers may change the chip settings, so...
694 * if chip_info exists, use it
696 chip_info = spi->controller_data;
698 /* chip_info doesn't always exist */
700 if (chip_info->cs_control)
701 chip->cs_control = chip_info->cs_control;
703 chip->poll_mode = chip_info->poll_mode;
704 chip->type = chip_info->type;
706 chip->rx_threshold = 0;
707 chip->tx_threshold = 0;
709 chip->enable_dma = chip_info->enable_dma;
712 if (spi->bits_per_word <= 8) {
715 chip->read = u8_reader;
716 chip->write = u8_writer;
717 } else if (spi->bits_per_word <= 16) {
720 chip->read = u16_reader;
721 chip->write = u16_writer;
723 /* Never take >16b case for MRST SPIC */
724 dev_err(&spi->dev, "invalid wordsize\n");
727 chip->bits_per_word = spi->bits_per_word;
729 if (!spi->max_speed_hz) {
730 dev_err(&spi->dev, "No max speed HZ parameter\n");
733 chip->speed_hz = spi->max_speed_hz;
735 chip->tmode = 0; /* Tx & Rx */
736 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
737 chip->cr0 = (chip->bits_per_word - 1)
738 | (chip->type << SPI_FRF_OFFSET)
739 | (spi->mode << SPI_MODE_OFFSET)
740 | (chip->tmode << SPI_TMOD_OFFSET);
742 spi_set_ctldata(spi, chip);
746 static void dw_spi_cleanup(struct spi_device *spi)
748 struct chip_data *chip = spi_get_ctldata(spi);
752 static int __devinit init_queue(struct dw_spi *dws)
754 INIT_LIST_HEAD(&dws->queue);
755 spin_lock_init(&dws->lock);
757 dws->run = QUEUE_STOPPED;
760 tasklet_init(&dws->pump_transfers,
761 pump_transfers, (unsigned long)dws);
763 INIT_WORK(&dws->pump_messages, pump_messages);
764 dws->workqueue = create_singlethread_workqueue(
765 dev_name(dws->master->dev.parent));
766 if (dws->workqueue == NULL)
772 static int start_queue(struct dw_spi *dws)
776 spin_lock_irqsave(&dws->lock, flags);
778 if (dws->run == QUEUE_RUNNING || dws->busy) {
779 spin_unlock_irqrestore(&dws->lock, flags);
783 dws->run = QUEUE_RUNNING;
785 dws->cur_transfer = NULL;
786 dws->cur_chip = NULL;
787 dws->prev_chip = NULL;
788 spin_unlock_irqrestore(&dws->lock, flags);
790 queue_work(dws->workqueue, &dws->pump_messages);
795 static int stop_queue(struct dw_spi *dws)
801 spin_lock_irqsave(&dws->lock, flags);
802 dws->run = QUEUE_STOPPED;
803 while (!list_empty(&dws->queue) && dws->busy && limit--) {
804 spin_unlock_irqrestore(&dws->lock, flags);
806 spin_lock_irqsave(&dws->lock, flags);
809 if (!list_empty(&dws->queue) || dws->busy)
811 spin_unlock_irqrestore(&dws->lock, flags);
816 static int destroy_queue(struct dw_spi *dws)
820 status = stop_queue(dws);
823 destroy_workqueue(dws->workqueue);
827 /* Restart the controller, disable all interrupts, clean rx fifo */
828 static void spi_hw_init(struct dw_spi *dws)
830 spi_enable_chip(dws, 0);
831 spi_mask_intr(dws, 0xff);
832 spi_enable_chip(dws, 1);
836 * Try to detect the FIFO depth if not set by interface driver,
837 * the depth could be from 2 to 256 from HW spec
839 if (!dws->fifo_len) {
841 for (fifo = 2; fifo <= 257; fifo++) {
842 dw_writew(dws, txfltr, fifo);
843 if (fifo != dw_readw(dws, txfltr))
847 dws->fifo_len = (fifo == 257) ? 0 : fifo;
848 dw_writew(dws, txfltr, 0);
852 int __devinit dw_spi_add_host(struct dw_spi *dws)
854 struct spi_master *master;
859 master = spi_alloc_master(dws->parent_dev, 0);
865 dws->master = master;
866 dws->type = SSI_MOTO_SPI;
867 dws->prev_chip = NULL;
869 dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
871 ret = request_irq(dws->irq, dw_spi_irq, 0,
874 dev_err(&master->dev, "can not get IRQ\n");
875 goto err_free_master;
878 master->mode_bits = SPI_CPOL | SPI_CPHA;
879 master->bus_num = dws->bus_num;
880 master->num_chipselect = dws->num_cs;
881 master->cleanup = dw_spi_cleanup;
882 master->setup = dw_spi_setup;
883 master->transfer = dw_spi_transfer;
890 /* Initial and start queue */
891 ret = init_queue(dws);
893 dev_err(&master->dev, "problem initializing queue\n");
896 ret = start_queue(dws);
898 dev_err(&master->dev, "problem starting queue\n");
902 spi_master_set_devdata(master, dws);
903 ret = spi_register_master(master);
905 dev_err(&master->dev, "problem registering spi master\n");
906 goto err_queue_alloc;
909 mrst_spi_debugfs_init(dws);
915 spi_enable_chip(dws, 0);
916 free_irq(dws->irq, dws);
918 spi_master_put(master);
922 EXPORT_SYMBOL(dw_spi_add_host);
924 void __devexit dw_spi_remove_host(struct dw_spi *dws)
930 mrst_spi_debugfs_remove(dws);
932 /* Remove the queue */
933 status = destroy_queue(dws);
935 dev_err(&dws->master->dev, "dw_spi_remove: workqueue will not "
936 "complete, message memory not freed\n");
938 spi_enable_chip(dws, 0);
941 free_irq(dws->irq, dws);
943 /* Disconnect from the SPI framework */
944 spi_unregister_master(dws->master);
947 int dw_spi_suspend_host(struct dw_spi *dws)
951 ret = stop_queue(dws);
954 spi_enable_chip(dws, 0);
958 EXPORT_SYMBOL(dw_spi_suspend_host);
960 int dw_spi_resume_host(struct dw_spi *dws)
965 ret = start_queue(dws);
967 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
970 EXPORT_SYMBOL(dw_spi_resume_host);
972 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
973 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
974 MODULE_LICENSE("GPL v2");