SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/spi/dw_spi.c

   1 /*
   2  * dw_spi.c - Designware SPI core controller driver (refer pxa2xx_spi.c)
   3  *
   4  * Copyright (c) 2009, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  */
  19
  20 #include <linux/dma-mapping.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/highmem.h>
  23 #include <linux/delay.h>
  24
  25 #include <linux/spi/dw_spi.h>
  26 #include <linux/spi/spi.h>
  27
  28 #ifdef CONFIG_DEBUG_FS
  29 #include <linux/debugfs.h>
  30 #endif
  31
  32 #define START_STATE     ((void *)0)
  33 #define RUNNING_STATE   ((void *)1)
  34 #define DONE_STATE      ((void *)2)
  35 #define ERROR_STATE     ((void *)-1)
  36
  37 #define QUEUE_RUNNING   0
  38 #define QUEUE_STOPPED   1
  39
  40 #define MRST_SPI_DEASSERT       0
  41 #define MRST_SPI_ASSERT         1
  42
  43 /* Slave spi_dev related */
  44 struct chip_data {
  45         u16 cr0;
  46         u8 cs;                  /* chip select pin */
  47         u8 n_bytes;             /* current is a 1/2/4 byte op */
  48         u8 tmode;               /* TR/TO/RO/EEPROM */
  49         u8 type;                /* SPI/SSP/MicroWire */
  50
  51         u8 poll_mode;           /* 1 means use poll mode */
  52
  53         u32 dma_width;
  54         u32 rx_threshold;
  55         u32 tx_threshold;
  56         u8 enable_dma;
  57         u8 bits_per_word;
  58         u16 clk_div;            /* baud rate divider */
  59         u32 speed_hz;           /* baud rate */
  60         int (*write)(struct dw_spi *dws);
  61         int (*read)(struct dw_spi *dws);
  62         void (*cs_control)(u32 command);
  63 };
  64
  65 #ifdef CONFIG_DEBUG_FS
  66 static int spi_show_regs_open(struct inode *inode, struct file *file)
  67 {
  68         file->private_data = inode->i_private;
  69         return 0;
  70 }
  71
  72 #define SPI_REGS_BUFSIZE        1024
  73 static ssize_t  spi_show_regs(struct file *file, char __user *user_buf,
  74                                 size_t count, loff_t *ppos)
  75 {
  76         struct dw_spi *dws;
  77         char *buf;
  78         u32 len = 0;
  79         ssize_t ret;
  80
  81         dws = file->private_data;
  82
  83         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
  84         if (!buf)
  85                 return 0;
  86
  87         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  88                         "MRST SPI0 registers:\n");
  89         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  90                         "=================================\n");
  91         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  92                         "CTRL0: \t\t0x%08x\n", dw_readl(dws, ctrl0));
  93         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  94                         "CTRL1: \t\t0x%08x\n", dw_readl(dws, ctrl1));
  95         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  96                         "SSIENR: \t0x%08x\n", dw_readl(dws, ssienr));
  97         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  98                         "SER: \t\t0x%08x\n", dw_readl(dws, ser));
  99         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 100                         "BAUDR: \t\t0x%08x\n", dw_readl(dws, baudr));
 101         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 102                         "TXFTLR: \t0x%08x\n", dw_readl(dws, txfltr));
 103         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 104                         "RXFTLR: \t0x%08x\n", dw_readl(dws, rxfltr));
 105         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 106                         "TXFLR: \t\t0x%08x\n", dw_readl(dws, txflr));
 107         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 108                         "RXFLR: \t\t0x%08x\n", dw_readl(dws, rxflr));
 109         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 110                         "SR: \t\t0x%08x\n", dw_readl(dws, sr));
 111         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 112                         "IMR: \t\t0x%08x\n", dw_readl(dws, imr));
 113         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 114                         "ISR: \t\t0x%08x\n", dw_readl(dws, isr));
 115         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 116                         "DMACR: \t\t0x%08x\n", dw_readl(dws, dmacr));
 117         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 118                         "DMATDLR: \t0x%08x\n", dw_readl(dws, dmatdlr));
 119         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 120                         "DMARDLR: \t0x%08x\n", dw_readl(dws, dmardlr));
 121         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 122                         "=================================\n");
 123
 124         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 125         kfree(buf);
 126         return ret;
 127 }
 128
 129 static const struct file_operations mrst_spi_regs_ops = {
 130         .owner          = THIS_MODULE,
 131         .open           = spi_show_regs_open,
 132         .read           = spi_show_regs,
 133 };
 134
 135 static int mrst_spi_debugfs_init(struct dw_spi *dws)
 136 {
 137         dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
 138         if (!dws->debugfs)
 139                 return -ENOMEM;
 140
 141         debugfs_create_file("registers", S_IFREG | S_IRUGO,
 142                 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
 143         return 0;
 144 }
 145
 146 static void mrst_spi_debugfs_remove(struct dw_spi *dws)
 147 {
 148         if (dws->debugfs)
 149                 debugfs_remove_recursive(dws->debugfs);
 150 }
 151
 152 #else
 153 static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
 154 {
 155 }
 156
 157 static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
 158 {
 159 }
 160 #endif /* CONFIG_DEBUG_FS */
 161
 162 static void wait_till_not_busy(struct dw_spi *dws)
 163 {
 164         unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);
 165
 166         while (time_before(jiffies, end)) {
 167                 if (!(dw_readw(dws, sr) & SR_BUSY))
 168                         return;
 169         }
 170         dev_err(&dws->master->dev,
 171                 "DW SPI: Stutus keeps busy for 1000us after a read/write!\n");
 172 }
 173
 174 static void flush(struct dw_spi *dws)
 175 {
 176         while (dw_readw(dws, sr) & SR_RF_NOT_EMPT)
 177                 dw_readw(dws, dr);
 178
 179         wait_till_not_busy(dws);
 180 }
 181
 182 static void null_cs_control(u32 command)
 183 {
 184 }
 185
 186 static int null_writer(struct dw_spi *dws)
 187 {
 188         u8 n_bytes = dws->n_bytes;
 189
 190         if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
 191                 || (dws->tx == dws->tx_end))
 192                 return 0;
 193         dw_writew(dws, dr, 0);
 194         dws->tx += n_bytes;
 195
 196         wait_till_not_busy(dws);
 197         return 1;
 198 }
 199
 200 static int null_reader(struct dw_spi *dws)
 201 {
 202         u8 n_bytes = dws->n_bytes;
 203
 204         while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
 205                 && (dws->rx < dws->rx_end)) {
 206                 dw_readw(dws, dr);
 207                 dws->rx += n_bytes;
 208         }
 209         wait_till_not_busy(dws);
 210         return dws->rx == dws->rx_end;
 211 }
 212
 213 static int u8_writer(struct dw_spi *dws)
 214 {
 215         if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
 216                 || (dws->tx == dws->tx_end))
 217                 return 0;
 218
 219         dw_writew(dws, dr, *(u8 *)(dws->tx));
 220         ++dws->tx;
 221
 222         wait_till_not_busy(dws);
 223         return 1;
 224 }
 225
 226 static int u8_reader(struct dw_spi *dws)
 227 {
 228         while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
 229                 && (dws->rx < dws->rx_end)) {
 230                 *(u8 *)(dws->rx) = dw_readw(dws, dr);
 231                 ++dws->rx;
 232         }
 233
 234         wait_till_not_busy(dws);
 235         return dws->rx == dws->rx_end;
 236 }
 237
 238 static int u16_writer(struct dw_spi *dws)
 239 {
 240         if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
 241                 || (dws->tx == dws->tx_end))
 242                 return 0;
 243
 244         dw_writew(dws, dr, *(u16 *)(dws->tx));
 245         dws->tx += 2;
 246
 247         wait_till_not_busy(dws);
 248         return 1;
 249 }
 250
 251 static int u16_reader(struct dw_spi *dws)
 252 {
 253         u16 temp;
 254
 255         while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
 256                 && (dws->rx < dws->rx_end)) {
 257                 temp = dw_readw(dws, dr);
 258                 *(u16 *)(dws->rx) = temp;
 259                 dws->rx += 2;
 260         }
 261
 262         wait_till_not_busy(dws);
 263         return dws->rx == dws->rx_end;
 264 }
 265
 266 static void *next_transfer(struct dw_spi *dws)
 267 {
 268         struct spi_message *msg = dws->cur_msg;
 269         struct spi_transfer *trans = dws->cur_transfer;
 270
 271         /* Move to next transfer */
 272         if (trans->transfer_list.next != &msg->transfers) {
 273                 dws->cur_transfer =
 274                         list_entry(trans->transfer_list.next,
 275                                         struct spi_transfer,
 276                                         transfer_list);
 277                 return RUNNING_STATE;
 278         } else
 279                 return DONE_STATE;
 280 }
 281
 282 /*
 283  * Note: first step is the protocol driver prepares
 284  * a dma-capable memory, and this func just need translate
 285  * the virt addr to physical
 286  */
 287 static int map_dma_buffers(struct dw_spi *dws)
 288 {
 289         if (!dws->cur_msg->is_dma_mapped || !dws->dma_inited
 290                 || !dws->cur_chip->enable_dma)
 291                 return 0;
 292
 293         if (dws->cur_transfer->tx_dma)
 294                 dws->tx_dma = dws->cur_transfer->tx_dma;
 295
 296         if (dws->cur_transfer->rx_dma)
 297                 dws->rx_dma = dws->cur_transfer->rx_dma;
 298
 299         return 1;
 300 }
 301
 302 /* Caller already set message->status; dma and pio irqs are blocked */
 303 static void giveback(struct dw_spi *dws)
 304 {
 305         struct spi_transfer *last_transfer;
 306         unsigned long flags;
 307         struct spi_message *msg;
 308
 309         spin_lock_irqsave(&dws->lock, flags);
 310         msg = dws->cur_msg;
 311         dws->cur_msg = NULL;
 312         dws->cur_transfer = NULL;
 313         dws->prev_chip = dws->cur_chip;
 314         dws->cur_chip = NULL;
 315         dws->dma_mapped = 0;
 316         queue_work(dws->workqueue, &dws->pump_messages);
 317         spin_unlock_irqrestore(&dws->lock, flags);
 318
 319         last_transfer = list_entry(msg->transfers.prev,
 320                                         struct spi_transfer,
 321                                         transfer_list);
 322
 323         if (!last_transfer->cs_change)
 324                 dws->cs_control(MRST_SPI_DEASSERT);
 325
 326         msg->state = NULL;
 327         if (msg->complete)
 328                 msg->complete(msg->context);
 329 }
 330
 331 static void int_error_stop(struct dw_spi *dws, const char *msg)
 332 {
 333         /* Stop and reset hw */
 334         flush(dws);
 335         spi_enable_chip(dws, 0);
 336
 337         dev_err(&dws->master->dev, "%s\n", msg);
 338         dws->cur_msg->state = ERROR_STATE;
 339         tasklet_schedule(&dws->pump_transfers);
 340 }
 341
 342 static void transfer_complete(struct dw_spi *dws)
 343 {
 344         /* Update total byte transfered return count actual bytes read */
 345         dws->cur_msg->actual_length += dws->len;
 346
 347         /* Move to next transfer */
 348         dws->cur_msg->state = next_transfer(dws);
 349
 350         /* Handle end of message */
 351         if (dws->cur_msg->state == DONE_STATE) {
 352                 dws->cur_msg->status = 0;
 353                 giveback(dws);
 354         } else
 355                 tasklet_schedule(&dws->pump_transfers);
 356 }
 357
 358 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
 359 {
 360         u16 irq_status, irq_mask = 0x3f;
 361         u32 int_level = dws->fifo_len / 2;
 362         u32 left;
 363
 364         irq_status = dw_readw(dws, isr) & irq_mask;
 365         /* Error handling */
 366         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
 367                 dw_readw(dws, txoicr);
 368                 dw_readw(dws, rxoicr);
 369                 dw_readw(dws, rxuicr);
 370                 int_error_stop(dws, "interrupt_transfer: fifo overrun");
 371                 return IRQ_HANDLED;
 372         }
 373
 374         if (irq_status & SPI_INT_TXEI) {
 375                 spi_mask_intr(dws, SPI_INT_TXEI);
 376
 377                 left = (dws->tx_end - dws->tx) / dws->n_bytes;
 378                 left = (left > int_level) ? int_level : left;
 379
 380                 while (left--)
 381                         dws->write(dws);
 382                 dws->read(dws);
 383
 384                 /* Re-enable the IRQ if there is still data left to tx */
 385                 if (dws->tx_end > dws->tx)
 386                         spi_umask_intr(dws, SPI_INT_TXEI);
 387                 else
 388                         transfer_complete(dws);
 389         }
 390
 391         return IRQ_HANDLED;
 392 }
 393
 394 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
 395 {
 396         struct dw_spi *dws = dev_id;
 397
 398         if (!dws->cur_msg) {
 399                 spi_mask_intr(dws, SPI_INT_TXEI);
 400                 /* Never fail */
 401                 return IRQ_HANDLED;
 402         }
 403
 404         return dws->transfer_handler(dws);
 405 }
 406
 407 /* Must be called inside pump_transfers() */
 408 static void poll_transfer(struct dw_spi *dws)
 409 {
 410         if (dws->tx) {
 411                 while (dws->write(dws))
 412                         dws->read(dws);
 413         }
 414
 415         dws->read(dws);
 416         transfer_complete(dws);
 417 }
 418
 419 static void dma_transfer(struct dw_spi *dws, int cs_change)
 420 {
 421 }
 422
 423 static void pump_transfers(unsigned long data)
 424 {
 425         struct dw_spi *dws = (struct dw_spi *)data;
 426         struct spi_message *message = NULL;
 427         struct spi_transfer *transfer = NULL;
 428         struct spi_transfer *previous = NULL;
 429         struct spi_device *spi = NULL;
 430         struct chip_data *chip = NULL;
 431         u8 bits = 0;
 432         u8 imask = 0;
 433         u8 cs_change = 0;
 434         u16 txint_level = 0;
 435         u16 clk_div = 0;
 436         u32 speed = 0;
 437         u32 cr0 = 0;
 438
 439         /* Get current state information */
 440         message = dws->cur_msg;
 441         transfer = dws->cur_transfer;
 442         chip = dws->cur_chip;
 443         spi = message->spi;
 444
 445         if (unlikely(!chip->clk_div))
 446                 chip->clk_div = dws->max_freq / chip->speed_hz;
 447
 448         if (message->state == ERROR_STATE) {
 449                 message->status = -EIO;
 450                 goto early_exit;
 451         }
 452
 453         /* Handle end of message */
 454         if (message->state == DONE_STATE) {
 455                 message->status = 0;
 456                 goto early_exit;
 457         }
 458
 459         /* Delay if requested at end of transfer*/
 460         if (message->state == RUNNING_STATE) {
 461                 previous = list_entry(transfer->transfer_list.prev,
 462                                         struct spi_transfer,
 463                                         transfer_list);
 464                 if (previous->delay_usecs)
 465                         udelay(previous->delay_usecs);
 466         }
 467
 468         dws->n_bytes = chip->n_bytes;
 469         dws->dma_width = chip->dma_width;
 470         dws->cs_control = chip->cs_control;
 471
 472         dws->rx_dma = transfer->rx_dma;
 473         dws->tx_dma = transfer->tx_dma;
 474         dws->tx = (void *)transfer->tx_buf;
 475         dws->tx_end = dws->tx + transfer->len;
 476         dws->rx = transfer->rx_buf;
 477         dws->rx_end = dws->rx + transfer->len;
 478         dws->write = dws->tx ? chip->write : null_writer;
 479         dws->read = dws->rx ? chip->read : null_reader;
 480         dws->cs_change = transfer->cs_change;
 481         dws->len = dws->cur_transfer->len;
 482         if (chip != dws->prev_chip)
 483                 cs_change = 1;
 484
 485         cr0 = chip->cr0;
 486
 487         /* Handle per transfer options for bpw and speed */
 488         if (transfer->speed_hz) {
 489                 speed = chip->speed_hz;
 490
 491                 if (transfer->speed_hz != speed) {
 492                         speed = transfer->speed_hz;
 493                         if (speed > dws->max_freq) {
 494                                 printk(KERN_ERR "MRST SPI0: unsupported"
 495                                         "freq: %dHz\n", speed);
 496                                 message->status = -EIO;
 497                                 goto early_exit;
 498                         }
 499
 500                         /* clk_div doesn't support odd number */
 501                         clk_div = dws->max_freq / speed;
 502                         clk_div = (clk_div + 1) & 0xfffe;
 503
 504                         chip->speed_hz = speed;
 505                         chip->clk_div = clk_div;
 506                 }
 507         }
 508         if (transfer->bits_per_word) {
 509                 bits = transfer->bits_per_word;
 510
 511                 switch (bits) {
 512                 case 8:
 513                         dws->n_bytes = 1;
 514                         dws->dma_width = 1;
 515                         dws->read = (dws->read != null_reader) ?
 516                                         u8_reader : null_reader;
 517                         dws->write = (dws->write != null_writer) ?
 518                                         u8_writer : null_writer;
 519                         break;
 520                 case 16:
 521                         dws->n_bytes = 2;
 522                         dws->dma_width = 2;
 523                         dws->read = (dws->read != null_reader) ?
 524                                         u16_reader : null_reader;
 525                         dws->write = (dws->write != null_writer) ?
 526                                         u16_writer : null_writer;
 527                         break;
 528                 default:
 529                         printk(KERN_ERR "MRST SPI0: unsupported bits:"
 530                                 "%db\n", bits);
 531                         message->status = -EIO;
 532                         goto early_exit;
 533                 }
 534
 535                 cr0 = (bits - 1)
 536                         | (chip->type << SPI_FRF_OFFSET)
 537                         | (spi->mode << SPI_MODE_OFFSET)
 538                         | (chip->tmode << SPI_TMOD_OFFSET);
 539         }
 540         message->state = RUNNING_STATE;
 541
 542         /* Check if current transfer is a DMA transaction */
 543         dws->dma_mapped = map_dma_buffers(dws);
 544
 545         /*
 546          * Interrupt mode
 547          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
 548          */
 549         if (!dws->dma_mapped && !chip->poll_mode) {
 550                 int templen = dws->len / dws->n_bytes;
 551                 txint_level = dws->fifo_len / 2;
 552                 txint_level = (templen > txint_level) ? txint_level : templen;
 553
 554                 imask |= SPI_INT_TXEI;
 555                 dws->transfer_handler = interrupt_transfer;
 556         }
 557
 558         /*
 559          * Reprogram registers only if
 560          *      1. chip select changes
 561          *      2. clk_div is changed
 562          *      3. control value changes
 563          */
 564         if (dw_readw(dws, ctrl0) != cr0 || cs_change || clk_div || imask) {
 565                 spi_enable_chip(dws, 0);
 566
 567                 if (dw_readw(dws, ctrl0) != cr0)
 568                         dw_writew(dws, ctrl0, cr0);
 569
 570                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
 571                 spi_chip_sel(dws, spi->chip_select);
 572
 573                 /* Set the interrupt mask, for poll mode just diable all int */
 574                 spi_mask_intr(dws, 0xff);
 575                 if (imask)
 576                         spi_umask_intr(dws, imask);
 577                 if (txint_level)
 578                         dw_writew(dws, txfltr, txint_level);
 579
 580                 spi_enable_chip(dws, 1);
 581                 if (cs_change)
 582                         dws->prev_chip = chip;
 583         }
 584
 585         if (dws->dma_mapped)
 586                 dma_transfer(dws, cs_change);
 587
 588         if (chip->poll_mode)
 589                 poll_transfer(dws);
 590
 591         return;
 592
 593 early_exit:
 594         giveback(dws);
 595         return;
 596 }
 597
 598 static void pump_messages(struct work_struct *work)
 599 {
 600         struct dw_spi *dws =
 601                 container_of(work, struct dw_spi, pump_messages);
 602         unsigned long flags;
 603
 604         /* Lock queue and check for queue work */
 605         spin_lock_irqsave(&dws->lock, flags);
 606         if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
 607                 dws->busy = 0;
 608                 spin_unlock_irqrestore(&dws->lock, flags);
 609                 return;
 610         }
 611
 612         /* Make sure we are not already running a message */
 613         if (dws->cur_msg) {
 614                 spin_unlock_irqrestore(&dws->lock, flags);
 615                 return;
 616         }
 617
 618         /* Extract head of queue */
 619         dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
 620         list_del_init(&dws->cur_msg->queue);
 621
 622         /* Initial message state*/
 623         dws->cur_msg->state = START_STATE;
 624         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
 625                                                 struct spi_transfer,
 626                                                 transfer_list);
 627         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
 628
 629         /* Mark as busy and launch transfers */
 630         tasklet_schedule(&dws->pump_transfers);
 631
 632         dws->busy = 1;
 633         spin_unlock_irqrestore(&dws->lock, flags);
 634 }
 635
 636 /* spi_device use this to queue in their spi_msg */
 637 static int dw_spi_transfer(struct spi_device *spi, struct spi_message *msg)
 638 {
 639         struct dw_spi *dws = spi_master_get_devdata(spi->master);
 640         unsigned long flags;
 641
 642         spin_lock_irqsave(&dws->lock, flags);
 643
 644         if (dws->run == QUEUE_STOPPED) {
 645                 spin_unlock_irqrestore(&dws->lock, flags);
 646                 return -ESHUTDOWN;
 647         }
 648
 649         msg->actual_length = 0;
 650         msg->status = -EINPROGRESS;
 651         msg->state = START_STATE;
 652
 653         list_add_tail(&msg->queue, &dws->queue);
 654
 655         if (dws->run == QUEUE_RUNNING && !dws->busy) {
 656
 657                 if (dws->cur_transfer || dws->cur_msg)
 658                         queue_work(dws->workqueue,
 659                                         &dws->pump_messages);
 660                 else {
 661                         /* If no other data transaction in air, just go */
 662                         spin_unlock_irqrestore(&dws->lock, flags);
 663                         pump_messages(&dws->pump_messages);
 664                         return 0;
 665                 }
 666         }
 667
 668         spin_unlock_irqrestore(&dws->lock, flags);
 669         return 0;
 670 }
 671
 672 /* This may be called twice for each spi dev */
 673 static int dw_spi_setup(struct spi_device *spi)
 674 {
 675         struct dw_spi_chip *chip_info = NULL;
 676         struct chip_data *chip;
 677
 678         if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
 679                 return -EINVAL;
 680
 681         /* Only alloc on first setup */
 682         chip = spi_get_ctldata(spi);
 683         if (!chip) {
 684                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 685                 if (!chip)
 686                         return -ENOMEM;
 687
 688                 chip->cs_control = null_cs_control;
 689                 chip->enable_dma = 0;
 690         }
 691
 692         /*
 693          * Protocol drivers may change the chip settings, so...
 694          * if chip_info exists, use it
 695          */
 696         chip_info = spi->controller_data;
 697
 698         /* chip_info doesn't always exist */
 699         if (chip_info) {
 700                 if (chip_info->cs_control)
 701                         chip->cs_control = chip_info->cs_control;
 702
 703                 chip->poll_mode = chip_info->poll_mode;
 704                 chip->type = chip_info->type;
 705
 706                 chip->rx_threshold = 0;
 707                 chip->tx_threshold = 0;
 708
 709                 chip->enable_dma = chip_info->enable_dma;
 710         }
 711
 712         if (spi->bits_per_word <= 8) {
 713                 chip->n_bytes = 1;
 714                 chip->dma_width = 1;
 715                 chip->read = u8_reader;
 716                 chip->write = u8_writer;
 717         } else if (spi->bits_per_word <= 16) {
 718                 chip->n_bytes = 2;
 719                 chip->dma_width = 2;
 720                 chip->read = u16_reader;
 721                 chip->write = u16_writer;
 722         } else {
 723                 /* Never take >16b case for MRST SPIC */
 724                 dev_err(&spi->dev, "invalid wordsize\n");
 725                 return -EINVAL;
 726         }
 727         chip->bits_per_word = spi->bits_per_word;
 728
 729         if (!spi->max_speed_hz) {
 730                 dev_err(&spi->dev, "No max speed HZ parameter\n");
 731                 return -EINVAL;
 732         }
 733         chip->speed_hz = spi->max_speed_hz;
 734
 735         chip->tmode = 0; /* Tx & Rx */
 736         /* Default SPI mode is SCPOL = 0, SCPH = 0 */
 737         chip->cr0 = (chip->bits_per_word - 1)
 738                         | (chip->type << SPI_FRF_OFFSET)
 739                         | (spi->mode  << SPI_MODE_OFFSET)
 740                         | (chip->tmode << SPI_TMOD_OFFSET);
 741
 742         spi_set_ctldata(spi, chip);
 743         return 0;
 744 }
 745
 746 static void dw_spi_cleanup(struct spi_device *spi)
 747 {
 748         struct chip_data *chip = spi_get_ctldata(spi);
 749         kfree(chip);
 750 }
 751
 752 static int __init init_queue(struct dw_spi *dws)
 753 {
 754         INIT_LIST_HEAD(&dws->queue);
 755         spin_lock_init(&dws->lock);
 756
 757         dws->run = QUEUE_STOPPED;
 758         dws->busy = 0;
 759
 760         tasklet_init(&dws->pump_transfers,
 761                         pump_transfers, (unsigned long)dws);
 762
 763         INIT_WORK(&dws->pump_messages, pump_messages);
 764         dws->workqueue = create_singlethread_workqueue(
 765                                         dev_name(dws->master->dev.parent));
 766         if (dws->workqueue == NULL)
 767                 return -EBUSY;
 768
 769         return 0;
 770 }
 771
 772 static int start_queue(struct dw_spi *dws)
 773 {
 774         unsigned long flags;
 775
 776         spin_lock_irqsave(&dws->lock, flags);
 777
 778         if (dws->run == QUEUE_RUNNING || dws->busy) {
 779                 spin_unlock_irqrestore(&dws->lock, flags);
 780                 return -EBUSY;
 781         }
 782
 783         dws->run = QUEUE_RUNNING;
 784         dws->cur_msg = NULL;
 785         dws->cur_transfer = NULL;
 786         dws->cur_chip = NULL;
 787         dws->prev_chip = NULL;
 788         spin_unlock_irqrestore(&dws->lock, flags);
 789
 790         queue_work(dws->workqueue, &dws->pump_messages);
 791
 792         return 0;
 793 }
 794
 795 static int stop_queue(struct dw_spi *dws)
 796 {
 797         unsigned long flags;
 798         unsigned limit = 50;
 799         int status = 0;
 800
 801         spin_lock_irqsave(&dws->lock, flags);
 802         dws->run = QUEUE_STOPPED;
 803         while (!list_empty(&dws->queue) && dws->busy && limit--) {
 804                 spin_unlock_irqrestore(&dws->lock, flags);
 805                 msleep(10);
 806                 spin_lock_irqsave(&dws->lock, flags);
 807         }
 808
 809         if (!list_empty(&dws->queue) || dws->busy)
 810                 status = -EBUSY;
 811         spin_unlock_irqrestore(&dws->lock, flags);
 812
 813         return status;
 814 }
 815
 816 static int destroy_queue(struct dw_spi *dws)
 817 {
 818         int status;
 819
 820         status = stop_queue(dws);
 821         if (status != 0)
 822                 return status;
 823         destroy_workqueue(dws->workqueue);
 824         return 0;
 825 }
 826
 827 /* Restart the controller, disable all interrupts, clean rx fifo */
 828 static void spi_hw_init(struct dw_spi *dws)
 829 {
 830         spi_enable_chip(dws, 0);
 831         spi_mask_intr(dws, 0xff);
 832         spi_enable_chip(dws, 1);
 833         flush(dws);
 834 }
 835
 836 int __devinit dw_spi_add_host(struct dw_spi *dws)
 837 {
 838         struct spi_master *master;
 839         int ret;
 840
 841         BUG_ON(dws == NULL);
 842
 843         master = spi_alloc_master(dws->parent_dev, 0);
 844         if (!master) {
 845                 ret = -ENOMEM;
 846                 goto exit;
 847         }
 848
 849         dws->master = master;
 850         dws->type = SSI_MOTO_SPI;
 851         dws->prev_chip = NULL;
 852         dws->dma_inited = 0;
 853         dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
 854
 855         ret = request_irq(dws->irq, dw_spi_irq, 0,
 856                         "dw_spi", dws);
 857         if (ret < 0) {
 858                 dev_err(&master->dev, "can not get IRQ\n");
 859                 goto err_free_master;
 860         }
 861
 862         master->mode_bits = SPI_CPOL | SPI_CPHA;
 863         master->bus_num = dws->bus_num;
 864         master->num_chipselect = dws->num_cs;
 865         master->cleanup = dw_spi_cleanup;
 866         master->setup = dw_spi_setup;
 867         master->transfer = dw_spi_transfer;
 868
 869         dws->dma_inited = 0;
 870
 871         /* Basic HW init */
 872         spi_hw_init(dws);
 873
 874         /* Initial and start queue */
 875         ret = init_queue(dws);
 876         if (ret) {
 877                 dev_err(&master->dev, "problem initializing queue\n");
 878                 goto err_diable_hw;
 879         }
 880         ret = start_queue(dws);
 881         if (ret) {
 882                 dev_err(&master->dev, "problem starting queue\n");
 883                 goto err_diable_hw;
 884         }
 885
 886         spi_master_set_devdata(master, dws);
 887         ret = spi_register_master(master);
 888         if (ret) {
 889                 dev_err(&master->dev, "problem registering spi master\n");
 890                 goto err_queue_alloc;
 891         }
 892
 893         mrst_spi_debugfs_init(dws);
 894         return 0;
 895
 896 err_queue_alloc:
 897         destroy_queue(dws);
 898 err_diable_hw:
 899         spi_enable_chip(dws, 0);
 900         free_irq(dws->irq, dws);
 901 err_free_master:
 902         spi_master_put(master);
 903 exit:
 904         return ret;
 905 }
 906 EXPORT_SYMBOL(dw_spi_add_host);
 907
 908 void __devexit dw_spi_remove_host(struct dw_spi *dws)
 909 {
 910         int status = 0;
 911
 912         if (!dws)
 913                 return;
 914         mrst_spi_debugfs_remove(dws);
 915
 916         /* Remove the queue */
 917         status = destroy_queue(dws);
 918         if (status != 0)
 919                 dev_err(&dws->master->dev, "dw_spi_remove: workqueue will not "
 920                         "complete, message memory not freed\n");
 921
 922         spi_enable_chip(dws, 0);
 923         /* Disable clk */
 924         spi_set_clk(dws, 0);
 925         free_irq(dws->irq, dws);
 926
 927         /* Disconnect from the SPI framework */
 928         spi_unregister_master(dws->master);
 929 }
 930
 931 int dw_spi_suspend_host(struct dw_spi *dws)
 932 {
 933         int ret = 0;
 934
 935         ret = stop_queue(dws);
 936         if (ret)
 937                 return ret;
 938         spi_enable_chip(dws, 0);
 939         spi_set_clk(dws, 0);
 940         return ret;
 941 }
 942 EXPORT_SYMBOL(dw_spi_suspend_host);
 943
 944 int dw_spi_resume_host(struct dw_spi *dws)
 945 {
 946         int ret;
 947
 948         spi_hw_init(dws);
 949         ret = start_queue(dws);
 950         if (ret)
 951                 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
 952         return ret;
 953 }
 954 EXPORT_SYMBOL(dw_spi_resume_host);
 955
 956 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
 957 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
 958 MODULE_LICENSE("GPL v2");