SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/spi/dw_spi.c

   1 /*
   2  * dw_spi.c - Designware SPI core controller driver (refer pxa2xx_spi.c)
   3  *
   4  * Copyright (c) 2009, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  */
  19
  20 #include <linux/dma-mapping.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/highmem.h>
  23 #include <linux/delay.h>
  24
  25 #include <linux/spi/dw_spi.h>
  26 #include <linux/spi/spi.h>
  27
  28 #ifdef CONFIG_DEBUG_FS
  29 #include <linux/debugfs.h>
  30 #endif
  31
  32 #define START_STATE     ((void *)0)
  33 #define RUNNING_STATE   ((void *)1)
  34 #define DONE_STATE      ((void *)2)
  35 #define ERROR_STATE     ((void *)-1)
  36
  37 #define QUEUE_RUNNING   0
  38 #define QUEUE_STOPPED   1
  39
  40 #define MRST_SPI_DEASSERT       0
  41 #define MRST_SPI_ASSERT         1
  42
  43 /* Slave spi_dev related */
  44 struct chip_data {
  45         u16 cr0;
  46         u8 cs;                  /* chip select pin */
  47         u8 n_bytes;             /* current is a 1/2/4 byte op */
  48         u8 tmode;               /* TR/TO/RO/EEPROM */
  49         u8 type;                /* SPI/SSP/MicroWire */
  50
  51         u8 poll_mode;           /* 1 means use poll mode */
  52
  53         u32 dma_width;
  54         u32 rx_threshold;
  55         u32 tx_threshold;
  56         u8 enable_dma;
  57         u8 bits_per_word;
  58         u16 clk_div;            /* baud rate divider */
  59         u32 speed_hz;           /* baud rate */
  60         int (*write)(struct dw_spi *dws);
  61         int (*read)(struct dw_spi *dws);
  62         void (*cs_control)(u32 command);
  63 };
  64
  65 #ifdef CONFIG_DEBUG_FS
  66 static int spi_show_regs_open(struct inode *inode, struct file *file)
  67 {
  68         file->private_data = inode->i_private;
  69         return 0;
  70 }
  71
  72 #define SPI_REGS_BUFSIZE        1024
  73 static ssize_t  spi_show_regs(struct file *file, char __user *user_buf,
  74                                 size_t count, loff_t *ppos)
  75 {
  76         struct dw_spi *dws;
  77         char *buf;
  78         u32 len = 0;
  79         ssize_t ret;
  80
  81         dws = file->private_data;
  82
  83         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
  84         if (!buf)
  85                 return 0;
  86
  87         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  88                         "MRST SPI0 registers:\n");
  89         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  90                         "=================================\n");
  91         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  92                         "CTRL0: \t\t0x%08x\n", dw_readl(dws, ctrl0));
  93         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  94                         "CTRL1: \t\t0x%08x\n", dw_readl(dws, ctrl1));
  95         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  96                         "SSIENR: \t0x%08x\n", dw_readl(dws, ssienr));
  97         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  98                         "SER: \t\t0x%08x\n", dw_readl(dws, ser));
  99         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 100                         "BAUDR: \t\t0x%08x\n", dw_readl(dws, baudr));
 101         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 102                         "TXFTLR: \t0x%08x\n", dw_readl(dws, txfltr));
 103         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 104                         "RXFTLR: \t0x%08x\n", dw_readl(dws, rxfltr));
 105         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 106                         "TXFLR: \t\t0x%08x\n", dw_readl(dws, txflr));
 107         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 108                         "RXFLR: \t\t0x%08x\n", dw_readl(dws, rxflr));
 109         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 110                         "SR: \t\t0x%08x\n", dw_readl(dws, sr));
 111         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 112                         "IMR: \t\t0x%08x\n", dw_readl(dws, imr));
 113         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 114                         "ISR: \t\t0x%08x\n", dw_readl(dws, isr));
 115         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 116                         "DMACR: \t\t0x%08x\n", dw_readl(dws, dmacr));
 117         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 118                         "DMATDLR: \t0x%08x\n", dw_readl(dws, dmatdlr));
 119         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 120                         "DMARDLR: \t0x%08x\n", dw_readl(dws, dmardlr));
 121         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 122                         "=================================\n");
 123
 124         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 125         kfree(buf);
 126         return ret;
 127 }
 128
 129 static const struct file_operations mrst_spi_regs_ops = {
 130         .owner          = THIS_MODULE,
 131         .open           = spi_show_regs_open,
 132         .read           = spi_show_regs,
 133 };
 134
 135 static int mrst_spi_debugfs_init(struct dw_spi *dws)
 136 {
 137         dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
 138         if (!dws->debugfs)
 139                 return -ENOMEM;
 140
 141         debugfs_create_file("registers", S_IFREG | S_IRUGO,
 142                 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
 143         return 0;
 144 }
 145
 146 static void mrst_spi_debugfs_remove(struct dw_spi *dws)
 147 {
 148         if (dws->debugfs)
 149                 debugfs_remove_recursive(dws->debugfs);
 150 }
 151
 152 #else
 153 static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
 154 {
 155         return 0;
 156 }
 157
 158 static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
 159 {
 160 }
 161 #endif /* CONFIG_DEBUG_FS */
 162
 163 static void wait_till_not_busy(struct dw_spi *dws)
 164 {
 165         unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);
 166
 167         while (time_before(jiffies, end)) {
 168                 if (!(dw_readw(dws, sr) & SR_BUSY))
 169                         return;
 170         }
 171         dev_err(&dws->master->dev,
 172                 "DW SPI: Status keeps busy for 1000us after a read/write!\n");
 173 }
 174
 175 static void flush(struct dw_spi *dws)
 176 {
 177         while (dw_readw(dws, sr) & SR_RF_NOT_EMPT)
 178                 dw_readw(dws, dr);
 179
 180         wait_till_not_busy(dws);
 181 }
 182
 183 static void null_cs_control(u32 command)
 184 {
 185 }
 186
 187 static int null_writer(struct dw_spi *dws)
 188 {
 189         u8 n_bytes = dws->n_bytes;
 190
 191         if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
 192                 || (dws->tx == dws->tx_end))
 193                 return 0;
 194         dw_writew(dws, dr, 0);
 195         dws->tx += n_bytes;
 196
 197         wait_till_not_busy(dws);
 198         return 1;
 199 }
 200
 201 static int null_reader(struct dw_spi *dws)
 202 {
 203         u8 n_bytes = dws->n_bytes;
 204
 205         while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
 206                 && (dws->rx < dws->rx_end)) {
 207                 dw_readw(dws, dr);
 208                 dws->rx += n_bytes;
 209         }
 210         wait_till_not_busy(dws);
 211         return dws->rx == dws->rx_end;
 212 }
 213
 214 static int u8_writer(struct dw_spi *dws)
 215 {
 216         if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
 217                 || (dws->tx == dws->tx_end))
 218                 return 0;
 219
 220         dw_writew(dws, dr, *(u8 *)(dws->tx));
 221         ++dws->tx;
 222
 223         wait_till_not_busy(dws);
 224         return 1;
 225 }
 226
 227 static int u8_reader(struct dw_spi *dws)
 228 {
 229         while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
 230                 && (dws->rx < dws->rx_end)) {
 231                 *(u8 *)(dws->rx) = dw_readw(dws, dr);
 232                 ++dws->rx;
 233         }
 234
 235         wait_till_not_busy(dws);
 236         return dws->rx == dws->rx_end;
 237 }
 238
 239 static int u16_writer(struct dw_spi *dws)
 240 {
 241         if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
 242                 || (dws->tx == dws->tx_end))
 243                 return 0;
 244
 245         dw_writew(dws, dr, *(u16 *)(dws->tx));
 246         dws->tx += 2;
 247
 248         wait_till_not_busy(dws);
 249         return 1;
 250 }
 251
 252 static int u16_reader(struct dw_spi *dws)
 253 {
 254         u16 temp;
 255
 256         while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
 257                 && (dws->rx < dws->rx_end)) {
 258                 temp = dw_readw(dws, dr);
 259                 *(u16 *)(dws->rx) = temp;
 260                 dws->rx += 2;
 261         }
 262
 263         wait_till_not_busy(dws);
 264         return dws->rx == dws->rx_end;
 265 }
 266
 267 static void *next_transfer(struct dw_spi *dws)
 268 {
 269         struct spi_message *msg = dws->cur_msg;
 270         struct spi_transfer *trans = dws->cur_transfer;
 271
 272         /* Move to next transfer */
 273         if (trans->transfer_list.next != &msg->transfers) {
 274                 dws->cur_transfer =
 275                         list_entry(trans->transfer_list.next,
 276                                         struct spi_transfer,
 277                                         transfer_list);
 278                 return RUNNING_STATE;
 279         } else
 280                 return DONE_STATE;
 281 }
 282
 283 /*
 284  * Note: first step is the protocol driver prepares
 285  * a dma-capable memory, and this func just need translate
 286  * the virt addr to physical
 287  */
 288 static int map_dma_buffers(struct dw_spi *dws)
 289 {
 290         if (!dws->cur_msg->is_dma_mapped || !dws->dma_inited
 291                 || !dws->cur_chip->enable_dma)
 292                 return 0;
 293
 294         if (dws->cur_transfer->tx_dma)
 295                 dws->tx_dma = dws->cur_transfer->tx_dma;
 296
 297         if (dws->cur_transfer->rx_dma)
 298                 dws->rx_dma = dws->cur_transfer->rx_dma;
 299
 300         return 1;
 301 }
 302
 303 /* Caller already set message->status; dma and pio irqs are blocked */
 304 static void giveback(struct dw_spi *dws)
 305 {
 306         struct spi_transfer *last_transfer;
 307         unsigned long flags;
 308         struct spi_message *msg;
 309
 310         spin_lock_irqsave(&dws->lock, flags);
 311         msg = dws->cur_msg;
 312         dws->cur_msg = NULL;
 313         dws->cur_transfer = NULL;
 314         dws->prev_chip = dws->cur_chip;
 315         dws->cur_chip = NULL;
 316         dws->dma_mapped = 0;
 317         queue_work(dws->workqueue, &dws->pump_messages);
 318         spin_unlock_irqrestore(&dws->lock, flags);
 319
 320         last_transfer = list_entry(msg->transfers.prev,
 321                                         struct spi_transfer,
 322                                         transfer_list);
 323
 324         if (!last_transfer->cs_change)
 325                 dws->cs_control(MRST_SPI_DEASSERT);
 326
 327         msg->state = NULL;
 328         if (msg->complete)
 329                 msg->complete(msg->context);
 330 }
 331
 332 static void int_error_stop(struct dw_spi *dws, const char *msg)
 333 {
 334         /* Stop and reset hw */
 335         flush(dws);
 336         spi_enable_chip(dws, 0);
 337
 338         dev_err(&dws->master->dev, "%s\n", msg);
 339         dws->cur_msg->state = ERROR_STATE;
 340         tasklet_schedule(&dws->pump_transfers);
 341 }
 342
 343 static void transfer_complete(struct dw_spi *dws)
 344 {
 345         /* Update total byte transfered return count actual bytes read */
 346         dws->cur_msg->actual_length += dws->len;
 347
 348         /* Move to next transfer */
 349         dws->cur_msg->state = next_transfer(dws);
 350
 351         /* Handle end of message */
 352         if (dws->cur_msg->state == DONE_STATE) {
 353                 dws->cur_msg->status = 0;
 354                 giveback(dws);
 355         } else
 356                 tasklet_schedule(&dws->pump_transfers);
 357 }
 358
 359 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
 360 {
 361         u16 irq_status, irq_mask = 0x3f;
 362         u32 int_level = dws->fifo_len / 2;
 363         u32 left;
 364
 365         irq_status = dw_readw(dws, isr) & irq_mask;
 366         /* Error handling */
 367         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
 368                 dw_readw(dws, txoicr);
 369                 dw_readw(dws, rxoicr);
 370                 dw_readw(dws, rxuicr);
 371                 int_error_stop(dws, "interrupt_transfer: fifo overrun");
 372                 return IRQ_HANDLED;
 373         }
 374
 375         if (irq_status & SPI_INT_TXEI) {
 376                 spi_mask_intr(dws, SPI_INT_TXEI);
 377
 378                 left = (dws->tx_end - dws->tx) / dws->n_bytes;
 379                 left = (left > int_level) ? int_level : left;
 380
 381                 while (left--)
 382                         dws->write(dws);
 383                 dws->read(dws);
 384
 385                 /* Re-enable the IRQ if there is still data left to tx */
 386                 if (dws->tx_end > dws->tx)
 387                         spi_umask_intr(dws, SPI_INT_TXEI);
 388                 else
 389                         transfer_complete(dws);
 390         }
 391
 392         return IRQ_HANDLED;
 393 }
 394
 395 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
 396 {
 397         struct dw_spi *dws = dev_id;
 398
 399         if (!dws->cur_msg) {
 400                 spi_mask_intr(dws, SPI_INT_TXEI);
 401                 /* Never fail */
 402                 return IRQ_HANDLED;
 403         }
 404
 405         return dws->transfer_handler(dws);
 406 }
 407
 408 /* Must be called inside pump_transfers() */
 409 static void poll_transfer(struct dw_spi *dws)
 410 {
 411         if (dws->tx) {
 412                 while (dws->write(dws))
 413                         dws->read(dws);
 414         }
 415
 416         dws->read(dws);
 417         transfer_complete(dws);
 418 }
 419
 420 static void dma_transfer(struct dw_spi *dws, int cs_change)
 421 {
 422 }
 423
 424 static void pump_transfers(unsigned long data)
 425 {
 426         struct dw_spi *dws = (struct dw_spi *)data;
 427         struct spi_message *message = NULL;
 428         struct spi_transfer *transfer = NULL;
 429         struct spi_transfer *previous = NULL;
 430         struct spi_device *spi = NULL;
 431         struct chip_data *chip = NULL;
 432         u8 bits = 0;
 433         u8 imask = 0;
 434         u8 cs_change = 0;
 435         u16 txint_level = 0;
 436         u16 clk_div = 0;
 437         u32 speed = 0;
 438         u32 cr0 = 0;
 439
 440         /* Get current state information */
 441         message = dws->cur_msg;
 442         transfer = dws->cur_transfer;
 443         chip = dws->cur_chip;
 444         spi = message->spi;
 445
 446         if (unlikely(!chip->clk_div))
 447                 chip->clk_div = dws->max_freq / chip->speed_hz;
 448
 449         if (message->state == ERROR_STATE) {
 450                 message->status = -EIO;
 451                 goto early_exit;
 452         }
 453
 454         /* Handle end of message */
 455         if (message->state == DONE_STATE) {
 456                 message->status = 0;
 457                 goto early_exit;
 458         }
 459
 460         /* Delay if requested at end of transfer*/
 461         if (message->state == RUNNING_STATE) {
 462                 previous = list_entry(transfer->transfer_list.prev,
 463                                         struct spi_transfer,
 464                                         transfer_list);
 465                 if (previous->delay_usecs)
 466                         udelay(previous->delay_usecs);
 467         }
 468
 469         dws->n_bytes = chip->n_bytes;
 470         dws->dma_width = chip->dma_width;
 471         dws->cs_control = chip->cs_control;
 472
 473         dws->rx_dma = transfer->rx_dma;
 474         dws->tx_dma = transfer->tx_dma;
 475         dws->tx = (void *)transfer->tx_buf;
 476         dws->tx_end = dws->tx + transfer->len;
 477         dws->rx = transfer->rx_buf;
 478         dws->rx_end = dws->rx + transfer->len;
 479         dws->write = dws->tx ? chip->write : null_writer;
 480         dws->read = dws->rx ? chip->read : null_reader;
 481         dws->cs_change = transfer->cs_change;
 482         dws->len = dws->cur_transfer->len;
 483         if (chip != dws->prev_chip)
 484                 cs_change = 1;
 485
 486         cr0 = chip->cr0;
 487
 488         /* Handle per transfer options for bpw and speed */
 489         if (transfer->speed_hz) {
 490                 speed = chip->speed_hz;
 491
 492                 if (transfer->speed_hz != speed) {
 493                         speed = transfer->speed_hz;
 494                         if (speed > dws->max_freq) {
 495                                 printk(KERN_ERR "MRST SPI0: unsupported"
 496                                         "freq: %dHz\n", speed);
 497                                 message->status = -EIO;
 498                                 goto early_exit;
 499                         }
 500
 501                         /* clk_div doesn't support odd number */
 502                         clk_div = dws->max_freq / speed;
 503                         clk_div = (clk_div + 1) & 0xfffe;
 504
 505                         chip->speed_hz = speed;
 506                         chip->clk_div = clk_div;
 507                 }
 508         }
 509         if (transfer->bits_per_word) {
 510                 bits = transfer->bits_per_word;
 511
 512                 switch (bits) {
 513                 case 8:
 514                         dws->n_bytes = 1;
 515                         dws->dma_width = 1;
 516                         dws->read = (dws->read != null_reader) ?
 517                                         u8_reader : null_reader;
 518                         dws->write = (dws->write != null_writer) ?
 519                                         u8_writer : null_writer;
 520                         break;
 521                 case 16:
 522                         dws->n_bytes = 2;
 523                         dws->dma_width = 2;
 524                         dws->read = (dws->read != null_reader) ?
 525                                         u16_reader : null_reader;
 526                         dws->write = (dws->write != null_writer) ?
 527                                         u16_writer : null_writer;
 528                         break;
 529                 default:
 530                         printk(KERN_ERR "MRST SPI0: unsupported bits:"
 531                                 "%db\n", bits);
 532                         message->status = -EIO;
 533                         goto early_exit;
 534                 }
 535
 536                 cr0 = (bits - 1)
 537                         | (chip->type << SPI_FRF_OFFSET)
 538                         | (spi->mode << SPI_MODE_OFFSET)
 539                         | (chip->tmode << SPI_TMOD_OFFSET);
 540         }
 541         message->state = RUNNING_STATE;
 542
 543         /* Check if current transfer is a DMA transaction */
 544         dws->dma_mapped = map_dma_buffers(dws);
 545
 546         /*
 547          * Interrupt mode
 548          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
 549          */
 550         if (!dws->dma_mapped && !chip->poll_mode) {
 551                 int templen = dws->len / dws->n_bytes;
 552                 txint_level = dws->fifo_len / 2;
 553                 txint_level = (templen > txint_level) ? txint_level : templen;
 554
 555                 imask |= SPI_INT_TXEI;
 556                 dws->transfer_handler = interrupt_transfer;
 557         }
 558
 559         /*
 560          * Reprogram registers only if
 561          *      1. chip select changes
 562          *      2. clk_div is changed
 563          *      3. control value changes
 564          */
 565         if (dw_readw(dws, ctrl0) != cr0 || cs_change || clk_div || imask) {
 566                 spi_enable_chip(dws, 0);
 567
 568                 if (dw_readw(dws, ctrl0) != cr0)
 569                         dw_writew(dws, ctrl0, cr0);
 570
 571                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
 572                 spi_chip_sel(dws, spi->chip_select);
 573
 574                 /* Set the interrupt mask, for poll mode just diable all int */
 575                 spi_mask_intr(dws, 0xff);
 576                 if (imask)
 577                         spi_umask_intr(dws, imask);
 578                 if (txint_level)
 579                         dw_writew(dws, txfltr, txint_level);
 580
 581                 spi_enable_chip(dws, 1);
 582                 if (cs_change)
 583                         dws->prev_chip = chip;
 584         }
 585
 586         if (dws->dma_mapped)
 587                 dma_transfer(dws, cs_change);
 588
 589         if (chip->poll_mode)
 590                 poll_transfer(dws);
 591
 592         return;
 593
 594 early_exit:
 595         giveback(dws);
 596         return;
 597 }
 598
 599 static void pump_messages(struct work_struct *work)
 600 {
 601         struct dw_spi *dws =
 602                 container_of(work, struct dw_spi, pump_messages);
 603         unsigned long flags;
 604
 605         /* Lock queue and check for queue work */
 606         spin_lock_irqsave(&dws->lock, flags);
 607         if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
 608                 dws->busy = 0;
 609                 spin_unlock_irqrestore(&dws->lock, flags);
 610                 return;
 611         }
 612
 613         /* Make sure we are not already running a message */
 614         if (dws->cur_msg) {
 615                 spin_unlock_irqrestore(&dws->lock, flags);
 616                 return;
 617         }
 618
 619         /* Extract head of queue */
 620         dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
 621         list_del_init(&dws->cur_msg->queue);
 622
 623         /* Initial message state*/
 624         dws->cur_msg->state = START_STATE;
 625         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
 626                                                 struct spi_transfer,
 627                                                 transfer_list);
 628         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
 629
 630         /* Mark as busy and launch transfers */
 631         tasklet_schedule(&dws->pump_transfers);
 632
 633         dws->busy = 1;
 634         spin_unlock_irqrestore(&dws->lock, flags);
 635 }
 636
 637 /* spi_device use this to queue in their spi_msg */
 638 static int dw_spi_transfer(struct spi_device *spi, struct spi_message *msg)
 639 {
 640         struct dw_spi *dws = spi_master_get_devdata(spi->master);
 641         unsigned long flags;
 642
 643         spin_lock_irqsave(&dws->lock, flags);
 644
 645         if (dws->run == QUEUE_STOPPED) {
 646                 spin_unlock_irqrestore(&dws->lock, flags);
 647                 return -ESHUTDOWN;
 648         }
 649
 650         msg->actual_length = 0;
 651         msg->status = -EINPROGRESS;
 652         msg->state = START_STATE;
 653
 654         list_add_tail(&msg->queue, &dws->queue);
 655
 656         if (dws->run == QUEUE_RUNNING && !dws->busy) {
 657
 658                 if (dws->cur_transfer || dws->cur_msg)
 659                         queue_work(dws->workqueue,
 660                                         &dws->pump_messages);
 661                 else {
 662                         /* If no other data transaction in air, just go */
 663                         spin_unlock_irqrestore(&dws->lock, flags);
 664                         pump_messages(&dws->pump_messages);
 665                         return 0;
 666                 }
 667         }
 668
 669         spin_unlock_irqrestore(&dws->lock, flags);
 670         return 0;
 671 }
 672
 673 /* This may be called twice for each spi dev */
 674 static int dw_spi_setup(struct spi_device *spi)
 675 {
 676         struct dw_spi_chip *chip_info = NULL;
 677         struct chip_data *chip;
 678
 679         if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
 680                 return -EINVAL;
 681
 682         /* Only alloc on first setup */
 683         chip = spi_get_ctldata(spi);
 684         if (!chip) {
 685                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 686                 if (!chip)
 687                         return -ENOMEM;
 688
 689                 chip->cs_control = null_cs_control;
 690                 chip->enable_dma = 0;
 691         }
 692
 693         /*
 694          * Protocol drivers may change the chip settings, so...
 695          * if chip_info exists, use it
 696          */
 697         chip_info = spi->controller_data;
 698
 699         /* chip_info doesn't always exist */
 700         if (chip_info) {
 701                 if (chip_info->cs_control)
 702                         chip->cs_control = chip_info->cs_control;
 703
 704                 chip->poll_mode = chip_info->poll_mode;
 705                 chip->type = chip_info->type;
 706
 707                 chip->rx_threshold = 0;
 708                 chip->tx_threshold = 0;
 709
 710                 chip->enable_dma = chip_info->enable_dma;
 711         }
 712
 713         if (spi->bits_per_word <= 8) {
 714                 chip->n_bytes = 1;
 715                 chip->dma_width = 1;
 716                 chip->read = u8_reader;
 717                 chip->write = u8_writer;
 718         } else if (spi->bits_per_word <= 16) {
 719                 chip->n_bytes = 2;
 720                 chip->dma_width = 2;
 721                 chip->read = u16_reader;
 722                 chip->write = u16_writer;
 723         } else {
 724                 /* Never take >16b case for MRST SPIC */
 725                 dev_err(&spi->dev, "invalid wordsize\n");
 726                 return -EINVAL;
 727         }
 728         chip->bits_per_word = spi->bits_per_word;
 729
 730         if (!spi->max_speed_hz) {
 731                 dev_err(&spi->dev, "No max speed HZ parameter\n");
 732                 return -EINVAL;
 733         }
 734         chip->speed_hz = spi->max_speed_hz;
 735
 736         chip->tmode = 0; /* Tx & Rx */
 737         /* Default SPI mode is SCPOL = 0, SCPH = 0 */
 738         chip->cr0 = (chip->bits_per_word - 1)
 739                         | (chip->type << SPI_FRF_OFFSET)
 740                         | (spi->mode  << SPI_MODE_OFFSET)
 741                         | (chip->tmode << SPI_TMOD_OFFSET);
 742
 743         spi_set_ctldata(spi, chip);
 744         return 0;
 745 }
 746
 747 static void dw_spi_cleanup(struct spi_device *spi)
 748 {
 749         struct chip_data *chip = spi_get_ctldata(spi);
 750         kfree(chip);
 751 }
 752
 753 static int __devinit init_queue(struct dw_spi *dws)
 754 {
 755         INIT_LIST_HEAD(&dws->queue);
 756         spin_lock_init(&dws->lock);
 757
 758         dws->run = QUEUE_STOPPED;
 759         dws->busy = 0;
 760
 761         tasklet_init(&dws->pump_transfers,
 762                         pump_transfers, (unsigned long)dws);
 763
 764         INIT_WORK(&dws->pump_messages, pump_messages);
 765         dws->workqueue = create_singlethread_workqueue(
 766                                         dev_name(dws->master->dev.parent));
 767         if (dws->workqueue == NULL)
 768                 return -EBUSY;
 769
 770         return 0;
 771 }
 772
 773 static int start_queue(struct dw_spi *dws)
 774 {
 775         unsigned long flags;
 776
 777         spin_lock_irqsave(&dws->lock, flags);
 778
 779         if (dws->run == QUEUE_RUNNING || dws->busy) {
 780                 spin_unlock_irqrestore(&dws->lock, flags);
 781                 return -EBUSY;
 782         }
 783
 784         dws->run = QUEUE_RUNNING;
 785         dws->cur_msg = NULL;
 786         dws->cur_transfer = NULL;
 787         dws->cur_chip = NULL;
 788         dws->prev_chip = NULL;
 789         spin_unlock_irqrestore(&dws->lock, flags);
 790
 791         queue_work(dws->workqueue, &dws->pump_messages);
 792
 793         return 0;
 794 }
 795
 796 static int stop_queue(struct dw_spi *dws)
 797 {
 798         unsigned long flags;
 799         unsigned limit = 50;
 800         int status = 0;
 801
 802         spin_lock_irqsave(&dws->lock, flags);
 803         dws->run = QUEUE_STOPPED;
 804         while (!list_empty(&dws->queue) && dws->busy && limit--) {
 805                 spin_unlock_irqrestore(&dws->lock, flags);
 806                 msleep(10);
 807                 spin_lock_irqsave(&dws->lock, flags);
 808         }
 809
 810         if (!list_empty(&dws->queue) || dws->busy)
 811                 status = -EBUSY;
 812         spin_unlock_irqrestore(&dws->lock, flags);
 813
 814         return status;
 815 }
 816
 817 static int destroy_queue(struct dw_spi *dws)
 818 {
 819         int status;
 820
 821         status = stop_queue(dws);
 822         if (status != 0)
 823                 return status;
 824         destroy_workqueue(dws->workqueue);
 825         return 0;
 826 }
 827
 828 /* Restart the controller, disable all interrupts, clean rx fifo */
 829 static void spi_hw_init(struct dw_spi *dws)
 830 {
 831         spi_enable_chip(dws, 0);
 832         spi_mask_intr(dws, 0xff);
 833         spi_enable_chip(dws, 1);
 834         flush(dws);
 835
 836         /*
 837          * Try to detect the FIFO depth if not set by interface driver,
 838          * the depth could be from 2 to 256 from HW spec
 839          */
 840         if (!dws->fifo_len) {
 841                 u32 fifo;
 842                 for (fifo = 2; fifo <= 257; fifo++) {
 843                         dw_writew(dws, txfltr, fifo);
 844                         if (fifo != dw_readw(dws, txfltr))
 845                                 break;
 846                 }
 847
 848                 dws->fifo_len = (fifo == 257) ? 0 : fifo;
 849                 dw_writew(dws, txfltr, 0);
 850         }
 851 }
 852
 853 int __devinit dw_spi_add_host(struct dw_spi *dws)
 854 {
 855         struct spi_master *master;
 856         int ret;
 857
 858         BUG_ON(dws == NULL);
 859
 860         master = spi_alloc_master(dws->parent_dev, 0);
 861         if (!master) {
 862                 ret = -ENOMEM;
 863                 goto exit;
 864         }
 865
 866         dws->master = master;
 867         dws->type = SSI_MOTO_SPI;
 868         dws->prev_chip = NULL;
 869         dws->dma_inited = 0;
 870         dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
 871
 872         ret = request_irq(dws->irq, dw_spi_irq, 0,
 873                         "dw_spi", dws);
 874         if (ret < 0) {
 875                 dev_err(&master->dev, "can not get IRQ\n");
 876                 goto err_free_master;
 877         }
 878
 879         master->mode_bits = SPI_CPOL | SPI_CPHA;
 880         master->bus_num = dws->bus_num;
 881         master->num_chipselect = dws->num_cs;
 882         master->cleanup = dw_spi_cleanup;
 883         master->setup = dw_spi_setup;
 884         master->transfer = dw_spi_transfer;
 885
 886         dws->dma_inited = 0;
 887
 888         /* Basic HW init */
 889         spi_hw_init(dws);
 890
 891         /* Initial and start queue */
 892         ret = init_queue(dws);
 893         if (ret) {
 894                 dev_err(&master->dev, "problem initializing queue\n");
 895                 goto err_diable_hw;
 896         }
 897         ret = start_queue(dws);
 898         if (ret) {
 899                 dev_err(&master->dev, "problem starting queue\n");
 900                 goto err_diable_hw;
 901         }
 902
 903         spi_master_set_devdata(master, dws);
 904         ret = spi_register_master(master);
 905         if (ret) {
 906                 dev_err(&master->dev, "problem registering spi master\n");
 907                 goto err_queue_alloc;
 908         }
 909
 910         mrst_spi_debugfs_init(dws);
 911         return 0;
 912
 913 err_queue_alloc:
 914         destroy_queue(dws);
 915 err_diable_hw:
 916         spi_enable_chip(dws, 0);
 917         free_irq(dws->irq, dws);
 918 err_free_master:
 919         spi_master_put(master);
 920 exit:
 921         return ret;
 922 }
 923 EXPORT_SYMBOL(dw_spi_add_host);
 924
 925 void __devexit dw_spi_remove_host(struct dw_spi *dws)
 926 {
 927         int status = 0;
 928
 929         if (!dws)
 930                 return;
 931         mrst_spi_debugfs_remove(dws);
 932
 933         /* Remove the queue */
 934         status = destroy_queue(dws);
 935         if (status != 0)
 936                 dev_err(&dws->master->dev, "dw_spi_remove: workqueue will not "
 937                         "complete, message memory not freed\n");
 938
 939         spi_enable_chip(dws, 0);
 940         /* Disable clk */
 941         spi_set_clk(dws, 0);
 942         free_irq(dws->irq, dws);
 943
 944         /* Disconnect from the SPI framework */
 945         spi_unregister_master(dws->master);
 946 }
 947
 948 int dw_spi_suspend_host(struct dw_spi *dws)
 949 {
 950         int ret = 0;
 951
 952         ret = stop_queue(dws);
 953         if (ret)
 954                 return ret;
 955         spi_enable_chip(dws, 0);
 956         spi_set_clk(dws, 0);
 957         return ret;
 958 }
 959 EXPORT_SYMBOL(dw_spi_suspend_host);
 960
 961 int dw_spi_resume_host(struct dw_spi *dws)
 962 {
 963         int ret;
 964
 965         spi_hw_init(dws);
 966         ret = start_queue(dws);
 967         if (ret)
 968                 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
 969         return ret;
 970 }
 971 EXPORT_SYMBOL(dw_spi_resume_host);
 972
 973 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
 974 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
 975 MODULE_LICENSE("GPL v2");