2 * drivers/serial/sh-sci.c
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
6 * Copyright (C) 2002 - 2008 Paul Mundt
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
9 * based off of the old drivers/char/sh-sci.c by:
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file "COPYING" in the main directory of this archive
22 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28 #include <linux/module.h>
29 #include <linux/errno.h>
30 #include <linux/timer.h>
31 #include <linux/interrupt.h>
32 #include <linux/tty.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial.h>
35 #include <linux/major.h>
36 #include <linux/string.h>
37 #include <linux/sysrq.h>
38 #include <linux/ioport.h>
40 #include <linux/init.h>
41 #include <linux/delay.h>
42 #include <linux/console.h>
43 #include <linux/platform_device.h>
44 #include <linux/serial_sci.h>
45 #include <linux/notifier.h>
46 #include <linux/cpufreq.h>
47 #include <linux/clk.h>
48 #include <linux/ctype.h>
49 #include <linux/err.h>
52 #include <asm/clock.h>
53 #include <asm/sh_bios.h>
59 struct uart_port port;
64 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
65 unsigned int irqs[SCIx_NR_IRQS];
67 /* Port enable callback */
68 void (*enable)(struct uart_port *port);
70 /* Port disable callback */
71 void (*disable)(struct uart_port *port);
74 struct timer_list break_timer;
77 #ifdef CONFIG_HAVE_CLK
83 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
84 static struct sci_port *serial_console_port;
87 /* Function prototypes */
88 static void sci_stop_tx(struct uart_port *port);
90 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
92 static struct sci_port sci_ports[SCI_NPORTS];
93 static struct uart_driver sci_uart_driver;
95 static inline struct sci_port *
96 to_sci_port(struct uart_port *uart)
98 return container_of(uart, struct sci_port, port);
101 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
102 static inline void handle_error(struct uart_port *port)
104 /* Clear error flags */
105 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
108 static int sci_poll_get_char(struct uart_port *port)
110 unsigned short status;
114 status = sci_in(port, SCxSR);
115 if (status & SCxSR_ERRORS(port)) {
119 } while (!(status & SCxSR_RDxF(port)));
121 c = sci_in(port, SCxRDR);
125 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
130 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
132 unsigned short status;
135 status = sci_in(port, SCxSR);
136 } while (!(status & SCxSR_TDxE(port)));
138 sci_in(port, SCxSR); /* Dummy read */
139 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
140 sci_out(port, SCxTDR, c);
142 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
144 #if defined(__H8300S__)
145 enum { sci_disable, sci_enable };
147 static void h8300_sci_config(struct uart_port *port, unsigned int ctrl)
149 volatile unsigned char *mstpcrl = (volatile unsigned char *)MSTPCRL;
150 int ch = (port->mapbase - SMR0) >> 3;
151 unsigned char mask = 1 << (ch+1);
153 if (ctrl == sci_disable)
159 static inline void h8300_sci_enable(struct uart_port *port)
161 h8300_sci_config(port, sci_enable);
164 static inline void h8300_sci_disable(struct uart_port *port)
166 h8300_sci_config(port, sci_disable);
170 #if defined(__H8300H__) || defined(__H8300S__)
171 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
173 int ch = (port->mapbase - SMR0) >> 3;
176 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
177 h8300_sci_pins[ch].rx,
179 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
180 h8300_sci_pins[ch].tx,
184 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
186 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
187 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
189 if (port->mapbase == 0xA4400000) {
190 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
191 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
192 } else if (port->mapbase == 0xA4410000)
193 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
195 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
196 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
200 if (cflag & CRTSCTS) {
202 if (port->mapbase == 0xa4430000) { /* SCIF0 */
203 /* Clear PTCR bit 9-2; enable all scif pins but sck */
204 data = __raw_readw(PORT_PTCR);
205 __raw_writew((data & 0xfc03), PORT_PTCR);
206 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
207 /* Clear PVCR bit 9-2 */
208 data = __raw_readw(PORT_PVCR);
209 __raw_writew((data & 0xfc03), PORT_PVCR);
212 if (port->mapbase == 0xa4430000) { /* SCIF0 */
213 /* Clear PTCR bit 5-2; enable only tx and rx */
214 data = __raw_readw(PORT_PTCR);
215 __raw_writew((data & 0xffc3), PORT_PTCR);
216 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
217 /* Clear PVCR bit 5-2 */
218 data = __raw_readw(PORT_PVCR);
219 __raw_writew((data & 0xffc3), PORT_PVCR);
223 #elif defined(CONFIG_CPU_SH3)
224 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
225 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
229 /* We need to set SCPCR to enable RTS/CTS */
230 data = __raw_readw(SCPCR);
231 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
232 __raw_writew(data & 0x0fcf, SCPCR);
234 if (!(cflag & CRTSCTS)) {
235 /* We need to set SCPCR to enable RTS/CTS */
236 data = __raw_readw(SCPCR);
237 /* Clear out SCP7MD1,0, SCP4MD1,0,
238 Set SCP6MD1,0 = {01} (output) */
239 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
241 data = ctrl_inb(SCPDR);
242 /* Set /RTS2 (bit6) = 0 */
243 ctrl_outb(data & 0xbf, SCPDR);
246 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
247 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
251 if (port->mapbase == 0xffe00000) {
252 data = __raw_readw(PSCR);
254 if (!(cflag & CRTSCTS))
257 __raw_writew(data, PSCR);
260 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
261 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
262 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
263 defined(CONFIG_CPU_SUBTYPE_SHX3)
264 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
266 if (!(cflag & CRTSCTS))
267 __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
269 #elif defined(CONFIG_CPU_SH4)
270 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
272 if (!(cflag & CRTSCTS))
273 __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */
276 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
282 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
283 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
284 defined(CONFIG_CPU_SUBTYPE_SH7785)
285 static inline int scif_txroom(struct uart_port *port)
287 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
290 static inline int scif_rxroom(struct uart_port *port)
292 return sci_in(port, SCRFDR) & 0xff;
294 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
295 static inline int scif_txroom(struct uart_port *port)
297 if ((port->mapbase == 0xffe00000) ||
298 (port->mapbase == 0xffe08000)) {
300 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
303 return SCIF2_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
307 static inline int scif_rxroom(struct uart_port *port)
309 if ((port->mapbase == 0xffe00000) ||
310 (port->mapbase == 0xffe08000)) {
312 return sci_in(port, SCRFDR) & 0xff;
315 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
319 static inline int scif_txroom(struct uart_port *port)
321 return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
324 static inline int scif_rxroom(struct uart_port *port)
326 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
330 static inline int sci_txroom(struct uart_port *port)
332 return (sci_in(port, SCxSR) & SCI_TDRE) != 0;
335 static inline int sci_rxroom(struct uart_port *port)
337 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
340 /* ********************************************************************** *
341 * the interrupt related routines *
342 * ********************************************************************** */
344 static void sci_transmit_chars(struct uart_port *port)
346 struct circ_buf *xmit = &port->info->xmit;
347 unsigned int stopped = uart_tx_stopped(port);
348 unsigned short status;
352 status = sci_in(port, SCxSR);
353 if (!(status & SCxSR_TDxE(port))) {
354 ctrl = sci_in(port, SCSCR);
355 if (uart_circ_empty(xmit))
356 ctrl &= ~SCI_CTRL_FLAGS_TIE;
358 ctrl |= SCI_CTRL_FLAGS_TIE;
359 sci_out(port, SCSCR, ctrl);
363 if (port->type == PORT_SCI)
364 count = sci_txroom(port);
366 count = scif_txroom(port);
374 } else if (!uart_circ_empty(xmit) && !stopped) {
375 c = xmit->buf[xmit->tail];
376 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
381 sci_out(port, SCxTDR, c);
384 } while (--count > 0);
386 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
388 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
389 uart_write_wakeup(port);
390 if (uart_circ_empty(xmit)) {
393 ctrl = sci_in(port, SCSCR);
395 if (port->type != PORT_SCI) {
396 sci_in(port, SCxSR); /* Dummy read */
397 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
400 ctrl |= SCI_CTRL_FLAGS_TIE;
401 sci_out(port, SCSCR, ctrl);
405 /* On SH3, SCIF may read end-of-break as a space->mark char */
406 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
408 static inline void sci_receive_chars(struct uart_port *port)
410 struct sci_port *sci_port = to_sci_port(port);
411 struct tty_struct *tty = port->info->port.tty;
412 int i, count, copied = 0;
413 unsigned short status;
416 status = sci_in(port, SCxSR);
417 if (!(status & SCxSR_RDxF(port)))
421 if (port->type == PORT_SCI)
422 count = sci_rxroom(port);
424 count = scif_rxroom(port);
426 /* Don't copy more bytes than there is room for in the buffer */
427 count = tty_buffer_request_room(tty, count);
429 /* If for any reason we can't copy more data, we're done! */
433 if (port->type == PORT_SCI) {
434 char c = sci_in(port, SCxRDR);
435 if (uart_handle_sysrq_char(port, c) ||
436 sci_port->break_flag)
439 tty_insert_flip_char(tty, c, TTY_NORMAL);
441 for (i = 0; i < count; i++) {
442 char c = sci_in(port, SCxRDR);
443 status = sci_in(port, SCxSR);
444 #if defined(CONFIG_CPU_SH3)
445 /* Skip "chars" during break */
446 if (sci_port->break_flag) {
448 (status & SCxSR_FER(port))) {
453 /* Nonzero => end-of-break */
454 dev_dbg(port->dev, "debounce<%02x>\n", c);
455 sci_port->break_flag = 0;
462 #endif /* CONFIG_CPU_SH3 */
463 if (uart_handle_sysrq_char(port, c)) {
468 /* Store data and status */
469 if (status&SCxSR_FER(port)) {
471 dev_notice(port->dev, "frame error\n");
472 } else if (status&SCxSR_PER(port)) {
474 dev_notice(port->dev, "parity error\n");
478 tty_insert_flip_char(tty, c, flag);
482 sci_in(port, SCxSR); /* dummy read */
483 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
486 port->icount.rx += count;
490 /* Tell the rest of the system the news. New characters! */
491 tty_flip_buffer_push(tty);
493 sci_in(port, SCxSR); /* dummy read */
494 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
498 #define SCI_BREAK_JIFFIES (HZ/20)
499 /* The sci generates interrupts during the break,
500 * 1 per millisecond or so during the break period, for 9600 baud.
501 * So dont bother disabling interrupts.
502 * But dont want more than 1 break event.
503 * Use a kernel timer to periodically poll the rx line until
504 * the break is finished.
506 static void sci_schedule_break_timer(struct sci_port *port)
508 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
509 add_timer(&port->break_timer);
511 /* Ensure that two consecutive samples find the break over. */
512 static void sci_break_timer(unsigned long data)
514 struct sci_port *port = (struct sci_port *)data;
516 if (sci_rxd_in(&port->port) == 0) {
517 port->break_flag = 1;
518 sci_schedule_break_timer(port);
519 } else if (port->break_flag == 1) {
521 port->break_flag = 2;
522 sci_schedule_break_timer(port);
524 port->break_flag = 0;
527 static inline int sci_handle_errors(struct uart_port *port)
530 unsigned short status = sci_in(port, SCxSR);
531 struct tty_struct *tty = port->info->port.tty;
533 if (status & SCxSR_ORER(port)) {
535 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
538 dev_notice(port->dev, "overrun error");
541 if (status & SCxSR_FER(port)) {
542 if (sci_rxd_in(port) == 0) {
543 /* Notify of BREAK */
544 struct sci_port *sci_port = to_sci_port(port);
546 if (!sci_port->break_flag) {
547 sci_port->break_flag = 1;
548 sci_schedule_break_timer(sci_port);
550 /* Do sysrq handling. */
551 if (uart_handle_break(port))
554 dev_dbg(port->dev, "BREAK detected\n");
556 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
562 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
565 dev_notice(port->dev, "frame error\n");
569 if (status & SCxSR_PER(port)) {
571 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
574 dev_notice(port->dev, "parity error");
578 tty_flip_buffer_push(tty);
583 static inline int sci_handle_fifo_overrun(struct uart_port *port)
585 struct tty_struct *tty = port->info->port.tty;
588 if (port->type != PORT_SCIF)
591 if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
592 sci_out(port, SCLSR, 0);
594 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
595 tty_flip_buffer_push(tty);
597 dev_notice(port->dev, "overrun error\n");
604 static inline int sci_handle_breaks(struct uart_port *port)
607 unsigned short status = sci_in(port, SCxSR);
608 struct tty_struct *tty = port->info->port.tty;
609 struct sci_port *s = &sci_ports[port->line];
611 if (uart_handle_break(port))
614 if (!s->break_flag && status & SCxSR_BRK(port)) {
615 #if defined(CONFIG_CPU_SH3)
619 /* Notify of BREAK */
620 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
623 dev_dbg(port->dev, "BREAK detected\n");
627 tty_flip_buffer_push(tty);
629 copied += sci_handle_fifo_overrun(port);
634 static irqreturn_t sci_rx_interrupt(int irq, void *port)
636 /* I think sci_receive_chars has to be called irrespective
637 * of whether the I_IXOFF is set, otherwise, how is the interrupt
640 sci_receive_chars(port);
645 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
647 struct uart_port *port = ptr;
649 spin_lock_irq(&port->lock);
650 sci_transmit_chars(port);
651 spin_unlock_irq(&port->lock);
656 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
658 struct uart_port *port = ptr;
661 if (port->type == PORT_SCI) {
662 if (sci_handle_errors(port)) {
663 /* discard character in rx buffer */
665 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
668 sci_handle_fifo_overrun(port);
669 sci_rx_interrupt(irq, ptr);
672 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
674 /* Kick the transmission */
675 sci_tx_interrupt(irq, ptr);
680 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
682 struct uart_port *port = ptr;
685 sci_handle_breaks(port);
686 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
691 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
693 unsigned short ssr_status, scr_status;
694 struct uart_port *port = ptr;
695 irqreturn_t ret = IRQ_NONE;
697 ssr_status = sci_in(port, SCxSR);
698 scr_status = sci_in(port, SCSCR);
701 if ((ssr_status & 0x0020) && (scr_status & SCI_CTRL_FLAGS_TIE))
702 ret = sci_tx_interrupt(irq, ptr);
704 if ((ssr_status & 0x0002) && (scr_status & SCI_CTRL_FLAGS_RIE))
705 ret = sci_rx_interrupt(irq, ptr);
706 /* Error Interrupt */
707 if ((ssr_status & 0x0080) && (scr_status & SCI_CTRL_FLAGS_REIE))
708 ret = sci_er_interrupt(irq, ptr);
709 /* Break Interrupt */
710 if ((ssr_status & 0x0010) && (scr_status & SCI_CTRL_FLAGS_REIE))
711 ret = sci_br_interrupt(irq, ptr);
716 #ifdef CONFIG_HAVE_CLK
718 * Here we define a transistion notifier so that we can update all of our
719 * ports' baud rate when the peripheral clock changes.
721 static int sci_notifier(struct notifier_block *self,
722 unsigned long phase, void *p)
726 if ((phase == CPUFREQ_POSTCHANGE) ||
727 (phase == CPUFREQ_RESUMECHANGE))
728 for (i = 0; i < SCI_NPORTS; i++) {
729 struct sci_port *s = &sci_ports[i];
730 s->port.uartclk = clk_get_rate(s->clk);
736 static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 };
739 static int sci_request_irq(struct sci_port *port)
742 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
743 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
746 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
747 "SCI Transmit Data Empty", "SCI Break" };
749 if (port->irqs[0] == port->irqs[1]) {
750 if (unlikely(!port->irqs[0]))
753 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
754 IRQF_DISABLED, "sci", port)) {
755 dev_err(port->port.dev, "Can't allocate IRQ\n");
759 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
760 if (unlikely(!port->irqs[i]))
763 if (request_irq(port->irqs[i], handlers[i],
764 IRQF_DISABLED, desc[i], port)) {
765 dev_err(port->port.dev, "Can't allocate IRQ\n");
774 static void sci_free_irq(struct sci_port *port)
778 if (port->irqs[0] == port->irqs[1])
779 free_irq(port->irqs[0], port);
781 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
785 free_irq(port->irqs[i], port);
790 static unsigned int sci_tx_empty(struct uart_port *port)
796 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
798 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
799 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
800 /* If you have signals for DTR and DCD, please implement here. */
803 static unsigned int sci_get_mctrl(struct uart_port *port)
805 /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
808 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
811 static void sci_start_tx(struct uart_port *port)
815 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
816 ctrl = sci_in(port, SCSCR);
817 ctrl |= SCI_CTRL_FLAGS_TIE;
818 sci_out(port, SCSCR, ctrl);
821 static void sci_stop_tx(struct uart_port *port)
825 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
826 ctrl = sci_in(port, SCSCR);
827 ctrl &= ~SCI_CTRL_FLAGS_TIE;
828 sci_out(port, SCSCR, ctrl);
831 static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
835 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
836 ctrl = sci_in(port, SCSCR);
837 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
838 sci_out(port, SCSCR, ctrl);
841 static void sci_stop_rx(struct uart_port *port)
845 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
846 ctrl = sci_in(port, SCSCR);
847 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
848 sci_out(port, SCSCR, ctrl);
851 static void sci_enable_ms(struct uart_port *port)
853 /* Nothing here yet .. */
856 static void sci_break_ctl(struct uart_port *port, int break_state)
858 /* Nothing here yet .. */
861 static int sci_startup(struct uart_port *port)
863 struct sci_port *s = &sci_ports[port->line];
868 #ifdef CONFIG_HAVE_CLK
869 s->clk = clk_get(NULL, "module_clk");
874 sci_start_rx(port, 1);
879 static void sci_shutdown(struct uart_port *port)
881 struct sci_port *s = &sci_ports[port->line];
890 #ifdef CONFIG_HAVE_CLK
896 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
897 struct ktermios *old)
899 unsigned int status, baud, smr_val;
902 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
904 t = SCBRR_VALUE(baud, port->uartclk);
907 status = sci_in(port, SCxSR);
908 } while (!(status & SCxSR_TEND(port)));
910 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
912 if (port->type != PORT_SCI)
913 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
915 smr_val = sci_in(port, SCSMR) & 3;
916 if ((termios->c_cflag & CSIZE) == CS7)
918 if (termios->c_cflag & PARENB)
920 if (termios->c_cflag & PARODD)
922 if (termios->c_cflag & CSTOPB)
925 uart_update_timeout(port, termios->c_cflag, baud);
927 sci_out(port, SCSMR, smr_val);
931 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
934 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
936 sci_out(port, SCBRR, t);
937 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
940 sci_init_pins(port, termios->c_cflag);
941 sci_out(port, SCFCR, (termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0);
943 sci_out(port, SCSCR, SCSCR_INIT(port));
945 if ((termios->c_cflag & CREAD) != 0)
946 sci_start_rx(port, 0);
949 static const char *sci_type(struct uart_port *port)
951 switch (port->type) {
965 static void sci_release_port(struct uart_port *port)
967 /* Nothing here yet .. */
970 static int sci_request_port(struct uart_port *port)
972 /* Nothing here yet .. */
976 static void sci_config_port(struct uart_port *port, int flags)
978 struct sci_port *s = &sci_ports[port->line];
980 port->type = s->type;
982 if (port->flags & UPF_IOREMAP && !port->membase) {
983 #if defined(CONFIG_SUPERH64)
984 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
985 port->membase = (void __iomem *)port->mapbase;
987 port->membase = ioremap_nocache(port->mapbase, 0x40);
990 dev_err(port->dev, "can't remap port#%d\n", port->line);
994 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
996 struct sci_port *s = &sci_ports[port->line];
998 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1000 if (ser->baud_base < 2400)
1001 /* No paper tape reader for Mitch.. */
1007 static struct uart_ops sci_uart_ops = {
1008 .tx_empty = sci_tx_empty,
1009 .set_mctrl = sci_set_mctrl,
1010 .get_mctrl = sci_get_mctrl,
1011 .start_tx = sci_start_tx,
1012 .stop_tx = sci_stop_tx,
1013 .stop_rx = sci_stop_rx,
1014 .enable_ms = sci_enable_ms,
1015 .break_ctl = sci_break_ctl,
1016 .startup = sci_startup,
1017 .shutdown = sci_shutdown,
1018 .set_termios = sci_set_termios,
1020 .release_port = sci_release_port,
1021 .request_port = sci_request_port,
1022 .config_port = sci_config_port,
1023 .verify_port = sci_verify_port,
1024 #ifdef CONFIG_CONSOLE_POLL
1025 .poll_get_char = sci_poll_get_char,
1026 .poll_put_char = sci_poll_put_char,
1030 static void __init sci_init_ports(void)
1032 static int first = 1;
1040 for (i = 0; i < SCI_NPORTS; i++) {
1041 sci_ports[i].port.ops = &sci_uart_ops;
1042 sci_ports[i].port.iotype = UPIO_MEM;
1043 sci_ports[i].port.line = i;
1044 sci_ports[i].port.fifosize = 1;
1046 #if defined(__H8300H__) || defined(__H8300S__)
1048 sci_ports[i].enable = h8300_sci_enable;
1049 sci_ports[i].disable = h8300_sci_disable;
1051 sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK;
1052 #elif defined(CONFIG_HAVE_CLK)
1054 * XXX: We should use a proper SCI/SCIF clock
1057 struct clk *clk = clk_get(NULL, "module_clk");
1058 sci_ports[i].port.uartclk = clk_get_rate(clk);
1062 #error "Need a valid uartclk"
1065 sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i];
1066 sci_ports[i].break_timer.function = sci_break_timer;
1068 init_timer(&sci_ports[i].break_timer);
1072 int __init early_sci_setup(struct uart_port *port)
1074 if (unlikely(port->line > SCI_NPORTS))
1079 sci_ports[port->line].port.membase = port->membase;
1080 sci_ports[port->line].port.mapbase = port->mapbase;
1081 sci_ports[port->line].port.type = port->type;
1086 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1088 * Print a string to the serial port trying not to disturb
1089 * any possible real use of the port...
1091 static void serial_console_write(struct console *co, const char *s,
1094 struct uart_port *port = &serial_console_port->port;
1097 for (i = 0; i < count; i++) {
1099 sci_poll_put_char(port, '\r');
1101 sci_poll_put_char(port, *s++);
1105 static int __init serial_console_setup(struct console *co, char *options)
1107 struct uart_port *port;
1115 * Check whether an invalid uart number has been specified, and
1116 * if so, search for the first available port that does have
1119 if (co->index >= SCI_NPORTS)
1122 serial_console_port = &sci_ports[co->index];
1123 port = &serial_console_port->port;
1126 * Also need to check port->type, we don't actually have any
1127 * UPIO_PORT ports, but uart_report_port() handily misreports
1128 * it anyways if we don't have a port available by the time this is
1133 if (!port->membase || !port->mapbase)
1136 port->type = serial_console_port->type;
1138 #ifdef CONFIG_HAVE_CLK
1139 if (!serial_console_port->clk)
1140 serial_console_port->clk = clk_get(NULL, "module_clk");
1143 if (port->flags & UPF_IOREMAP)
1144 sci_config_port(port, 0);
1146 if (serial_console_port->enable)
1147 serial_console_port->enable(port);
1150 uart_parse_options(options, &baud, &parity, &bits, &flow);
1152 ret = uart_set_options(port, co, baud, parity, bits, flow);
1153 #if defined(__H8300H__) || defined(__H8300S__)
1154 /* disable rx interrupt */
1161 static struct console serial_console = {
1163 .device = uart_console_device,
1164 .write = serial_console_write,
1165 .setup = serial_console_setup,
1166 .flags = CON_PRINTBUFFER,
1168 .data = &sci_uart_driver,
1171 static int __init sci_console_init(void)
1174 register_console(&serial_console);
1177 console_initcall(sci_console_init);
1178 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1180 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1181 #define SCI_CONSOLE (&serial_console)
1183 #define SCI_CONSOLE 0
1186 static char banner[] __initdata =
1187 KERN_INFO "SuperH SCI(F) driver initialized\n";
1189 static struct uart_driver sci_uart_driver = {
1190 .owner = THIS_MODULE,
1191 .driver_name = "sci",
1192 .dev_name = "ttySC",
1194 .minor = SCI_MINOR_START,
1196 .cons = SCI_CONSOLE,
1200 * Register a set of serial devices attached to a platform device. The
1201 * list is terminated with a zero flags entry, which means we expect
1202 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1203 * remapping (such as sh64) should also set UPF_IOREMAP.
1205 static int __devinit sci_probe(struct platform_device *dev)
1207 struct plat_sci_port *p = dev->dev.platform_data;
1208 int i, ret = -EINVAL;
1210 for (i = 0; p && p->flags != 0; p++, i++) {
1211 struct sci_port *sciport = &sci_ports[i];
1214 if (unlikely(i == SCI_NPORTS)) {
1215 dev_notice(&dev->dev, "Attempting to register port "
1216 "%d when only %d are available.\n",
1218 dev_notice(&dev->dev, "Consider bumping "
1219 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1223 sciport->port.mapbase = p->mapbase;
1225 if (p->mapbase && !p->membase) {
1226 if (p->flags & UPF_IOREMAP) {
1227 p->membase = ioremap_nocache(p->mapbase, 0x40);
1228 if (IS_ERR(p->membase)) {
1229 ret = PTR_ERR(p->membase);
1234 * For the simple (and majority of) cases
1235 * where we don't need to do any remapping,
1236 * just cast the cookie directly.
1238 p->membase = (void __iomem *)p->mapbase;
1242 sciport->port.membase = p->membase;
1244 sciport->port.irq = p->irqs[SCIx_TXI_IRQ];
1245 sciport->port.flags = p->flags;
1246 sciport->port.dev = &dev->dev;
1248 sciport->type = sciport->port.type = p->type;
1250 memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs));
1252 uart_add_one_port(&sci_uart_driver, &sciport->port);
1255 #ifdef CONFIG_HAVE_CLK
1256 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1259 #ifdef CONFIG_SH_STANDARD_BIOS
1260 sh_bios_gdb_detach();
1266 for (i = i - 1; i >= 0; i--)
1267 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1272 static int __devexit sci_remove(struct platform_device *dev)
1276 #ifdef CONFIG_HAVE_CLK
1277 cpufreq_unregister_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1280 for (i = 0; i < SCI_NPORTS; i++)
1281 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1286 static int sci_suspend(struct platform_device *dev, pm_message_t state)
1290 for (i = 0; i < SCI_NPORTS; i++) {
1291 struct sci_port *p = &sci_ports[i];
1293 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1294 uart_suspend_port(&sci_uart_driver, &p->port);
1300 static int sci_resume(struct platform_device *dev)
1304 for (i = 0; i < SCI_NPORTS; i++) {
1305 struct sci_port *p = &sci_ports[i];
1307 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1308 uart_resume_port(&sci_uart_driver, &p->port);
1314 static struct platform_driver sci_driver = {
1316 .remove = __devexit_p(sci_remove),
1317 .suspend = sci_suspend,
1318 .resume = sci_resume,
1321 .owner = THIS_MODULE,
1325 static int __init sci_init(void)
1333 ret = uart_register_driver(&sci_uart_driver);
1334 if (likely(ret == 0)) {
1335 ret = platform_driver_register(&sci_driver);
1337 uart_unregister_driver(&sci_uart_driver);
1343 static void __exit sci_exit(void)
1345 platform_driver_unregister(&sci_driver);
1346 uart_unregister_driver(&sci_uart_driver);
1349 module_init(sci_init);
1350 module_exit(sci_exit);
1352 MODULE_LICENSE("GPL");
1353 MODULE_ALIAS("platform:sh-sci");