2 * drivers/serial/sh-sci.c
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
6 * Copyright (C) 2002 - 2008 Paul Mundt
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
9 * based off of the old drivers/char/sh-sci.c by:
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file "COPYING" in the main directory of this archive
22 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28 #include <linux/module.h>
29 #include <linux/errno.h>
30 #include <linux/timer.h>
31 #include <linux/interrupt.h>
32 #include <linux/tty.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial.h>
35 #include <linux/major.h>
36 #include <linux/string.h>
37 #include <linux/sysrq.h>
38 #include <linux/ioport.h>
40 #include <linux/init.h>
41 #include <linux/delay.h>
42 #include <linux/console.h>
43 #include <linux/platform_device.h>
44 #include <linux/serial_sci.h>
45 #include <linux/notifier.h>
46 #include <linux/cpufreq.h>
47 #include <linux/clk.h>
48 #include <linux/ctype.h>
49 #include <linux/err.h>
50 #include <linux/list.h>
53 #include <asm/clock.h>
54 #include <asm/sh_bios.h>
60 struct uart_port port;
65 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
66 unsigned int irqs[SCIx_NR_IRQS];
68 /* Port enable callback */
69 void (*enable)(struct uart_port *port);
71 /* Port disable callback */
72 void (*disable)(struct uart_port *port);
75 struct timer_list break_timer;
78 #ifdef CONFIG_HAVE_CLK
82 struct list_head node;
87 struct list_head ports;
89 #ifdef CONFIG_HAVE_CLK
90 struct notifier_block clk_nb;
94 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
95 static struct sci_port *serial_console_port;
98 /* Function prototypes */
99 static void sci_stop_tx(struct uart_port *port);
101 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
103 static struct sci_port sci_ports[SCI_NPORTS];
104 static struct uart_driver sci_uart_driver;
106 static inline struct sci_port *
107 to_sci_port(struct uart_port *uart)
109 return container_of(uart, struct sci_port, port);
112 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
114 #ifdef CONFIG_CONSOLE_POLL
115 static inline void handle_error(struct uart_port *port)
117 /* Clear error flags */
118 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
121 static int sci_poll_get_char(struct uart_port *port)
123 unsigned short status;
127 status = sci_in(port, SCxSR);
128 if (status & SCxSR_ERRORS(port)) {
132 } while (!(status & SCxSR_RDxF(port)));
134 c = sci_in(port, SCxRDR);
138 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
144 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
146 unsigned short status;
149 status = sci_in(port, SCxSR);
150 } while (!(status & SCxSR_TDxE(port)));
152 sci_in(port, SCxSR); /* Dummy read */
153 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
154 sci_out(port, SCxTDR, c);
156 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
158 #if defined(__H8300S__)
159 enum { sci_disable, sci_enable };
161 static void h8300_sci_config(struct uart_port *port, unsigned int ctrl)
163 volatile unsigned char *mstpcrl = (volatile unsigned char *)MSTPCRL;
164 int ch = (port->mapbase - SMR0) >> 3;
165 unsigned char mask = 1 << (ch+1);
167 if (ctrl == sci_disable)
173 static inline void h8300_sci_enable(struct uart_port *port)
175 h8300_sci_config(port, sci_enable);
178 static inline void h8300_sci_disable(struct uart_port *port)
180 h8300_sci_config(port, sci_disable);
184 #if defined(__H8300H__) || defined(__H8300S__)
185 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
187 int ch = (port->mapbase - SMR0) >> 3;
190 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
191 h8300_sci_pins[ch].rx,
193 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
194 h8300_sci_pins[ch].tx,
198 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
200 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
201 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
203 if (port->mapbase == 0xA4400000) {
204 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
205 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
206 } else if (port->mapbase == 0xA4410000)
207 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
209 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
210 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
214 if (cflag & CRTSCTS) {
216 if (port->mapbase == 0xa4430000) { /* SCIF0 */
217 /* Clear PTCR bit 9-2; enable all scif pins but sck */
218 data = __raw_readw(PORT_PTCR);
219 __raw_writew((data & 0xfc03), PORT_PTCR);
220 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
221 /* Clear PVCR bit 9-2 */
222 data = __raw_readw(PORT_PVCR);
223 __raw_writew((data & 0xfc03), PORT_PVCR);
226 if (port->mapbase == 0xa4430000) { /* SCIF0 */
227 /* Clear PTCR bit 5-2; enable only tx and rx */
228 data = __raw_readw(PORT_PTCR);
229 __raw_writew((data & 0xffc3), PORT_PTCR);
230 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
231 /* Clear PVCR bit 5-2 */
232 data = __raw_readw(PORT_PVCR);
233 __raw_writew((data & 0xffc3), PORT_PVCR);
237 #elif defined(CONFIG_CPU_SH3)
238 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
239 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
243 /* We need to set SCPCR to enable RTS/CTS */
244 data = __raw_readw(SCPCR);
245 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
246 __raw_writew(data & 0x0fcf, SCPCR);
248 if (!(cflag & CRTSCTS)) {
249 /* We need to set SCPCR to enable RTS/CTS */
250 data = __raw_readw(SCPCR);
251 /* Clear out SCP7MD1,0, SCP4MD1,0,
252 Set SCP6MD1,0 = {01} (output) */
253 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
255 data = ctrl_inb(SCPDR);
256 /* Set /RTS2 (bit6) = 0 */
257 ctrl_outb(data & 0xbf, SCPDR);
260 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
261 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
265 if (port->mapbase == 0xffe00000) {
266 data = __raw_readw(PSCR);
268 if (!(cflag & CRTSCTS))
271 __raw_writew(data, PSCR);
274 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
275 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
276 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
277 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
278 defined(CONFIG_CPU_SUBTYPE_SHX3)
279 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
281 if (!(cflag & CRTSCTS))
282 __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
284 #elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A)
285 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
287 if (!(cflag & CRTSCTS))
288 __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */
291 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
297 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
298 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
299 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
300 defined(CONFIG_CPU_SUBTYPE_SH7786)
301 static inline int scif_txroom(struct uart_port *port)
303 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
306 static inline int scif_rxroom(struct uart_port *port)
308 return sci_in(port, SCRFDR) & 0xff;
310 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
311 static inline int scif_txroom(struct uart_port *port)
313 if ((port->mapbase == 0xffe00000) ||
314 (port->mapbase == 0xffe08000)) {
316 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
319 return SCIF2_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
323 static inline int scif_rxroom(struct uart_port *port)
325 if ((port->mapbase == 0xffe00000) ||
326 (port->mapbase == 0xffe08000)) {
328 return sci_in(port, SCRFDR) & 0xff;
331 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
335 static inline int scif_txroom(struct uart_port *port)
337 return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
340 static inline int scif_rxroom(struct uart_port *port)
342 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
346 static inline int sci_txroom(struct uart_port *port)
348 return (sci_in(port, SCxSR) & SCI_TDRE) != 0;
351 static inline int sci_rxroom(struct uart_port *port)
353 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
356 /* ********************************************************************** *
357 * the interrupt related routines *
358 * ********************************************************************** */
360 static void sci_transmit_chars(struct uart_port *port)
362 struct circ_buf *xmit = &port->info->xmit;
363 unsigned int stopped = uart_tx_stopped(port);
364 unsigned short status;
368 status = sci_in(port, SCxSR);
369 if (!(status & SCxSR_TDxE(port))) {
370 ctrl = sci_in(port, SCSCR);
371 if (uart_circ_empty(xmit))
372 ctrl &= ~SCI_CTRL_FLAGS_TIE;
374 ctrl |= SCI_CTRL_FLAGS_TIE;
375 sci_out(port, SCSCR, ctrl);
379 if (port->type == PORT_SCI)
380 count = sci_txroom(port);
382 count = scif_txroom(port);
390 } else if (!uart_circ_empty(xmit) && !stopped) {
391 c = xmit->buf[xmit->tail];
392 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
397 sci_out(port, SCxTDR, c);
400 } while (--count > 0);
402 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
404 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
405 uart_write_wakeup(port);
406 if (uart_circ_empty(xmit)) {
409 ctrl = sci_in(port, SCSCR);
411 if (port->type != PORT_SCI) {
412 sci_in(port, SCxSR); /* Dummy read */
413 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
416 ctrl |= SCI_CTRL_FLAGS_TIE;
417 sci_out(port, SCSCR, ctrl);
421 /* On SH3, SCIF may read end-of-break as a space->mark char */
422 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
424 static inline void sci_receive_chars(struct uart_port *port)
426 struct sci_port *sci_port = to_sci_port(port);
427 struct tty_struct *tty = port->info->port.tty;
428 int i, count, copied = 0;
429 unsigned short status;
432 status = sci_in(port, SCxSR);
433 if (!(status & SCxSR_RDxF(port)))
437 if (port->type == PORT_SCI)
438 count = sci_rxroom(port);
440 count = scif_rxroom(port);
442 /* Don't copy more bytes than there is room for in the buffer */
443 count = tty_buffer_request_room(tty, count);
445 /* If for any reason we can't copy more data, we're done! */
449 if (port->type == PORT_SCI) {
450 char c = sci_in(port, SCxRDR);
451 if (uart_handle_sysrq_char(port, c) ||
452 sci_port->break_flag)
455 tty_insert_flip_char(tty, c, TTY_NORMAL);
457 for (i = 0; i < count; i++) {
458 char c = sci_in(port, SCxRDR);
459 status = sci_in(port, SCxSR);
460 #if defined(CONFIG_CPU_SH3)
461 /* Skip "chars" during break */
462 if (sci_port->break_flag) {
464 (status & SCxSR_FER(port))) {
469 /* Nonzero => end-of-break */
470 dev_dbg(port->dev, "debounce<%02x>\n", c);
471 sci_port->break_flag = 0;
478 #endif /* CONFIG_CPU_SH3 */
479 if (uart_handle_sysrq_char(port, c)) {
484 /* Store data and status */
485 if (status&SCxSR_FER(port)) {
487 dev_notice(port->dev, "frame error\n");
488 } else if (status&SCxSR_PER(port)) {
490 dev_notice(port->dev, "parity error\n");
494 tty_insert_flip_char(tty, c, flag);
498 sci_in(port, SCxSR); /* dummy read */
499 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
502 port->icount.rx += count;
506 /* Tell the rest of the system the news. New characters! */
507 tty_flip_buffer_push(tty);
509 sci_in(port, SCxSR); /* dummy read */
510 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
514 #define SCI_BREAK_JIFFIES (HZ/20)
515 /* The sci generates interrupts during the break,
516 * 1 per millisecond or so during the break period, for 9600 baud.
517 * So dont bother disabling interrupts.
518 * But dont want more than 1 break event.
519 * Use a kernel timer to periodically poll the rx line until
520 * the break is finished.
522 static void sci_schedule_break_timer(struct sci_port *port)
524 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
525 add_timer(&port->break_timer);
527 /* Ensure that two consecutive samples find the break over. */
528 static void sci_break_timer(unsigned long data)
530 struct sci_port *port = (struct sci_port *)data;
532 if (sci_rxd_in(&port->port) == 0) {
533 port->break_flag = 1;
534 sci_schedule_break_timer(port);
535 } else if (port->break_flag == 1) {
537 port->break_flag = 2;
538 sci_schedule_break_timer(port);
540 port->break_flag = 0;
543 static inline int sci_handle_errors(struct uart_port *port)
546 unsigned short status = sci_in(port, SCxSR);
547 struct tty_struct *tty = port->info->port.tty;
549 if (status & SCxSR_ORER(port)) {
551 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
554 dev_notice(port->dev, "overrun error");
557 if (status & SCxSR_FER(port)) {
558 if (sci_rxd_in(port) == 0) {
559 /* Notify of BREAK */
560 struct sci_port *sci_port = to_sci_port(port);
562 if (!sci_port->break_flag) {
563 sci_port->break_flag = 1;
564 sci_schedule_break_timer(sci_port);
566 /* Do sysrq handling. */
567 if (uart_handle_break(port))
570 dev_dbg(port->dev, "BREAK detected\n");
572 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
578 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
581 dev_notice(port->dev, "frame error\n");
585 if (status & SCxSR_PER(port)) {
587 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
590 dev_notice(port->dev, "parity error");
594 tty_flip_buffer_push(tty);
599 static inline int sci_handle_fifo_overrun(struct uart_port *port)
601 struct tty_struct *tty = port->info->port.tty;
604 if (port->type != PORT_SCIF)
607 if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
608 sci_out(port, SCLSR, 0);
610 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
611 tty_flip_buffer_push(tty);
613 dev_notice(port->dev, "overrun error\n");
620 static inline int sci_handle_breaks(struct uart_port *port)
623 unsigned short status = sci_in(port, SCxSR);
624 struct tty_struct *tty = port->info->port.tty;
625 struct sci_port *s = &sci_ports[port->line];
627 if (uart_handle_break(port))
630 if (!s->break_flag && status & SCxSR_BRK(port)) {
631 #if defined(CONFIG_CPU_SH3)
635 /* Notify of BREAK */
636 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
639 dev_dbg(port->dev, "BREAK detected\n");
643 tty_flip_buffer_push(tty);
645 copied += sci_handle_fifo_overrun(port);
650 static irqreturn_t sci_rx_interrupt(int irq, void *port)
652 /* I think sci_receive_chars has to be called irrespective
653 * of whether the I_IXOFF is set, otherwise, how is the interrupt
656 sci_receive_chars(port);
661 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
663 struct uart_port *port = ptr;
665 spin_lock_irq(&port->lock);
666 sci_transmit_chars(port);
667 spin_unlock_irq(&port->lock);
672 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
674 struct uart_port *port = ptr;
677 if (port->type == PORT_SCI) {
678 if (sci_handle_errors(port)) {
679 /* discard character in rx buffer */
681 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
684 sci_handle_fifo_overrun(port);
685 sci_rx_interrupt(irq, ptr);
688 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
690 /* Kick the transmission */
691 sci_tx_interrupt(irq, ptr);
696 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
698 struct uart_port *port = ptr;
701 sci_handle_breaks(port);
702 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
707 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
709 unsigned short ssr_status, scr_status;
710 struct uart_port *port = ptr;
711 irqreturn_t ret = IRQ_NONE;
713 ssr_status = sci_in(port, SCxSR);
714 scr_status = sci_in(port, SCSCR);
717 if ((ssr_status & 0x0020) && (scr_status & SCI_CTRL_FLAGS_TIE))
718 ret = sci_tx_interrupt(irq, ptr);
720 if ((ssr_status & 0x0002) && (scr_status & SCI_CTRL_FLAGS_RIE))
721 ret = sci_rx_interrupt(irq, ptr);
722 /* Error Interrupt */
723 if ((ssr_status & 0x0080) && (scr_status & SCI_CTRL_FLAGS_REIE))
724 ret = sci_er_interrupt(irq, ptr);
725 /* Break Interrupt */
726 if ((ssr_status & 0x0010) && (scr_status & SCI_CTRL_FLAGS_REIE))
727 ret = sci_br_interrupt(irq, ptr);
732 #ifdef CONFIG_HAVE_CLK
734 * Here we define a transistion notifier so that we can update all of our
735 * ports' baud rate when the peripheral clock changes.
737 static int sci_notifier(struct notifier_block *self,
738 unsigned long phase, void *p)
740 struct sh_sci_priv *priv = container_of(self,
741 struct sh_sci_priv, clk_nb);
742 struct sci_port *sci_port;
745 if ((phase == CPUFREQ_POSTCHANGE) ||
746 (phase == CPUFREQ_RESUMECHANGE)) {
747 spin_lock_irqsave(&priv->lock, flags);
748 list_for_each_entry(sci_port, &priv->ports, node)
749 sci_port->port.uartclk = clk_get_rate(sci_port->clk);
751 spin_unlock_irqrestore(&priv->lock, flags);
758 static int sci_request_irq(struct sci_port *port)
761 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
762 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
765 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
766 "SCI Transmit Data Empty", "SCI Break" };
768 if (port->irqs[0] == port->irqs[1]) {
769 if (unlikely(!port->irqs[0]))
772 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
773 IRQF_DISABLED, "sci", port)) {
774 dev_err(port->port.dev, "Can't allocate IRQ\n");
778 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
779 if (unlikely(!port->irqs[i]))
782 if (request_irq(port->irqs[i], handlers[i],
783 IRQF_DISABLED, desc[i], port)) {
784 dev_err(port->port.dev, "Can't allocate IRQ\n");
793 static void sci_free_irq(struct sci_port *port)
797 if (port->irqs[0] == port->irqs[1])
798 free_irq(port->irqs[0], port);
800 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
804 free_irq(port->irqs[i], port);
809 static unsigned int sci_tx_empty(struct uart_port *port)
815 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
817 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
818 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
819 /* If you have signals for DTR and DCD, please implement here. */
822 static unsigned int sci_get_mctrl(struct uart_port *port)
824 /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
827 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
830 static void sci_start_tx(struct uart_port *port)
834 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
835 ctrl = sci_in(port, SCSCR);
836 ctrl |= SCI_CTRL_FLAGS_TIE;
837 sci_out(port, SCSCR, ctrl);
840 static void sci_stop_tx(struct uart_port *port)
844 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
845 ctrl = sci_in(port, SCSCR);
846 ctrl &= ~SCI_CTRL_FLAGS_TIE;
847 sci_out(port, SCSCR, ctrl);
850 static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
854 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
855 ctrl = sci_in(port, SCSCR);
856 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
857 sci_out(port, SCSCR, ctrl);
860 static void sci_stop_rx(struct uart_port *port)
864 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
865 ctrl = sci_in(port, SCSCR);
866 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
867 sci_out(port, SCSCR, ctrl);
870 static void sci_enable_ms(struct uart_port *port)
872 /* Nothing here yet .. */
875 static void sci_break_ctl(struct uart_port *port, int break_state)
877 /* Nothing here yet .. */
880 static int sci_startup(struct uart_port *port)
882 struct sci_port *s = &sci_ports[port->line];
887 #ifdef CONFIG_HAVE_CLK
888 s->clk = clk_get(NULL, "module_clk");
893 sci_start_rx(port, 1);
898 static void sci_shutdown(struct uart_port *port)
900 struct sci_port *s = &sci_ports[port->line];
909 #ifdef CONFIG_HAVE_CLK
915 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
916 struct ktermios *old)
918 unsigned int status, baud, smr_val;
921 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
923 t = SCBRR_VALUE(baud, port->uartclk);
926 status = sci_in(port, SCxSR);
927 } while (!(status & SCxSR_TEND(port)));
929 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
931 if (port->type != PORT_SCI)
932 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
934 smr_val = sci_in(port, SCSMR) & 3;
935 if ((termios->c_cflag & CSIZE) == CS7)
937 if (termios->c_cflag & PARENB)
939 if (termios->c_cflag & PARODD)
941 if (termios->c_cflag & CSTOPB)
944 uart_update_timeout(port, termios->c_cflag, baud);
946 sci_out(port, SCSMR, smr_val);
950 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
953 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
955 sci_out(port, SCBRR, t);
956 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
959 sci_init_pins(port, termios->c_cflag);
960 sci_out(port, SCFCR, (termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0);
962 sci_out(port, SCSCR, SCSCR_INIT(port));
964 if ((termios->c_cflag & CREAD) != 0)
965 sci_start_rx(port, 0);
968 static const char *sci_type(struct uart_port *port)
970 switch (port->type) {
984 static void sci_release_port(struct uart_port *port)
986 /* Nothing here yet .. */
989 static int sci_request_port(struct uart_port *port)
991 /* Nothing here yet .. */
995 static void sci_config_port(struct uart_port *port, int flags)
997 struct sci_port *s = &sci_ports[port->line];
999 port->type = s->type;
1001 if (port->flags & UPF_IOREMAP && !port->membase) {
1002 port->membase = ioremap_nocache(port->mapbase, 0x40);
1003 dev_err(port->dev, "can't remap port#%d\n", port->line);
1007 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1009 struct sci_port *s = &sci_ports[port->line];
1011 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1013 if (ser->baud_base < 2400)
1014 /* No paper tape reader for Mitch.. */
1020 static struct uart_ops sci_uart_ops = {
1021 .tx_empty = sci_tx_empty,
1022 .set_mctrl = sci_set_mctrl,
1023 .get_mctrl = sci_get_mctrl,
1024 .start_tx = sci_start_tx,
1025 .stop_tx = sci_stop_tx,
1026 .stop_rx = sci_stop_rx,
1027 .enable_ms = sci_enable_ms,
1028 .break_ctl = sci_break_ctl,
1029 .startup = sci_startup,
1030 .shutdown = sci_shutdown,
1031 .set_termios = sci_set_termios,
1033 .release_port = sci_release_port,
1034 .request_port = sci_request_port,
1035 .config_port = sci_config_port,
1036 .verify_port = sci_verify_port,
1037 #ifdef CONFIG_CONSOLE_POLL
1038 .poll_get_char = sci_poll_get_char,
1039 .poll_put_char = sci_poll_put_char,
1043 static void __init sci_init_ports(void)
1045 static int first = 1;
1053 for (i = 0; i < SCI_NPORTS; i++) {
1054 sci_ports[i].port.ops = &sci_uart_ops;
1055 sci_ports[i].port.iotype = UPIO_MEM;
1056 sci_ports[i].port.line = i;
1057 sci_ports[i].port.fifosize = 1;
1059 #if defined(__H8300H__) || defined(__H8300S__)
1061 sci_ports[i].enable = h8300_sci_enable;
1062 sci_ports[i].disable = h8300_sci_disable;
1064 sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK;
1065 #elif defined(CONFIG_HAVE_CLK)
1067 * XXX: We should use a proper SCI/SCIF clock
1070 struct clk *clk = clk_get(NULL, "module_clk");
1071 sci_ports[i].port.uartclk = clk_get_rate(clk);
1075 #error "Need a valid uartclk"
1078 sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i];
1079 sci_ports[i].break_timer.function = sci_break_timer;
1081 init_timer(&sci_ports[i].break_timer);
1085 int __init early_sci_setup(struct uart_port *port)
1087 if (unlikely(port->line > SCI_NPORTS))
1092 sci_ports[port->line].port.membase = port->membase;
1093 sci_ports[port->line].port.mapbase = port->mapbase;
1094 sci_ports[port->line].port.type = port->type;
1099 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1101 * Print a string to the serial port trying not to disturb
1102 * any possible real use of the port...
1104 static void serial_console_write(struct console *co, const char *s,
1107 struct uart_port *port = &serial_console_port->port;
1108 unsigned short bits;
1111 for (i = 0; i < count; i++) {
1113 sci_poll_put_char(port, '\r');
1115 sci_poll_put_char(port, *s++);
1118 /* wait until fifo is empty and last bit has been transmitted */
1119 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
1120 while ((sci_in(port, SCxSR) & bits) != bits)
1124 static int __init serial_console_setup(struct console *co, char *options)
1126 struct uart_port *port;
1134 * Check whether an invalid uart number has been specified, and
1135 * if so, search for the first available port that does have
1138 if (co->index >= SCI_NPORTS)
1141 serial_console_port = &sci_ports[co->index];
1142 port = &serial_console_port->port;
1145 * Also need to check port->type, we don't actually have any
1146 * UPIO_PORT ports, but uart_report_port() handily misreports
1147 * it anyways if we don't have a port available by the time this is
1152 if (!port->membase || !port->mapbase)
1155 port->type = serial_console_port->type;
1157 #ifdef CONFIG_HAVE_CLK
1158 if (!serial_console_port->clk)
1159 serial_console_port->clk = clk_get(NULL, "module_clk");
1162 if (port->flags & UPF_IOREMAP)
1163 sci_config_port(port, 0);
1165 if (serial_console_port->enable)
1166 serial_console_port->enable(port);
1169 uart_parse_options(options, &baud, &parity, &bits, &flow);
1171 ret = uart_set_options(port, co, baud, parity, bits, flow);
1172 #if defined(__H8300H__) || defined(__H8300S__)
1173 /* disable rx interrupt */
1180 static struct console serial_console = {
1182 .device = uart_console_device,
1183 .write = serial_console_write,
1184 .setup = serial_console_setup,
1185 .flags = CON_PRINTBUFFER,
1187 .data = &sci_uart_driver,
1190 static int __init sci_console_init(void)
1193 register_console(&serial_console);
1196 console_initcall(sci_console_init);
1197 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1199 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1200 #define SCI_CONSOLE (&serial_console)
1202 #define SCI_CONSOLE 0
1205 static char banner[] __initdata =
1206 KERN_INFO "SuperH SCI(F) driver initialized\n";
1208 static struct uart_driver sci_uart_driver = {
1209 .owner = THIS_MODULE,
1210 .driver_name = "sci",
1211 .dev_name = "ttySC",
1213 .minor = SCI_MINOR_START,
1215 .cons = SCI_CONSOLE,
1219 static int __devexit sci_remove(struct platform_device *dev)
1221 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1223 unsigned long flags;
1225 #ifdef CONFIG_HAVE_CLK
1226 cpufreq_unregister_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
1229 spin_lock_irqsave(&priv->lock, flags);
1230 list_for_each_entry(p, &priv->ports, node)
1231 uart_remove_one_port(&sci_uart_driver, &p->port);
1233 spin_unlock_irqrestore(&priv->lock, flags);
1240 * Register a set of serial devices attached to a platform device. The
1241 * list is terminated with a zero flags entry, which means we expect
1242 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1243 * remapping (such as sh64) should also set UPF_IOREMAP.
1245 static int __devinit sci_probe(struct platform_device *dev)
1247 struct plat_sci_port *p = dev->dev.platform_data;
1248 struct sh_sci_priv *priv;
1249 int i, ret = -EINVAL;
1250 unsigned long flags;
1252 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1256 INIT_LIST_HEAD(&priv->ports);
1257 spin_lock_init(&priv->lock);
1258 platform_set_drvdata(dev, priv);
1260 #ifdef CONFIG_HAVE_CLK
1261 priv->clk_nb.notifier_call = sci_notifier;
1262 cpufreq_register_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
1265 for (i = 0; p && p->flags != 0; p++, i++) {
1266 struct sci_port *sciport = &sci_ports[i];
1269 if (unlikely(i == SCI_NPORTS)) {
1270 dev_notice(&dev->dev, "Attempting to register port "
1271 "%d when only %d are available.\n",
1273 dev_notice(&dev->dev, "Consider bumping "
1274 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1278 sciport->port.mapbase = p->mapbase;
1280 if (p->mapbase && !p->membase) {
1281 if (p->flags & UPF_IOREMAP) {
1282 p->membase = ioremap_nocache(p->mapbase, 0x40);
1283 if (IS_ERR(p->membase)) {
1284 ret = PTR_ERR(p->membase);
1289 * For the simple (and majority of) cases
1290 * where we don't need to do any remapping,
1291 * just cast the cookie directly.
1293 p->membase = (void __iomem *)p->mapbase;
1297 sciport->port.membase = p->membase;
1299 sciport->port.irq = p->irqs[SCIx_TXI_IRQ];
1300 sciport->port.flags = p->flags;
1301 sciport->port.dev = &dev->dev;
1303 sciport->type = sciport->port.type = p->type;
1305 memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs));
1307 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
1309 if (ret && (p->flags & UPF_IOREMAP)) {
1310 iounmap(p->membase);
1314 INIT_LIST_HEAD(&sciport->node);
1316 spin_lock_irqsave(&priv->lock, flags);
1317 list_add(&sciport->node, &priv->ports);
1318 spin_unlock_irqrestore(&priv->lock, flags);
1321 #ifdef CONFIG_SH_STANDARD_BIOS
1322 sh_bios_gdb_detach();
1332 static int sci_suspend(struct platform_device *dev, pm_message_t state)
1334 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1336 unsigned long flags;
1338 spin_lock_irqsave(&priv->lock, flags);
1339 list_for_each_entry(p, &priv->ports, node)
1340 uart_suspend_port(&sci_uart_driver, &p->port);
1342 spin_unlock_irqrestore(&priv->lock, flags);
1347 static int sci_resume(struct platform_device *dev)
1349 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1351 unsigned long flags;
1353 spin_lock_irqsave(&priv->lock, flags);
1354 list_for_each_entry(p, &priv->ports, node)
1355 uart_resume_port(&sci_uart_driver, &p->port);
1357 spin_unlock_irqrestore(&priv->lock, flags);
1362 static struct platform_driver sci_driver = {
1364 .remove = __devexit_p(sci_remove),
1365 .suspend = sci_suspend,
1366 .resume = sci_resume,
1369 .owner = THIS_MODULE,
1373 static int __init sci_init(void)
1381 ret = uart_register_driver(&sci_uart_driver);
1382 if (likely(ret == 0)) {
1383 ret = platform_driver_register(&sci_driver);
1385 uart_unregister_driver(&sci_uart_driver);
1391 static void __exit sci_exit(void)
1393 platform_driver_unregister(&sci_driver);
1394 uart_unregister_driver(&sci_uart_driver);
1397 module_init(sci_init);
1398 module_exit(sci_exit);
1400 MODULE_LICENSE("GPL");
1401 MODULE_ALIAS("platform:sh-sci");