2 * drivers/serial/msm_serial.c - driver for msm7k serial device and console
4 * Copyright (C) 2007 Google, Inc.
5 * Author: Robert Love <rlove@google.com>
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
18 # define SUPPORT_SYSRQ
21 #include <linux/hrtimer.h>
22 #include <linux/module.h>
24 #include <linux/ioport.h>
25 #include <linux/irq.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/tty.h>
29 #include <linux/tty_flip.h>
30 #include <linux/serial_core.h>
31 #include <linux/serial.h>
32 #include <linux/clk.h>
33 #include <linux/platform_device.h>
35 #include "msm_serial.h"
38 struct uart_port uart;
44 #define UART_TO_MSM(uart_port) ((struct msm_port *) uart_port)
46 static inline void msm_write(struct uart_port *port, unsigned int val,
49 __raw_writel(val, port->membase + off);
52 static inline unsigned int msm_read(struct uart_port *port, unsigned int off)
54 return __raw_readl(port->membase + off);
57 static void msm_stop_tx(struct uart_port *port)
59 struct msm_port *msm_port = UART_TO_MSM(port);
61 msm_port->imr &= ~UART_IMR_TXLEV;
62 msm_write(port, msm_port->imr, UART_IMR);
65 static void msm_start_tx(struct uart_port *port)
67 struct msm_port *msm_port = UART_TO_MSM(port);
69 msm_port->imr |= UART_IMR_TXLEV;
70 msm_write(port, msm_port->imr, UART_IMR);
73 static void msm_stop_rx(struct uart_port *port)
75 struct msm_port *msm_port = UART_TO_MSM(port);
77 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
78 msm_write(port, msm_port->imr, UART_IMR);
81 static void msm_enable_ms(struct uart_port *port)
83 struct msm_port *msm_port = UART_TO_MSM(port);
85 msm_port->imr |= UART_IMR_DELTA_CTS;
86 msm_write(port, msm_port->imr, UART_IMR);
89 static void handle_rx(struct uart_port *port)
91 struct tty_struct *tty = port->info->port.tty;
95 * Handle overrun. My understanding of the hardware is that overrun
96 * is not tied to the RX buffer, so we handle the case out of band.
98 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
99 port->icount.overrun++;
100 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
101 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
104 /* and now the main RX loop */
105 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
107 char flag = TTY_NORMAL;
109 c = msm_read(port, UART_RF);
111 if (sr & UART_SR_RX_BREAK) {
113 if (uart_handle_break(port))
115 } else if (sr & UART_SR_PAR_FRAME_ERR) {
116 port->icount.frame++;
121 /* Mask conditions we're ignorning. */
122 sr &= port->read_status_mask;
124 if (sr & UART_SR_RX_BREAK) {
126 } else if (sr & UART_SR_PAR_FRAME_ERR) {
130 if (!uart_handle_sysrq_char(port, c))
131 tty_insert_flip_char(tty, c, flag);
134 tty_flip_buffer_push(tty);
137 static void handle_tx(struct uart_port *port)
139 struct circ_buf *xmit = &port->info->xmit;
140 struct msm_port *msm_port = UART_TO_MSM(port);
144 msm_write(port, port->x_char, UART_TF);
149 while (msm_read(port, UART_SR) & UART_SR_TX_READY) {
150 if (uart_circ_empty(xmit)) {
151 /* disable tx interrupts */
152 msm_port->imr &= ~UART_IMR_TXLEV;
153 msm_write(port, msm_port->imr, UART_IMR);
157 msm_write(port, xmit->buf[xmit->tail], UART_TF);
159 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
164 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
165 uart_write_wakeup(port);
168 static void handle_delta_cts(struct uart_port *port)
170 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
172 wake_up_interruptible(&port->info->delta_msr_wait);
175 static irqreturn_t msm_irq(int irq, void *dev_id)
177 struct uart_port *port = dev_id;
178 struct msm_port *msm_port = UART_TO_MSM(port);
181 spin_lock(&port->lock);
182 misr = msm_read(port, UART_MISR);
183 msm_write(port, 0, UART_IMR); /* disable interrupt */
185 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE))
187 if (misr & UART_IMR_TXLEV)
189 if (misr & UART_IMR_DELTA_CTS)
190 handle_delta_cts(port);
192 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
193 spin_unlock(&port->lock);
198 static unsigned int msm_tx_empty(struct uart_port *port)
200 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
203 static unsigned int msm_get_mctrl(struct uart_port *port)
205 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
208 static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
212 mr = msm_read(port, UART_MR1);
214 if (!(mctrl & TIOCM_RTS)) {
215 mr &= ~UART_MR1_RX_RDY_CTL;
216 msm_write(port, mr, UART_MR1);
217 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
219 mr |= UART_MR1_RX_RDY_CTL;
220 msm_write(port, mr, UART_MR1);
224 static void msm_break_ctl(struct uart_port *port, int break_ctl)
227 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
229 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
232 static void msm_set_baud_rate(struct uart_port *port, unsigned int baud)
234 unsigned int baud_code, rxstale, watermark;
238 baud_code = UART_CSR_300;
242 baud_code = UART_CSR_600;
246 baud_code = UART_CSR_1200;
250 baud_code = UART_CSR_2400;
254 baud_code = UART_CSR_4800;
258 baud_code = UART_CSR_9600;
262 baud_code = UART_CSR_14400;
266 baud_code = UART_CSR_19200;
270 baud_code = UART_CSR_28800;
274 baud_code = UART_CSR_38400;
278 baud_code = UART_CSR_57600;
283 baud_code = UART_CSR_115200;
288 msm_write(port, baud_code, UART_CSR);
290 /* RX stale watermark */
291 watermark = UART_IPR_STALE_LSB & rxstale;
292 watermark |= UART_IPR_RXSTALE_LAST;
293 watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2);
294 msm_write(port, watermark, UART_IPR);
296 /* set RX watermark */
297 watermark = (port->fifosize * 3) / 4;
298 msm_write(port, watermark, UART_RFWR);
300 /* set TX watermark */
301 msm_write(port, 10, UART_TFWR);
304 static void msm_reset(struct uart_port *port)
306 /* reset everything */
307 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
308 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
309 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
310 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
311 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
312 msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
315 static void msm_init_clock(struct uart_port *port)
317 struct msm_port *msm_port = UART_TO_MSM(port);
319 clk_enable(msm_port->clk);
321 msm_write(port, 0xC0, UART_MREG);
322 msm_write(port, 0xB2, UART_NREG);
323 msm_write(port, 0x7D, UART_DREG);
324 msm_write(port, 0x1C, UART_MNDREG);
327 static int msm_startup(struct uart_port *port)
329 struct msm_port *msm_port = UART_TO_MSM(port);
330 unsigned int data, rfr_level;
333 snprintf(msm_port->name, sizeof(msm_port->name),
334 "msm_serial%d", port->line);
336 ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH,
337 msm_port->name, port);
341 msm_init_clock(port);
343 if (likely(port->fifosize > 12))
344 rfr_level = port->fifosize - 12;
346 rfr_level = port->fifosize;
348 /* set automatic RFR level */
349 data = msm_read(port, UART_MR1);
350 data &= ~UART_MR1_AUTO_RFR_LEVEL1;
351 data &= ~UART_MR1_AUTO_RFR_LEVEL0;
352 data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2);
353 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
354 msm_write(port, data, UART_MR1);
356 /* make sure that RXSTALE count is non-zero */
357 data = msm_read(port, UART_IPR);
358 if (unlikely(!data)) {
359 data |= UART_IPR_RXSTALE_LAST;
360 data |= UART_IPR_STALE_LSB;
361 msm_write(port, data, UART_IPR);
366 msm_write(port, 0x05, UART_CR); /* enable TX & RX */
368 /* turn on RX and CTS interrupts */
369 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
370 UART_IMR_CURRENT_CTS;
371 msm_write(port, msm_port->imr, UART_IMR);
376 static void msm_shutdown(struct uart_port *port)
378 struct msm_port *msm_port = UART_TO_MSM(port);
381 msm_write(port, 0, UART_IMR); /* disable interrupts */
383 clk_disable(msm_port->clk);
385 free_irq(port->irq, port);
388 static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
389 struct ktermios *old)
392 unsigned int baud, mr;
394 spin_lock_irqsave(&port->lock, flags);
396 /* calculate and set baud rate */
397 baud = uart_get_baud_rate(port, termios, old, 300, 115200);
398 msm_set_baud_rate(port, baud);
400 /* calculate parity */
401 mr = msm_read(port, UART_MR2);
402 mr &= ~UART_MR2_PARITY_MODE;
403 if (termios->c_cflag & PARENB) {
404 if (termios->c_cflag & PARODD)
405 mr |= UART_MR2_PARITY_MODE_ODD;
406 else if (termios->c_cflag & CMSPAR)
407 mr |= UART_MR2_PARITY_MODE_SPACE;
409 mr |= UART_MR2_PARITY_MODE_EVEN;
412 /* calculate bits per char */
413 mr &= ~UART_MR2_BITS_PER_CHAR;
414 switch (termios->c_cflag & CSIZE) {
416 mr |= UART_MR2_BITS_PER_CHAR_5;
419 mr |= UART_MR2_BITS_PER_CHAR_6;
422 mr |= UART_MR2_BITS_PER_CHAR_7;
426 mr |= UART_MR2_BITS_PER_CHAR_8;
430 /* calculate stop bits */
431 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
432 if (termios->c_cflag & CSTOPB)
433 mr |= UART_MR2_STOP_BIT_LEN_TWO;
435 mr |= UART_MR2_STOP_BIT_LEN_ONE;
437 /* set parity, bits per char, and stop bit */
438 msm_write(port, mr, UART_MR2);
440 /* calculate and set hardware flow control */
441 mr = msm_read(port, UART_MR1);
442 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
443 if (termios->c_cflag & CRTSCTS) {
444 mr |= UART_MR1_CTS_CTL;
445 mr |= UART_MR1_RX_RDY_CTL;
447 msm_write(port, mr, UART_MR1);
449 /* Configure status bits to ignore based on termio flags. */
450 port->read_status_mask = 0;
451 if (termios->c_iflag & INPCK)
452 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
453 if (termios->c_iflag & (BRKINT | PARMRK))
454 port->read_status_mask |= UART_SR_RX_BREAK;
456 uart_update_timeout(port, termios->c_cflag, baud);
458 spin_unlock_irqrestore(&port->lock, flags);
461 static const char *msm_type(struct uart_port *port)
466 static void msm_release_port(struct uart_port *port)
468 struct platform_device *pdev = to_platform_device(port->dev);
469 struct resource *resource;
470 resource_size_t size;
472 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
473 if (unlikely(!resource))
475 size = resource->end - resource->start + 1;
477 release_mem_region(port->mapbase, size);
478 iounmap(port->membase);
479 port->membase = NULL;
482 static int msm_request_port(struct uart_port *port)
484 struct platform_device *pdev = to_platform_device(port->dev);
485 struct resource *resource;
486 resource_size_t size;
488 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
489 if (unlikely(!resource))
491 size = resource->end - resource->start + 1;
493 if (unlikely(!request_mem_region(port->mapbase, size, "msm_serial")))
496 port->membase = ioremap(port->mapbase, size);
497 if (!port->membase) {
498 release_mem_region(port->mapbase, size);
505 static void msm_config_port(struct uart_port *port, int flags)
507 if (flags & UART_CONFIG_TYPE) {
508 port->type = PORT_MSM;
509 msm_request_port(port);
513 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
515 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
517 if (unlikely(port->irq != ser->irq))
522 static void msm_power(struct uart_port *port, unsigned int state,
523 unsigned int oldstate)
525 struct msm_port *msm_port = UART_TO_MSM(port);
529 clk_enable(msm_port->clk);
532 clk_disable(msm_port->clk);
535 printk(KERN_ERR "msm_serial: Unknown PM state %d\n", state);
539 static struct uart_ops msm_uart_pops = {
540 .tx_empty = msm_tx_empty,
541 .set_mctrl = msm_set_mctrl,
542 .get_mctrl = msm_get_mctrl,
543 .stop_tx = msm_stop_tx,
544 .start_tx = msm_start_tx,
545 .stop_rx = msm_stop_rx,
546 .enable_ms = msm_enable_ms,
547 .break_ctl = msm_break_ctl,
548 .startup = msm_startup,
549 .shutdown = msm_shutdown,
550 .set_termios = msm_set_termios,
552 .release_port = msm_release_port,
553 .request_port = msm_request_port,
554 .config_port = msm_config_port,
555 .verify_port = msm_verify_port,
559 static struct msm_port msm_uart_ports[] = {
563 .ops = &msm_uart_pops,
564 .flags = UPF_BOOT_AUTOCONF,
572 .ops = &msm_uart_pops,
573 .flags = UPF_BOOT_AUTOCONF,
581 .ops = &msm_uart_pops,
582 .flags = UPF_BOOT_AUTOCONF,
589 #define UART_NR ARRAY_SIZE(msm_uart_ports)
591 static inline struct uart_port *get_port_from_line(unsigned int line)
593 return &msm_uart_ports[line].uart;
596 #ifdef CONFIG_SERIAL_MSM_CONSOLE
598 static void msm_console_putchar(struct uart_port *port, int c)
600 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
602 msm_write(port, c, UART_TF);
605 static void msm_console_write(struct console *co, const char *s,
608 struct uart_port *port;
609 struct msm_port *msm_port;
611 BUG_ON(co->index < 0 || co->index >= UART_NR);
613 port = get_port_from_line(co->index);
614 msm_port = UART_TO_MSM(port);
616 spin_lock(&port->lock);
617 uart_console_write(port, s, count, msm_console_putchar);
618 spin_unlock(&port->lock);
621 static int __init msm_console_setup(struct console *co, char *options)
623 struct uart_port *port;
624 int baud, flow, bits, parity;
626 if (unlikely(co->index >= UART_NR || co->index < 0))
629 port = get_port_from_line(co->index);
631 if (unlikely(!port->membase))
636 msm_init_clock(port);
639 uart_parse_options(options, &baud, &parity, &bits, &flow);
644 msm_write(port, UART_MR2_BITS_PER_CHAR_8 | UART_MR2_STOP_BIT_LEN_ONE,
647 if (baud < 300 || baud > 115200)
649 msm_set_baud_rate(port, baud);
653 printk(KERN_INFO "msm_serial: console setup on port #%d\n", port->line);
655 return uart_set_options(port, co, baud, parity, bits, flow);
658 static struct uart_driver msm_uart_driver;
660 static struct console msm_console = {
662 .write = msm_console_write,
663 .device = uart_console_device,
664 .setup = msm_console_setup,
665 .flags = CON_PRINTBUFFER,
667 .data = &msm_uart_driver,
670 #define MSM_CONSOLE (&msm_console)
673 #define MSM_CONSOLE NULL
676 static struct uart_driver msm_uart_driver = {
677 .owner = THIS_MODULE,
678 .driver_name = "msm_serial",
679 .dev_name = "ttyMSM",
684 static int __init msm_serial_probe(struct platform_device *pdev)
686 struct msm_port *msm_port;
687 struct resource *resource;
688 struct uart_port *port;
690 if (unlikely(pdev->id < 0 || pdev->id >= UART_NR))
693 printk(KERN_INFO "msm_serial: detected port #%d\n", pdev->id);
695 port = get_port_from_line(pdev->id);
696 port->dev = &pdev->dev;
697 msm_port = UART_TO_MSM(port);
699 msm_port->clk = clk_get(&pdev->dev, "uart_clk");
700 if (unlikely(IS_ERR(msm_port->clk)))
701 return PTR_ERR(msm_port->clk);
702 port->uartclk = clk_get_rate(msm_port->clk);
704 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
705 if (unlikely(!resource))
707 port->mapbase = resource->start;
709 port->irq = platform_get_irq(pdev, 0);
710 if (unlikely(port->irq < 0))
713 platform_set_drvdata(pdev, port);
715 return uart_add_one_port(&msm_uart_driver, port);
718 static int __devexit msm_serial_remove(struct platform_device *pdev)
720 struct msm_port *msm_port = platform_get_drvdata(pdev);
722 clk_put(msm_port->clk);
727 static struct platform_driver msm_platform_driver = {
728 .probe = msm_serial_probe,
729 .remove = msm_serial_remove,
731 .name = "msm_serial",
732 .owner = THIS_MODULE,
736 static int __init msm_serial_init(void)
740 ret = uart_register_driver(&msm_uart_driver);
744 ret = platform_driver_probe(&msm_platform_driver, msm_serial_probe);
746 uart_unregister_driver(&msm_uart_driver);
748 printk(KERN_INFO "msm_serial: driver initialized\n");
753 static void __exit msm_serial_exit(void)
755 #ifdef CONFIG_SERIAL_MSM_CONSOLE
756 unregister_console(&msm_console);
758 platform_driver_unregister(&msm_platform_driver);
759 uart_unregister_driver(&msm_uart_driver);
762 module_init(msm_serial_init);
763 module_exit(msm_serial_exit);
765 MODULE_AUTHOR("Robert Love <rlove@google.com>");
766 MODULE_DESCRIPTION("Driver for msm7x serial device");
767 MODULE_LICENSE("GPL");