SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/scsi/stex.c

   1 /*
   2  * SuperTrak EX Series Storage Controller driver for Linux
   3  *
   4  *      Copyright (C) 2005-2009 Promise Technology Inc.
   5  *
   6  *      This program is free software; you can redistribute it and/or
   7  *      modify it under the terms of the GNU General Public License
   8  *      as published by the Free Software Foundation; either version
   9  *      2 of the License, or (at your option) any later version.
  10  *
  11  *      Written By:
  12  *              Ed Lin <promise_linux@promise.com>
  13  *
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/kernel.h>
  19 #include <linux/delay.h>
  20 #include <linux/time.h>
  21 #include <linux/pci.h>
  22 #include <linux/blkdev.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/types.h>
  25 #include <linux/module.h>
  26 #include <linux/spinlock.h>
  27 #include <asm/io.h>
  28 #include <asm/irq.h>
  29 #include <asm/byteorder.h>
  30 #include <scsi/scsi.h>
  31 #include <scsi/scsi_device.h>
  32 #include <scsi/scsi_cmnd.h>
  33 #include <scsi/scsi_host.h>
  34 #include <scsi/scsi_tcq.h>
  35 #include <scsi/scsi_dbg.h>
  36 #include <scsi/scsi_eh.h>
  37
  38 #define DRV_NAME "stex"
  39 #define ST_DRIVER_VERSION "4.6.0000.1"
  40 #define ST_VER_MAJOR            4
  41 #define ST_VER_MINOR            6
  42 #define ST_OEM                  0
  43 #define ST_BUILD_VER            1
  44
  45 enum {
  46         /* MU register offset */
  47         IMR0    = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
  48         IMR1    = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
  49         OMR0    = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
  50         OMR1    = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
  51         IDBL    = 0x20, /* MU_INBOUND_DOORBELL */
  52         IIS     = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
  53         IIM     = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
  54         ODBL    = 0x2c, /* MU_OUTBOUND_DOORBELL */
  55         OIS     = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
  56         OIM     = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
  57
  58         /* MU register value */
  59         MU_INBOUND_DOORBELL_HANDSHAKE           = 1,
  60         MU_INBOUND_DOORBELL_REQHEADCHANGED      = 2,
  61         MU_INBOUND_DOORBELL_STATUSTAILCHANGED   = 4,
  62         MU_INBOUND_DOORBELL_HMUSTOPPED          = 8,
  63         MU_INBOUND_DOORBELL_RESET               = 16,
  64
  65         MU_OUTBOUND_DOORBELL_HANDSHAKE          = 1,
  66         MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = 2,
  67         MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED  = 4,
  68         MU_OUTBOUND_DOORBELL_BUSCHANGE          = 8,
  69         MU_OUTBOUND_DOORBELL_HASEVENT           = 16,
  70
  71         /* MU status code */
  72         MU_STATE_STARTING                       = 1,
  73         MU_STATE_FMU_READY_FOR_HANDSHAKE        = 2,
  74         MU_STATE_SEND_HANDSHAKE_FRAME           = 3,
  75         MU_STATE_STARTED                        = 4,
  76         MU_STATE_RESETTING                      = 5,
  77
  78         MU_MAX_DELAY                            = 120,
  79         MU_HANDSHAKE_SIGNATURE                  = 0x55aaaa55,
  80         MU_HANDSHAKE_SIGNATURE_HALF             = 0x5a5a0000,
  81         MU_HARD_RESET_WAIT                      = 30000,
  82         HMU_PARTNER_TYPE                        = 2,
  83
  84         /* firmware returned values */
  85         SRB_STATUS_SUCCESS                      = 0x01,
  86         SRB_STATUS_ERROR                        = 0x04,
  87         SRB_STATUS_BUSY                         = 0x05,
  88         SRB_STATUS_INVALID_REQUEST              = 0x06,
  89         SRB_STATUS_SELECTION_TIMEOUT            = 0x0A,
  90         SRB_SEE_SENSE                           = 0x80,
  91
  92         /* task attribute */
  93         TASK_ATTRIBUTE_SIMPLE                   = 0x0,
  94         TASK_ATTRIBUTE_HEADOFQUEUE              = 0x1,
  95         TASK_ATTRIBUTE_ORDERED                  = 0x2,
  96         TASK_ATTRIBUTE_ACA                      = 0x4,
  97
  98         /* request count, etc. */
  99         MU_MAX_REQUEST                          = 32,
 100
 101         /* one message wasted, use MU_MAX_REQUEST+1
 102                 to handle MU_MAX_REQUEST messages */
 103         MU_REQ_COUNT                            = (MU_MAX_REQUEST + 1),
 104         MU_STATUS_COUNT                         = (MU_MAX_REQUEST + 1),
 105
 106         STEX_CDB_LENGTH                         = 16,
 107         REQ_VARIABLE_LEN                        = 1024,
 108         STATUS_VAR_LEN                          = 128,
 109         ST_CAN_QUEUE                            = MU_MAX_REQUEST,
 110         ST_CMD_PER_LUN                          = MU_MAX_REQUEST,
 111         ST_MAX_SG                               = 32,
 112
 113         /* sg flags */
 114         SG_CF_EOT                               = 0x80, /* end of table */
 115         SG_CF_64B                               = 0x40, /* 64 bit item */
 116         SG_CF_HOST                              = 0x20, /* sg in host memory */
 117         MSG_DATA_DIR_ND                         = 0,
 118         MSG_DATA_DIR_IN                         = 1,
 119         MSG_DATA_DIR_OUT                        = 2,
 120
 121         st_shasta                               = 0,
 122         st_vsc                                  = 1,
 123         st_vsc1                                 = 2,
 124         st_yosemite                             = 3,
 125         st_seq                                  = 4,
 126
 127         PASSTHRU_REQ_TYPE                       = 0x00000001,
 128         PASSTHRU_REQ_NO_WAKEUP                  = 0x00000100,
 129         ST_INTERNAL_TIMEOUT                     = 180,
 130
 131         ST_TO_CMD                               = 0,
 132         ST_FROM_CMD                             = 1,
 133
 134         /* vendor specific commands of Promise */
 135         MGT_CMD                                 = 0xd8,
 136         SINBAND_MGT_CMD                         = 0xd9,
 137         ARRAY_CMD                               = 0xe0,
 138         CONTROLLER_CMD                          = 0xe1,
 139         DEBUGGING_CMD                           = 0xe2,
 140         PASSTHRU_CMD                            = 0xe3,
 141
 142         PASSTHRU_GET_ADAPTER                    = 0x05,
 143         PASSTHRU_GET_DRVVER                     = 0x10,
 144
 145         CTLR_CONFIG_CMD                         = 0x03,
 146         CTLR_SHUTDOWN                           = 0x0d,
 147
 148         CTLR_POWER_STATE_CHANGE                 = 0x0e,
 149         CTLR_POWER_SAVING                       = 0x01,
 150
 151         PASSTHRU_SIGNATURE                      = 0x4e415041,
 152         MGT_CMD_SIGNATURE                       = 0xba,
 153
 154         INQUIRY_EVPD                            = 0x01,
 155
 156         ST_ADDITIONAL_MEM                       = 0x200000,
 157 };
 158
 159 struct st_sgitem {
 160         u8 ctrl;        /* SG_CF_xxx */
 161         u8 reserved[3];
 162         __le32 count;
 163         __le64 addr;
 164 };
 165
 166 struct st_sgtable {
 167         __le16 sg_count;
 168         __le16 max_sg_count;
 169         __le32 sz_in_byte;
 170 };
 171
 172 struct handshake_frame {
 173         __le64 rb_phy;          /* request payload queue physical address */
 174         __le16 req_sz;          /* size of each request payload */
 175         __le16 req_cnt;         /* count of reqs the buffer can hold */
 176         __le16 status_sz;       /* size of each status payload */
 177         __le16 status_cnt;      /* count of status the buffer can hold */
 178         __le64 hosttime;        /* seconds from Jan 1, 1970 (GMT) */
 179         u8 partner_type;        /* who sends this frame */
 180         u8 reserved0[7];
 181         __le32 partner_ver_major;
 182         __le32 partner_ver_minor;
 183         __le32 partner_ver_oem;
 184         __le32 partner_ver_build;
 185         __le32 extra_offset;    /* NEW */
 186         __le32 extra_size;      /* NEW */
 187         u32 reserved1[2];
 188 };
 189
 190 struct req_msg {
 191         __le16 tag;
 192         u8 lun;
 193         u8 target;
 194         u8 task_attr;
 195         u8 task_manage;
 196         u8 data_dir;
 197         u8 payload_sz;          /* payload size in 4-byte, not used */
 198         u8 cdb[STEX_CDB_LENGTH];
 199         u8 variable[REQ_VARIABLE_LEN];
 200 };
 201
 202 struct status_msg {
 203         __le16 tag;
 204         u8 lun;
 205         u8 target;
 206         u8 srb_status;
 207         u8 scsi_status;
 208         u8 reserved;
 209         u8 payload_sz;          /* payload size in 4-byte */
 210         u8 variable[STATUS_VAR_LEN];
 211 };
 212
 213 struct ver_info {
 214         u32 major;
 215         u32 minor;
 216         u32 oem;
 217         u32 build;
 218         u32 reserved[2];
 219 };
 220
 221 struct st_frame {
 222         u32 base[6];
 223         u32 rom_addr;
 224
 225         struct ver_info drv_ver;
 226         struct ver_info bios_ver;
 227
 228         u32 bus;
 229         u32 slot;
 230         u32 irq_level;
 231         u32 irq_vec;
 232         u32 id;
 233         u32 subid;
 234
 235         u32 dimm_size;
 236         u8 dimm_type;
 237         u8 reserved[3];
 238
 239         u32 channel;
 240         u32 reserved1;
 241 };
 242
 243 struct st_drvver {
 244         u32 major;
 245         u32 minor;
 246         u32 oem;
 247         u32 build;
 248         u32 signature[2];
 249         u8 console_id;
 250         u8 host_no;
 251         u8 reserved0[2];
 252         u32 reserved[3];
 253 };
 254
 255 #define MU_REQ_BUFFER_SIZE      (MU_REQ_COUNT * sizeof(struct req_msg))
 256 #define MU_STATUS_BUFFER_SIZE   (MU_STATUS_COUNT * sizeof(struct status_msg))
 257 #define MU_BUFFER_SIZE          (MU_REQ_BUFFER_SIZE + MU_STATUS_BUFFER_SIZE)
 258 #define STEX_EXTRA_SIZE         sizeof(struct st_frame)
 259 #define STEX_BUFFER_SIZE        (MU_BUFFER_SIZE + STEX_EXTRA_SIZE)
 260
 261 struct st_ccb {
 262         struct req_msg *req;
 263         struct scsi_cmnd *cmd;
 264
 265         void *sense_buffer;
 266         unsigned int sense_bufflen;
 267         int sg_count;
 268
 269         u32 req_type;
 270         u8 srb_status;
 271         u8 scsi_status;
 272         u8 reserved[2];
 273 };
 274
 275 struct st_hba {
 276         void __iomem *mmio_base;        /* iomapped PCI memory space */
 277         void *dma_mem;
 278         dma_addr_t dma_handle;
 279         size_t dma_size;
 280
 281         struct Scsi_Host *host;
 282         struct pci_dev *pdev;
 283
 284         u32 req_head;
 285         u32 req_tail;
 286         u32 status_head;
 287         u32 status_tail;
 288
 289         struct status_msg *status_buffer;
 290         void *copy_buffer; /* temp buffer for driver-handled commands */
 291         struct st_ccb ccb[MU_MAX_REQUEST];
 292         struct st_ccb *wait_ccb;
 293
 294         unsigned int mu_status;
 295         int out_req_cnt;
 296
 297         unsigned int cardtype;
 298 };
 299
 300 static const char console_inq_page[] =
 301 {
 302         0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
 303         0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20,        /* "Promise " */
 304         0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E,        /* "RAID Con" */
 305         0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20,        /* "sole    " */
 306         0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20,        /* "1.00    " */
 307         0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D,        /* "SX/RSAF-" */
 308         0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20,        /* "TE1.00  " */
 309         0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
 310 };
 311
 312 MODULE_AUTHOR("Ed Lin");
 313 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
 314 MODULE_LICENSE("GPL");
 315 MODULE_VERSION(ST_DRIVER_VERSION);
 316
 317 static void stex_gettime(__le64 *time)
 318 {
 319         struct timeval tv;
 320
 321         do_gettimeofday(&tv);
 322         *time = cpu_to_le64(tv.tv_sec);
 323 }
 324
 325 static struct status_msg *stex_get_status(struct st_hba *hba)
 326 {
 327         struct status_msg *status = hba->status_buffer + hba->status_tail;
 328
 329         ++hba->status_tail;
 330         hba->status_tail %= MU_STATUS_COUNT;
 331
 332         return status;
 333 }
 334
 335 static void stex_invalid_field(struct scsi_cmnd *cmd,
 336                                void (*done)(struct scsi_cmnd *))
 337 {
 338         cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
 339
 340         /* "Invalid field in cdb" */
 341         scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24,
 342                                 0x0);
 343         done(cmd);
 344 }
 345
 346 static struct req_msg *stex_alloc_req(struct st_hba *hba)
 347 {
 348         struct req_msg *req = ((struct req_msg *)hba->dma_mem) +
 349                 hba->req_head;
 350
 351         ++hba->req_head;
 352         hba->req_head %= MU_REQ_COUNT;
 353
 354         return req;
 355 }
 356
 357 static int stex_map_sg(struct st_hba *hba,
 358         struct req_msg *req, struct st_ccb *ccb)
 359 {
 360         struct scsi_cmnd *cmd;
 361         struct scatterlist *sg;
 362         struct st_sgtable *dst;
 363         struct st_sgitem *table;
 364         int i, nseg;
 365
 366         cmd = ccb->cmd;
 367         nseg = scsi_dma_map(cmd);
 368         BUG_ON(nseg < 0);
 369         if (nseg) {
 370                 dst = (struct st_sgtable *)req->variable;
 371
 372                 ccb->sg_count = nseg;
 373                 dst->sg_count = cpu_to_le16((u16)nseg);
 374                 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
 375                 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
 376
 377                 table = (struct st_sgitem *)(dst + 1);
 378                 scsi_for_each_sg(cmd, sg, nseg, i) {
 379                         table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
 380                         table[i].addr = cpu_to_le64(sg_dma_address(sg));
 381                         table[i].ctrl = SG_CF_64B | SG_CF_HOST;
 382                 }
 383                 table[--i].ctrl |= SG_CF_EOT;
 384         }
 385
 386         return nseg;
 387 }
 388
 389 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
 390 {
 391         struct st_frame *p;
 392         size_t count = sizeof(struct st_frame);
 393
 394         p = hba->copy_buffer;
 395         scsi_sg_copy_to_buffer(ccb->cmd, p, count);
 396         memset(p->base, 0, sizeof(u32)*6);
 397         *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
 398         p->rom_addr = 0;
 399
 400         p->drv_ver.major = ST_VER_MAJOR;
 401         p->drv_ver.minor = ST_VER_MINOR;
 402         p->drv_ver.oem = ST_OEM;
 403         p->drv_ver.build = ST_BUILD_VER;
 404
 405         p->bus = hba->pdev->bus->number;
 406         p->slot = hba->pdev->devfn;
 407         p->irq_level = 0;
 408         p->irq_vec = hba->pdev->irq;
 409         p->id = hba->pdev->vendor << 16 | hba->pdev->device;
 410         p->subid =
 411                 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
 412
 413         scsi_sg_copy_from_buffer(ccb->cmd, p, count);
 414 }
 415
 416 static void
 417 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 418 {
 419         req->tag = cpu_to_le16(tag);
 420
 421         hba->ccb[tag].req = req;
 422         hba->out_req_cnt++;
 423
 424         writel(hba->req_head, hba->mmio_base + IMR0);
 425         writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
 426         readl(hba->mmio_base + IDBL); /* flush */
 427 }
 428
 429 static int
 430 stex_slave_alloc(struct scsi_device *sdev)
 431 {
 432         /* Cheat: usually extracted from Inquiry data */
 433         sdev->tagged_supported = 1;
 434
 435         scsi_activate_tcq(sdev, sdev->host->can_queue);
 436
 437         return 0;
 438 }
 439
 440 static int
 441 stex_slave_config(struct scsi_device *sdev)
 442 {
 443         sdev->use_10_for_rw = 1;
 444         sdev->use_10_for_ms = 1;
 445         blk_queue_rq_timeout(sdev->request_queue, 60 * HZ);
 446         sdev->tagged_supported = 1;
 447
 448         return 0;
 449 }
 450
 451 static void
 452 stex_slave_destroy(struct scsi_device *sdev)
 453 {
 454         scsi_deactivate_tcq(sdev, 1);
 455 }
 456
 457 static int
 458 stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *))
 459 {
 460         struct st_hba *hba;
 461         struct Scsi_Host *host;
 462         unsigned int id, lun;
 463         struct req_msg *req;
 464         u16 tag;
 465
 466         host = cmd->device->host;
 467         id = cmd->device->id;
 468         lun = cmd->device->lun;
 469         hba = (struct st_hba *) &host->hostdata[0];
 470
 471         switch (cmd->cmnd[0]) {
 472         case MODE_SENSE_10:
 473         {
 474                 static char ms10_caching_page[12] =
 475                         { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
 476                 unsigned char page;
 477
 478                 page = cmd->cmnd[2] & 0x3f;
 479                 if (page == 0x8 || page == 0x3f) {
 480                         scsi_sg_copy_from_buffer(cmd, ms10_caching_page,
 481                                                  sizeof(ms10_caching_page));
 482                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 483                         done(cmd);
 484                 } else
 485                         stex_invalid_field(cmd, done);
 486                 return 0;
 487         }
 488         case REPORT_LUNS:
 489                 /*
 490                  * The shasta firmware does not report actual luns in the
 491                  * target, so fail the command to force sequential lun scan.
 492                  * Also, the console device does not support this command.
 493                  */
 494                 if (hba->cardtype == st_shasta || id == host->max_id - 1) {
 495                         stex_invalid_field(cmd, done);
 496                         return 0;
 497                 }
 498                 break;
 499         case TEST_UNIT_READY:
 500                 if (id == host->max_id - 1) {
 501                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 502                         done(cmd);
 503                         return 0;
 504                 }
 505                 break;
 506         case INQUIRY:
 507                 if (id != host->max_id - 1)
 508                         break;
 509                 if (lun == 0 && (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
 510                         scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page,
 511                                                  sizeof(console_inq_page));
 512                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 513                         done(cmd);
 514                 } else
 515                         stex_invalid_field(cmd, done);
 516                 return 0;
 517         case PASSTHRU_CMD:
 518                 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
 519                         struct st_drvver ver;
 520                         size_t cp_len = sizeof(ver);
 521
 522                         ver.major = ST_VER_MAJOR;
 523                         ver.minor = ST_VER_MINOR;
 524                         ver.oem = ST_OEM;
 525                         ver.build = ST_BUILD_VER;
 526                         ver.signature[0] = PASSTHRU_SIGNATURE;
 527                         ver.console_id = host->max_id - 1;
 528                         ver.host_no = hba->host->host_no;
 529                         cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len);
 530                         cmd->result = sizeof(ver) == cp_len ?
 531                                 DID_OK << 16 | COMMAND_COMPLETE << 8 :
 532                                 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 533                         done(cmd);
 534                         return 0;
 535                 }
 536         default:
 537                 break;
 538         }
 539
 540         cmd->scsi_done = done;
 541
 542         tag = cmd->request->tag;
 543
 544         if (unlikely(tag >= host->can_queue))
 545                 return SCSI_MLQUEUE_HOST_BUSY;
 546
 547         req = stex_alloc_req(hba);
 548
 549         req->lun = lun;
 550         req->target = id;
 551
 552         /* cdb */
 553         memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
 554
 555         if (cmd->sc_data_direction == DMA_FROM_DEVICE)
 556                 req->data_dir = MSG_DATA_DIR_IN;
 557         else if (cmd->sc_data_direction == DMA_TO_DEVICE)
 558                 req->data_dir = MSG_DATA_DIR_OUT;
 559         else
 560                 req->data_dir = MSG_DATA_DIR_ND;
 561
 562         hba->ccb[tag].cmd = cmd;
 563         hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
 564         hba->ccb[tag].sense_buffer = cmd->sense_buffer;
 565
 566         if (cmd->sc_data_direction != DMA_NONE)
 567                 stex_map_sg(hba, req, &hba->ccb[tag]);
 568
 569         stex_send_cmd(hba, req, tag);
 570         return 0;
 571 }
 572
 573 static void stex_scsi_done(struct st_ccb *ccb)
 574 {
 575         struct scsi_cmnd *cmd = ccb->cmd;
 576         int result;
 577
 578         if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
 579                 result = ccb->scsi_status;
 580                 switch (ccb->scsi_status) {
 581                 case SAM_STAT_GOOD:
 582                         result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
 583                         break;
 584                 case SAM_STAT_CHECK_CONDITION:
 585                         result |= DRIVER_SENSE << 24;
 586                         break;
 587                 case SAM_STAT_BUSY:
 588                         result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 589                         break;
 590                 default:
 591                         result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 592                         break;
 593                 }
 594         }
 595         else if (ccb->srb_status & SRB_SEE_SENSE)
 596                 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
 597         else switch (ccb->srb_status) {
 598                 case SRB_STATUS_SELECTION_TIMEOUT:
 599                         result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
 600                         break;
 601                 case SRB_STATUS_BUSY:
 602                         result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 603                         break;
 604                 case SRB_STATUS_INVALID_REQUEST:
 605                 case SRB_STATUS_ERROR:
 606                 default:
 607                         result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 608                         break;
 609         }
 610
 611         cmd->result = result;
 612         cmd->scsi_done(cmd);
 613 }
 614
 615 static void stex_copy_data(struct st_ccb *ccb,
 616         struct status_msg *resp, unsigned int variable)
 617 {
 618         if (resp->scsi_status != SAM_STAT_GOOD) {
 619                 if (ccb->sense_buffer != NULL)
 620                         memcpy(ccb->sense_buffer, resp->variable,
 621                                 min(variable, ccb->sense_bufflen));
 622                 return;
 623         }
 624
 625         if (ccb->cmd == NULL)
 626                 return;
 627         scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable);
 628 }
 629
 630 static void stex_check_cmd(struct st_hba *hba,
 631         struct st_ccb *ccb, struct status_msg *resp)
 632 {
 633         if (ccb->cmd->cmnd[0] == MGT_CMD &&
 634                 resp->scsi_status != SAM_STAT_CHECK_CONDITION)
 635                 scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
 636                         le32_to_cpu(*(__le32 *)&resp->variable[0]));
 637 }
 638
 639 static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
 640 {
 641         void __iomem *base = hba->mmio_base;
 642         struct status_msg *resp;
 643         struct st_ccb *ccb;
 644         unsigned int size;
 645         u16 tag;
 646
 647         if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED)))
 648                 return;
 649
 650         /* status payloads */
 651         hba->status_head = readl(base + OMR1);
 652         if (unlikely(hba->status_head >= MU_STATUS_COUNT)) {
 653                 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
 654                         pci_name(hba->pdev));
 655                 return;
 656         }
 657
 658         /*
 659          * it's not a valid status payload if:
 660          * 1. there are no pending requests(e.g. during init stage)
 661          * 2. there are some pending requests, but the controller is in
 662          *     reset status, and its type is not st_yosemite
 663          * firmware of st_yosemite in reset status will return pending requests
 664          * to driver, so we allow it to pass
 665          */
 666         if (unlikely(hba->out_req_cnt <= 0 ||
 667                         (hba->mu_status == MU_STATE_RESETTING &&
 668                          hba->cardtype != st_yosemite))) {
 669                 hba->status_tail = hba->status_head;
 670                 goto update_status;
 671         }
 672
 673         while (hba->status_tail != hba->status_head) {
 674                 resp = stex_get_status(hba);
 675                 tag = le16_to_cpu(resp->tag);
 676                 if (unlikely(tag >= hba->host->can_queue)) {
 677                         printk(KERN_WARNING DRV_NAME
 678                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 679                         continue;
 680                 }
 681
 682                 hba->out_req_cnt--;
 683                 ccb = &hba->ccb[tag];
 684                 if (unlikely(hba->wait_ccb == ccb))
 685                         hba->wait_ccb = NULL;
 686                 if (unlikely(ccb->req == NULL)) {
 687                         printk(KERN_WARNING DRV_NAME
 688                                 "(%s): lagging req\n", pci_name(hba->pdev));
 689                         continue;
 690                 }
 691
 692                 size = resp->payload_sz * sizeof(u32); /* payload size */
 693                 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 694                         size > sizeof(*resp))) {
 695                         printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
 696                                 pci_name(hba->pdev));
 697                 } else {
 698                         size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
 699                         if (size)
 700                                 stex_copy_data(ccb, resp, size);
 701                 }
 702
 703                 ccb->req = NULL;
 704                 ccb->srb_status = resp->srb_status;
 705                 ccb->scsi_status = resp->scsi_status;
 706
 707                 if (likely(ccb->cmd != NULL)) {
 708                         if (hba->cardtype == st_yosemite)
 709                                 stex_check_cmd(hba, ccb, resp);
 710
 711                         if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
 712                                 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
 713                                 stex_controller_info(hba, ccb);
 714
 715                         scsi_dma_unmap(ccb->cmd);
 716                         stex_scsi_done(ccb);
 717                 } else
 718                         ccb->req_type = 0;
 719         }
 720
 721 update_status:
 722         writel(hba->status_head, base + IMR1);
 723         readl(base + IMR1); /* flush */
 724 }
 725
 726 static irqreturn_t stex_intr(int irq, void *__hba)
 727 {
 728         struct st_hba *hba = __hba;
 729         void __iomem *base = hba->mmio_base;
 730         u32 data;
 731         unsigned long flags;
 732         int handled = 0;
 733
 734         spin_lock_irqsave(hba->host->host_lock, flags);
 735
 736         data = readl(base + ODBL);
 737
 738         if (data && data != 0xffffffff) {
 739                 /* clear the interrupt */
 740                 writel(data, base + ODBL);
 741                 readl(base + ODBL); /* flush */
 742                 stex_mu_intr(hba, data);
 743                 handled = 1;
 744         }
 745
 746         spin_unlock_irqrestore(hba->host->host_lock, flags);
 747
 748         return IRQ_RETVAL(handled);
 749 }
 750
 751 static int stex_handshake(struct st_hba *hba)
 752 {
 753         void __iomem *base = hba->mmio_base;
 754         struct handshake_frame *h;
 755         dma_addr_t status_phys;
 756         u32 data;
 757         unsigned long before;
 758
 759         if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 760                 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
 761                 readl(base + IDBL);
 762                 before = jiffies;
 763                 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 764                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
 765                                 printk(KERN_ERR DRV_NAME
 766                                         "(%s): no handshake signature\n",
 767                                         pci_name(hba->pdev));
 768                                 return -1;
 769                         }
 770                         rmb();
 771                         msleep(1);
 772                 }
 773         }
 774
 775         udelay(10);
 776
 777         data = readl(base + OMR1);
 778         if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
 779                 data &= 0x0000ffff;
 780                 if (hba->host->can_queue > data) {
 781                         hba->host->can_queue = data;
 782                         hba->host->cmd_per_lun = data;
 783                 }
 784         }
 785
 786         h = (struct handshake_frame *)hba->status_buffer;
 787         h->rb_phy = cpu_to_le64(hba->dma_handle);
 788         h->req_sz = cpu_to_le16(sizeof(struct req_msg));
 789         h->req_cnt = cpu_to_le16(MU_REQ_COUNT);
 790         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
 791         h->status_cnt = cpu_to_le16(MU_STATUS_COUNT);
 792         stex_gettime(&h->hosttime);
 793         h->partner_type = HMU_PARTNER_TYPE;
 794         if (hba->dma_size > STEX_BUFFER_SIZE) {
 795                 h->extra_offset = cpu_to_le32(STEX_BUFFER_SIZE);
 796                 h->extra_size = cpu_to_le32(ST_ADDITIONAL_MEM);
 797         } else
 798                 h->extra_offset = h->extra_size = 0;
 799
 800         status_phys = hba->dma_handle + MU_REQ_BUFFER_SIZE;
 801         writel(status_phys, base + IMR0);
 802         readl(base + IMR0);
 803         writel((status_phys >> 16) >> 16, base + IMR1);
 804         readl(base + IMR1);
 805
 806         writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
 807         readl(base + OMR0);
 808         writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
 809         readl(base + IDBL); /* flush */
 810
 811         udelay(10);
 812         before = jiffies;
 813         while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 814                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
 815                         printk(KERN_ERR DRV_NAME
 816                                 "(%s): no signature after handshake frame\n",
 817                                 pci_name(hba->pdev));
 818                         return -1;
 819                 }
 820                 rmb();
 821                 msleep(1);
 822         }
 823
 824         writel(0, base + IMR0);
 825         readl(base + IMR0);
 826         writel(0, base + OMR0);
 827         readl(base + OMR0);
 828         writel(0, base + IMR1);
 829         readl(base + IMR1);
 830         writel(0, base + OMR1);
 831         readl(base + OMR1); /* flush */
 832         hba->mu_status = MU_STATE_STARTED;
 833         return 0;
 834 }
 835
 836 static int stex_abort(struct scsi_cmnd *cmd)
 837 {
 838         struct Scsi_Host *host = cmd->device->host;
 839         struct st_hba *hba = (struct st_hba *)host->hostdata;
 840         u16 tag = cmd->request->tag;
 841         void __iomem *base;
 842         u32 data;
 843         int result = SUCCESS;
 844         unsigned long flags;
 845
 846         printk(KERN_INFO DRV_NAME
 847                 "(%s): aborting command\n", pci_name(hba->pdev));
 848         scsi_print_command(cmd);
 849
 850         base = hba->mmio_base;
 851         spin_lock_irqsave(host->host_lock, flags);
 852         if (tag < host->can_queue && hba->ccb[tag].cmd == cmd)
 853                 hba->wait_ccb = &hba->ccb[tag];
 854         else {
 855                 for (tag = 0; tag < host->can_queue; tag++)
 856                         if (hba->ccb[tag].cmd == cmd) {
 857                                 hba->wait_ccb = &hba->ccb[tag];
 858                                 break;
 859                         }
 860                 if (tag >= host->can_queue)
 861                         goto out;
 862         }
 863
 864         data = readl(base + ODBL);
 865         if (data == 0 || data == 0xffffffff)
 866                 goto fail_out;
 867
 868         writel(data, base + ODBL);
 869         readl(base + ODBL); /* flush */
 870
 871         stex_mu_intr(hba, data);
 872
 873         if (hba->wait_ccb == NULL) {
 874                 printk(KERN_WARNING DRV_NAME
 875                         "(%s): lost interrupt\n", pci_name(hba->pdev));
 876                 goto out;
 877         }
 878
 879 fail_out:
 880         scsi_dma_unmap(cmd);
 881         hba->wait_ccb->req = NULL; /* nullify the req's future return */
 882         hba->wait_ccb = NULL;
 883         result = FAILED;
 884 out:
 885         spin_unlock_irqrestore(host->host_lock, flags);
 886         return result;
 887 }
 888
 889 static void stex_hard_reset(struct st_hba *hba)
 890 {
 891         struct pci_bus *bus;
 892         int i;
 893         u16 pci_cmd;
 894         u8 pci_bctl;
 895
 896         for (i = 0; i < 16; i++)
 897                 pci_read_config_dword(hba->pdev, i * 4,
 898                         &hba->pdev->saved_config_space[i]);
 899
 900         /* Reset secondary bus. Our controller(MU/ATU) is the only device on
 901            secondary bus. Consult Intel 80331/3 developer's manual for detail */
 902         bus = hba->pdev->bus;
 903         pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
 904         pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
 905         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
 906
 907         /*
 908          * 1 ms may be enough for 8-port controllers. But 16-port controllers
 909          * require more time to finish bus reset. Use 100 ms here for safety
 910          */
 911         msleep(100);
 912         pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
 913         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
 914
 915         for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
 916                 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
 917                 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
 918                         break;
 919                 msleep(1);
 920         }
 921
 922         ssleep(5);
 923         for (i = 0; i < 16; i++)
 924                 pci_write_config_dword(hba->pdev, i * 4,
 925                         hba->pdev->saved_config_space[i]);
 926 }
 927
 928 static int stex_reset(struct scsi_cmnd *cmd)
 929 {
 930         struct st_hba *hba;
 931         void __iomem *base;
 932         unsigned long flags, before;
 933
 934         hba = (struct st_hba *) &cmd->device->host->hostdata[0];
 935
 936         printk(KERN_INFO DRV_NAME
 937                 "(%s): resetting host\n", pci_name(hba->pdev));
 938         scsi_print_command(cmd);
 939
 940         hba->mu_status = MU_STATE_RESETTING;
 941
 942         if (hba->cardtype == st_shasta)
 943                 stex_hard_reset(hba);
 944
 945         if (hba->cardtype != st_yosemite) {
 946                 if (stex_handshake(hba)) {
 947                         printk(KERN_WARNING DRV_NAME
 948                                 "(%s): resetting: handshake failed\n",
 949                                 pci_name(hba->pdev));
 950                         return FAILED;
 951                 }
 952                 spin_lock_irqsave(hba->host->host_lock, flags);
 953                 hba->req_head = 0;
 954                 hba->req_tail = 0;
 955                 hba->status_head = 0;
 956                 hba->status_tail = 0;
 957                 hba->out_req_cnt = 0;
 958                 spin_unlock_irqrestore(hba->host->host_lock, flags);
 959                 return SUCCESS;
 960         }
 961
 962         /* st_yosemite */
 963         writel(MU_INBOUND_DOORBELL_RESET, hba->mmio_base + IDBL);
 964         readl(hba->mmio_base + IDBL); /* flush */
 965         before = jiffies;
 966         while (hba->out_req_cnt > 0) {
 967                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
 968                         printk(KERN_WARNING DRV_NAME
 969                                 "(%s): reset timeout\n", pci_name(hba->pdev));
 970                         return FAILED;
 971                 }
 972                 msleep(1);
 973         }
 974
 975         base = hba->mmio_base;
 976         writel(0, base + IMR0);
 977         readl(base + IMR0);
 978         writel(0, base + OMR0);
 979         readl(base + OMR0);
 980         writel(0, base + IMR1);
 981         readl(base + IMR1);
 982         writel(0, base + OMR1);
 983         readl(base + OMR1); /* flush */
 984         spin_lock_irqsave(hba->host->host_lock, flags);
 985         hba->req_head = 0;
 986         hba->req_tail = 0;
 987         hba->status_head = 0;
 988         hba->status_tail = 0;
 989         hba->out_req_cnt = 0;
 990         hba->mu_status = MU_STATE_STARTED;
 991         spin_unlock_irqrestore(hba->host->host_lock, flags);
 992         return SUCCESS;
 993 }
 994
 995 static int stex_biosparam(struct scsi_device *sdev,
 996         struct block_device *bdev, sector_t capacity, int geom[])
 997 {
 998         int heads = 255, sectors = 63;
 999
1000         if (capacity < 0x200000) {
1001                 heads = 64;
1002                 sectors = 32;
1003         }
1004
1005         sector_div(capacity, heads * sectors);
1006
1007         geom[0] = heads;
1008         geom[1] = sectors;
1009         geom[2] = capacity;
1010
1011         return 0;
1012 }
1013
1014 static struct scsi_host_template driver_template = {
1015         .module                         = THIS_MODULE,
1016         .name                           = DRV_NAME,
1017         .proc_name                      = DRV_NAME,
1018         .bios_param                     = stex_biosparam,
1019         .queuecommand                   = stex_queuecommand,
1020         .slave_alloc                    = stex_slave_alloc,
1021         .slave_configure                = stex_slave_config,
1022         .slave_destroy                  = stex_slave_destroy,
1023         .eh_abort_handler               = stex_abort,
1024         .eh_host_reset_handler          = stex_reset,
1025         .can_queue                      = ST_CAN_QUEUE,
1026         .this_id                        = -1,
1027         .sg_tablesize                   = ST_MAX_SG,
1028         .cmd_per_lun                    = ST_CMD_PER_LUN,
1029 };
1030
1031 static int stex_set_dma_mask(struct pci_dev * pdev)
1032 {
1033         int ret;
1034
1035         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)
1036                 && !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
1037                 return 0;
1038         ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1039         if (!ret)
1040                 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1041         return ret;
1042 }
1043
1044 static int __devinit
1045 stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1046 {
1047         struct st_hba *hba;
1048         struct Scsi_Host *host;
1049         int err;
1050
1051         err = pci_enable_device(pdev);
1052         if (err)
1053                 return err;
1054
1055         pci_set_master(pdev);
1056
1057         host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1058
1059         if (!host) {
1060                 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1061                         pci_name(pdev));
1062                 err = -ENOMEM;
1063                 goto out_disable;
1064         }
1065
1066         hba = (struct st_hba *)host->hostdata;
1067         memset(hba, 0, sizeof(struct st_hba));
1068
1069         err = pci_request_regions(pdev, DRV_NAME);
1070         if (err < 0) {
1071                 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1072                         pci_name(pdev));
1073                 goto out_scsi_host_put;
1074         }
1075
1076         hba->mmio_base = pci_ioremap_bar(pdev, 0);
1077         if ( !hba->mmio_base) {
1078                 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1079                         pci_name(pdev));
1080                 err = -ENOMEM;
1081                 goto out_release_regions;
1082         }
1083
1084         err = stex_set_dma_mask(pdev);
1085         if (err) {
1086                 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1087                         pci_name(pdev));
1088                 goto out_iounmap;
1089         }
1090
1091         hba->cardtype = (unsigned int) id->driver_data;
1092         if (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))
1093                 hba->cardtype = st_vsc1;
1094         hba->dma_size = (hba->cardtype == st_vsc1 || hba->cardtype == st_seq) ?
1095                 (STEX_BUFFER_SIZE + ST_ADDITIONAL_MEM) : (STEX_BUFFER_SIZE);
1096         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1097                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1098         if (!hba->dma_mem) {
1099                 err = -ENOMEM;
1100                 printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1101                         pci_name(pdev));
1102                 goto out_iounmap;
1103         }
1104
1105         hba->status_buffer =
1106                 (struct status_msg *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
1107         hba->copy_buffer = hba->dma_mem + MU_BUFFER_SIZE;
1108         hba->mu_status = MU_STATE_STARTING;
1109
1110         if (hba->cardtype == st_shasta) {
1111                 host->max_lun = 8;
1112                 host->max_id = 16 + 1;
1113         } else if (hba->cardtype == st_yosemite) {
1114                 host->max_lun = 256;
1115                 host->max_id = 1 + 1;
1116         } else {
1117                 /* st_vsc , st_vsc1 and st_seq */
1118                 host->max_lun = 1;
1119                 host->max_id = 128 + 1;
1120         }
1121         host->max_channel = 0;
1122         host->unique_id = host->host_no;
1123         host->max_cmd_len = STEX_CDB_LENGTH;
1124
1125         hba->host = host;
1126         hba->pdev = pdev;
1127
1128         err = request_irq(pdev->irq, stex_intr, IRQF_SHARED, DRV_NAME, hba);
1129         if (err) {
1130                 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1131                         pci_name(pdev));
1132                 goto out_pci_free;
1133         }
1134
1135         err = stex_handshake(hba);
1136         if (err)
1137                 goto out_free_irq;
1138
1139         err = scsi_init_shared_tag_map(host, host->can_queue);
1140         if (err) {
1141                 printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
1142                         pci_name(pdev));
1143                 goto out_free_irq;
1144         }
1145
1146         pci_set_drvdata(pdev, hba);
1147
1148         err = scsi_add_host(host, &pdev->dev);
1149         if (err) {
1150                 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1151                         pci_name(pdev));
1152                 goto out_free_irq;
1153         }
1154
1155         scsi_scan_host(host);
1156
1157         return 0;
1158
1159 out_free_irq:
1160         free_irq(pdev->irq, hba);
1161 out_pci_free:
1162         dma_free_coherent(&pdev->dev, hba->dma_size,
1163                           hba->dma_mem, hba->dma_handle);
1164 out_iounmap:
1165         iounmap(hba->mmio_base);
1166 out_release_regions:
1167         pci_release_regions(pdev);
1168 out_scsi_host_put:
1169         scsi_host_put(host);
1170 out_disable:
1171         pci_disable_device(pdev);
1172
1173         return err;
1174 }
1175
1176 static void stex_hba_stop(struct st_hba *hba)
1177 {
1178         struct req_msg *req;
1179         unsigned long flags;
1180         unsigned long before;
1181         u16 tag = 0;
1182
1183         spin_lock_irqsave(hba->host->host_lock, flags);
1184         req = stex_alloc_req(hba);
1185         memset(req->cdb, 0, STEX_CDB_LENGTH);
1186
1187         if (hba->cardtype == st_yosemite) {
1188                 req->cdb[0] = MGT_CMD;
1189                 req->cdb[1] = MGT_CMD_SIGNATURE;
1190                 req->cdb[2] = CTLR_CONFIG_CMD;
1191                 req->cdb[3] = CTLR_SHUTDOWN;
1192         } else {
1193                 req->cdb[0] = CONTROLLER_CMD;
1194                 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1195                 req->cdb[2] = CTLR_POWER_SAVING;
1196         }
1197
1198         hba->ccb[tag].cmd = NULL;
1199         hba->ccb[tag].sg_count = 0;
1200         hba->ccb[tag].sense_bufflen = 0;
1201         hba->ccb[tag].sense_buffer = NULL;
1202         hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE;
1203
1204         stex_send_cmd(hba, req, tag);
1205         spin_unlock_irqrestore(hba->host->host_lock, flags);
1206
1207         before = jiffies;
1208         while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1209                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1210                         hba->ccb[tag].req_type = 0;
1211                         return;
1212                 }
1213                 msleep(1);
1214         }
1215 }
1216
1217 static void stex_hba_free(struct st_hba *hba)
1218 {
1219         free_irq(hba->pdev->irq, hba);
1220
1221         iounmap(hba->mmio_base);
1222
1223         pci_release_regions(hba->pdev);
1224
1225         dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1226                           hba->dma_mem, hba->dma_handle);
1227 }
1228
1229 static void stex_remove(struct pci_dev *pdev)
1230 {
1231         struct st_hba *hba = pci_get_drvdata(pdev);
1232
1233         scsi_remove_host(hba->host);
1234
1235         pci_set_drvdata(pdev, NULL);
1236
1237         stex_hba_stop(hba);
1238
1239         stex_hba_free(hba);
1240
1241         scsi_host_put(hba->host);
1242
1243         pci_disable_device(pdev);
1244 }
1245
1246 static void stex_shutdown(struct pci_dev *pdev)
1247 {
1248         struct st_hba *hba = pci_get_drvdata(pdev);
1249
1250         stex_hba_stop(hba);
1251 }
1252
1253 static struct pci_device_id stex_pci_tbl[] = {
1254         /* st_shasta */
1255         { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1256                 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1257         { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1258                 st_shasta }, /* SuperTrak EX12350 */
1259         { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1260                 st_shasta }, /* SuperTrak EX4350 */
1261         { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1262                 st_shasta }, /* SuperTrak EX24350 */
1263
1264         /* st_vsc */
1265         { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1266
1267         /* st_yosemite */
1268         { 0x105a, 0x8650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yosemite },
1269
1270         /* st_seq */
1271         { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq },
1272         { }     /* terminate list */
1273 };
1274 MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1275
1276 static struct pci_driver stex_pci_driver = {
1277         .name           = DRV_NAME,
1278         .id_table       = stex_pci_tbl,
1279         .probe          = stex_probe,
1280         .remove         = __devexit_p(stex_remove),
1281         .shutdown       = stex_shutdown,
1282 };
1283
1284 static int __init stex_init(void)
1285 {
1286         printk(KERN_INFO DRV_NAME
1287                 ": Promise SuperTrak EX Driver version: %s\n",
1288                  ST_DRIVER_VERSION);
1289
1290         return pci_register_driver(&stex_pci_driver);
1291 }
1292
1293 static void __exit stex_exit(void)
1294 {
1295         pci_unregister_driver(&stex_pci_driver);
1296 }
1297
1298 module_init(stex_init);
1299 module_exit(stex_exit);