SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/scsi/stex.c

   1 /*
   2  * SuperTrak EX Series Storage Controller driver for Linux
   3  *
   4  *      Copyright (C) 2005, 2006 Promise Technology Inc.
   5  *
   6  *      This program is free software; you can redistribute it and/or
   7  *      modify it under the terms of the GNU General Public License
   8  *      as published by the Free Software Foundation; either version
   9  *      2 of the License, or (at your option) any later version.
  10  *
  11  *      Written By:
  12  *              Ed Lin <promise_linux@promise.com>
  13  *
  14  *      Version: 2.9.0.13
  15  *
  16  */
  17
  18 #include <linux/init.h>
  19 #include <linux/errno.h>
  20 #include <linux/kernel.h>
  21 #include <linux/delay.h>
  22 #include <linux/sched.h>
  23 #include <linux/time.h>
  24 #include <linux/pci.h>
  25 #include <linux/blkdev.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/types.h>
  28 #include <linux/module.h>
  29 #include <linux/spinlock.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/byteorder.h>
  33 #include <scsi/scsi.h>
  34 #include <scsi/scsi_device.h>
  35 #include <scsi/scsi_cmnd.h>
  36 #include <scsi/scsi_host.h>
  37 #include <scsi/scsi_tcq.h>
  38
  39 #define DRV_NAME "stex"
  40 #define ST_DRIVER_VERSION "2.9.0.13"
  41 #define ST_VER_MAJOR            2
  42 #define ST_VER_MINOR            9
  43 #define ST_OEM                  0
  44 #define ST_BUILD_VER            13
  45
  46 enum {
  47         /* MU register offset */
  48         IMR0    = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
  49         IMR1    = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
  50         OMR0    = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
  51         OMR1    = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
  52         IDBL    = 0x20, /* MU_INBOUND_DOORBELL */
  53         IIS     = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
  54         IIM     = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
  55         ODBL    = 0x2c, /* MU_OUTBOUND_DOORBELL */
  56         OIS     = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
  57         OIM     = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
  58
  59         /* MU register value */
  60         MU_INBOUND_DOORBELL_HANDSHAKE           = 1,
  61         MU_INBOUND_DOORBELL_REQHEADCHANGED      = 2,
  62         MU_INBOUND_DOORBELL_STATUSTAILCHANGED   = 4,
  63         MU_INBOUND_DOORBELL_HMUSTOPPED          = 8,
  64         MU_INBOUND_DOORBELL_RESET               = 16,
  65
  66         MU_OUTBOUND_DOORBELL_HANDSHAKE          = 1,
  67         MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = 2,
  68         MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED  = 4,
  69         MU_OUTBOUND_DOORBELL_BUSCHANGE          = 8,
  70         MU_OUTBOUND_DOORBELL_HASEVENT           = 16,
  71
  72         /* MU status code */
  73         MU_STATE_STARTING                       = 1,
  74         MU_STATE_FMU_READY_FOR_HANDSHAKE        = 2,
  75         MU_STATE_SEND_HANDSHAKE_FRAME           = 3,
  76         MU_STATE_STARTED                        = 4,
  77         MU_STATE_RESETTING                      = 5,
  78
  79         MU_MAX_DELAY_TIME                       = 240000,
  80         MU_HANDSHAKE_SIGNATURE                  = 0x55aaaa55,
  81         HMU_PARTNER_TYPE                        = 2,
  82
  83         /* firmware returned values */
  84         SRB_STATUS_SUCCESS                      = 0x01,
  85         SRB_STATUS_ERROR                        = 0x04,
  86         SRB_STATUS_BUSY                         = 0x05,
  87         SRB_STATUS_INVALID_REQUEST              = 0x06,
  88         SRB_STATUS_SELECTION_TIMEOUT            = 0x0A,
  89         SRB_SEE_SENSE                           = 0x80,
  90
  91         /* task attribute */
  92         TASK_ATTRIBUTE_SIMPLE                   = 0x0,
  93         TASK_ATTRIBUTE_HEADOFQUEUE              = 0x1,
  94         TASK_ATTRIBUTE_ORDERED                  = 0x2,
  95         TASK_ATTRIBUTE_ACA                      = 0x4,
  96
  97         /* request count, etc. */
  98         MU_MAX_REQUEST                          = 32,
  99
 100         /* one message wasted, use MU_MAX_REQUEST+1
 101                 to handle MU_MAX_REQUEST messages */
 102         MU_REQ_COUNT                            = (MU_MAX_REQUEST + 1),
 103         MU_STATUS_COUNT                         = (MU_MAX_REQUEST + 1),
 104
 105         STEX_CDB_LENGTH                         = MAX_COMMAND_SIZE,
 106         REQ_VARIABLE_LEN                        = 1024,
 107         STATUS_VAR_LEN                          = 128,
 108         ST_CAN_QUEUE                            = MU_MAX_REQUEST,
 109         ST_CMD_PER_LUN                          = MU_MAX_REQUEST,
 110         ST_MAX_SG                               = 32,
 111
 112         /* sg flags */
 113         SG_CF_EOT                               = 0x80, /* end of table */
 114         SG_CF_64B                               = 0x40, /* 64 bit item */
 115         SG_CF_HOST                              = 0x20, /* sg in host memory */
 116
 117         ST_MAX_ARRAY_SUPPORTED                  = 16,
 118         ST_MAX_TARGET_NUM                       = (ST_MAX_ARRAY_SUPPORTED+1),
 119         ST_MAX_LUN_PER_TARGET                   = 16,
 120
 121         st_shasta                               = 0,
 122         st_vsc                                  = 1,
 123
 124         PASSTHRU_REQ_TYPE                       = 0x00000001,
 125         PASSTHRU_REQ_NO_WAKEUP                  = 0x00000100,
 126         ST_INTERNAL_TIMEOUT                     = 30,
 127
 128         /* vendor specific commands of Promise */
 129         ARRAY_CMD                               = 0xe0,
 130         CONTROLLER_CMD                          = 0xe1,
 131         DEBUGGING_CMD                           = 0xe2,
 132         PASSTHRU_CMD                            = 0xe3,
 133
 134         PASSTHRU_GET_ADAPTER                    = 0x05,
 135         PASSTHRU_GET_DRVVER                     = 0x10,
 136         CTLR_POWER_STATE_CHANGE                 = 0x0e,
 137         CTLR_POWER_SAVING                       = 0x01,
 138
 139         PASSTHRU_SIGNATURE                      = 0x4e415041,
 140
 141         INQUIRY_EVPD                            = 0x01,
 142 };
 143
 144 struct st_sgitem {
 145         u8 ctrl;        /* SG_CF_xxx */
 146         u8 reserved[3];
 147         __le32 count;
 148         __le32 addr;
 149         __le32 addr_hi;
 150 };
 151
 152 struct st_sgtable {
 153         __le16 sg_count;
 154         __le16 max_sg_count;
 155         __le32 sz_in_byte;
 156         struct st_sgitem table[ST_MAX_SG];
 157 };
 158
 159 struct handshake_frame {
 160         __le32 rb_phy;          /* request payload queue physical address */
 161         __le32 rb_phy_hi;
 162         __le16 req_sz;          /* size of each request payload */
 163         __le16 req_cnt;         /* count of reqs the buffer can hold */
 164         __le16 status_sz;       /* size of each status payload */
 165         __le16 status_cnt;      /* count of status the buffer can hold */
 166         __le32 hosttime;        /* seconds from Jan 1, 1970 (GMT) */
 167         __le32 hosttime_hi;
 168         u8 partner_type;        /* who sends this frame */
 169         u8 reserved0[7];
 170         __le32 partner_ver_major;
 171         __le32 partner_ver_minor;
 172         __le32 partner_ver_oem;
 173         __le32 partner_ver_build;
 174         u32 reserved1[4];
 175 };
 176
 177 struct req_msg {
 178         __le16 tag;
 179         u8 lun;
 180         u8 target;
 181         u8 task_attr;
 182         u8 task_manage;
 183         u8 prd_entry;
 184         u8 payload_sz;          /* payload size in 4-byte, not used */
 185         u8 cdb[STEX_CDB_LENGTH];
 186         u8 variable[REQ_VARIABLE_LEN];
 187 };
 188
 189 struct status_msg {
 190         __le16 tag;
 191         u8 lun;
 192         u8 target;
 193         u8 srb_status;
 194         u8 scsi_status;
 195         u8 reserved;
 196         u8 payload_sz;          /* payload size in 4-byte */
 197         u8 variable[STATUS_VAR_LEN];
 198 };
 199
 200 struct ver_info {
 201         u32 major;
 202         u32 minor;
 203         u32 oem;
 204         u32 build;
 205         u32 reserved[2];
 206 };
 207
 208 struct st_frame {
 209         u32 base[6];
 210         u32 rom_addr;
 211
 212         struct ver_info drv_ver;
 213         struct ver_info bios_ver;
 214
 215         u32 bus;
 216         u32 slot;
 217         u32 irq_level;
 218         u32 irq_vec;
 219         u32 id;
 220         u32 subid;
 221
 222         u32 dimm_size;
 223         u8 dimm_type;
 224         u8 reserved[3];
 225
 226         u32 channel;
 227         u32 reserved1;
 228 };
 229
 230 struct st_drvver {
 231         u32 major;
 232         u32 minor;
 233         u32 oem;
 234         u32 build;
 235         u32 signature[2];
 236         u8 console_id;
 237         u8 host_no;
 238         u8 reserved0[2];
 239         u32 reserved[3];
 240 };
 241
 242 #define MU_REQ_BUFFER_SIZE      (MU_REQ_COUNT * sizeof(struct req_msg))
 243 #define MU_STATUS_BUFFER_SIZE   (MU_STATUS_COUNT * sizeof(struct status_msg))
 244 #define MU_BUFFER_SIZE          (MU_REQ_BUFFER_SIZE + MU_STATUS_BUFFER_SIZE)
 245 #define STEX_BUFFER_SIZE        (MU_BUFFER_SIZE + sizeof(struct st_frame))
 246
 247 struct st_ccb {
 248         struct req_msg *req;
 249         struct scsi_cmnd *cmd;
 250
 251         void *sense_buffer;
 252         unsigned int sense_bufflen;
 253         int sg_count;
 254
 255         u32 req_type;
 256         u8 srb_status;
 257         u8 scsi_status;
 258 };
 259
 260 struct st_hba {
 261         void __iomem *mmio_base;        /* iomapped PCI memory space */
 262         void *dma_mem;
 263         dma_addr_t dma_handle;
 264
 265         struct Scsi_Host *host;
 266         struct pci_dev *pdev;
 267
 268         u32 req_head;
 269         u32 req_tail;
 270         u32 status_head;
 271         u32 status_tail;
 272
 273         struct status_msg *status_buffer;
 274         void *copy_buffer; /* temp buffer for driver-handled commands */
 275         struct st_ccb ccb[MU_MAX_REQUEST];
 276         struct st_ccb *wait_ccb;
 277         wait_queue_head_t waitq;
 278
 279         unsigned int mu_status;
 280         int out_req_cnt;
 281
 282         unsigned int cardtype;
 283 };
 284
 285 static const char console_inq_page[] =
 286 {
 287         0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
 288         0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20,        /* "Promise " */
 289         0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E,        /* "RAID Con" */
 290         0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20,        /* "sole    " */
 291         0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20,        /* "1.00    " */
 292         0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D,        /* "SX/RSAF-" */
 293         0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20,        /* "TE1.00  " */
 294         0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
 295 };
 296
 297 MODULE_AUTHOR("Ed Lin");
 298 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
 299 MODULE_LICENSE("GPL");
 300 MODULE_VERSION(ST_DRIVER_VERSION);
 301
 302 static void stex_gettime(__le32 *time)
 303 {
 304         struct timeval tv;
 305         do_gettimeofday(&tv);
 306
 307         *time = cpu_to_le32(tv.tv_sec & 0xffffffff);
 308         *(time + 1) = cpu_to_le32((tv.tv_sec >> 16) >> 16);
 309 }
 310
 311 static struct status_msg *stex_get_status(struct st_hba *hba)
 312 {
 313         struct status_msg *status =
 314                 hba->status_buffer + hba->status_tail;
 315
 316         ++hba->status_tail;
 317         hba->status_tail %= MU_STATUS_COUNT;
 318
 319         return status;
 320 }
 321
 322 static void stex_set_sense(struct scsi_cmnd *cmd, u8 sk, u8 asc, u8 ascq)
 323 {
 324         cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
 325
 326         cmd->sense_buffer[0] = 0x70;    /* fixed format, current */
 327         cmd->sense_buffer[2] = sk;
 328         cmd->sense_buffer[7] = 18 - 8;  /* additional sense length */
 329         cmd->sense_buffer[12] = asc;
 330         cmd->sense_buffer[13] = ascq;
 331 }
 332
 333 static void stex_invalid_field(struct scsi_cmnd *cmd,
 334                                void (*done)(struct scsi_cmnd *))
 335 {
 336         /* "Invalid field in cbd" */
 337         stex_set_sense(cmd, ILLEGAL_REQUEST, 0x24, 0x0);
 338         done(cmd);
 339 }
 340
 341 static struct req_msg *stex_alloc_req(struct st_hba *hba)
 342 {
 343         struct req_msg *req = ((struct req_msg *)hba->dma_mem) +
 344                 hba->req_head;
 345
 346         ++hba->req_head;
 347         hba->req_head %= MU_REQ_COUNT;
 348
 349         return req;
 350 }
 351
 352 static int stex_map_sg(struct st_hba *hba,
 353         struct req_msg *req, struct st_ccb *ccb)
 354 {
 355         struct pci_dev *pdev = hba->pdev;
 356         struct scsi_cmnd *cmd;
 357         dma_addr_t dma_handle;
 358         struct scatterlist *src;
 359         struct st_sgtable *dst;
 360         int i;
 361
 362         cmd = ccb->cmd;
 363         dst = (struct st_sgtable *)req->variable;
 364         dst->max_sg_count = cpu_to_le16(ST_MAX_SG);
 365         dst->sz_in_byte = cpu_to_le32(cmd->request_bufflen);
 366
 367         if (cmd->use_sg) {
 368                 int n_elem;
 369
 370                 src = (struct scatterlist *) cmd->request_buffer;
 371                 n_elem = pci_map_sg(pdev, src,
 372                         cmd->use_sg, cmd->sc_data_direction);
 373                 if (n_elem <= 0)
 374                         return -EIO;
 375
 376                 ccb->sg_count = n_elem;
 377                 dst->sg_count = cpu_to_le16((u16)n_elem);
 378
 379                 for (i = 0; i < n_elem; i++, src++) {
 380                         dst->table[i].count = cpu_to_le32((u32)sg_dma_len(src));
 381                         dst->table[i].addr =
 382                                 cpu_to_le32(sg_dma_address(src) & 0xffffffff);
 383                         dst->table[i].addr_hi =
 384                                 cpu_to_le32((sg_dma_address(src) >> 16) >> 16);
 385                         dst->table[i].ctrl = SG_CF_64B | SG_CF_HOST;
 386                 }
 387                 dst->table[--i].ctrl |= SG_CF_EOT;
 388                 return 0;
 389         }
 390
 391         dma_handle = pci_map_single(pdev, cmd->request_buffer,
 392                 cmd->request_bufflen, cmd->sc_data_direction);
 393         cmd->SCp.dma_handle = dma_handle;
 394
 395         ccb->sg_count = 1;
 396         dst->sg_count = cpu_to_le16(1);
 397         dst->table[0].addr = cpu_to_le32(dma_handle & 0xffffffff);
 398         dst->table[0].addr_hi = cpu_to_le32((dma_handle >> 16) >> 16);
 399         dst->table[0].count = cpu_to_le32((u32)cmd->request_bufflen);
 400         dst->table[0].ctrl = SG_CF_EOT | SG_CF_64B | SG_CF_HOST;
 401
 402         return 0;
 403 }
 404
 405 static void stex_internal_copy(struct scsi_cmnd *cmd,
 406         const void *src, size_t *count, int sg_count)
 407 {
 408         size_t lcount;
 409         size_t len;
 410         void *s, *d, *base = NULL;
 411         if (*count > cmd->request_bufflen)
 412                 *count = cmd->request_bufflen;
 413         lcount = *count;
 414         while (lcount) {
 415                 len = lcount;
 416                 s = (void *)src;
 417                 if (cmd->use_sg) {
 418                         size_t offset = *count - lcount;
 419                         s += offset;
 420                         base = scsi_kmap_atomic_sg(cmd->request_buffer,
 421                                 sg_count, &offset, &len);
 422                         if (base == NULL) {
 423                                 *count -= lcount;
 424                                 return;
 425                         }
 426                         d = base + offset;
 427                 } else
 428                         d = cmd->request_buffer;
 429
 430                 memcpy(d, s, len);
 431
 432                 lcount -= len;
 433                 if (cmd->use_sg)
 434                         scsi_kunmap_atomic_sg(base);
 435         }
 436 }
 437
 438 static int stex_direct_copy(struct scsi_cmnd *cmd,
 439         const void *src, size_t count)
 440 {
 441         struct st_hba *hba = (struct st_hba *) &cmd->device->host->hostdata[0];
 442         size_t cp_len = count;
 443         int n_elem = 0;
 444
 445         if (cmd->use_sg) {
 446                 n_elem = pci_map_sg(hba->pdev, cmd->request_buffer,
 447                         cmd->use_sg, cmd->sc_data_direction);
 448                 if (n_elem <= 0)
 449                         return 0;
 450         }
 451
 452         stex_internal_copy(cmd, src, &cp_len, n_elem);
 453
 454         if (cmd->use_sg)
 455                 pci_unmap_sg(hba->pdev, cmd->request_buffer,
 456                         cmd->use_sg, cmd->sc_data_direction);
 457         return cp_len == count;
 458 }
 459
 460 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
 461 {
 462         struct st_frame *p;
 463         size_t count = sizeof(struct st_frame);
 464
 465         p = hba->copy_buffer;
 466         memset(p->base, 0, sizeof(u32)*6);
 467         *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
 468         p->rom_addr = 0;
 469
 470         p->drv_ver.major = ST_VER_MAJOR;
 471         p->drv_ver.minor = ST_VER_MINOR;
 472         p->drv_ver.oem = ST_OEM;
 473         p->drv_ver.build = ST_BUILD_VER;
 474
 475         p->bus = hba->pdev->bus->number;
 476         p->slot = hba->pdev->devfn;
 477         p->irq_level = 0;
 478         p->irq_vec = hba->pdev->irq;
 479         p->id = hba->pdev->vendor << 16 | hba->pdev->device;
 480         p->subid =
 481                 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
 482
 483         stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count);
 484 }
 485
 486 static void
 487 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 488 {
 489         req->tag = cpu_to_le16(tag);
 490         req->task_attr = TASK_ATTRIBUTE_SIMPLE;
 491         req->task_manage = 0; /* not supported yet */
 492
 493         hba->ccb[tag].req = req;
 494         hba->out_req_cnt++;
 495
 496         writel(hba->req_head, hba->mmio_base + IMR0);
 497         writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
 498         readl(hba->mmio_base + IDBL); /* flush */
 499 }
 500
 501 static int
 502 stex_slave_alloc(struct scsi_device *sdev)
 503 {
 504         /* Cheat: usually extracted from Inquiry data */
 505         sdev->tagged_supported = 1;
 506
 507         scsi_activate_tcq(sdev, sdev->host->can_queue);
 508
 509         return 0;
 510 }
 511
 512 static int
 513 stex_slave_config(struct scsi_device *sdev)
 514 {
 515         sdev->use_10_for_rw = 1;
 516         sdev->use_10_for_ms = 1;
 517         sdev->timeout = 60 * HZ;
 518         sdev->tagged_supported = 1;
 519
 520         return 0;
 521 }
 522
 523 static void
 524 stex_slave_destroy(struct scsi_device *sdev)
 525 {
 526         scsi_deactivate_tcq(sdev, 1);
 527 }
 528
 529 static int
 530 stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *))
 531 {
 532         struct st_hba *hba;
 533         struct Scsi_Host *host;
 534         unsigned int id,lun;
 535         struct req_msg *req;
 536         u16 tag;
 537         host = cmd->device->host;
 538         id = cmd->device->id;
 539         lun = cmd->device->channel; /* firmware lun issue work around */
 540         hba = (struct st_hba *) &host->hostdata[0];
 541
 542         switch (cmd->cmnd[0]) {
 543         case MODE_SENSE_10:
 544         {
 545                 static char ms10_caching_page[12] =
 546                         { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
 547                 unsigned char page;
 548                 page = cmd->cmnd[2] & 0x3f;
 549                 if (page == 0x8 || page == 0x3f) {
 550                         stex_direct_copy(cmd, ms10_caching_page,
 551                                         sizeof(ms10_caching_page));
 552                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 553                         done(cmd);
 554                 } else
 555                         stex_invalid_field(cmd, done);
 556                 return 0;
 557         }
 558         case INQUIRY:
 559                 if (id != ST_MAX_ARRAY_SUPPORTED)
 560                         break;
 561                 if (lun == 0 && (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
 562                         stex_direct_copy(cmd, console_inq_page,
 563                                 sizeof(console_inq_page));
 564                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 565                         done(cmd);
 566                 } else
 567                         stex_invalid_field(cmd, done);
 568                 return 0;
 569         case PASSTHRU_CMD:
 570                 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
 571                         struct st_drvver ver;
 572                         ver.major = ST_VER_MAJOR;
 573                         ver.minor = ST_VER_MINOR;
 574                         ver.oem = ST_OEM;
 575                         ver.build = ST_BUILD_VER;
 576                         ver.signature[0] = PASSTHRU_SIGNATURE;
 577                         ver.console_id = ST_MAX_ARRAY_SUPPORTED;
 578                         ver.host_no = hba->host->host_no;
 579                         cmd->result = stex_direct_copy(cmd, &ver, sizeof(ver)) ?
 580                                 DID_OK << 16 | COMMAND_COMPLETE << 8 :
 581                                 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 582                         done(cmd);
 583                         return 0;
 584                 }
 585         default:
 586                 break;
 587         }
 588
 589         cmd->scsi_done = done;
 590
 591         tag = cmd->request->tag;
 592
 593         if (unlikely(tag >= host->can_queue))
 594                 return SCSI_MLQUEUE_HOST_BUSY;
 595
 596         req = stex_alloc_req(hba);
 597         req->lun = lun;
 598         req->target = id;
 599
 600         /* cdb */
 601         memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
 602
 603         hba->ccb[tag].cmd = cmd;
 604         hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
 605         hba->ccb[tag].sense_buffer = cmd->sense_buffer;
 606         hba->ccb[tag].req_type = 0;
 607
 608         if (cmd->sc_data_direction != DMA_NONE)
 609                 stex_map_sg(hba, req, &hba->ccb[tag]);
 610
 611         stex_send_cmd(hba, req, tag);
 612         return 0;
 613 }
 614
 615 static void stex_unmap_sg(struct st_hba *hba, struct scsi_cmnd *cmd)
 616 {
 617         if (cmd->sc_data_direction != DMA_NONE) {
 618                 if (cmd->use_sg)
 619                         pci_unmap_sg(hba->pdev, cmd->request_buffer,
 620                                 cmd->use_sg, cmd->sc_data_direction);
 621                 else
 622                         pci_unmap_single(hba->pdev, cmd->SCp.dma_handle,
 623                                 cmd->request_bufflen, cmd->sc_data_direction);
 624         }
 625 }
 626
 627 static void stex_scsi_done(struct st_ccb *ccb)
 628 {
 629         struct scsi_cmnd *cmd = ccb->cmd;
 630         int result;
 631
 632         if (ccb->srb_status == SRB_STATUS_SUCCESS ||  ccb->srb_status == 0) {
 633                 result = ccb->scsi_status;
 634                 switch (ccb->scsi_status) {
 635                 case SAM_STAT_GOOD:
 636                         result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
 637                         break;
 638                 case SAM_STAT_CHECK_CONDITION:
 639                         result |= DRIVER_SENSE << 24;
 640                         break;
 641                 case SAM_STAT_BUSY:
 642                         result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 643                         break;
 644                 default:
 645                         result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 646                         break;
 647                 }
 648         }
 649         else if (ccb->srb_status & SRB_SEE_SENSE)
 650                 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
 651         else switch (ccb->srb_status) {
 652                 case SRB_STATUS_SELECTION_TIMEOUT:
 653                         result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
 654                         break;
 655                 case SRB_STATUS_BUSY:
 656                         result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 657                         break;
 658                 case SRB_STATUS_INVALID_REQUEST:
 659                 case SRB_STATUS_ERROR:
 660                 default:
 661                         result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 662                         break;
 663         }
 664
 665         cmd->result = result;
 666         cmd->scsi_done(cmd);
 667 }
 668
 669 static void stex_copy_data(struct st_ccb *ccb,
 670         struct status_msg *resp, unsigned int variable)
 671 {
 672         size_t count = variable;
 673         if (resp->scsi_status != SAM_STAT_GOOD) {
 674                 if (ccb->sense_buffer != NULL)
 675                         memcpy(ccb->sense_buffer, resp->variable,
 676                                 min(variable, ccb->sense_bufflen));
 677                 return;
 678         }
 679
 680         if (ccb->cmd == NULL)
 681                 return;
 682         stex_internal_copy(ccb->cmd, resp->variable, &count, ccb->sg_count);
 683 }
 684
 685 static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
 686 {
 687         void __iomem *base = hba->mmio_base;
 688         struct status_msg *resp;
 689         struct st_ccb *ccb;
 690         unsigned int size;
 691         u16 tag;
 692
 693         if (!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED))
 694                 return;
 695
 696         /* status payloads */
 697         hba->status_head = readl(base + OMR1);
 698         if (unlikely(hba->status_head >= MU_STATUS_COUNT)) {
 699                 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
 700                         pci_name(hba->pdev));
 701                 return;
 702         }
 703
 704         if (unlikely(hba->mu_status != MU_STATE_STARTED ||
 705                 hba->out_req_cnt <= 0)) {
 706                 hba->status_tail = hba->status_head;
 707                 goto update_status;
 708         }
 709
 710         while (hba->status_tail != hba->status_head) {
 711                 resp = stex_get_status(hba);
 712                 tag = le16_to_cpu(resp->tag);
 713                 if (unlikely(tag >= hba->host->can_queue)) {
 714                         printk(KERN_WARNING DRV_NAME
 715                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 716                         continue;
 717                 }
 718
 719                 ccb = &hba->ccb[tag];
 720                 if (hba->wait_ccb == ccb)
 721                         hba->wait_ccb = NULL;
 722                 if (unlikely(ccb->req == NULL)) {
 723                         printk(KERN_WARNING DRV_NAME
 724                                 "(%s): lagging req\n", pci_name(hba->pdev));
 725                         continue;
 726                 }
 727
 728                 size = resp->payload_sz * sizeof(u32); /* payload size */
 729                 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 730                         size > sizeof(*resp))) {
 731                         printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
 732                                 pci_name(hba->pdev));
 733                 } else {
 734                         size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
 735                         if (size)
 736                                 stex_copy_data(ccb, resp, size);
 737                 }
 738
 739                 ccb->srb_status = resp->srb_status;
 740                 ccb->scsi_status = resp->scsi_status;
 741
 742                 if (likely(ccb->cmd != NULL)) {
 743                         if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
 744                                 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
 745                                 stex_controller_info(hba, ccb);
 746                         stex_unmap_sg(hba, ccb->cmd);
 747                         stex_scsi_done(ccb);
 748                         hba->out_req_cnt--;
 749                 } else if (ccb->req_type & PASSTHRU_REQ_TYPE) {
 750                         hba->out_req_cnt--;
 751                         if (ccb->req_type & PASSTHRU_REQ_NO_WAKEUP) {
 752                                 ccb->req_type = 0;
 753                                 continue;
 754                         }
 755                         ccb->req_type = 0;
 756                         if (waitqueue_active(&hba->waitq))
 757                                 wake_up(&hba->waitq);
 758                 }
 759         }
 760
 761 update_status:
 762         writel(hba->status_head, base + IMR1);
 763         readl(base + IMR1); /* flush */
 764 }
 765
 766 static irqreturn_t stex_intr(int irq, void *__hba, struct pt_regs *regs)
 767 {
 768         struct st_hba *hba = __hba;
 769         void __iomem *base = hba->mmio_base;
 770         u32 data;
 771         unsigned long flags;
 772         int handled = 0;
 773
 774         spin_lock_irqsave(hba->host->host_lock, flags);
 775
 776         data = readl(base + ODBL);
 777
 778         if (data && data != 0xffffffff) {
 779                 /* clear the interrupt */
 780                 writel(data, base + ODBL);
 781                 readl(base + ODBL); /* flush */
 782                 stex_mu_intr(hba, data);
 783                 handled = 1;
 784         }
 785
 786         spin_unlock_irqrestore(hba->host->host_lock, flags);
 787
 788         return IRQ_RETVAL(handled);
 789 }
 790
 791 static int stex_handshake(struct st_hba *hba)
 792 {
 793         void __iomem *base = hba->mmio_base;
 794         struct handshake_frame *h;
 795         dma_addr_t status_phys;
 796         int i;
 797
 798         if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 799                 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
 800                 readl(base + IDBL);
 801                 for (i = 0; readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE
 802                         && i < MU_MAX_DELAY_TIME; i++) {
 803                         rmb();
 804                         msleep(1);
 805                 }
 806
 807                 if (i == MU_MAX_DELAY_TIME) {
 808                         printk(KERN_ERR DRV_NAME
 809                                 "(%s): no handshake signature\n",
 810                                 pci_name(hba->pdev));
 811                         return -1;
 812                 }
 813         }
 814
 815         udelay(10);
 816
 817         h = (struct handshake_frame *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
 818         h->rb_phy = cpu_to_le32(hba->dma_handle);
 819         h->rb_phy_hi = cpu_to_le32((hba->dma_handle >> 16) >> 16);
 820         h->req_sz = cpu_to_le16(sizeof(struct req_msg));
 821         h->req_cnt = cpu_to_le16(MU_REQ_COUNT);
 822         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
 823         h->status_cnt = cpu_to_le16(MU_STATUS_COUNT);
 824         stex_gettime(&h->hosttime);
 825         h->partner_type = HMU_PARTNER_TYPE;
 826
 827         status_phys = hba->dma_handle + MU_REQ_BUFFER_SIZE;
 828         writel(status_phys, base + IMR0);
 829         readl(base + IMR0);
 830         writel((status_phys >> 16) >> 16, base + IMR1);
 831         readl(base + IMR1);
 832
 833         writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
 834         readl(base + OMR0);
 835         writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
 836         readl(base + IDBL); /* flush */
 837
 838         udelay(10);
 839         for (i = 0; readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE
 840                 && i < MU_MAX_DELAY_TIME; i++) {
 841                 rmb();
 842                 msleep(1);
 843         }
 844
 845         if (i == MU_MAX_DELAY_TIME) {
 846                 printk(KERN_ERR DRV_NAME
 847                         "(%s): no signature after handshake frame\n",
 848                         pci_name(hba->pdev));
 849                 return -1;
 850         }
 851
 852         writel(0, base + IMR0);
 853         readl(base + IMR0);
 854         writel(0, base + OMR0);
 855         readl(base + OMR0);
 856         writel(0, base + IMR1);
 857         readl(base + IMR1);
 858         writel(0, base + OMR1);
 859         readl(base + OMR1); /* flush */
 860         hba->mu_status = MU_STATE_STARTED;
 861         return 0;
 862 }
 863
 864 static int stex_abort(struct scsi_cmnd *cmd)
 865 {
 866         struct Scsi_Host *host = cmd->device->host;
 867         struct st_hba *hba = (struct st_hba *)host->hostdata;
 868         u16 tag = cmd->request->tag;
 869         void __iomem *base;
 870         u32 data;
 871         int result = SUCCESS;
 872         unsigned long flags;
 873         base = hba->mmio_base;
 874         spin_lock_irqsave(host->host_lock, flags);
 875         if (tag < host->can_queue && hba->ccb[tag].cmd == cmd)
 876                 hba->wait_ccb = &hba->ccb[tag];
 877         else {
 878                 for (tag = 0; tag < host->can_queue; tag++)
 879                         if (hba->ccb[tag].cmd == cmd) {
 880                                 hba->wait_ccb = &hba->ccb[tag];
 881                                 break;
 882                         }
 883                 if (tag >= host->can_queue)
 884                         goto out;
 885         }
 886
 887         data = readl(base + ODBL);
 888         if (data == 0 || data == 0xffffffff)
 889                 goto fail_out;
 890
 891         writel(data, base + ODBL);
 892         readl(base + ODBL); /* flush */
 893
 894         stex_mu_intr(hba, data);
 895
 896         if (hba->wait_ccb == NULL) {
 897                 printk(KERN_WARNING DRV_NAME
 898                         "(%s): lost interrupt\n", pci_name(hba->pdev));
 899                 goto out;
 900         }
 901
 902 fail_out:
 903         stex_unmap_sg(hba, cmd);
 904         hba->wait_ccb->req = NULL; /* nullify the req's future return */
 905         hba->wait_ccb = NULL;
 906         result = FAILED;
 907 out:
 908         spin_unlock_irqrestore(host->host_lock, flags);
 909         return result;
 910 }
 911
 912 static void stex_hard_reset(struct st_hba *hba)
 913 {
 914         struct pci_bus *bus;
 915         int i;
 916         u16 pci_cmd;
 917         u8 pci_bctl;
 918
 919         for (i = 0; i < 16; i++)
 920                 pci_read_config_dword(hba->pdev, i * 4,
 921                         &hba->pdev->saved_config_space[i]);
 922
 923         /* Reset secondary bus. Our controller(MU/ATU) is the only device on
 924            secondary bus. Consult Intel 80331/3 developer's manual for detail */
 925         bus = hba->pdev->bus;
 926         pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
 927         pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
 928         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
 929         msleep(1);
 930         pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
 931         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
 932
 933         for (i = 0; i < MU_MAX_DELAY_TIME; i++) {
 934                 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
 935                 if (pci_cmd & PCI_COMMAND_MASTER)
 936                         break;
 937                 msleep(1);
 938         }
 939
 940         ssleep(5);
 941         for (i = 0; i < 16; i++)
 942                 pci_write_config_dword(hba->pdev, i * 4,
 943                         hba->pdev->saved_config_space[i]);
 944 }
 945
 946 static int stex_reset(struct scsi_cmnd *cmd)
 947 {
 948         struct st_hba *hba;
 949         unsigned long flags;
 950         hba = (struct st_hba *) &cmd->device->host->hostdata[0];
 951
 952         hba->mu_status = MU_STATE_RESETTING;
 953
 954         if (hba->cardtype == st_shasta)
 955                 stex_hard_reset(hba);
 956
 957         if (stex_handshake(hba)) {
 958                 printk(KERN_WARNING DRV_NAME
 959                         "(%s): resetting: handshake failed\n",
 960                         pci_name(hba->pdev));
 961                 return FAILED;
 962         }
 963         spin_lock_irqsave(hba->host->host_lock, flags);
 964         hba->req_head = 0;
 965         hba->req_tail = 0;
 966         hba->status_head = 0;
 967         hba->status_tail = 0;
 968         hba->out_req_cnt = 0;
 969         spin_unlock_irqrestore(hba->host->host_lock, flags);
 970
 971         return SUCCESS;
 972 }
 973
 974 static int stex_biosparam(struct scsi_device *sdev,
 975         struct block_device *bdev, sector_t capacity, int geom[])
 976 {
 977         int heads = 255, sectors = 63, cylinders;
 978
 979         if (capacity < 0x200000) {
 980                 heads = 64;
 981                 sectors = 32;
 982         }
 983
 984         cylinders = sector_div(capacity, heads * sectors);
 985
 986         geom[0] = heads;
 987         geom[1] = sectors;
 988         geom[2] = cylinders;
 989
 990         return 0;
 991 }
 992
 993 static struct scsi_host_template driver_template = {
 994         .module                         = THIS_MODULE,
 995         .name                           = DRV_NAME,
 996         .proc_name                      = DRV_NAME,
 997         .bios_param                     = stex_biosparam,
 998         .queuecommand                   = stex_queuecommand,
 999         .slave_alloc                    = stex_slave_alloc,
1000         .slave_configure                = stex_slave_config,
1001         .slave_destroy                  = stex_slave_destroy,
1002         .eh_abort_handler               = stex_abort,
1003         .eh_host_reset_handler          = stex_reset,
1004         .can_queue                      = ST_CAN_QUEUE,
1005         .this_id                        = -1,
1006         .sg_tablesize                   = ST_MAX_SG,
1007         .cmd_per_lun                    = ST_CMD_PER_LUN,
1008 };
1009
1010 static int stex_set_dma_mask(struct pci_dev * pdev)
1011 {
1012         int ret;
1013         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)
1014                 && !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
1015                 return 0;
1016         ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1017         if (!ret)
1018                 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1019         return ret;
1020 }
1021
1022 static int __devinit
1023 stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1024 {
1025         struct st_hba *hba;
1026         struct Scsi_Host *host;
1027         int err;
1028
1029         err = pci_enable_device(pdev);
1030         if (err)
1031                 return err;
1032
1033         pci_set_master(pdev);
1034
1035         host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1036
1037         if (!host) {
1038                 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1039                         pci_name(pdev));
1040                 err = -ENOMEM;
1041                 goto out_disable;
1042         }
1043
1044         hba = (struct st_hba *)host->hostdata;
1045         memset(hba, 0, sizeof(struct st_hba));
1046
1047         err = pci_request_regions(pdev, DRV_NAME);
1048         if (err < 0) {
1049                 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1050                         pci_name(pdev));
1051                 goto out_scsi_host_put;
1052         }
1053
1054         hba->mmio_base = ioremap(pci_resource_start(pdev, 0),
1055                 pci_resource_len(pdev, 0));
1056         if ( !hba->mmio_base) {
1057                 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1058                         pci_name(pdev));
1059                 err = -ENOMEM;
1060                 goto out_release_regions;
1061         }
1062
1063         err = stex_set_dma_mask(pdev);
1064         if (err) {
1065                 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1066                         pci_name(pdev));
1067                 goto out_iounmap;
1068         }
1069
1070         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1071                 STEX_BUFFER_SIZE, &hba->dma_handle, GFP_KERNEL);
1072         if (!hba->dma_mem) {
1073                 err = -ENOMEM;
1074                 printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1075                         pci_name(pdev));
1076                 goto out_iounmap;
1077         }
1078
1079         hba->status_buffer =
1080                 (struct status_msg *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
1081         hba->copy_buffer = hba->dma_mem + MU_BUFFER_SIZE;
1082         hba->mu_status = MU_STATE_STARTING;
1083
1084         hba->cardtype = (unsigned int) id->driver_data;
1085
1086         /* firmware uses id/lun pair for a logical drive, but lun would be
1087            always 0 if CONFIG_SCSI_MULTI_LUN not configured, so we use
1088            channel to map lun here */
1089         host->max_channel = ST_MAX_LUN_PER_TARGET - 1;
1090         host->max_id = ST_MAX_TARGET_NUM;
1091         host->max_lun = 1;
1092         host->unique_id = host->host_no;
1093         host->max_cmd_len = STEX_CDB_LENGTH;
1094
1095         hba->host = host;
1096         hba->pdev = pdev;
1097         init_waitqueue_head(&hba->waitq);
1098
1099         err = request_irq(pdev->irq, stex_intr, IRQF_SHARED, DRV_NAME, hba);
1100         if (err) {
1101                 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1102                         pci_name(pdev));
1103                 goto out_pci_free;
1104         }
1105
1106         err = stex_handshake(hba);
1107         if (err)
1108                 goto out_free_irq;
1109
1110         err = scsi_init_shared_tag_map(host, ST_CAN_QUEUE);
1111         if (err) {
1112                 printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
1113                         pci_name(pdev));
1114                 goto out_free_irq;
1115         }
1116
1117         pci_set_drvdata(pdev, hba);
1118
1119         err = scsi_add_host(host, &pdev->dev);
1120         if (err) {
1121                 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1122                         pci_name(pdev));
1123                 goto out_free_irq;
1124         }
1125
1126         scsi_scan_host(host);
1127
1128         return 0;
1129
1130 out_free_irq:
1131         free_irq(pdev->irq, hba);
1132 out_pci_free:
1133         dma_free_coherent(&pdev->dev, STEX_BUFFER_SIZE,
1134                           hba->dma_mem, hba->dma_handle);
1135 out_iounmap:
1136         iounmap(hba->mmio_base);
1137 out_release_regions:
1138         pci_release_regions(pdev);
1139 out_scsi_host_put:
1140         scsi_host_put(host);
1141 out_disable:
1142         pci_disable_device(pdev);
1143
1144         return err;
1145 }
1146
1147 static void stex_hba_stop(struct st_hba *hba)
1148 {
1149         struct req_msg *req;
1150         unsigned long flags;
1151         unsigned long before;
1152         u16 tag = 0;
1153
1154         spin_lock_irqsave(hba->host->host_lock, flags);
1155         req = stex_alloc_req(hba);
1156         memset(req->cdb, 0, STEX_CDB_LENGTH);
1157
1158         req->cdb[0] = CONTROLLER_CMD;
1159         req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1160         req->cdb[2] = CTLR_POWER_SAVING;
1161
1162         hba->ccb[tag].cmd = NULL;
1163         hba->ccb[tag].sg_count = 0;
1164         hba->ccb[tag].sense_bufflen = 0;
1165         hba->ccb[tag].sense_buffer = NULL;
1166         hba->ccb[tag].req_type |= PASSTHRU_REQ_TYPE;
1167
1168         stex_send_cmd(hba, req, tag);
1169         spin_unlock_irqrestore(hba->host->host_lock, flags);
1170
1171         before = jiffies;
1172         while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1173                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ))
1174                         return;
1175                 msleep(10);
1176         }
1177 }
1178
1179 static void stex_hba_free(struct st_hba *hba)
1180 {
1181         free_irq(hba->pdev->irq, hba);
1182
1183         iounmap(hba->mmio_base);
1184
1185         pci_release_regions(hba->pdev);
1186
1187         dma_free_coherent(&hba->pdev->dev, STEX_BUFFER_SIZE,
1188                           hba->dma_mem, hba->dma_handle);
1189 }
1190
1191 static void stex_remove(struct pci_dev *pdev)
1192 {
1193         struct st_hba *hba = pci_get_drvdata(pdev);
1194
1195         scsi_remove_host(hba->host);
1196
1197         pci_set_drvdata(pdev, NULL);
1198
1199         stex_hba_stop(hba);
1200
1201         stex_hba_free(hba);
1202
1203         scsi_host_put(hba->host);
1204
1205         pci_disable_device(pdev);
1206 }
1207
1208 static void stex_shutdown(struct pci_dev *pdev)
1209 {
1210         struct st_hba *hba = pci_get_drvdata(pdev);
1211
1212         stex_hba_stop(hba);
1213 }
1214
1215 static struct pci_device_id stex_pci_tbl[] = {
1216         { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_shasta },
1217         { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_shasta },
1218         { 0x105a, 0xf350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_shasta },
1219         { 0x105a, 0x4301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_shasta },
1220         { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_shasta },
1221         { 0x105a, 0x8301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_shasta },
1222         { 0x105a, 0x8302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_shasta },
1223         { 0x1725, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1224         { }     /* terminate list */
1225 };
1226 MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1227
1228 static struct pci_driver stex_pci_driver = {
1229         .name           = DRV_NAME,
1230         .id_table       = stex_pci_tbl,
1231         .probe          = stex_probe,
1232         .remove         = __devexit_p(stex_remove),
1233         .shutdown       = stex_shutdown,
1234 };
1235
1236 static int __init stex_init(void)
1237 {
1238         printk(KERN_INFO DRV_NAME
1239                 ": Promise SuperTrak EX Driver version: %s\n",
1240                  ST_DRIVER_VERSION);
1241
1242         return pci_register_driver(&stex_pci_driver);
1243 }
1244
1245 static void __exit stex_exit(void)
1246 {
1247         pci_unregister_driver(&stex_pci_driver);
1248 }
1249
1250 module_init(stex_init);
1251 module_exit(stex_exit);