2 * sata_mv.c - Marvell SATA support
4 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/init.h>
27 #include <linux/blkdev.h>
28 #include <linux/delay.h>
29 #include <linux/interrupt.h>
30 #include <linux/sched.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/device.h>
33 #include <scsi/scsi_host.h>
34 #include <scsi/scsi_cmnd.h>
35 #include <linux/libata.h>
38 #define DRV_NAME "sata_mv"
39 #define DRV_VERSION "0.25"
42 /* BAR's are enumerated in terms of pci_resource_start() terms */
43 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
44 MV_IO_BAR = 2, /* offset 0x18: IO space */
45 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
47 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
48 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
51 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
52 MV_SATAHC0_REG_BASE = 0x20000,
53 MV_FLASH_CTL = 0x1046c,
54 MV_GPIO_PORT_CTL = 0x104f0,
55 MV_RESET_CFG = 0x180d8,
57 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
58 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
59 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
60 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
62 MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
65 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
67 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
68 * CRPB needs alignment on a 256B boundary. Size == 256B
69 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
70 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
72 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
73 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
75 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
76 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
79 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
81 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
85 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
86 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
87 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
88 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO),
89 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
91 CRQB_FLAG_READ = (1 << 0),
93 CRQB_CMD_ADDR_SHIFT = 8,
94 CRQB_CMD_CS = (0x2 << 11),
95 CRQB_CMD_LAST = (1 << 15),
97 CRPB_FLAG_STATUS_SHIFT = 8,
99 EPRD_FLAG_END_OF_TBL = (1 << 31),
101 /* PCI interface registers */
103 PCI_COMMAND_OFS = 0xc00,
105 PCI_MAIN_CMD_STS_OFS = 0xd30,
106 STOP_PCI_MASTER = (1 << 2),
107 PCI_MASTER_EMPTY = (1 << 3),
108 GLOB_SFT_RST = (1 << 4),
111 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
112 MV_PCI_DISC_TIMER = 0xd04,
113 MV_PCI_MSI_TRIGGER = 0xc38,
114 MV_PCI_SERR_MASK = 0xc28,
115 MV_PCI_XBAR_TMOUT = 0x1d04,
116 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
117 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
118 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
119 MV_PCI_ERR_COMMAND = 0x1d50,
121 PCI_IRQ_CAUSE_OFS = 0x1d58,
122 PCI_IRQ_MASK_OFS = 0x1d5c,
123 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
125 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
126 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
127 PORT0_ERR = (1 << 0), /* shift by port # */
128 PORT0_DONE = (1 << 1), /* shift by port # */
129 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
130 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
132 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
133 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
134 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
135 GPIO_INT = (1 << 22),
136 SELF_INT = (1 << 23),
137 TWSI_INT = (1 << 24),
138 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
139 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
140 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
143 /* SATAHC registers */
146 HC_IRQ_CAUSE_OFS = 0x14,
147 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
148 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
149 DEV_IRQ = (1 << 8), /* shift by port # */
151 /* Shadow block registers */
153 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
156 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
157 SATA_ACTIVE_OFS = 0x350,
164 SATA_INTERFACE_CTL = 0x050,
166 MV_M2_PREAMP_MASK = 0x7e0,
170 EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
171 EDMA_CFG_NCQ = (1 << 5),
172 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
173 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
174 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
176 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
177 EDMA_ERR_IRQ_MASK_OFS = 0xc,
178 EDMA_ERR_D_PAR = (1 << 0),
179 EDMA_ERR_PRD_PAR = (1 << 1),
180 EDMA_ERR_DEV = (1 << 2),
181 EDMA_ERR_DEV_DCON = (1 << 3),
182 EDMA_ERR_DEV_CON = (1 << 4),
183 EDMA_ERR_SERR = (1 << 5),
184 EDMA_ERR_SELF_DIS = (1 << 7),
185 EDMA_ERR_BIST_ASYNC = (1 << 8),
186 EDMA_ERR_CRBQ_PAR = (1 << 9),
187 EDMA_ERR_CRPB_PAR = (1 << 10),
188 EDMA_ERR_INTRL_PAR = (1 << 11),
189 EDMA_ERR_IORDY = (1 << 12),
190 EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
191 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
192 EDMA_ERR_LNK_DATA_RX = (0xf << 17),
193 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
194 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
195 EDMA_ERR_TRANS_PROTO = (1 << 31),
196 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
197 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
198 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
199 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
200 EDMA_ERR_LNK_DATA_RX |
201 EDMA_ERR_LNK_DATA_TX |
202 EDMA_ERR_TRANS_PROTO),
204 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
205 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
207 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
208 EDMA_REQ_Q_PTR_SHIFT = 5,
210 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
211 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
212 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
213 EDMA_RSP_Q_PTR_SHIFT = 3,
220 EDMA_IORDY_TMOUT = 0x34,
223 /* Host private flags (hp_flags) */
224 MV_HP_FLAG_MSI = (1 << 0),
225 MV_HP_ERRATA_50XXB0 = (1 << 1),
226 MV_HP_ERRATA_50XXB2 = (1 << 2),
227 MV_HP_ERRATA_60X1B2 = (1 << 3),
228 MV_HP_ERRATA_60X1C0 = (1 << 4),
229 MV_HP_50XX = (1 << 5),
231 /* Port private flags (pp_flags) */
232 MV_PP_FLAG_EDMA_EN = (1 << 0),
233 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
236 #define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
237 #define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
240 /* Our DMA boundary is determined by an ePRD being unable to handle
241 * anything larger than 64KB
243 MV_DMA_BOUNDARY = 0xffffU,
245 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
247 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
258 /* Command ReQuest Block: 32B */
266 /* Command ResPonse Block: 8B */
273 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
281 struct mv_port_priv {
282 struct mv_crqb *crqb;
284 struct mv_crpb *crpb;
286 struct mv_sg *sg_tbl;
287 dma_addr_t sg_tbl_dma;
289 unsigned req_producer; /* cp of req_in_ptr */
290 unsigned rsp_consumer; /* cp of rsp_out_ptr */
294 struct mv_port_signal {
301 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
303 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
304 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
306 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
308 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
309 void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
312 struct mv_host_priv {
314 struct mv_port_signal signal[8];
315 const struct mv_hw_ops *ops;
318 static void mv_irq_clear(struct ata_port *ap);
319 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
320 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
321 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
322 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
323 static void mv_phy_reset(struct ata_port *ap);
324 static void __mv_phy_reset(struct ata_port *ap, int can_sleep);
325 static void mv_host_stop(struct ata_host_set *host_set);
326 static int mv_port_start(struct ata_port *ap);
327 static void mv_port_stop(struct ata_port *ap);
328 static void mv_qc_prep(struct ata_queued_cmd *qc);
329 static int mv_qc_issue(struct ata_queued_cmd *qc);
330 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
331 struct pt_regs *regs);
332 static void mv_eng_timeout(struct ata_port *ap);
333 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
335 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
337 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
338 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
340 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
342 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
343 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
345 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
347 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
348 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
350 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
352 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
353 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
354 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
355 unsigned int port_no);
356 static void mv_stop_and_reset(struct ata_port *ap);
358 static struct scsi_host_template mv_sht = {
359 .module = THIS_MODULE,
361 .ioctl = ata_scsi_ioctl,
362 .queuecommand = ata_scsi_queuecmd,
363 .eh_strategy_handler = ata_scsi_error,
364 .can_queue = MV_USE_Q_DEPTH,
365 .this_id = ATA_SHT_THIS_ID,
366 .sg_tablesize = MV_MAX_SG_CT / 2,
367 .max_sectors = ATA_MAX_SECTORS,
368 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
369 .emulated = ATA_SHT_EMULATED,
370 .use_clustering = ATA_SHT_USE_CLUSTERING,
371 .proc_name = DRV_NAME,
372 .dma_boundary = MV_DMA_BOUNDARY,
373 .slave_configure = ata_scsi_slave_config,
374 .bios_param = ata_std_bios_param,
378 static const struct ata_port_operations mv5_ops = {
379 .port_disable = ata_port_disable,
381 .tf_load = ata_tf_load,
382 .tf_read = ata_tf_read,
383 .check_status = ata_check_status,
384 .exec_command = ata_exec_command,
385 .dev_select = ata_std_dev_select,
387 .phy_reset = mv_phy_reset,
389 .qc_prep = mv_qc_prep,
390 .qc_issue = mv_qc_issue,
392 .eng_timeout = mv_eng_timeout,
394 .irq_handler = mv_interrupt,
395 .irq_clear = mv_irq_clear,
397 .scr_read = mv5_scr_read,
398 .scr_write = mv5_scr_write,
400 .port_start = mv_port_start,
401 .port_stop = mv_port_stop,
402 .host_stop = mv_host_stop,
405 static const struct ata_port_operations mv6_ops = {
406 .port_disable = ata_port_disable,
408 .tf_load = ata_tf_load,
409 .tf_read = ata_tf_read,
410 .check_status = ata_check_status,
411 .exec_command = ata_exec_command,
412 .dev_select = ata_std_dev_select,
414 .phy_reset = mv_phy_reset,
416 .qc_prep = mv_qc_prep,
417 .qc_issue = mv_qc_issue,
419 .eng_timeout = mv_eng_timeout,
421 .irq_handler = mv_interrupt,
422 .irq_clear = mv_irq_clear,
424 .scr_read = mv_scr_read,
425 .scr_write = mv_scr_write,
427 .port_start = mv_port_start,
428 .port_stop = mv_port_stop,
429 .host_stop = mv_host_stop,
432 static struct ata_port_info mv_port_info[] = {
435 .host_flags = MV_COMMON_FLAGS,
436 .pio_mask = 0x1f, /* pio0-4 */
437 .udma_mask = 0x7f, /* udma0-6 */
438 .port_ops = &mv5_ops,
442 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
443 .pio_mask = 0x1f, /* pio0-4 */
444 .udma_mask = 0x7f, /* udma0-6 */
445 .port_ops = &mv5_ops,
449 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
450 .pio_mask = 0x1f, /* pio0-4 */
451 .udma_mask = 0x7f, /* udma0-6 */
452 .port_ops = &mv5_ops,
456 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
457 .pio_mask = 0x1f, /* pio0-4 */
458 .udma_mask = 0x7f, /* udma0-6 */
459 .port_ops = &mv6_ops,
463 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
465 .pio_mask = 0x1f, /* pio0-4 */
466 .udma_mask = 0x7f, /* udma0-6 */
467 .port_ops = &mv6_ops,
471 static const struct pci_device_id mv_pci_tbl[] = {
472 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x},
473 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x},
474 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_5080},
475 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x},
477 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x},
478 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6041), 0, 0, chip_604x},
479 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6080), 0, 0, chip_608x},
480 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6081), 0, 0, chip_608x},
482 {PCI_DEVICE(PCI_VENDOR_ID_ADAPTEC2, 0x0241), 0, 0, chip_604x},
483 {} /* terminate list */
486 static struct pci_driver mv_pci_driver = {
488 .id_table = mv_pci_tbl,
489 .probe = mv_init_one,
490 .remove = ata_pci_remove_one,
493 static const struct mv_hw_ops mv5xxx_ops = {
494 .phy_errata = mv5_phy_errata,
495 .enable_leds = mv5_enable_leds,
496 .read_preamp = mv5_read_preamp,
497 .reset_hc = mv5_reset_hc,
498 .reset_flash = mv5_reset_flash,
499 .reset_bus = mv5_reset_bus,
502 static const struct mv_hw_ops mv6xxx_ops = {
503 .phy_errata = mv6_phy_errata,
504 .enable_leds = mv6_enable_leds,
505 .read_preamp = mv6_read_preamp,
506 .reset_hc = mv6_reset_hc,
507 .reset_flash = mv6_reset_flash,
508 .reset_bus = mv_reset_pci_bus,
515 static inline void writelfl(unsigned long data, void __iomem *addr)
518 (void) readl(addr); /* flush to avoid PCI posted write */
521 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
523 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
526 static inline unsigned int mv_hc_from_port(unsigned int port)
528 return port >> MV_PORT_HC_SHIFT;
531 static inline unsigned int mv_hardport_from_port(unsigned int port)
533 return port & MV_PORT_MASK;
536 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
539 return mv_hc_base(base, mv_hc_from_port(port));
542 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
544 return mv_hc_base_from_port(base, port) +
545 MV_SATAHC_ARBTR_REG_SZ +
546 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
549 static inline void __iomem *mv_ap_base(struct ata_port *ap)
551 return mv_port_base(ap->host_set->mmio_base, ap->port_no);
554 static inline int mv_get_hc_count(unsigned long host_flags)
556 return ((host_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
559 static void mv_irq_clear(struct ata_port *ap)
564 * mv_start_dma - Enable eDMA engine
565 * @base: port base address
566 * @pp: port private data
568 * Verify the local cache of the eDMA state is accurate with an
572 * Inherited from caller.
574 static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
576 if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
577 writelfl(EDMA_EN, base + EDMA_CMD_OFS);
578 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
580 assert(EDMA_EN & readl(base + EDMA_CMD_OFS));
584 * mv_stop_dma - Disable eDMA engine
585 * @ap: ATA channel to manipulate
587 * Verify the local cache of the eDMA state is accurate with an
591 * Inherited from caller.
593 static void mv_stop_dma(struct ata_port *ap)
595 void __iomem *port_mmio = mv_ap_base(ap);
596 struct mv_port_priv *pp = ap->private_data;
600 if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
601 /* Disable EDMA if active. The disable bit auto clears.
603 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
604 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
606 assert(!(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS)));
609 /* now properly wait for the eDMA to stop */
610 for (i = 1000; i > 0; i--) {
611 reg = readl(port_mmio + EDMA_CMD_OFS);
612 if (!(EDMA_EN & reg)) {
619 printk(KERN_ERR "ata%u: Unable to stop eDMA\n", ap->id);
620 /* FIXME: Consider doing a reset here to recover */
625 static void mv_dump_mem(void __iomem *start, unsigned bytes)
628 for (b = 0; b < bytes; ) {
629 DPRINTK("%p: ", start + b);
630 for (w = 0; b < bytes && w < 4; w++) {
631 printk("%08x ",readl(start + b));
639 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
644 for (b = 0; b < bytes; ) {
645 DPRINTK("%02x: ", b);
646 for (w = 0; b < bytes && w < 4; w++) {
647 (void) pci_read_config_dword(pdev,b,&dw);
655 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
656 struct pci_dev *pdev)
659 void __iomem *hc_base = mv_hc_base(mmio_base,
660 port >> MV_PORT_HC_SHIFT);
661 void __iomem *port_base;
662 int start_port, num_ports, p, start_hc, num_hcs, hc;
665 start_hc = start_port = 0;
666 num_ports = 8; /* shld be benign for 4 port devs */
669 start_hc = port >> MV_PORT_HC_SHIFT;
671 num_ports = num_hcs = 1;
673 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
674 num_ports > 1 ? num_ports - 1 : start_port);
677 DPRINTK("PCI config space regs:\n");
678 mv_dump_pci_cfg(pdev, 0x68);
680 DPRINTK("PCI regs:\n");
681 mv_dump_mem(mmio_base+0xc00, 0x3c);
682 mv_dump_mem(mmio_base+0xd00, 0x34);
683 mv_dump_mem(mmio_base+0xf00, 0x4);
684 mv_dump_mem(mmio_base+0x1d00, 0x6c);
685 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
686 hc_base = mv_hc_base(mmio_base, port >> MV_PORT_HC_SHIFT);
687 DPRINTK("HC regs (HC %i):\n", hc);
688 mv_dump_mem(hc_base, 0x1c);
690 for (p = start_port; p < start_port + num_ports; p++) {
691 port_base = mv_port_base(mmio_base, p);
692 DPRINTK("EDMA regs (port %i):\n",p);
693 mv_dump_mem(port_base, 0x54);
694 DPRINTK("SATA regs (port %i):\n",p);
695 mv_dump_mem(port_base+0x300, 0x60);
700 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
708 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
711 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
720 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
722 unsigned int ofs = mv_scr_offset(sc_reg_in);
724 if (0xffffffffU != ofs) {
725 return readl(mv_ap_base(ap) + ofs);
731 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
733 unsigned int ofs = mv_scr_offset(sc_reg_in);
735 if (0xffffffffU != ofs) {
736 writelfl(val, mv_ap_base(ap) + ofs);
741 * mv_host_stop - Host specific cleanup/stop routine.
742 * @host_set: host data structure
744 * Disable ints, cleanup host memory, call general purpose
748 * Inherited from caller.
750 static void mv_host_stop(struct ata_host_set *host_set)
752 struct mv_host_priv *hpriv = host_set->private_data;
753 struct pci_dev *pdev = to_pci_dev(host_set->dev);
755 if (hpriv->hp_flags & MV_HP_FLAG_MSI) {
756 pci_disable_msi(pdev);
761 ata_host_stop(host_set);
764 static inline void mv_priv_free(struct mv_port_priv *pp, struct device *dev)
766 dma_free_coherent(dev, MV_PORT_PRIV_DMA_SZ, pp->crpb, pp->crpb_dma);
770 * mv_port_start - Port specific init/start routine.
771 * @ap: ATA channel to manipulate
773 * Allocate and point to DMA memory, init port private memory,
777 * Inherited from caller.
779 static int mv_port_start(struct ata_port *ap)
781 struct device *dev = ap->host_set->dev;
782 struct mv_port_priv *pp;
783 void __iomem *port_mmio = mv_ap_base(ap);
788 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
791 memset(pp, 0, sizeof(*pp));
793 mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
797 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
799 rc = ata_pad_alloc(ap, dev);
803 /* First item in chunk of DMA memory:
804 * 32-slot command request table (CRQB), 32 bytes each in size
807 pp->crqb_dma = mem_dma;
809 mem_dma += MV_CRQB_Q_SZ;
812 * 32-slot command response table (CRPB), 8 bytes each in size
815 pp->crpb_dma = mem_dma;
817 mem_dma += MV_CRPB_Q_SZ;
820 * Table of scatter-gather descriptors (ePRD), 16 bytes each
823 pp->sg_tbl_dma = mem_dma;
825 writelfl(EDMA_CFG_Q_DEPTH | EDMA_CFG_RD_BRST_EXT |
826 EDMA_CFG_WR_BUFF_LEN, port_mmio + EDMA_CFG_OFS);
828 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
829 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
830 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
832 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
833 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
835 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
836 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
837 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
839 pp->req_producer = pp->rsp_consumer = 0;
841 /* Don't turn on EDMA here...do it before DMA commands only. Else
842 * we'll be unable to send non-data, PIO, etc due to restricted access
845 ap->private_data = pp;
849 mv_priv_free(pp, dev);
857 * mv_port_stop - Port specific cleanup/stop routine.
858 * @ap: ATA channel to manipulate
860 * Stop DMA, cleanup port memory.
863 * This routine uses the host_set lock to protect the DMA stop.
865 static void mv_port_stop(struct ata_port *ap)
867 struct device *dev = ap->host_set->dev;
868 struct mv_port_priv *pp = ap->private_data;
871 spin_lock_irqsave(&ap->host_set->lock, flags);
873 spin_unlock_irqrestore(&ap->host_set->lock, flags);
875 ap->private_data = NULL;
876 ata_pad_free(ap, dev);
877 mv_priv_free(pp, dev);
882 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
883 * @qc: queued command whose SG list to source from
885 * Populate the SG list and mark the last entry.
888 * Inherited from caller.
890 static void mv_fill_sg(struct ata_queued_cmd *qc)
892 struct mv_port_priv *pp = qc->ap->private_data;
894 struct scatterlist *sg;
896 ata_for_each_sg(sg, qc) {
898 u32 sg_len, len, offset;
900 addr = sg_dma_address(sg);
901 sg_len = sg_dma_len(sg);
904 offset = addr & MV_DMA_BOUNDARY;
906 if ((offset + sg_len) > 0x10000)
907 len = 0x10000 - offset;
909 pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff);
910 pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
911 pp->sg_tbl[i].flags_size = cpu_to_le32(len);
916 if (!sg_len && ata_sg_is_last(sg, qc))
917 pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
924 static inline unsigned mv_inc_q_index(unsigned *index)
926 *index = (*index + 1) & MV_MAX_Q_DEPTH_MASK;
930 static inline void mv_crqb_pack_cmd(u16 *cmdw, u8 data, u8 addr, unsigned last)
932 *cmdw = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
933 (last ? CRQB_CMD_LAST : 0);
937 * mv_qc_prep - Host specific command preparation.
938 * @qc: queued command to prepare
940 * This routine simply redirects to the general purpose routine
941 * if command is not DMA. Else, it handles prep of the CRQB
942 * (command request block), does some sanity checking, and calls
943 * the SG load routine.
946 * Inherited from caller.
948 static void mv_qc_prep(struct ata_queued_cmd *qc)
950 struct ata_port *ap = qc->ap;
951 struct mv_port_priv *pp = ap->private_data;
953 struct ata_taskfile *tf;
956 if (ATA_PROT_DMA != qc->tf.protocol) {
960 /* the req producer index should be the same as we remember it */
961 assert(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >>
962 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
965 /* Fill in command request block
967 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
968 flags |= CRQB_FLAG_READ;
970 assert(MV_MAX_Q_DEPTH > qc->tag);
971 flags |= qc->tag << CRQB_TAG_SHIFT;
973 pp->crqb[pp->req_producer].sg_addr =
974 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
975 pp->crqb[pp->req_producer].sg_addr_hi =
976 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
977 pp->crqb[pp->req_producer].ctrl_flags = cpu_to_le16(flags);
979 cw = &pp->crqb[pp->req_producer].ata_cmd[0];
982 /* Sadly, the CRQB cannot accomodate all registers--there are
983 * only 11 bytes...so we must pick and choose required
984 * registers based on the command. So, we drop feature and
985 * hob_feature for [RW] DMA commands, but they are needed for
986 * NCQ. NCQ will drop hob_nsect.
988 switch (tf->command) {
990 case ATA_CMD_READ_EXT:
992 case ATA_CMD_WRITE_EXT:
993 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
995 #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
996 case ATA_CMD_FPDMA_READ:
997 case ATA_CMD_FPDMA_WRITE:
998 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
999 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1001 #endif /* FIXME: remove this line when NCQ added */
1003 /* The only other commands EDMA supports in non-queued and
1004 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1005 * of which are defined/used by Linux. If we get here, this
1006 * driver needs work.
1008 * FIXME: modify libata to give qc_prep a return value and
1009 * return error here.
1011 BUG_ON(tf->command);
1014 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1015 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1016 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1017 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1018 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1019 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1020 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1021 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1022 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1024 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) {
1031 * mv_qc_issue - Initiate a command to the host
1032 * @qc: queued command to start
1034 * This routine simply redirects to the general purpose routine
1035 * if command is not DMA. Else, it sanity checks our local
1036 * caches of the request producer/consumer indices then enables
1037 * DMA and bumps the request producer index.
1040 * Inherited from caller.
1042 static int mv_qc_issue(struct ata_queued_cmd *qc)
1044 void __iomem *port_mmio = mv_ap_base(qc->ap);
1045 struct mv_port_priv *pp = qc->ap->private_data;
1048 if (ATA_PROT_DMA != qc->tf.protocol) {
1049 /* We're about to send a non-EDMA capable command to the
1050 * port. Turn off EDMA so there won't be problems accessing
1051 * shadow block, etc registers.
1053 mv_stop_dma(qc->ap);
1054 return ata_qc_issue_prot(qc);
1057 in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1059 /* the req producer index should be the same as we remember it */
1060 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1062 /* until we do queuing, the queue should be empty at this point */
1063 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1064 ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) >>
1065 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
1067 mv_inc_q_index(&pp->req_producer); /* now incr producer index */
1069 mv_start_dma(port_mmio, pp);
1071 /* and write the request in pointer to kick the EDMA to life */
1072 in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
1073 in_ptr |= pp->req_producer << EDMA_REQ_Q_PTR_SHIFT;
1074 writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1080 * mv_get_crpb_status - get status from most recently completed cmd
1081 * @ap: ATA channel to manipulate
1083 * This routine is for use when the port is in DMA mode, when it
1084 * will be using the CRPB (command response block) method of
1085 * returning command completion information. We assert indices
1086 * are good, grab status, and bump the response consumer index to
1087 * prove that we're up to date.
1090 * Inherited from caller.
1092 static u8 mv_get_crpb_status(struct ata_port *ap)
1094 void __iomem *port_mmio = mv_ap_base(ap);
1095 struct mv_port_priv *pp = ap->private_data;
1098 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1100 /* the response consumer index should be the same as we remember it */
1101 assert(((out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1104 /* increment our consumer index... */
1105 pp->rsp_consumer = mv_inc_q_index(&pp->rsp_consumer);
1107 /* and, until we do NCQ, there should only be 1 CRPB waiting */
1108 assert(((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) >>
1109 EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1112 /* write out our inc'd consumer index so EDMA knows we're caught up */
1113 out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
1114 out_ptr |= pp->rsp_consumer << EDMA_RSP_Q_PTR_SHIFT;
1115 writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1117 /* Return ATA status register for completed CRPB */
1118 return (pp->crpb[pp->rsp_consumer].flags >> CRPB_FLAG_STATUS_SHIFT);
1122 * mv_err_intr - Handle error interrupts on the port
1123 * @ap: ATA channel to manipulate
1125 * In most cases, just clear the interrupt and move on. However,
1126 * some cases require an eDMA reset, which is done right before
1127 * the COMRESET in mv_phy_reset(). The SERR case requires a
1128 * clear of pending errors in the SATA SERROR register. Finally,
1129 * if the port disabled DMA, update our cached copy to match.
1132 * Inherited from caller.
1134 static void mv_err_intr(struct ata_port *ap)
1136 void __iomem *port_mmio = mv_ap_base(ap);
1137 u32 edma_err_cause, serr = 0;
1139 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1141 if (EDMA_ERR_SERR & edma_err_cause) {
1142 serr = scr_read(ap, SCR_ERROR);
1143 scr_write_flush(ap, SCR_ERROR, serr);
1145 if (EDMA_ERR_SELF_DIS & edma_err_cause) {
1146 struct mv_port_priv *pp = ap->private_data;
1147 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1149 DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
1150 "SERR: 0x%08x\n", ap->id, edma_err_cause, serr);
1152 /* Clear EDMA now that SERR cleanup done */
1153 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1155 /* check for fatal here and recover if needed */
1156 if (EDMA_ERR_FATAL & edma_err_cause) {
1157 mv_stop_and_reset(ap);
1162 * mv_host_intr - Handle all interrupts on the given host controller
1163 * @host_set: host specific structure
1164 * @relevant: port error bits relevant to this host controller
1165 * @hc: which host controller we're to look at
1167 * Read then write clear the HC interrupt status then walk each
1168 * port connected to the HC and see if it needs servicing. Port
1169 * success ints are reported in the HC interrupt status reg, the
1170 * port error ints are reported in the higher level main
1171 * interrupt status register and thus are passed in via the
1172 * 'relevant' argument.
1175 * Inherited from caller.
1177 static void mv_host_intr(struct ata_host_set *host_set, u32 relevant,
1180 void __iomem *mmio = host_set->mmio_base;
1181 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1182 struct ata_port *ap;
1183 struct ata_queued_cmd *qc;
1185 int shift, port, port0, hard_port, handled;
1186 unsigned int err_mask;
1192 port0 = MV_PORTS_PER_HC;
1195 /* we'll need the HC success int register in most cases */
1196 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1198 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1201 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1202 hc,relevant,hc_irq_cause);
1204 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
1205 ap = host_set->ports[port];
1206 hard_port = port & MV_PORT_MASK; /* range 0-3 */
1207 handled = 0; /* ensure ata_status is set if handled++ */
1209 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
1210 /* new CRPB on the queue; just one at a time until NCQ
1212 ata_status = mv_get_crpb_status(ap);
1214 } else if ((DEV_IRQ << hard_port) & hc_irq_cause) {
1215 /* received ATA IRQ; read the status reg to clear INTRQ
1217 ata_status = readb((void __iomem *)
1218 ap->ioaddr.status_addr);
1222 err_mask = ac_err_mask(ata_status);
1224 shift = port << 1; /* (port * 2) */
1225 if (port >= MV_PORTS_PER_HC) {
1226 shift++; /* skip bit 8 in the HC Main IRQ reg */
1228 if ((PORT0_ERR << shift) & relevant) {
1230 err_mask |= AC_ERR_OTHER;
1234 if (handled && ap) {
1235 qc = ata_qc_from_tag(ap, ap->active_tag);
1237 VPRINTK("port %u IRQ found for qc, "
1238 "ata_status 0x%x\n", port,ata_status);
1239 /* mark qc status appropriately */
1240 ata_qc_complete(qc, err_mask);
1250 * @dev_instance: private data; in this case the host structure
1253 * Read the read only register to determine if any host
1254 * controllers have pending interrupts. If so, call lower level
1255 * routine to handle. Also check for PCI errors which are only
1259 * This routine holds the host_set lock while processing pending
1262 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
1263 struct pt_regs *regs)
1265 struct ata_host_set *host_set = dev_instance;
1266 unsigned int hc, handled = 0, n_hcs;
1267 void __iomem *mmio = host_set->mmio_base;
1270 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
1272 /* check the cases where we either have nothing pending or have read
1273 * a bogus register value which can indicate HW removal or PCI fault
1275 if (!irq_stat || (0xffffffffU == irq_stat)) {
1279 n_hcs = mv_get_hc_count(host_set->ports[0]->flags);
1280 spin_lock(&host_set->lock);
1282 for (hc = 0; hc < n_hcs; hc++) {
1283 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1285 mv_host_intr(host_set, relevant, hc);
1289 if (PCI_ERR & irq_stat) {
1290 printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
1291 readl(mmio + PCI_IRQ_CAUSE_OFS));
1293 DPRINTK("All regs @ PCI error\n");
1294 mv_dump_all_regs(mmio, -1, to_pci_dev(host_set->dev));
1296 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1299 spin_unlock(&host_set->lock);
1301 return IRQ_RETVAL(handled);
1304 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
1306 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
1307 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
1309 return hc_mmio + ofs;
1312 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1316 switch (sc_reg_in) {
1320 ofs = sc_reg_in * sizeof(u32);
1329 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
1331 void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
1332 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1334 if (ofs != 0xffffffffU)
1335 return readl(mmio + ofs);
1340 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1342 void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
1343 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1345 if (ofs != 0xffffffffU)
1346 writelfl(val, mmio + ofs);
1349 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
1354 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1356 early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
1359 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1361 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1364 mv_reset_pci_bus(pdev, mmio);
1367 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1369 writel(0x0fcfffff, mmio + MV_FLASH_CTL);
1372 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
1375 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1378 tmp = readl(phy_mmio + MV5_PHY_MODE);
1380 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1381 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
1384 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1388 writel(0, mmio + MV_GPIO_PORT_CTL);
1390 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1392 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1394 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1397 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1400 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1401 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1403 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1406 tmp = readl(phy_mmio + MV5_LT_MODE);
1408 writel(tmp, phy_mmio + MV5_LT_MODE);
1410 tmp = readl(phy_mmio + MV5_PHY_CTL);
1413 writel(tmp, phy_mmio + MV5_PHY_CTL);
1416 tmp = readl(phy_mmio + MV5_PHY_MODE);
1418 tmp |= hpriv->signal[port].pre;
1419 tmp |= hpriv->signal[port].amps;
1420 writel(tmp, phy_mmio + MV5_PHY_MODE);
1425 #define ZERO(reg) writel(0, port_mmio + (reg))
1426 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1429 void __iomem *port_mmio = mv_port_base(mmio, port);
1431 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1433 mv_channel_reset(hpriv, mmio, port);
1435 ZERO(0x028); /* command */
1436 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1437 ZERO(0x004); /* timer */
1438 ZERO(0x008); /* irq err cause */
1439 ZERO(0x00c); /* irq err mask */
1440 ZERO(0x010); /* rq bah */
1441 ZERO(0x014); /* rq inp */
1442 ZERO(0x018); /* rq outp */
1443 ZERO(0x01c); /* respq bah */
1444 ZERO(0x024); /* respq outp */
1445 ZERO(0x020); /* respq inp */
1446 ZERO(0x02c); /* test control */
1447 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
1451 #define ZERO(reg) writel(0, hc_mmio + (reg))
1452 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1455 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1463 tmp = readl(hc_mmio + 0x20);
1466 writel(tmp, hc_mmio + 0x20);
1470 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1473 unsigned int hc, port;
1475 for (hc = 0; hc < n_hc; hc++) {
1476 for (port = 0; port < MV_PORTS_PER_HC; port++)
1477 mv5_reset_hc_port(hpriv, mmio,
1478 (hc * MV_PORTS_PER_HC) + port);
1480 mv5_reset_one_hc(hpriv, mmio, hc);
1487 #define ZERO(reg) writel(0, mmio + (reg))
1488 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
1492 tmp = readl(mmio + MV_PCI_MODE);
1494 writel(tmp, mmio + MV_PCI_MODE);
1496 ZERO(MV_PCI_DISC_TIMER);
1497 ZERO(MV_PCI_MSI_TRIGGER);
1498 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
1499 ZERO(HC_MAIN_IRQ_MASK_OFS);
1500 ZERO(MV_PCI_SERR_MASK);
1501 ZERO(PCI_IRQ_CAUSE_OFS);
1502 ZERO(PCI_IRQ_MASK_OFS);
1503 ZERO(MV_PCI_ERR_LOW_ADDRESS);
1504 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
1505 ZERO(MV_PCI_ERR_ATTRIBUTE);
1506 ZERO(MV_PCI_ERR_COMMAND);
1510 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1514 mv5_reset_flash(hpriv, mmio);
1516 tmp = readl(mmio + MV_GPIO_PORT_CTL);
1518 tmp |= (1 << 5) | (1 << 6);
1519 writel(tmp, mmio + MV_GPIO_PORT_CTL);
1523 * mv6_reset_hc - Perform the 6xxx global soft reset
1524 * @mmio: base address of the HBA
1526 * This routine only applies to 6xxx parts.
1529 * Inherited from caller.
1531 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1534 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
1538 /* Following procedure defined in PCI "main command and status
1542 writel(t | STOP_PCI_MASTER, reg);
1544 for (i = 0; i < 1000; i++) {
1547 if (PCI_MASTER_EMPTY & t) {
1551 if (!(PCI_MASTER_EMPTY & t)) {
1552 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
1560 writel(t | GLOB_SFT_RST, reg);
1563 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
1565 if (!(GLOB_SFT_RST & t)) {
1566 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
1571 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
1574 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
1577 } while ((GLOB_SFT_RST & t) && (i-- > 0));
1579 if (GLOB_SFT_RST & t) {
1580 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
1587 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
1590 void __iomem *port_mmio;
1593 tmp = readl(mmio + MV_RESET_CFG);
1594 if ((tmp & (1 << 0)) == 0) {
1595 hpriv->signal[idx].amps = 0x7 << 8;
1596 hpriv->signal[idx].pre = 0x1 << 5;
1600 port_mmio = mv_port_base(mmio, idx);
1601 tmp = readl(port_mmio + PHY_MODE2);
1603 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
1604 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
1607 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1609 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
1612 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1615 void __iomem *port_mmio = mv_port_base(mmio, port);
1617 u32 hp_flags = hpriv->hp_flags;
1619 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1621 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1624 if (fix_phy_mode2) {
1625 m2 = readl(port_mmio + PHY_MODE2);
1628 writel(m2, port_mmio + PHY_MODE2);
1632 m2 = readl(port_mmio + PHY_MODE2);
1633 m2 &= ~((1 << 16) | (1 << 31));
1634 writel(m2, port_mmio + PHY_MODE2);
1639 /* who knows what this magic does */
1640 tmp = readl(port_mmio + PHY_MODE3);
1643 writel(tmp, port_mmio + PHY_MODE3);
1645 if (fix_phy_mode4) {
1648 m4 = readl(port_mmio + PHY_MODE4);
1650 if (hp_flags & MV_HP_ERRATA_60X1B2)
1651 tmp = readl(port_mmio + 0x310);
1653 m4 = (m4 & ~(1 << 1)) | (1 << 0);
1655 writel(m4, port_mmio + PHY_MODE4);
1657 if (hp_flags & MV_HP_ERRATA_60X1B2)
1658 writel(tmp, port_mmio + 0x310);
1661 /* Revert values of pre-emphasis and signal amps to the saved ones */
1662 m2 = readl(port_mmio + PHY_MODE2);
1664 m2 &= ~MV_M2_PREAMP_MASK;
1665 m2 |= hpriv->signal[port].amps;
1666 m2 |= hpriv->signal[port].pre;
1669 writel(m2, port_mmio + PHY_MODE2);
1672 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
1673 unsigned int port_no)
1675 void __iomem *port_mmio = mv_port_base(mmio, port_no);
1677 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1679 if (IS_60XX(hpriv)) {
1680 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
1681 ifctl |= (1 << 12) | (1 << 7);
1682 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
1685 udelay(25); /* allow reset propagation */
1687 /* Spec never mentions clearing the bit. Marvell's driver does
1688 * clear the bit, however.
1690 writelfl(0, port_mmio + EDMA_CMD_OFS);
1692 hpriv->ops->phy_errata(hpriv, mmio, port_no);
1698 static void mv_stop_and_reset(struct ata_port *ap)
1700 struct mv_host_priv *hpriv = ap->host_set->private_data;
1701 void __iomem *mmio = ap->host_set->mmio_base;
1705 mv_channel_reset(hpriv, mmio, ap->port_no);
1707 __mv_phy_reset(ap, 0);
1710 static inline void __msleep(unsigned int msec, int can_sleep)
1719 * __mv_phy_reset - Perform eDMA reset followed by COMRESET
1720 * @ap: ATA channel to manipulate
1722 * Part of this is taken from __sata_phy_reset and modified to
1723 * not sleep since this routine gets called from interrupt level.
1726 * Inherited from caller. This is coded to safe to call at
1727 * interrupt level, i.e. it does not sleep.
1729 static void __mv_phy_reset(struct ata_port *ap, int can_sleep)
1731 struct mv_port_priv *pp = ap->private_data;
1732 struct mv_host_priv *hpriv = ap->host_set->private_data;
1733 void __iomem *port_mmio = mv_ap_base(ap);
1734 struct ata_taskfile tf;
1735 struct ata_device *dev = &ap->device[0];
1736 unsigned long timeout;
1740 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1742 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1743 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1744 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1746 /* Issue COMRESET via SControl */
1748 scr_write_flush(ap, SCR_CONTROL, 0x301);
1749 __msleep(1, can_sleep);
1751 scr_write_flush(ap, SCR_CONTROL, 0x300);
1752 __msleep(20, can_sleep);
1754 timeout = jiffies + msecs_to_jiffies(200);
1756 sstatus = scr_read(ap, SCR_STATUS) & 0x3;
1757 if ((sstatus == 3) || (sstatus == 0))
1760 __msleep(1, can_sleep);
1761 } while (time_before(jiffies, timeout));
1763 /* work around errata */
1764 if (IS_60XX(hpriv) &&
1765 (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
1767 goto comreset_retry;
1769 DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
1770 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1771 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1773 if (sata_dev_present(ap)) {
1776 printk(KERN_INFO "ata%u: no device found (phy stat %08x)\n",
1777 ap->id, scr_read(ap, SCR_STATUS));
1778 ata_port_disable(ap);
1781 ap->cbl = ATA_CBL_SATA;
1783 /* even after SStatus reflects that device is ready,
1784 * it seems to take a while for link to be fully
1785 * established (and thus Status no longer 0x80/0x7F),
1786 * so we poll a bit for that, here.
1790 u8 drv_stat = ata_check_status(ap);
1791 if ((drv_stat != 0x80) && (drv_stat != 0x7f))
1793 __msleep(500, can_sleep);
1798 tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr);
1799 tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr);
1800 tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr);
1801 tf.nsect = readb((void __iomem *) ap->ioaddr.nsect_addr);
1803 dev->class = ata_dev_classify(&tf);
1804 if (!ata_dev_present(dev)) {
1805 VPRINTK("Port disabled post-sig: No device present.\n");
1806 ata_port_disable(ap);
1809 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1811 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1816 static void mv_phy_reset(struct ata_port *ap)
1818 __mv_phy_reset(ap, 1);
1822 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
1823 * @ap: ATA channel to manipulate
1825 * Intent is to clear all pending error conditions, reset the
1826 * chip/bus, fail the command, and move on.
1829 * This routine holds the host_set lock while failing the command.
1831 static void mv_eng_timeout(struct ata_port *ap)
1833 struct ata_queued_cmd *qc;
1834 unsigned long flags;
1836 printk(KERN_ERR "ata%u: Entering mv_eng_timeout\n",ap->id);
1837 DPRINTK("All regs @ start of eng_timeout\n");
1838 mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no,
1839 to_pci_dev(ap->host_set->dev));
1841 qc = ata_qc_from_tag(ap, ap->active_tag);
1842 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
1843 ap->host_set->mmio_base, ap, qc, qc->scsicmd,
1844 &qc->scsicmd->cmnd);
1847 mv_stop_and_reset(ap);
1850 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
1853 /* hack alert! We cannot use the supplied completion
1854 * function from inside the ->eh_strategy_handler() thread.
1855 * libata is the only user of ->eh_strategy_handler() in
1856 * any kernel, so the default scsi_done() assumes it is
1857 * not being called from the SCSI EH.
1859 spin_lock_irqsave(&ap->host_set->lock, flags);
1860 qc->scsidone = scsi_finish_command;
1861 ata_qc_complete(qc, AC_ERR_OTHER);
1862 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1867 * mv_port_init - Perform some early initialization on a single port.
1868 * @port: libata data structure storing shadow register addresses
1869 * @port_mmio: base address of the port
1871 * Initialize shadow register mmio addresses, clear outstanding
1872 * interrupts on the port, and unmask interrupts for the future
1873 * start of the port.
1876 * Inherited from caller.
1878 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
1880 unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS;
1883 /* PIO related setup
1885 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
1887 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
1888 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
1889 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
1890 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
1891 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
1892 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
1894 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
1895 /* special case: control/altstatus doesn't have ATA_REG_ address */
1896 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
1899 port->cmd_addr = port->bmdma_addr = port->scr_addr = 0;
1901 /* Clear any currently outstanding port interrupt conditions */
1902 serr_ofs = mv_scr_offset(SCR_ERROR);
1903 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
1904 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1906 /* unmask all EDMA error interrupts */
1907 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
1909 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
1910 readl(port_mmio + EDMA_CFG_OFS),
1911 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
1912 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
1915 static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
1916 unsigned int board_idx)
1919 u32 hp_flags = hpriv->hp_flags;
1921 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1925 hpriv->ops = &mv5xxx_ops;
1926 hp_flags |= MV_HP_50XX;
1930 hp_flags |= MV_HP_ERRATA_50XXB0;
1933 hp_flags |= MV_HP_ERRATA_50XXB2;
1936 dev_printk(KERN_WARNING, &pdev->dev,
1937 "Applying 50XXB2 workarounds to unknown rev\n");
1938 hp_flags |= MV_HP_ERRATA_50XXB2;
1945 hpriv->ops = &mv5xxx_ops;
1946 hp_flags |= MV_HP_50XX;
1950 hp_flags |= MV_HP_ERRATA_50XXB0;
1953 hp_flags |= MV_HP_ERRATA_50XXB2;
1956 dev_printk(KERN_WARNING, &pdev->dev,
1957 "Applying B2 workarounds to unknown rev\n");
1958 hp_flags |= MV_HP_ERRATA_50XXB2;
1965 hpriv->ops = &mv6xxx_ops;
1969 hp_flags |= MV_HP_ERRATA_60X1B2;
1972 hp_flags |= MV_HP_ERRATA_60X1C0;
1975 dev_printk(KERN_WARNING, &pdev->dev,
1976 "Applying B2 workarounds to unknown rev\n");
1977 hp_flags |= MV_HP_ERRATA_60X1B2;
1983 printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
1987 hpriv->hp_flags = hp_flags;
1993 * mv_init_host - Perform some early initialization of the host.
1994 * @pdev: host PCI device
1995 * @probe_ent: early data struct representing the host
1997 * If possible, do an early global reset of the host. Then do
1998 * our port init and clear/unmask all/relevant host interrupts.
2001 * Inherited from caller.
2003 static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
2004 unsigned int board_idx)
2006 int rc = 0, n_hc, port, hc;
2007 void __iomem *mmio = probe_ent->mmio_base;
2008 struct mv_host_priv *hpriv = probe_ent->private_data;
2010 /* global interrupt mask */
2011 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
2013 rc = mv_chip_id(pdev, hpriv, board_idx);
2017 n_hc = mv_get_hc_count(probe_ent->host_flags);
2018 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
2020 for (port = 0; port < probe_ent->n_ports; port++)
2021 hpriv->ops->read_preamp(hpriv, port, mmio);
2023 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
2027 hpriv->ops->reset_flash(hpriv, mmio);
2028 hpriv->ops->reset_bus(pdev, mmio);
2029 hpriv->ops->enable_leds(hpriv, mmio);
2031 for (port = 0; port < probe_ent->n_ports; port++) {
2032 if (IS_60XX(hpriv)) {
2033 void __iomem *port_mmio = mv_port_base(mmio, port);
2035 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
2037 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
2040 hpriv->ops->phy_errata(hpriv, mmio, port);
2043 for (port = 0; port < probe_ent->n_ports; port++) {
2044 void __iomem *port_mmio = mv_port_base(mmio, port);
2045 mv_port_init(&probe_ent->port[port], port_mmio);
2048 for (hc = 0; hc < n_hc; hc++) {
2049 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2051 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2052 "(before clear)=0x%08x\n", hc,
2053 readl(hc_mmio + HC_CFG_OFS),
2054 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2056 /* Clear any currently outstanding hc interrupt conditions */
2057 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
2060 /* Clear any currently outstanding host interrupt conditions */
2061 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
2063 /* and unmask interrupt generation for host regs */
2064 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
2065 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
2067 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
2068 "PCI int cause/mask=0x%08x/0x%08x\n",
2069 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
2070 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
2071 readl(mmio + PCI_IRQ_CAUSE_OFS),
2072 readl(mmio + PCI_IRQ_MASK_OFS));
2079 * mv_print_info - Dump key info to kernel log for perusal.
2080 * @probe_ent: early data struct representing the host
2082 * FIXME: complete this.
2085 * Inherited from caller.
2087 static void mv_print_info(struct ata_probe_ent *probe_ent)
2089 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
2090 struct mv_host_priv *hpriv = probe_ent->private_data;
2094 /* Use this to determine the HW stepping of the chip so we know
2095 * what errata to workaround
2097 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2099 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
2102 else if (scc == 0x01)
2107 dev_printk(KERN_INFO, &pdev->dev,
2108 "%u slots %u ports %s mode IRQ via %s\n",
2109 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
2110 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
2114 * mv_init_one - handle a positive probe of a Marvell host
2115 * @pdev: PCI device found
2116 * @ent: PCI device ID entry for the matched host
2119 * Inherited from caller.
2121 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2123 static int printed_version = 0;
2124 struct ata_probe_ent *probe_ent = NULL;
2125 struct mv_host_priv *hpriv;
2126 unsigned int board_idx = (unsigned int)ent->driver_data;
2127 void __iomem *mmio_base;
2128 int pci_dev_busy = 0, rc;
2130 if (!printed_version++)
2131 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
2133 rc = pci_enable_device(pdev);
2138 rc = pci_request_regions(pdev, DRV_NAME);
2144 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
2145 if (probe_ent == NULL) {
2147 goto err_out_regions;
2150 memset(probe_ent, 0, sizeof(*probe_ent));
2151 probe_ent->dev = pci_dev_to_dev(pdev);
2152 INIT_LIST_HEAD(&probe_ent->node);
2154 mmio_base = pci_iomap(pdev, MV_PRIMARY_BAR, 0);
2155 if (mmio_base == NULL) {
2157 goto err_out_free_ent;
2160 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
2163 goto err_out_iounmap;
2165 memset(hpriv, 0, sizeof(*hpriv));
2167 probe_ent->sht = mv_port_info[board_idx].sht;
2168 probe_ent->host_flags = mv_port_info[board_idx].host_flags;
2169 probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
2170 probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
2171 probe_ent->port_ops = mv_port_info[board_idx].port_ops;
2173 probe_ent->irq = pdev->irq;
2174 probe_ent->irq_flags = SA_SHIRQ;
2175 probe_ent->mmio_base = mmio_base;
2176 probe_ent->private_data = hpriv;
2178 /* initialize adapter */
2179 rc = mv_init_host(pdev, probe_ent, board_idx);
2184 /* Enable interrupts */
2185 if (pci_enable_msi(pdev) == 0) {
2186 hpriv->hp_flags |= MV_HP_FLAG_MSI;
2191 mv_dump_pci_cfg(pdev, 0x68);
2192 mv_print_info(probe_ent);
2194 if (ata_device_add(probe_ent) == 0) {
2195 rc = -ENODEV; /* No devices discovered */
2196 goto err_out_dev_add;
2203 if (MV_HP_FLAG_MSI & hpriv->hp_flags) {
2204 pci_disable_msi(pdev);
2211 pci_iounmap(pdev, mmio_base);
2215 pci_release_regions(pdev);
2217 if (!pci_dev_busy) {
2218 pci_disable_device(pdev);
2224 static int __init mv_init(void)
2226 return pci_module_init(&mv_pci_driver);
2229 static void __exit mv_exit(void)
2231 pci_unregister_driver(&mv_pci_driver);
2234 MODULE_AUTHOR("Brett Russ");
2235 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
2236 MODULE_LICENSE("GPL");
2237 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
2238 MODULE_VERSION(DRV_VERSION);
2240 module_init(mv_init);
2241 module_exit(mv_exit);