SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/scsi/qla2xxx/qla_nx.c

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2008 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7 #include "qla_def.h"
   8 #include <linux/delay.h>
   9 #include <linux/pci.h>
  10
  11 #define MASK(n)                 ((1ULL<<(n))-1)
  12 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
  13         ((addr >> 25) & 0x3ff))
  14 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
  15         ((addr >> 25) & 0x3ff))
  16 #define MS_WIN(addr) (addr & 0x0ffc0000)
  17 #define QLA82XX_PCI_MN_2M   (0)
  18 #define QLA82XX_PCI_MS_2M   (0x80000)
  19 #define QLA82XX_PCI_OCM0_2M (0xc0000)
  20 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
  21 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
  22
  23 /* CRB window related */
  24 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
  25 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  26 #define CRB_WINDOW_2M   (0x130060)
  27 #define QLA82XX_PCI_CAMQM_2M_END        (0x04800800UL)
  28 #define CRB_HI(off)     ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
  29                         ((off) & 0xf0000))
  30 #define QLA82XX_PCI_CAMQM_2M_BASE       (0x000ff800UL)
  31 #define CRB_INDIRECT_2M (0x1e0000UL)
  32
  33 #define MAX_CRB_XFORM 60
  34 static unsigned long crb_addr_xform[MAX_CRB_XFORM];
  35 int qla82xx_crb_table_initialized;
  36
  37 #define qla82xx_crb_addr_transform(name) \
  38         (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
  39         QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
  40
  41 static void qla82xx_crb_addr_transform_setup(void)
  42 {
  43         qla82xx_crb_addr_transform(XDMA);
  44         qla82xx_crb_addr_transform(TIMR);
  45         qla82xx_crb_addr_transform(SRE);
  46         qla82xx_crb_addr_transform(SQN3);
  47         qla82xx_crb_addr_transform(SQN2);
  48         qla82xx_crb_addr_transform(SQN1);
  49         qla82xx_crb_addr_transform(SQN0);
  50         qla82xx_crb_addr_transform(SQS3);
  51         qla82xx_crb_addr_transform(SQS2);
  52         qla82xx_crb_addr_transform(SQS1);
  53         qla82xx_crb_addr_transform(SQS0);
  54         qla82xx_crb_addr_transform(RPMX7);
  55         qla82xx_crb_addr_transform(RPMX6);
  56         qla82xx_crb_addr_transform(RPMX5);
  57         qla82xx_crb_addr_transform(RPMX4);
  58         qla82xx_crb_addr_transform(RPMX3);
  59         qla82xx_crb_addr_transform(RPMX2);
  60         qla82xx_crb_addr_transform(RPMX1);
  61         qla82xx_crb_addr_transform(RPMX0);
  62         qla82xx_crb_addr_transform(ROMUSB);
  63         qla82xx_crb_addr_transform(SN);
  64         qla82xx_crb_addr_transform(QMN);
  65         qla82xx_crb_addr_transform(QMS);
  66         qla82xx_crb_addr_transform(PGNI);
  67         qla82xx_crb_addr_transform(PGND);
  68         qla82xx_crb_addr_transform(PGN3);
  69         qla82xx_crb_addr_transform(PGN2);
  70         qla82xx_crb_addr_transform(PGN1);
  71         qla82xx_crb_addr_transform(PGN0);
  72         qla82xx_crb_addr_transform(PGSI);
  73         qla82xx_crb_addr_transform(PGSD);
  74         qla82xx_crb_addr_transform(PGS3);
  75         qla82xx_crb_addr_transform(PGS2);
  76         qla82xx_crb_addr_transform(PGS1);
  77         qla82xx_crb_addr_transform(PGS0);
  78         qla82xx_crb_addr_transform(PS);
  79         qla82xx_crb_addr_transform(PH);
  80         qla82xx_crb_addr_transform(NIU);
  81         qla82xx_crb_addr_transform(I2Q);
  82         qla82xx_crb_addr_transform(EG);
  83         qla82xx_crb_addr_transform(MN);
  84         qla82xx_crb_addr_transform(MS);
  85         qla82xx_crb_addr_transform(CAS2);
  86         qla82xx_crb_addr_transform(CAS1);
  87         qla82xx_crb_addr_transform(CAS0);
  88         qla82xx_crb_addr_transform(CAM);
  89         qla82xx_crb_addr_transform(C2C1);
  90         qla82xx_crb_addr_transform(C2C0);
  91         qla82xx_crb_addr_transform(SMB);
  92         qla82xx_crb_addr_transform(OCM0);
  93         /*
  94          * Used only in P3 just define it for P2 also.
  95          */
  96         qla82xx_crb_addr_transform(I2C0);
  97
  98         qla82xx_crb_table_initialized = 1;
  99 }
 100
 101 struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
 102         {{{0, 0,         0,         0} } },
 103         {{{1, 0x0100000, 0x0102000, 0x120000},
 104         {1, 0x0110000, 0x0120000, 0x130000},
 105         {1, 0x0120000, 0x0122000, 0x124000},
 106         {1, 0x0130000, 0x0132000, 0x126000},
 107         {1, 0x0140000, 0x0142000, 0x128000},
 108         {1, 0x0150000, 0x0152000, 0x12a000},
 109         {1, 0x0160000, 0x0170000, 0x110000},
 110         {1, 0x0170000, 0x0172000, 0x12e000},
 111         {0, 0x0000000, 0x0000000, 0x000000},
 112         {0, 0x0000000, 0x0000000, 0x000000},
 113         {0, 0x0000000, 0x0000000, 0x000000},
 114         {0, 0x0000000, 0x0000000, 0x000000},
 115         {0, 0x0000000, 0x0000000, 0x000000},
 116         {0, 0x0000000, 0x0000000, 0x000000},
 117         {1, 0x01e0000, 0x01e0800, 0x122000},
 118         {0, 0x0000000, 0x0000000, 0x000000} } } ,
 119         {{{1, 0x0200000, 0x0210000, 0x180000} } },
 120         {{{0, 0,         0,         0} } },
 121         {{{1, 0x0400000, 0x0401000, 0x169000} } },
 122         {{{1, 0x0500000, 0x0510000, 0x140000} } },
 123         {{{1, 0x0600000, 0x0610000, 0x1c0000} } },
 124         {{{1, 0x0700000, 0x0704000, 0x1b8000} } },
 125         {{{1, 0x0800000, 0x0802000, 0x170000},
 126         {0, 0x0000000, 0x0000000, 0x000000},
 127         {0, 0x0000000, 0x0000000, 0x000000},
 128         {0, 0x0000000, 0x0000000, 0x000000},
 129         {0, 0x0000000, 0x0000000, 0x000000},
 130         {0, 0x0000000, 0x0000000, 0x000000},
 131         {0, 0x0000000, 0x0000000, 0x000000},
 132         {0, 0x0000000, 0x0000000, 0x000000},
 133         {0, 0x0000000, 0x0000000, 0x000000},
 134         {0, 0x0000000, 0x0000000, 0x000000},
 135         {0, 0x0000000, 0x0000000, 0x000000},
 136         {0, 0x0000000, 0x0000000, 0x000000},
 137         {0, 0x0000000, 0x0000000, 0x000000},
 138         {0, 0x0000000, 0x0000000, 0x000000},
 139         {0, 0x0000000, 0x0000000, 0x000000},
 140         {1, 0x08f0000, 0x08f2000, 0x172000} } },
 141         {{{1, 0x0900000, 0x0902000, 0x174000},
 142         {0, 0x0000000, 0x0000000, 0x000000},
 143         {0, 0x0000000, 0x0000000, 0x000000},
 144         {0, 0x0000000, 0x0000000, 0x000000},
 145         {0, 0x0000000, 0x0000000, 0x000000},
 146         {0, 0x0000000, 0x0000000, 0x000000},
 147         {0, 0x0000000, 0x0000000, 0x000000},
 148         {0, 0x0000000, 0x0000000, 0x000000},
 149         {0, 0x0000000, 0x0000000, 0x000000},
 150         {0, 0x0000000, 0x0000000, 0x000000},
 151         {0, 0x0000000, 0x0000000, 0x000000},
 152         {0, 0x0000000, 0x0000000, 0x000000},
 153         {0, 0x0000000, 0x0000000, 0x000000},
 154         {0, 0x0000000, 0x0000000, 0x000000},
 155         {0, 0x0000000, 0x0000000, 0x000000},
 156         {1, 0x09f0000, 0x09f2000, 0x176000} } },
 157         {{{0, 0x0a00000, 0x0a02000, 0x178000},
 158         {0, 0x0000000, 0x0000000, 0x000000},
 159         {0, 0x0000000, 0x0000000, 0x000000},
 160         {0, 0x0000000, 0x0000000, 0x000000},
 161         {0, 0x0000000, 0x0000000, 0x000000},
 162         {0, 0x0000000, 0x0000000, 0x000000},
 163         {0, 0x0000000, 0x0000000, 0x000000},
 164         {0, 0x0000000, 0x0000000, 0x000000},
 165         {0, 0x0000000, 0x0000000, 0x000000},
 166         {0, 0x0000000, 0x0000000, 0x000000},
 167         {0, 0x0000000, 0x0000000, 0x000000},
 168         {0, 0x0000000, 0x0000000, 0x000000},
 169         {0, 0x0000000, 0x0000000, 0x000000},
 170         {0, 0x0000000, 0x0000000, 0x000000},
 171         {0, 0x0000000, 0x0000000, 0x000000},
 172         {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 173         {{{0, 0x0b00000, 0x0b02000, 0x17c000},
 174         {0, 0x0000000, 0x0000000, 0x000000},
 175         {0, 0x0000000, 0x0000000, 0x000000},
 176         {0, 0x0000000, 0x0000000, 0x000000},
 177         {0, 0x0000000, 0x0000000, 0x000000},
 178         {0, 0x0000000, 0x0000000, 0x000000},
 179         {0, 0x0000000, 0x0000000, 0x000000},
 180         {0, 0x0000000, 0x0000000, 0x000000},
 181         {0, 0x0000000, 0x0000000, 0x000000},
 182         {0, 0x0000000, 0x0000000, 0x000000},
 183         {0, 0x0000000, 0x0000000, 0x000000},
 184         {0, 0x0000000, 0x0000000, 0x000000},
 185         {0, 0x0000000, 0x0000000, 0x000000},
 186         {0, 0x0000000, 0x0000000, 0x000000},
 187         {0, 0x0000000, 0x0000000, 0x000000},
 188         {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 189         {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
 190         {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
 191         {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
 192         {{{1, 0x0f00000, 0x0f01000, 0x164000} } },
 193         {{{0, 0x1000000, 0x1004000, 0x1a8000} } },
 194         {{{1, 0x1100000, 0x1101000, 0x160000} } },
 195         {{{1, 0x1200000, 0x1201000, 0x161000} } },
 196         {{{1, 0x1300000, 0x1301000, 0x162000} } },
 197         {{{1, 0x1400000, 0x1401000, 0x163000} } },
 198         {{{1, 0x1500000, 0x1501000, 0x165000} } },
 199         {{{1, 0x1600000, 0x1601000, 0x166000} } },
 200         {{{0, 0,         0,         0} } },
 201         {{{0, 0,         0,         0} } },
 202         {{{0, 0,         0,         0} } },
 203         {{{0, 0,         0,         0} } },
 204         {{{0, 0,         0,         0} } },
 205         {{{0, 0,         0,         0} } },
 206         {{{1, 0x1d00000, 0x1d10000, 0x190000} } },
 207         {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
 208         {{{1, 0x1f00000, 0x1f10000, 0x150000} } },
 209         {{{0} } },
 210         {{{1, 0x2100000, 0x2102000, 0x120000},
 211         {1, 0x2110000, 0x2120000, 0x130000},
 212         {1, 0x2120000, 0x2122000, 0x124000},
 213         {1, 0x2130000, 0x2132000, 0x126000},
 214         {1, 0x2140000, 0x2142000, 0x128000},
 215         {1, 0x2150000, 0x2152000, 0x12a000},
 216         {1, 0x2160000, 0x2170000, 0x110000},
 217         {1, 0x2170000, 0x2172000, 0x12e000},
 218         {0, 0x0000000, 0x0000000, 0x000000},
 219         {0, 0x0000000, 0x0000000, 0x000000},
 220         {0, 0x0000000, 0x0000000, 0x000000},
 221         {0, 0x0000000, 0x0000000, 0x000000},
 222         {0, 0x0000000, 0x0000000, 0x000000},
 223         {0, 0x0000000, 0x0000000, 0x000000},
 224         {0, 0x0000000, 0x0000000, 0x000000},
 225         {0, 0x0000000, 0x0000000, 0x000000} } },
 226         {{{1, 0x2200000, 0x2204000, 0x1b0000} } },
 227         {{{0} } },
 228         {{{0} } },
 229         {{{0} } },
 230         {{{0} } },
 231         {{{0} } },
 232         {{{1, 0x2800000, 0x2804000, 0x1a4000} } },
 233         {{{1, 0x2900000, 0x2901000, 0x16b000} } },
 234         {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
 235         {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
 236         {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
 237         {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
 238         {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
 239         {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
 240         {{{1, 0x3000000, 0x3000400, 0x1adc00} } },
 241         {{{0, 0x3100000, 0x3104000, 0x1a8000} } },
 242         {{{1, 0x3200000, 0x3204000, 0x1d4000} } },
 243         {{{1, 0x3300000, 0x3304000, 0x1a0000} } },
 244         {{{0} } },
 245         {{{1, 0x3500000, 0x3500400, 0x1ac000} } },
 246         {{{1, 0x3600000, 0x3600400, 0x1ae000} } },
 247         {{{1, 0x3700000, 0x3700400, 0x1ae400} } },
 248         {{{1, 0x3800000, 0x3804000, 0x1d0000} } },
 249         {{{1, 0x3900000, 0x3904000, 0x1b4000} } },
 250         {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
 251         {{{0} } },
 252         {{{0} } },
 253         {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },
 254         {{{1, 0x3e00000, 0x3e01000, 0x167000} } },
 255         {{{1, 0x3f00000, 0x3f01000, 0x168000} } }
 256 };
 257
 258 /*
 259  * top 12 bits of crb internal address (hub, agent)
 260  */
 261 unsigned qla82xx_crb_hub_agt[64] = {
 262         0,
 263         QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 264         QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
 265         QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
 266         0,
 267         QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
 268         QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
 269         QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
 270         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
 271         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
 272         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
 273         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
 274         QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 275         QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 276         QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 277         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
 278         QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 279         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
 280         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
 281         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
 282         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
 283         QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
 284         QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
 285         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
 286         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
 287         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
 288         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
 289         0,
 290         QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
 291         QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
 292         0,
 293         QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
 294         0,
 295         QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 296         QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
 297         0,
 298         0,
 299         0,
 300         0,
 301         0,
 302         QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 303         0,
 304         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
 305         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
 306         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
 307         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
 308         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
 309         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
 310         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
 311         QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 312         QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 313         QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 314         0,
 315         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
 316         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
 317         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
 318         QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
 319         0,
 320         QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
 321         QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
 322         QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
 323         0,
 324         QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
 325         0,
 326 };
 327
 328 /* Device states */
 329 char *qdev_state[] = {
 330          "Unknown",
 331         "Cold",
 332         "Initializing",
 333         "Ready",
 334         "Need Reset",
 335         "Need Quiescent",
 336         "Failed",
 337         "Quiescent",
 338 };
 339
 340 /*
 341  * In: 'off' is offset from CRB space in 128M pci map
 342  * Out: 'off' is 2M pci map addr
 343  * side effect: lock crb window
 344  */
 345 static void
 346 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off)
 347 {
 348         u32 win_read;
 349
 350         ha->crb_win = CRB_HI(*off);
 351         writel(ha->crb_win,
 352                 (void *)(CRB_WINDOW_2M + ha->nx_pcibase));
 353
 354         /* Read back value to make sure write has gone through before trying
 355          * to use it.
 356          */
 357         win_read = RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase));
 358         if (win_read != ha->crb_win) {
 359                 DEBUG2(qla_printk(KERN_INFO, ha,
 360                     "%s: Written crbwin (0x%x) != Read crbwin (0x%x), "
 361                     "off=0x%lx\n", __func__, ha->crb_win, win_read, *off));
 362         }
 363         *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
 364 }
 365
 366 static inline unsigned long
 367 qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off)
 368 {
 369         /* See if we are currently pointing to the region we want to use next */
 370         if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) {
 371                 /* No need to change window. PCIX and PCIEregs are in both
 372                  * regs are in both windows.
 373                  */
 374                 return off;
 375         }
 376
 377         if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) {
 378                 /* We are in first CRB window */
 379                 if (ha->curr_window != 0)
 380                         WARN_ON(1);
 381                 return off;
 382         }
 383
 384         if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) {
 385                 /* We are in second CRB window */
 386                 off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST;
 387
 388                 if (ha->curr_window != 1)
 389                         return off;
 390
 391                 /* We are in the QM or direct access
 392                  * register region - do nothing
 393                  */
 394                 if ((off >= QLA82XX_PCI_DIRECT_CRB) &&
 395                         (off < QLA82XX_PCI_CAMQM_MAX))
 396                         return off;
 397         }
 398         /* strange address given */
 399         qla_printk(KERN_WARNING, ha,
 400                 "%s: Warning: unm_nic_pci_set_crbwindow called with"
 401                 " an unknown address(%llx)\n", QLA2XXX_DRIVER_NAME, off);
 402         return off;
 403 }
 404
 405 int
 406 qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data)
 407 {
 408         unsigned long flags = 0;
 409         int rv;
 410
 411         rv = qla82xx_pci_get_crb_addr_2M(ha, &off);
 412
 413         BUG_ON(rv == -1);
 414
 415         if (rv == 1) {
 416                 write_lock_irqsave(&ha->hw_lock, flags);
 417                 qla82xx_crb_win_lock(ha);
 418                 qla82xx_pci_set_crbwindow_2M(ha, &off);
 419         }
 420
 421         writel(data, (void __iomem *)off);
 422
 423         if (rv == 1) {
 424                 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
 425                 write_unlock_irqrestore(&ha->hw_lock, flags);
 426         }
 427         return 0;
 428 }
 429
 430 int
 431 qla82xx_rd_32(struct qla_hw_data *ha, ulong off)
 432 {
 433         unsigned long flags = 0;
 434         int rv;
 435         u32 data;
 436
 437         rv = qla82xx_pci_get_crb_addr_2M(ha, &off);
 438
 439         BUG_ON(rv == -1);
 440
 441         if (rv == 1) {
 442                 write_lock_irqsave(&ha->hw_lock, flags);
 443                 qla82xx_crb_win_lock(ha);
 444                 qla82xx_pci_set_crbwindow_2M(ha, &off);
 445         }
 446         data = RD_REG_DWORD((void __iomem *)off);
 447
 448         if (rv == 1) {
 449                 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
 450                 write_unlock_irqrestore(&ha->hw_lock, flags);
 451         }
 452         return data;
 453 }
 454
 455 #define CRB_WIN_LOCK_TIMEOUT 100000000
 456 int qla82xx_crb_win_lock(struct qla_hw_data *ha)
 457 {
 458         int done = 0, timeout = 0;
 459
 460         while (!done) {
 461                 /* acquire semaphore3 from PCI HW block */
 462                 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
 463                 if (done == 1)
 464                         break;
 465                 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
 466                         return -1;
 467                 timeout++;
 468         }
 469         qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum);
 470         return 0;
 471 }
 472
 473 #define IDC_LOCK_TIMEOUT 100000000
 474 int qla82xx_idc_lock(struct qla_hw_data *ha)
 475 {
 476         int i;
 477         int done = 0, timeout = 0;
 478
 479         while (!done) {
 480                 /* acquire semaphore5 from PCI HW block */
 481                 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
 482                 if (done == 1)
 483                         break;
 484                 if (timeout >= IDC_LOCK_TIMEOUT)
 485                         return -1;
 486
 487                 timeout++;
 488
 489                 /* Yield CPU */
 490                 if (!in_interrupt())
 491                         schedule();
 492                 else {
 493                         for (i = 0; i < 20; i++)
 494                                 cpu_relax();
 495                 }
 496         }
 497
 498         return 0;
 499 }
 500
 501 void qla82xx_idc_unlock(struct qla_hw_data *ha)
 502 {
 503         qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
 504 }
 505
 506 int
 507 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off)
 508 {
 509         struct crb_128M_2M_sub_block_map *m;
 510
 511         if (*off >= QLA82XX_CRB_MAX)
 512                 return -1;
 513
 514         if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
 515                 *off = (*off - QLA82XX_PCI_CAMQM) +
 516                     QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
 517                 return 0;
 518         }
 519
 520         if (*off < QLA82XX_PCI_CRBSPACE)
 521                 return -1;
 522
 523         *off -= QLA82XX_PCI_CRBSPACE;
 524
 525         /* Try direct map */
 526         m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
 527
 528         if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
 529                 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
 530                 return 0;
 531         }
 532         /* Not in direct map, use crb window */
 533         return 1;
 534 }
 535
 536 /*  PCI Windowing for DDR regions.  */
 537 #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \
 538         (((addr) <= (high)) && ((addr) >= (low)))
 539 /*
 540  * check memory access boundary.
 541  * used by test agent. support ddr access only for now
 542  */
 543 static unsigned long
 544 qla82xx_pci_mem_bound_check(struct qla_hw_data *ha,
 545         unsigned long long addr, int size)
 546 {
 547         if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
 548                 QLA82XX_ADDR_DDR_NET_MAX) ||
 549                 !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET,
 550                 QLA82XX_ADDR_DDR_NET_MAX) ||
 551                 ((size != 1) && (size != 2) && (size != 4) && (size != 8)))
 552                         return 0;
 553         else
 554                 return 1;
 555 }
 556
 557 int qla82xx_pci_set_window_warning_count;
 558
 559 unsigned long
 560 qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr)
 561 {
 562         int window;
 563         u32 win_read;
 564
 565         if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
 566                 QLA82XX_ADDR_DDR_NET_MAX)) {
 567                 /* DDR network side */
 568                 window = MN_WIN(addr);
 569                 ha->ddr_mn_window = window;
 570                 qla82xx_wr_32(ha,
 571                         ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
 572                 win_read = qla82xx_rd_32(ha,
 573                         ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
 574                 if ((win_read << 17) != window) {
 575                         qla_printk(KERN_WARNING, ha,
 576                             "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n",
 577                             __func__, window, win_read);
 578                 }
 579                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
 580         } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
 581                 QLA82XX_ADDR_OCM0_MAX)) {
 582                 unsigned int temp1;
 583                 if ((addr & 0x00ff800) == 0xff800) {
 584                         qla_printk(KERN_WARNING, ha,
 585                             "%s: QM access not handled.\n", __func__);
 586                         addr = -1UL;
 587                 }
 588                 window = OCM_WIN(addr);
 589                 ha->ddr_mn_window = window;
 590                 qla82xx_wr_32(ha,
 591                         ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
 592                 win_read = qla82xx_rd_32(ha,
 593                         ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
 594                 temp1 = ((window & 0x1FF) << 7) |
 595                     ((window & 0x0FFFE0000) >> 17);
 596                 if (win_read != temp1) {
 597                         qla_printk(KERN_WARNING, ha,
 598                             "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x)\n",
 599                             __func__, temp1, win_read);
 600                 }
 601                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
 602
 603         } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
 604                 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
 605                 /* QDR network side */
 606                 window = MS_WIN(addr);
 607                 ha->qdr_sn_window = window;
 608                 qla82xx_wr_32(ha,
 609                         ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window);
 610                 win_read = qla82xx_rd_32(ha,
 611                         ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
 612                 if (win_read != window) {
 613                         qla_printk(KERN_WARNING, ha,
 614                             "%s: Written MSwin (0x%x) != Read MSwin (0x%x)\n",
 615                             __func__, window, win_read);
 616                 }
 617                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
 618         } else {
 619                 /*
 620                  * peg gdb frequently accesses memory that doesn't exist,
 621                  * this limits the chit chat so debugging isn't slowed down.
 622                  */
 623                 if ((qla82xx_pci_set_window_warning_count++ < 8) ||
 624                     (qla82xx_pci_set_window_warning_count%64 == 0)) {
 625                         qla_printk(KERN_WARNING, ha,
 626                             "%s: Warning:%s Unknown address range!\n", __func__,
 627                             QLA2XXX_DRIVER_NAME);
 628                 }
 629                 addr = -1UL;
 630         }
 631         return addr;
 632 }
 633
 634 /* check if address is in the same windows as the previous access */
 635 static int qla82xx_pci_is_same_window(struct qla_hw_data *ha,
 636         unsigned long long addr)
 637 {
 638         int                     window;
 639         unsigned long long      qdr_max;
 640
 641         qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
 642
 643         /* DDR network side */
 644         if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
 645                 QLA82XX_ADDR_DDR_NET_MAX))
 646                 BUG();
 647         else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
 648                 QLA82XX_ADDR_OCM0_MAX))
 649                 return 1;
 650         else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1,
 651                 QLA82XX_ADDR_OCM1_MAX))
 652                 return 1;
 653         else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) {
 654                 /* QDR network side */
 655                 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
 656                 if (ha->qdr_sn_window == window)
 657                         return 1;
 658         }
 659         return 0;
 660 }
 661
 662 static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha,
 663         u64 off, void *data, int size)
 664 {
 665         unsigned long   flags;
 666         void           *addr = NULL;
 667         int             ret = 0;
 668         u64             start;
 669         uint8_t         *mem_ptr = NULL;
 670         unsigned long   mem_base;
 671         unsigned long   mem_page;
 672
 673         write_lock_irqsave(&ha->hw_lock, flags);
 674
 675         /*
 676          * If attempting to access unknown address or straddle hw windows,
 677          * do not access.
 678          */
 679         start = qla82xx_pci_set_window(ha, off);
 680         if ((start == -1UL) ||
 681                 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
 682                 write_unlock_irqrestore(&ha->hw_lock, flags);
 683                 qla_printk(KERN_ERR, ha,
 684                         "%s out of bound pci memory access. "
 685                         "offset is 0x%llx\n", QLA2XXX_DRIVER_NAME, off);
 686                 return -1;
 687         }
 688
 689         write_unlock_irqrestore(&ha->hw_lock, flags);
 690         mem_base = pci_resource_start(ha->pdev, 0);
 691         mem_page = start & PAGE_MASK;
 692         /* Map two pages whenever user tries to access addresses in two
 693         * consecutive pages.
 694         */
 695         if (mem_page != ((start + size - 1) & PAGE_MASK))
 696                 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
 697         else
 698                 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 699         if (mem_ptr == 0UL) {
 700                 *(u8  *)data = 0;
 701                 return -1;
 702         }
 703         addr = mem_ptr;
 704         addr += start & (PAGE_SIZE - 1);
 705         write_lock_irqsave(&ha->hw_lock, flags);
 706
 707         switch (size) {
 708         case 1:
 709                 *(u8  *)data = readb(addr);
 710                 break;
 711         case 2:
 712                 *(u16 *)data = readw(addr);
 713                 break;
 714         case 4:
 715                 *(u32 *)data = readl(addr);
 716                 break;
 717         case 8:
 718                 *(u64 *)data = readq(addr);
 719                 break;
 720         default:
 721                 ret = -1;
 722                 break;
 723         }
 724         write_unlock_irqrestore(&ha->hw_lock, flags);
 725
 726         if (mem_ptr)
 727                 iounmap(mem_ptr);
 728         return ret;
 729 }
 730
 731 static int
 732 qla82xx_pci_mem_write_direct(struct qla_hw_data *ha,
 733         u64 off, void *data, int size)
 734 {
 735         unsigned long   flags;
 736         void           *addr = NULL;
 737         int             ret = 0;
 738         u64             start;
 739         uint8_t         *mem_ptr = NULL;
 740         unsigned long   mem_base;
 741         unsigned long   mem_page;
 742
 743         write_lock_irqsave(&ha->hw_lock, flags);
 744
 745         /*
 746          * If attempting to access unknown address or straddle hw windows,
 747          * do not access.
 748          */
 749         start = qla82xx_pci_set_window(ha, off);
 750         if ((start == -1UL) ||
 751                 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
 752                 write_unlock_irqrestore(&ha->hw_lock, flags);
 753                 qla_printk(KERN_ERR, ha,
 754                         "%s out of bound pci memory access. "
 755                         "offset is 0x%llx\n", QLA2XXX_DRIVER_NAME, off);
 756                 return -1;
 757         }
 758
 759         write_unlock_irqrestore(&ha->hw_lock, flags);
 760         mem_base = pci_resource_start(ha->pdev, 0);
 761         mem_page = start & PAGE_MASK;
 762         /* Map two pages whenever user tries to access addresses in two
 763          * consecutive pages.
 764          */
 765         if (mem_page != ((start + size - 1) & PAGE_MASK))
 766                 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
 767         else
 768                 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 769         if (mem_ptr == 0UL)
 770                 return -1;
 771
 772         addr = mem_ptr;
 773         addr += start & (PAGE_SIZE - 1);
 774         write_lock_irqsave(&ha->hw_lock, flags);
 775
 776         switch (size) {
 777         case 1:
 778                 writeb(*(u8  *)data, addr);
 779                 break;
 780         case 2:
 781                 writew(*(u16 *)data, addr);
 782                 break;
 783         case 4:
 784                 writel(*(u32 *)data, addr);
 785                 break;
 786         case 8:
 787                 writeq(*(u64 *)data, addr);
 788                 break;
 789         default:
 790                 ret = -1;
 791                 break;
 792         }
 793         write_unlock_irqrestore(&ha->hw_lock, flags);
 794         if (mem_ptr)
 795                 iounmap(mem_ptr);
 796         return ret;
 797 }
 798
 799 int
 800 qla82xx_wrmem(struct qla_hw_data *ha, u64 off, void *data, int size)
 801 {
 802         int i, j, ret = 0, loop, sz[2], off0;
 803         u32 temp;
 804         u64 off8, mem_crb, tmpw, word[2] = {0, 0};
 805 #define MAX_CTL_CHECK   1000
 806         /*
 807          * If not MN, go check for MS or invalid.
 808          */
 809         if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) {
 810                 mem_crb = QLA82XX_CRB_QDR_NET;
 811         } else {
 812                 mem_crb = QLA82XX_CRB_DDR_NET;
 813                 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
 814                         return qla82xx_pci_mem_write_direct(ha, off,
 815                             data, size);
 816         }
 817
 818         off8 = off & 0xfffffff8;
 819         off0 = off & 0x7;
 820         sz[0] = (size < (8 - off0)) ? size : (8 - off0);
 821         sz[1] = size - sz[0];
 822         loop = ((off0 + size - 1) >> 3) + 1;
 823
 824         if ((size != 8) || (off0 != 0))  {
 825                 for (i = 0; i < loop; i++) {
 826                         if (qla82xx_rdmem(ha, off8 + (i << 3), &word[i], 8))
 827                                 return -1;
 828                 }
 829         }
 830
 831         switch (size) {
 832         case 1:
 833                 tmpw = *((u8 *)data);
 834                 break;
 835         case 2:
 836                 tmpw = *((u16 *)data);
 837                 break;
 838         case 4:
 839                 tmpw = *((u32 *)data);
 840                 break;
 841         case 8:
 842         default:
 843                 tmpw = *((u64 *)data);
 844                 break;
 845         }
 846
 847         word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
 848         word[0] |= tmpw << (off0 * 8);
 849
 850         if (loop == 2) {
 851                 word[1] &= ~(~0ULL << (sz[1] * 8));
 852                 word[1] |= tmpw >> (sz[0] * 8);
 853         }
 854
 855         for (i = 0; i < loop; i++) {
 856                 temp = off8 + (i << 3);
 857                 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
 858                 temp = 0;
 859                 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
 860                 temp = word[i] & 0xffffffff;
 861                 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
 862                 temp = (word[i] >> 32) & 0xffffffff;
 863                 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
 864                 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
 865                 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
 866                 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
 867                 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
 868
 869                 for (j = 0; j < MAX_CTL_CHECK; j++) {
 870                         temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
 871                         if ((temp & MIU_TA_CTL_BUSY) == 0)
 872                                 break;
 873                 }
 874
 875                 if (j >= MAX_CTL_CHECK) {
 876                         qla_printk(KERN_WARNING, ha,
 877                                 "%s: Fail to write through agent\n",
 878                                 QLA2XXX_DRIVER_NAME);
 879                         ret = -1;
 880                         break;
 881                 }
 882         }
 883         return ret;
 884 }
 885
 886 int
 887 qla82xx_rdmem(struct qla_hw_data *ha, u64 off, void *data, int size)
 888 {
 889         int i, j = 0, k, start, end, loop, sz[2], off0[2];
 890         u32 temp;
 891         u64 off8, val, mem_crb, word[2] = {0, 0};
 892 #define MAX_CTL_CHECK   1000
 893
 894         /*
 895          * If not MN, go check for MS or invalid.
 896          */
 897         if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
 898                 mem_crb = QLA82XX_CRB_QDR_NET;
 899         else {
 900                 mem_crb = QLA82XX_CRB_DDR_NET;
 901                 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
 902                         return qla82xx_pci_mem_read_direct(ha, off,
 903                                 data, size);
 904         }
 905
 906         off8 = off & 0xfffffff8;
 907         off0[0] = off & 0x7;
 908         off0[1] = 0;
 909         sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
 910         sz[1] = size - sz[0];
 911         loop = ((off0[0] + size - 1) >> 3) + 1;
 912
 913         for (i = 0; i < loop; i++) {
 914                 temp = off8 + (i << 3);
 915                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
 916                 temp = 0;
 917                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
 918                 temp = MIU_TA_CTL_ENABLE;
 919                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
 920                 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
 921                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
 922
 923                 for (j = 0; j < MAX_CTL_CHECK; j++) {
 924                         temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
 925                         if ((temp & MIU_TA_CTL_BUSY) == 0)
 926                                 break;
 927                 }
 928
 929                 if (j >= MAX_CTL_CHECK) {
 930                         qla_printk(KERN_INFO, ha,
 931                                 "%s: Fail to read through agent\n",
 932                                 QLA2XXX_DRIVER_NAME);
 933                         break;
 934                 }
 935
 936                 start = off0[i] >> 2;
 937                 end   = (off0[i] + sz[i] - 1) >> 2;
 938                 for (k = start; k <= end; k++) {
 939                         temp = qla82xx_rd_32(ha,
 940                             mem_crb + MIU_TEST_AGT_RDDATA(k));
 941                         word[i] |= ((u64)temp << (32 * k));
 942                 }
 943         }
 944
 945         if (j >= MAX_CTL_CHECK)
 946                 return -1;
 947
 948         if (sz[0] == 8) {
 949                 val = word[0];
 950         } else {
 951                 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
 952                         ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
 953         }
 954
 955         switch (size) {
 956         case 1:
 957                 *(u8  *)data = val;
 958                 break;
 959         case 2:
 960                 *(u16 *)data = val;
 961                 break;
 962         case 4:
 963                 *(u32 *)data = val;
 964                 break;
 965         case 8:
 966                 *(u64 *)data = val;
 967                 break;
 968         }
 969         return 0;
 970 }
 971
 972 #define MTU_FUDGE_FACTOR 100
 973 unsigned long qla82xx_decode_crb_addr(unsigned long addr)
 974 {
 975         int i;
 976         unsigned long base_addr, offset, pci_base;
 977
 978         if (!qla82xx_crb_table_initialized)
 979                 qla82xx_crb_addr_transform_setup();
 980
 981         pci_base = ADDR_ERROR;
 982         base_addr = addr & 0xfff00000;
 983         offset = addr & 0x000fffff;
 984
 985         for (i = 0; i < MAX_CRB_XFORM; i++) {
 986                 if (crb_addr_xform[i] == base_addr) {
 987                         pci_base = i << 20;
 988                         break;
 989                 }
 990         }
 991         if (pci_base == ADDR_ERROR)
 992                 return pci_base;
 993         return pci_base + offset;
 994 }
 995
 996 static long rom_max_timeout = 100;
 997 static long qla82xx_rom_lock_timeout = 100;
 998
 999 int
1000 qla82xx_rom_lock(struct qla_hw_data *ha)
1001 {
1002         int done = 0, timeout = 0;
1003
1004         while (!done) {
1005                 /* acquire semaphore2 from PCI HW block */
1006                 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
1007                 if (done == 1)
1008                         break;
1009                 if (timeout >= qla82xx_rom_lock_timeout)
1010                         return -1;
1011                 timeout++;
1012         }
1013         qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
1014         return 0;
1015 }
1016
1017 int
1018 qla82xx_wait_rom_busy(struct qla_hw_data *ha)
1019 {
1020         long timeout = 0;
1021         long done = 0 ;
1022
1023         while (done == 0) {
1024                 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
1025                 done &= 4;
1026                 timeout++;
1027                 if (timeout >= rom_max_timeout) {
1028                         DEBUG(qla_printk(KERN_INFO, ha,
1029                                 "%s: Timeout reached waiting for rom busy",
1030                                 QLA2XXX_DRIVER_NAME));
1031                         return -1;
1032                 }
1033         }
1034         return 0;
1035 }
1036
1037 int
1038 qla82xx_wait_rom_done(struct qla_hw_data *ha)
1039 {
1040         long timeout = 0;
1041         long done = 0 ;
1042
1043         while (done == 0) {
1044                 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
1045                 done &= 2;
1046                 timeout++;
1047                 if (timeout >= rom_max_timeout) {
1048                         DEBUG(qla_printk(KERN_INFO, ha,
1049                                 "%s: Timeout reached  waiting for rom done",
1050                                 QLA2XXX_DRIVER_NAME));
1051                         return -1;
1052                 }
1053         }
1054         return 0;
1055 }
1056
1057 int
1058 qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
1059 {
1060         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
1061         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
1062         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
1063         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb);
1064         qla82xx_wait_rom_busy(ha);
1065         if (qla82xx_wait_rom_done(ha)) {
1066                 qla_printk(KERN_WARNING, ha,
1067                         "%s: Error waiting for rom done\n",
1068                         QLA2XXX_DRIVER_NAME);
1069                 return -1;
1070         }
1071         /* Reset abyte_cnt and dummy_byte_cnt */
1072         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
1073         udelay(10);
1074         cond_resched();
1075         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1076         *valp = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
1077         return 0;
1078 }
1079
1080 int
1081 qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
1082 {
1083         int ret, loops = 0;
1084
1085         while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
1086                 udelay(100);
1087                 schedule();
1088                 loops++;
1089         }
1090         if (loops >= 50000) {
1091                 qla_printk(KERN_INFO, ha,
1092                         "%s: qla82xx_rom_lock failed\n",
1093                         QLA2XXX_DRIVER_NAME);
1094                 return -1;
1095         }
1096         ret = qla82xx_do_rom_fast_read(ha, addr, valp);
1097         qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
1098         return ret;
1099 }
1100
1101 int
1102 qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val)
1103 {
1104         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR);
1105         qla82xx_wait_rom_busy(ha);
1106         if (qla82xx_wait_rom_done(ha)) {
1107                 qla_printk(KERN_WARNING, ha,
1108                     "Error waiting for rom done\n");
1109                 return -1;
1110         }
1111         *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
1112         return 0;
1113 }
1114
1115 int
1116 qla82xx_flash_wait_write_finish(struct qla_hw_data *ha)
1117 {
1118         long timeout = 0;
1119         uint32_t done = 1 ;
1120         uint32_t val;
1121         int ret = 0;
1122
1123         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1124         while ((done != 0) && (ret == 0)) {
1125                 ret = qla82xx_read_status_reg(ha, &val);
1126                 done = val & 1;
1127                 timeout++;
1128                 udelay(10);
1129                 cond_resched();
1130                 if (timeout >= 50000) {
1131                         qla_printk(KERN_WARNING, ha,
1132                             "Timeout reached  waiting for write finish");
1133                         return -1;
1134                 }
1135         }
1136         return ret;
1137 }
1138
1139 int
1140 qla82xx_flash_set_write_enable(struct qla_hw_data *ha)
1141 {
1142         uint32_t val;
1143         qla82xx_wait_rom_busy(ha);
1144         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1145         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN);
1146         qla82xx_wait_rom_busy(ha);
1147         if (qla82xx_wait_rom_done(ha))
1148                 return -1;
1149         if (qla82xx_read_status_reg(ha, &val) != 0)
1150                 return -1;
1151         if ((val & 2) != 2)
1152                 return -1;
1153         return 0;
1154 }
1155
1156 int
1157 qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val)
1158 {
1159         if (qla82xx_flash_set_write_enable(ha))
1160                 return -1;
1161         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val);
1162         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1);
1163         if (qla82xx_wait_rom_done(ha)) {
1164                 qla_printk(KERN_WARNING, ha,
1165                     "Error waiting for rom done\n");
1166                 return -1;
1167         }
1168         return qla82xx_flash_wait_write_finish(ha);
1169 }
1170
1171 int
1172 qla82xx_write_disable_flash(struct qla_hw_data *ha)
1173 {
1174         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI);
1175         if (qla82xx_wait_rom_done(ha)) {
1176                 qla_printk(KERN_WARNING, ha,
1177                     "Error waiting for rom done\n");
1178                 return -1;
1179         }
1180         return 0;
1181 }
1182
1183 int
1184 ql82xx_rom_lock_d(struct qla_hw_data *ha)
1185 {
1186         int loops = 0;
1187         while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
1188                 udelay(100);
1189                 cond_resched();
1190                 loops++;
1191         }
1192         if (loops >= 50000) {
1193                 qla_printk(KERN_WARNING, ha, "ROM lock failed\n");
1194                 return -1;
1195         }
1196         return 0;;
1197 }
1198
1199 int
1200 qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr,
1201         uint32_t data)
1202 {
1203         int ret = 0;
1204
1205         ret = ql82xx_rom_lock_d(ha);
1206         if (ret < 0) {
1207                 qla_printk(KERN_WARNING, ha, "ROM Lock failed\n");
1208                 return ret;
1209         }
1210
1211         if (qla82xx_flash_set_write_enable(ha))
1212                 goto done_write;
1213
1214         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data);
1215         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr);
1216         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
1217         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP);
1218         qla82xx_wait_rom_busy(ha);
1219         if (qla82xx_wait_rom_done(ha)) {
1220                 qla_printk(KERN_WARNING, ha,
1221                         "Error waiting for rom done\n");
1222                 ret = -1;
1223                 goto done_write;
1224         }
1225
1226         ret = qla82xx_flash_wait_write_finish(ha);
1227
1228 done_write:
1229         qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
1230         return ret;
1231 }
1232
1233 /* This routine does CRB initialize sequence
1234  *  to put the ISP into operational state
1235  */
1236 int qla82xx_pinit_from_rom(scsi_qla_host_t *vha)
1237 {
1238         int addr, val;
1239         int i ;
1240         struct crb_addr_pair *buf;
1241         unsigned long off;
1242         unsigned offset, n;
1243         struct qla_hw_data *ha = vha->hw;
1244
1245         struct crb_addr_pair {
1246                 long addr;
1247                 long data;
1248         };
1249
1250         /* Halt all the indiviual PEGs and other blocks of the ISP */
1251         qla82xx_rom_lock(ha);
1252         if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
1253                 /* don't reset CAM block on reset */
1254                 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1255         else
1256                 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1257         qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
1258
1259         /* Read the signature value from the flash.
1260          * Offset 0: Contain signature (0xcafecafe)
1261          * Offset 4: Offset and number of addr/value pairs
1262          * that present in CRB initialize sequence
1263          */
1264         if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1265             qla82xx_rom_fast_read(ha, 4, &n) != 0) {
1266                 qla_printk(KERN_WARNING, ha,
1267                     "[ERROR] Reading crb_init area: n: %08x\n", n);
1268                 return -1;
1269         }
1270
1271         /* Offset in flash = lower 16 bits
1272          * Number of enteries = upper 16 bits
1273          */
1274         offset = n & 0xffffU;
1275         n = (n >> 16) & 0xffffU;
1276
1277         /* number of addr/value pair should not exceed 1024 enteries */
1278         if (n  >= 1024) {
1279                 qla_printk(KERN_WARNING, ha,
1280                     "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n",
1281                     QLA2XXX_DRIVER_NAME, __func__, n);
1282                 return -1;
1283         }
1284
1285         qla_printk(KERN_INFO, ha,
1286             "%s: %d CRB init values found in ROM.\n", QLA2XXX_DRIVER_NAME, n);
1287
1288         buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL);
1289         if (buf == NULL) {
1290                 qla_printk(KERN_WARNING, ha,
1291                     "%s: [ERROR] Unable to malloc memory.\n",
1292                     QLA2XXX_DRIVER_NAME);
1293                 return -1;
1294         }
1295
1296         for (i = 0; i < n; i++) {
1297                 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1298                     qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) {
1299                         kfree(buf);
1300                         return -1;
1301                 }
1302
1303                 buf[i].addr = addr;
1304                 buf[i].data = val;
1305         }
1306
1307         for (i = 0; i < n; i++) {
1308                 /* Translate internal CRB initialization
1309                  * address to PCI bus address
1310                  */
1311                 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) +
1312                     QLA82XX_PCI_CRBSPACE;
1313                 /* Not all CRB  addr/value pair to be written,
1314                  * some of them are skipped
1315                  */
1316
1317                 /* skipping cold reboot MAGIC */
1318                 if (off == QLA82XX_CAM_RAM(0x1fc))
1319                         continue;
1320
1321                 /* do not reset PCI */
1322                 if (off == (ROMUSB_GLB + 0xbc))
1323                         continue;
1324
1325                 /* skip core clock, so that firmware can increase the clock */
1326                 if (off == (ROMUSB_GLB + 0xc8))
1327                         continue;
1328
1329                 /* skip the function enable register */
1330                 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1331                         continue;
1332
1333                 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1334                         continue;
1335
1336                 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1337                         continue;
1338
1339                 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1340                         continue;
1341
1342                 if (off == ADDR_ERROR) {
1343                         qla_printk(KERN_WARNING, ha,
1344                             "%s: [ERROR] Unknown addr: 0x%08lx\n",
1345                             QLA2XXX_DRIVER_NAME, buf[i].addr);
1346                         continue;
1347                 }
1348
1349                 if (off == (QLA82XX_CRB_PEG_NET_1 + 0x18)) {
1350                         if (!QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision))
1351                                 buf[i].data = 0x1020;
1352                 }
1353
1354                 qla82xx_wr_32(ha, off, buf[i].data);
1355
1356                 /* ISP requires much bigger delay to settle down,
1357                  * else crb_window returns 0xffffffff
1358                  */
1359                 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1360                         msleep(1000);
1361
1362                 /* ISP requires millisec delay between
1363                  * successive CRB register updation
1364                  */
1365                 msleep(1);
1366         }
1367
1368         kfree(buf);
1369
1370         /* Resetting the data and instruction cache */
1371         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1372         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1373         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1374
1375         /* Clear all protocol processing engines */
1376         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1377         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1378         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1379         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1380         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1381         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1382         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1383         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1384         return 0;
1385 }
1386
1387 int qla82xx_check_for_bad_spd(struct qla_hw_data *ha)
1388 {
1389         u32 val = 0;
1390         val = qla82xx_rd_32(ha, BOOT_LOADER_DIMM_STATUS);
1391         val &= QLA82XX_BOOT_LOADER_MN_ISSUE;
1392         if (val & QLA82XX_PEG_TUNE_MN_SPD_ZEROED) {
1393                 qla_printk(KERN_INFO, ha,
1394                         "Memory DIMM SPD not programmed. "
1395                         " Assumed valid.\n");
1396                 return 1;
1397         } else if (val) {
1398                 qla_printk(KERN_INFO, ha,
1399                         "Memory DIMM type incorrect.Info:%08X.\n", val);
1400                 return 2;
1401         }
1402         return 0;
1403 }
1404
1405 int
1406 qla82xx_fw_load_from_flash(struct qla_hw_data *ha)
1407 {
1408         int  i;
1409         long size = 0;
1410         long flashaddr = BOOTLD_START, memaddr = BOOTLD_START;
1411         u64 data;
1412         u32 high, low;
1413         size = (IMAGE_START - BOOTLD_START) / 8;
1414
1415         for (i = 0; i < size; i++) {
1416                 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1417                     (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) {
1418                         return -1;
1419                 }
1420                 data = ((u64)high << 32) | low ;
1421                 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1422                 flashaddr += 8;
1423                 memaddr += 8;
1424
1425                 if (i % 0x1000 == 0)
1426                         msleep(1);
1427         }
1428         udelay(100);
1429         read_lock(&ha->hw_lock);
1430         if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) {
1431                 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1432                 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1433         } else {
1434                 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001d);
1435         }
1436         read_unlock(&ha->hw_lock);
1437         return 0;
1438 }
1439
1440 int
1441 qla82xx_pci_mem_read_2M(struct qla_hw_data *ha,
1442                 u64 off, void *data, int size)
1443 {
1444         int i, j = 0, k, start, end, loop, sz[2], off0[2];
1445         int           shift_amount;
1446         uint32_t      temp;
1447         uint64_t      off8, val, mem_crb, word[2] = {0, 0};
1448
1449         /*
1450          * If not MN, go check for MS or invalid.
1451          */
1452
1453         if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1454                 mem_crb = QLA82XX_CRB_QDR_NET;
1455         else {
1456                 mem_crb = QLA82XX_CRB_DDR_NET;
1457                 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1458                         return qla82xx_pci_mem_read_direct(ha,
1459                             off, data, size);
1460         }
1461
1462         if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) {
1463                 off8 = off & 0xfffffff0;
1464                 off0[0] = off & 0xf;
1465                 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1466                 shift_amount = 4;
1467         } else {
1468                 off8 = off & 0xfffffff8;
1469                 off0[0] = off & 0x7;
1470                 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1471                 shift_amount = 4;
1472         }
1473         loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1474         off0[1] = 0;
1475         sz[1] = size - sz[0];
1476
1477         /*
1478          * don't lock here - write_wx gets the lock if each time
1479          * write_lock_irqsave(&adapter->adapter_lock, flags);
1480          * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1481          */
1482
1483         for (i = 0; i < loop; i++) {
1484                 temp = off8 + (i << shift_amount);
1485                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1486                 temp = 0;
1487                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1488                 temp = MIU_TA_CTL_ENABLE;
1489                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1490                 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1491                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1492
1493                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1494                         temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1495                         if ((temp & MIU_TA_CTL_BUSY) == 0)
1496                                 break;
1497                 }
1498
1499                 if (j >= MAX_CTL_CHECK) {
1500                         if (printk_ratelimit())
1501                                 dev_err(&ha->pdev->dev,
1502                                     "failed to read through agent\n");
1503                         break;
1504                 }
1505
1506                 start = off0[i] >> 2;
1507                 end   = (off0[i] + sz[i] - 1) >> 2;
1508                 for (k = start; k <= end; k++) {
1509                         temp = qla82xx_rd_32(ha,
1510                                         mem_crb + MIU_TEST_AGT_RDDATA(k));
1511                         word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1512                 }
1513         }
1514
1515         /*
1516          * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1517          * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1518          */
1519
1520         if (j >= MAX_CTL_CHECK)
1521                 return -1;
1522
1523         if ((off0[0] & 7) == 0) {
1524                 val = word[0];
1525         } else {
1526                 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1527                         ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1528         }
1529
1530         switch (size) {
1531         case 1:
1532                 *(uint8_t  *)data = val;
1533                 break;
1534         case 2:
1535                 *(uint16_t *)data = val;
1536                 break;
1537         case 4:
1538                 *(uint32_t *)data = val;
1539                 break;
1540         case 8:
1541                 *(uint64_t *)data = val;
1542                 break;
1543         }
1544         return 0;
1545 }
1546
1547 int
1548 qla82xx_pci_mem_write_2M(struct qla_hw_data *ha,
1549                 u64 off, void *data, int size)
1550 {
1551         int i, j, ret = 0, loop, sz[2], off0;
1552         int scale, shift_amount, p3p, startword;
1553         uint32_t temp;
1554         uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1555
1556         /*
1557          * If not MN, go check for MS or invalid.
1558          */
1559         if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1560                 mem_crb = QLA82XX_CRB_QDR_NET;
1561         else {
1562                 mem_crb = QLA82XX_CRB_DDR_NET;
1563                 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1564                         return qla82xx_pci_mem_write_direct(ha,
1565                             off, data, size);
1566         }
1567
1568         off0 = off & 0x7;
1569         sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1570         sz[1] = size - sz[0];
1571
1572         if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) {
1573                 off8 = off & 0xfffffff0;
1574                 loop = (((off & 0xf) + size - 1) >> 4) + 1;
1575                 shift_amount = 4;
1576                 scale = 2;
1577                 p3p = 1;
1578                 startword = (off & 0xf)/8;
1579         } else {
1580                 off8 = off & 0xfffffff8;
1581                 loop = ((off0 + size - 1) >> 3) + 1;
1582                 shift_amount = 3;
1583                 scale = 1;
1584                 p3p = 0;
1585                 startword = 0;
1586         }
1587
1588         if (p3p || (size != 8) || (off0 != 0)) {
1589                 for (i = 0; i < loop; i++) {
1590                         if (qla82xx_pci_mem_read_2M(ha, off8 +
1591                             (i << shift_amount), &word[i * scale], 8))
1592                                 return -1;
1593                 }
1594         }
1595
1596         switch (size) {
1597         case 1:
1598                 tmpw = *((uint8_t *)data);
1599                 break;
1600         case 2:
1601                 tmpw = *((uint16_t *)data);
1602                 break;
1603         case 4:
1604                 tmpw = *((uint32_t *)data);
1605                 break;
1606         case 8:
1607         default:
1608                 tmpw = *((uint64_t *)data);
1609                 break;
1610         }
1611
1612         if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) {
1613                 if (sz[0] == 8) {
1614                         word[startword] = tmpw;
1615                 } else {
1616                         word[startword] &=
1617                                 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1618                         word[startword] |= tmpw << (off0 * 8);
1619                 }
1620                 if (sz[1] != 0) {
1621                         word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1622                         word[startword+1] |= tmpw >> (sz[0] * 8);
1623                 }
1624         } else {
1625                 word[startword] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1626                 word[startword] |= tmpw << (off0 * 8);
1627
1628                 if (loop == 2) {
1629                         word[1] &= ~(~0ULL << (sz[1] * 8));
1630                         word[1] |= tmpw >> (sz[0] * 8);
1631                 }
1632         }
1633
1634         /*
1635          * don't lock here - write_wx gets the lock if each time
1636          * write_lock_irqsave(&adapter->adapter_lock, flags);
1637          * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1638          */
1639         for (i = 0; i < loop; i++) {
1640                 temp = off8 + (i << shift_amount);
1641                 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1642                 temp = 0;
1643                 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1644                 temp = word[i * scale] & 0xffffffff;
1645                 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1646                 temp = (word[i * scale] >> 32) & 0xffffffff;
1647                 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1648                 if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) {
1649                         temp = word[i*scale + 1] & 0xffffffff;
1650                         qla82xx_wr_32(ha, mem_crb +
1651                             MIU_TEST_AGT_WRDATA_UPPER_LO, temp);
1652                         temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1653                         qla82xx_wr_32(ha, mem_crb +
1654                             MIU_TEST_AGT_WRDATA_UPPER_HI, temp);
1655                 }
1656
1657                 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1658                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1659                 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1660                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1661
1662                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1663                         temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1664                         if ((temp & MIU_TA_CTL_BUSY) == 0)
1665                                 break;
1666                 }
1667
1668                 if (j >= MAX_CTL_CHECK) {
1669                         if (printk_ratelimit())
1670                                 dev_err(&ha->pdev->dev,
1671                                     "failed to write through agent\n");
1672                         ret = -1;
1673                         break;
1674                 }
1675         }
1676
1677         return ret;
1678 }
1679
1680 /* PCI related functions */
1681 char *
1682 qla82xx_pci_info_str(struct scsi_qla_host *vha, char *str)
1683 {
1684         int pcie_reg;
1685         struct qla_hw_data *ha = vha->hw;
1686         char lwstr[6];
1687         uint16_t lnk;
1688
1689         pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
1690         pci_read_config_word(ha->pdev, pcie_reg + PCI_EXP_LNKSTA, &lnk);
1691         ha->link_width = (lnk >> 4) & 0x3f;
1692
1693         strcpy(str, "PCIe (");
1694         strcat(str, "2.5Gb/s ");
1695         snprintf(lwstr, sizeof(lwstr), "x%d)", ha->link_width);
1696         strcat(str, lwstr);
1697         return str;
1698 }
1699
1700 int qla82xx_pci_region_offset(struct pci_dev *pdev, int region)
1701 {
1702         unsigned long val = 0;
1703         u32 control;
1704
1705         switch (region) {
1706         case 0:
1707                 val = 0;
1708                 break;
1709         case 1:
1710                 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control);
1711                 val = control + QLA82XX_MSIX_TBL_SPACE;
1712                 break;
1713         }
1714         return val;
1715 }
1716
1717 int qla82xx_pci_region_len(struct pci_dev *pdev, int region)
1718 {
1719         unsigned long val = 0;
1720         u32 control;
1721         switch (region) {
1722         case 0:
1723                 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control);
1724                 val = control;
1725                 break;
1726         case 1:
1727                 val = pci_resource_len(pdev, 0) -
1728                     qla82xx_pci_region_offset(pdev, 1);
1729                 break;
1730         }
1731         return val;
1732 }
1733
1734 int
1735 qla82xx_iospace_config(struct qla_hw_data *ha)
1736 {
1737         uint32_t len = 0;
1738
1739         if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) {
1740                 qla_printk(KERN_WARNING, ha,
1741                         "Failed to reserve selected regions (%s)\n",
1742                         pci_name(ha->pdev));
1743                 goto iospace_error_exit;
1744         }
1745
1746         /* Use MMIO operations for all accesses. */
1747         if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1748                 qla_printk(KERN_ERR, ha,
1749                         "region #0 not an MMIO resource (%s), aborting\n",
1750                         pci_name(ha->pdev));
1751                 goto iospace_error_exit;
1752         }
1753
1754         len = pci_resource_len(ha->pdev, 0);
1755         ha->nx_pcibase =
1756             (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len);
1757         if (!ha->nx_pcibase) {
1758                 qla_printk(KERN_ERR, ha,
1759                     "cannot remap pcibase MMIO (%s), aborting\n",
1760                     pci_name(ha->pdev));
1761                 pci_release_regions(ha->pdev);
1762                 goto iospace_error_exit;
1763         }
1764
1765         /* Mapping of IO base pointer */
1766         ha->iobase = (device_reg_t __iomem *)((uint8_t *)ha->nx_pcibase +
1767             0xbc000 + (ha->pdev->devfn << 11));
1768
1769         if (!ql2xdbwr) {
1770                 ha->nxdb_wr_ptr =
1771                     (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) +
1772                     (ha->pdev->devfn << 12)), 4);
1773                 if (!ha->nxdb_wr_ptr) {
1774                         qla_printk(KERN_ERR, ha,
1775                             "cannot remap MMIO (%s), aborting\n",
1776                             pci_name(ha->pdev));
1777                         pci_release_regions(ha->pdev);
1778                         goto iospace_error_exit;
1779                 }
1780
1781                 /* Mapping of IO base pointer,
1782                  * door bell read and write pointer
1783                  */
1784                 ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) +
1785                     (ha->pdev->devfn * 8);
1786         } else {
1787                 ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ?
1788                         QLA82XX_CAMRAM_DB1 :
1789                         QLA82XX_CAMRAM_DB2);
1790         }
1791
1792         ha->max_req_queues = ha->max_rsp_queues = 1;
1793         ha->msix_count = ha->max_rsp_queues + 1;
1794         return 0;
1795
1796 iospace_error_exit:
1797         return -ENOMEM;
1798 }
1799
1800 /* GS related functions */
1801
1802 /* Initialization related functions */
1803
1804 /**
1805  * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers.
1806  * @ha: HA context
1807  *
1808  * Returns 0 on success.
1809 */
1810 int
1811 qla82xx_pci_config(scsi_qla_host_t *vha)
1812 {
1813         struct qla_hw_data *ha = vha->hw;
1814         int ret;
1815
1816         pci_set_master(ha->pdev);
1817         ret = pci_set_mwi(ha->pdev);
1818         ha->chip_revision = ha->pdev->revision;
1819         return 0;
1820 }
1821
1822 /**
1823  * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers.
1824  * @ha: HA context
1825  *
1826  * Returns 0 on success.
1827  */
1828 void
1829 qla82xx_reset_chip(scsi_qla_host_t *vha)
1830 {
1831         struct qla_hw_data *ha = vha->hw;
1832         ha->isp_ops->disable_intrs(ha);
1833 }
1834
1835 void qla82xx_config_rings(struct scsi_qla_host *vha)
1836 {
1837         struct qla_hw_data *ha = vha->hw;
1838         struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1839         struct init_cb_81xx *icb;
1840         struct req_que *req = ha->req_q_map[0];
1841         struct rsp_que *rsp = ha->rsp_q_map[0];
1842
1843         /* Setup ring parameters in initialization control block. */
1844         icb = (struct init_cb_81xx *)ha->init_cb;
1845         icb->request_q_outpointer = __constant_cpu_to_le16(0);
1846         icb->response_q_inpointer = __constant_cpu_to_le16(0);
1847         icb->request_q_length = cpu_to_le16(req->length);
1848         icb->response_q_length = cpu_to_le16(rsp->length);
1849         icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1850         icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1851         icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1852         icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
1853
1854         icb->version = 1;
1855         icb->frame_payload_size = 2112;
1856         icb->execution_throttle = 8;
1857         icb->exchange_count = 128;
1858         icb->login_retry_count = 8;
1859
1860         WRT_REG_DWORD((unsigned long  __iomem *)&reg->req_q_out[0], 0);
1861         WRT_REG_DWORD((unsigned long  __iomem *)&reg->rsp_q_in[0], 0);
1862         WRT_REG_DWORD((unsigned long  __iomem *)&reg->rsp_q_out[0], 0);
1863 }
1864
1865 void qla82xx_reset_adapter(struct scsi_qla_host *vha)
1866 {
1867         struct qla_hw_data *ha = vha->hw;
1868         vha->flags.online = 0;
1869         qla2x00_try_to_stop_firmware(vha);
1870         ha->isp_ops->disable_intrs(ha);
1871 }
1872
1873 int qla82xx_fw_load_from_blob(struct qla_hw_data *ha)
1874 {
1875         u64 *ptr64;
1876         u32 i, flashaddr, size;
1877         __le64 data;
1878
1879         size = (IMAGE_START - BOOTLD_START) / 8;
1880
1881         ptr64 = (u64 *)&ha->hablob->fw->data[BOOTLD_START];
1882         flashaddr = BOOTLD_START;
1883
1884         for (i = 0; i < size; i++) {
1885                 data = cpu_to_le64(ptr64[i]);
1886                 qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8);
1887                 flashaddr += 8;
1888         }
1889
1890         size = *(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET];
1891         size = (__force u32)cpu_to_le32(size) / 8;
1892         ptr64 = (u64 *)&ha->hablob->fw->data[IMAGE_START];
1893         flashaddr = FLASH_ADDR_START;
1894
1895         for (i = 0; i < size; i++) {
1896                 data = cpu_to_le64(ptr64[i]);
1897
1898                 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1899                         return -EIO;
1900                 flashaddr += 8;
1901         }
1902
1903         /* Write a magic value to CAMRAM register
1904          * at a specified offset to indicate
1905          * that all data is written and
1906          * ready for firmware to initialize.
1907          */
1908         qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), 0x12345678);
1909
1910         if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) {
1911                 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1912                 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1913         } else
1914                 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001d);
1915         return 0;
1916 }
1917
1918 int qla82xx_check_cmdpeg_state(struct qla_hw_data *ha)
1919 {
1920         u32 val = 0;
1921         int retries = 60;
1922
1923         do {
1924                 read_lock(&ha->hw_lock);
1925                 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE);
1926                 read_unlock(&ha->hw_lock);
1927
1928                 switch (val) {
1929                 case PHAN_INITIALIZE_COMPLETE:
1930                 case PHAN_INITIALIZE_ACK:
1931                         return QLA_SUCCESS;
1932                 case PHAN_INITIALIZE_FAILED:
1933                         break;
1934                 default:
1935                         break;
1936                 }
1937                 qla_printk(KERN_WARNING, ha,
1938                         "CRB_CMDPEG_STATE: 0x%x and retries: 0x%x\n",
1939                         val, retries);
1940
1941                 msleep(500);
1942
1943         } while (--retries);
1944
1945         qla_printk(KERN_INFO, ha,
1946             "Cmd Peg initialization failed: 0x%x.\n", val);
1947
1948         qla82xx_check_for_bad_spd(ha);
1949         val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1950         read_lock(&ha->hw_lock);
1951         qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
1952         read_unlock(&ha->hw_lock);
1953         return QLA_FUNCTION_FAILED;
1954 }
1955
1956 int qla82xx_check_rcvpeg_state(struct qla_hw_data *ha)
1957 {
1958         u32 val = 0;
1959         int retries = 60;
1960
1961         do {
1962                 read_lock(&ha->hw_lock);
1963                 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE);
1964                 read_unlock(&ha->hw_lock);
1965
1966                 switch (val) {
1967                 case PHAN_INITIALIZE_COMPLETE:
1968                 case PHAN_INITIALIZE_ACK:
1969                         return QLA_SUCCESS;
1970                 case PHAN_INITIALIZE_FAILED:
1971                         break;
1972                 default:
1973                         break;
1974                 }
1975
1976                 qla_printk(KERN_WARNING, ha,
1977                         "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x\n",
1978                         val, retries);
1979
1980                 msleep(500);
1981
1982         } while (--retries);
1983
1984         qla_printk(KERN_INFO, ha,
1985                 "Rcv Peg initialization failed: 0x%x.\n", val);
1986         read_lock(&ha->hw_lock);
1987         qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED);
1988         read_unlock(&ha->hw_lock);
1989         return QLA_FUNCTION_FAILED;
1990 }
1991
1992 /* ISR related functions */
1993 uint32_t qla82xx_isr_int_target_mask_enable[8] = {
1994         ISR_INT_TARGET_MASK, ISR_INT_TARGET_MASK_F1,
1995         ISR_INT_TARGET_MASK_F2, ISR_INT_TARGET_MASK_F3,
1996         ISR_INT_TARGET_MASK_F4, ISR_INT_TARGET_MASK_F5,
1997         ISR_INT_TARGET_MASK_F7, ISR_INT_TARGET_MASK_F7
1998 };
1999
2000 uint32_t qla82xx_isr_int_target_status[8] = {
2001         ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1,
2002         ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3,
2003         ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5,
2004         ISR_INT_TARGET_STATUS_F7, ISR_INT_TARGET_STATUS_F7
2005 };
2006
2007 static struct qla82xx_legacy_intr_set legacy_intr[] = \
2008         QLA82XX_LEGACY_INTR_CONFIG;
2009
2010 /*
2011  * qla82xx_mbx_completion() - Process mailbox command completions.
2012  * @ha: SCSI driver HA context
2013  * @mb0: Mailbox0 register
2014  */
2015 void
2016 qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
2017 {
2018         uint16_t        cnt;
2019         uint16_t __iomem *wptr;
2020         struct qla_hw_data *ha = vha->hw;
2021         struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
2022         wptr = (uint16_t __iomem *)&reg->mailbox_out[1];
2023
2024         /* Load return mailbox registers. */
2025         ha->flags.mbox_int = 1;
2026         ha->mailbox_out[0] = mb0;
2027
2028         for (cnt = 1; cnt < ha->mbx_count; cnt++) {
2029                 ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
2030                 wptr++;
2031         }
2032
2033         if (ha->mcp) {
2034                 DEBUG3_11(printk(KERN_INFO "%s(%ld): "
2035                         "Got mailbox completion. cmd=%x.\n",
2036                         __func__, vha->host_no, ha->mcp->mb[0]));
2037         } else {
2038                 qla_printk(KERN_INFO, ha,
2039                         "%s(%ld): MBX pointer ERROR!\n",
2040                         __func__, vha->host_no);
2041         }
2042 }
2043
2044 /*
2045  * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
2046  * @irq:
2047  * @dev_id: SCSI driver HA context
2048  * @regs:
2049  *
2050  * Called by system whenever the host adapter generates an interrupt.
2051  *
2052  * Returns handled flag.
2053  */
2054 irqreturn_t
2055 qla82xx_intr_handler(int irq, void *dev_id)
2056 {
2057         scsi_qla_host_t *vha;
2058         struct qla_hw_data *ha;
2059         struct rsp_que *rsp;
2060         struct device_reg_82xx __iomem *reg;
2061         int status = 0, status1 = 0;
2062         unsigned long   flags;
2063         unsigned long   iter;
2064         uint32_t        stat;
2065         uint16_t        mb[4];
2066
2067         rsp = (struct rsp_que *) dev_id;
2068         if (!rsp) {
2069                 printk(KERN_INFO
2070                         "%s(): NULL response queue pointer\n", __func__);
2071                 return IRQ_NONE;
2072         }
2073         ha = rsp->hw;
2074
2075         if (!ha->flags.msi_enabled) {
2076                 status = qla82xx_rd_32(ha, ISR_INT_VECTOR);
2077                 if (!(status & ha->nx_legacy_intr.int_vec_bit))
2078                         return IRQ_NONE;
2079
2080                 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG);
2081                 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1))
2082                         return IRQ_NONE;
2083         }
2084
2085         /* clear the interrupt */
2086         qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff);
2087
2088         /* read twice to ensure write is flushed */
2089         qla82xx_rd_32(ha, ISR_INT_VECTOR);
2090         qla82xx_rd_32(ha, ISR_INT_VECTOR);
2091
2092         reg = &ha->iobase->isp82;
2093
2094         spin_lock_irqsave(&ha->hardware_lock, flags);
2095         vha = pci_get_drvdata(ha->pdev);
2096         for (iter = 1; iter--; ) {
2097
2098                 if (RD_REG_DWORD(&reg->host_int)) {
2099                         stat = RD_REG_DWORD(&reg->host_status);
2100                         if ((stat & HSRX_RISC_INT) == 0)
2101                                 break;
2102
2103                         switch (stat & 0xff) {
2104                         case 0x1:
2105                         case 0x2:
2106                         case 0x10:
2107                         case 0x11:
2108                                 qla82xx_mbx_completion(vha, MSW(stat));
2109                                 status |= MBX_INTERRUPT;
2110                                 break;
2111                         case 0x12:
2112                                 mb[0] = MSW(stat);
2113                                 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2114                                 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2115                                 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2116                                 qla2x00_async_event(vha, rsp, mb);
2117                                 break;
2118                         case 0x13:
2119                                 qla24xx_process_response_queue(vha, rsp);
2120                                 break;
2121                         default:
2122                                 DEBUG2(printk("scsi(%ld): "
2123                                         " Unrecognized interrupt type (%d).\n",
2124                                         vha->host_no, stat & 0xff));
2125                                 break;
2126                         }
2127                 }
2128                 WRT_REG_DWORD(&reg->host_int, 0);
2129         }
2130         spin_unlock_irqrestore(&ha->hardware_lock, flags);
2131         if (!ha->flags.msi_enabled)
2132                 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2133
2134 #ifdef QL_DEBUG_LEVEL_17
2135         if (!irq && ha->flags.eeh_busy)
2136                 qla_printk(KERN_WARNING, ha,
2137                     "isr: status %x, cmd_flags %lx, mbox_int %x, stat %x\n",
2138                     status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat);
2139 #endif
2140
2141         if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
2142             (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
2143                 set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
2144                 complete(&ha->mbx_intr_comp);
2145         }
2146         return IRQ_HANDLED;
2147 }
2148
2149 irqreturn_t
2150 qla82xx_msix_default(int irq, void *dev_id)
2151 {
2152         scsi_qla_host_t *vha;
2153         struct qla_hw_data *ha;
2154         struct rsp_que *rsp;
2155         struct device_reg_82xx __iomem *reg;
2156         int status = 0;
2157         unsigned long flags;
2158         uint32_t stat;
2159         uint16_t mb[4];
2160
2161         rsp = (struct rsp_que *) dev_id;
2162         if (!rsp) {
2163                 printk(KERN_INFO
2164                         "%s(): NULL response queue pointer\n", __func__);
2165                 return IRQ_NONE;
2166         }
2167         ha = rsp->hw;
2168
2169         reg = &ha->iobase->isp82;
2170
2171         spin_lock_irqsave(&ha->hardware_lock, flags);
2172         vha = pci_get_drvdata(ha->pdev);
2173         do {
2174                 if (RD_REG_DWORD(&reg->host_int)) {
2175                         stat = RD_REG_DWORD(&reg->host_status);
2176                         if ((stat & HSRX_RISC_INT) == 0)
2177                                 break;
2178
2179                         switch (stat & 0xff) {
2180                         case 0x1:
2181                         case 0x2:
2182                         case 0x10:
2183                         case 0x11:
2184                                 qla82xx_mbx_completion(vha, MSW(stat));
2185                                 status |= MBX_INTERRUPT;
2186                                 break;
2187                         case 0x12:
2188                                 mb[0] = MSW(stat);
2189                                 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2190                                 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2191                                 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2192                                 qla2x00_async_event(vha, rsp, mb);
2193                                 break;
2194                         case 0x13:
2195                                 qla24xx_process_response_queue(vha, rsp);
2196                                 break;
2197                         default:
2198                                 DEBUG2(printk("scsi(%ld): "
2199                                         " Unrecognized interrupt type (%d).\n",
2200                                         vha->host_no, stat & 0xff));
2201                                 break;
2202                         }
2203                 }
2204                 WRT_REG_DWORD(&reg->host_int, 0);
2205         } while (0);
2206
2207         spin_unlock_irqrestore(&ha->hardware_lock, flags);
2208
2209 #ifdef QL_DEBUG_LEVEL_17
2210         if (!irq && ha->flags.eeh_busy)
2211                 qla_printk(KERN_WARNING, ha,
2212                         "isr: status %x, cmd_flags %lx, mbox_int %x, stat %x\n",
2213                         status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat);
2214 #endif
2215
2216         if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
2217                 (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
2218                         set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
2219                         complete(&ha->mbx_intr_comp);
2220         }
2221         return IRQ_HANDLED;
2222 }
2223
2224 irqreturn_t
2225 qla82xx_msix_rsp_q(int irq, void *dev_id)
2226 {
2227         scsi_qla_host_t *vha;
2228         struct qla_hw_data *ha;
2229         struct rsp_que *rsp;
2230         struct device_reg_82xx __iomem *reg;
2231
2232         rsp = (struct rsp_que *) dev_id;
2233         if (!rsp) {
2234                 printk(KERN_INFO
2235                         "%s(): NULL response queue pointer\n", __func__);
2236                 return IRQ_NONE;
2237         }
2238
2239         ha = rsp->hw;
2240         reg = &ha->iobase->isp82;
2241         spin_lock_irq(&ha->hardware_lock);
2242         vha = pci_get_drvdata(ha->pdev);
2243         qla24xx_process_response_queue(vha, rsp);
2244         WRT_REG_DWORD(&reg->host_int, 0);
2245         spin_unlock_irq(&ha->hardware_lock);
2246         return IRQ_HANDLED;
2247 }
2248
2249 void
2250 qla82xx_poll(int irq, void *dev_id)
2251 {
2252         scsi_qla_host_t *vha;
2253         struct qla_hw_data *ha;
2254         struct rsp_que *rsp;
2255         struct device_reg_82xx __iomem *reg;
2256         int status = 0;
2257         uint32_t stat;
2258         uint16_t mb[4];
2259         unsigned long flags;
2260
2261         rsp = (struct rsp_que *) dev_id;
2262         if (!rsp) {
2263                 printk(KERN_INFO
2264                         "%s(): NULL response queue pointer\n", __func__);
2265                 return;
2266         }
2267         ha = rsp->hw;
2268
2269         reg = &ha->iobase->isp82;
2270         spin_lock_irqsave(&ha->hardware_lock, flags);
2271         vha = pci_get_drvdata(ha->pdev);
2272
2273         if (RD_REG_DWORD(&reg->host_int)) {
2274                 stat = RD_REG_DWORD(&reg->host_status);
2275                 switch (stat & 0xff) {
2276                 case 0x1:
2277                 case 0x2:
2278                 case 0x10:
2279                 case 0x11:
2280                         qla82xx_mbx_completion(vha, MSW(stat));
2281                         status |= MBX_INTERRUPT;
2282                         break;
2283                 case 0x12:
2284                         mb[0] = MSW(stat);
2285                         mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2286                         mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2287                         mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2288                         qla2x00_async_event(vha, rsp, mb);
2289                         break;
2290                 case 0x13:
2291                         qla24xx_process_response_queue(vha, rsp);
2292                         break;
2293                 default:
2294                         DEBUG2(printk("scsi(%ld): Unrecognized interrupt type "
2295                                 "(%d).\n",
2296                                 vha->host_no, stat & 0xff));
2297                         break;
2298                 }
2299         }
2300         WRT_REG_DWORD(&reg->host_int, 0);
2301         spin_unlock_irqrestore(&ha->hardware_lock, flags);
2302 }
2303
2304 void
2305 qla82xx_enable_intrs(struct qla_hw_data *ha)
2306 {
2307         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2308         qla82xx_mbx_intr_enable(vha);
2309         spin_lock_irq(&ha->hardware_lock);
2310         qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2311         spin_unlock_irq(&ha->hardware_lock);
2312         ha->interrupts_on = 1;
2313 }
2314
2315 void
2316 qla82xx_disable_intrs(struct qla_hw_data *ha)
2317 {
2318         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2319         qla82xx_mbx_intr_disable(vha);
2320         spin_lock_irq(&ha->hardware_lock);
2321         qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
2322         spin_unlock_irq(&ha->hardware_lock);
2323         ha->interrupts_on = 0;
2324 }
2325
2326 void qla82xx_init_flags(struct qla_hw_data *ha)
2327 {
2328         struct qla82xx_legacy_intr_set *nx_legacy_intr;
2329
2330         /* ISP 8021 initializations */
2331         rwlock_init(&ha->hw_lock);
2332         ha->qdr_sn_window = -1;
2333         ha->ddr_mn_window = -1;
2334         ha->curr_window = 255;
2335         ha->portnum = PCI_FUNC(ha->pdev->devfn);
2336         nx_legacy_intr = &legacy_intr[ha->portnum];
2337         ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit;
2338         ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg;
2339         ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg;
2340         ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg;
2341 }
2342
2343 static inline void
2344 qla82xx_set_drv_active(scsi_qla_host_t *vha)
2345 {
2346         uint32_t drv_active;
2347         struct qla_hw_data *ha = vha->hw;
2348
2349         drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2350
2351         /* If reset value is all FF's, initialize DRV_ACTIVE */
2352         if (drv_active == 0xffffffff) {
2353                 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 0);
2354                 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2355         }
2356         drv_active |= (1 << (ha->portnum * 4));
2357         qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2358 }
2359
2360 inline void
2361 qla82xx_clear_drv_active(struct qla_hw_data *ha)
2362 {
2363         uint32_t drv_active;
2364
2365         drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2366         drv_active &= ~(1 << (ha->portnum * 4));
2367         qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2368 }
2369
2370 static inline int
2371 qla82xx_need_reset(struct qla_hw_data *ha)
2372 {
2373         uint32_t drv_state;
2374         int rval;
2375
2376         drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2377         rval = drv_state & (1 << (ha->portnum * 4));
2378         return rval;
2379 }
2380
2381 static inline void
2382 qla82xx_set_rst_ready(struct qla_hw_data *ha)
2383 {
2384         uint32_t drv_state;
2385         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2386
2387         drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2388
2389         /* If reset value is all FF's, initialize DRV_STATE */
2390         if (drv_state == 0xffffffff) {
2391                 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
2392                 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2393         }
2394         drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2395         qla_printk(KERN_INFO, ha,
2396                 "%s(%ld):drv_state = 0x%x\n",
2397                 __func__, vha->host_no, drv_state);
2398         qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2399 }
2400
2401 static inline void
2402 qla82xx_clear_rst_ready(struct qla_hw_data *ha)
2403 {
2404         uint32_t drv_state;
2405
2406         drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2407         drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2408         qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2409 }
2410
2411 static inline void
2412 qla82xx_set_qsnt_ready(struct qla_hw_data *ha)
2413 {
2414         uint32_t qsnt_state;
2415
2416         qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2417         qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2418         qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2419 }
2420
2421 int qla82xx_load_fw(scsi_qla_host_t *vha)
2422 {
2423         int rst;
2424         struct fw_blob *blob;
2425         struct qla_hw_data *ha = vha->hw;
2426
2427         /* Put both the PEG CMD and RCV PEG to default state
2428          * of 0 before resetting the hardware
2429          */
2430         qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
2431         qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
2432
2433         if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) {
2434                 qla_printk(KERN_ERR, ha,
2435                         "%s: Error during CRB Initialization\n", __func__);
2436                 return QLA_FUNCTION_FAILED;
2437         }
2438         udelay(500);
2439
2440         /* Bring QM and CAMRAM out of reset */
2441         rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
2442         rst &= ~((1 << 28) | (1 << 24));
2443         qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
2444
2445         /*
2446          * FW Load priority:
2447          * 1) Operational firmware residing in flash.
2448          * 2) Firmware via request-firmware interface (.bin file).
2449          */
2450         if (ql2xfwloadbin == 2)
2451                 goto try_blob_fw;
2452
2453         qla_printk(KERN_INFO, ha,
2454                 "Attempting to load firmware from flash\n");
2455
2456         if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) {
2457                 qla_printk(KERN_ERR, ha,
2458                         "Firmware loaded successfully from flash\n");
2459                 return QLA_SUCCESS;
2460         }
2461 try_blob_fw:
2462         qla_printk(KERN_INFO, ha,
2463             "Attempting to load firmware from blob\n");
2464
2465         /* Load firmware blob. */
2466         blob = ha->hablob = qla2x00_request_firmware(vha);
2467         if (!blob) {
2468                 qla_printk(KERN_ERR, ha,
2469                         "Firmware image not present.\n");
2470                 goto fw_load_failed;
2471         }
2472
2473         if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) {
2474                 qla_printk(KERN_ERR, ha,
2475                         "%s: Firmware loaded successfully "
2476                         " from binary blob\n", __func__);
2477                 return QLA_SUCCESS;
2478         } else {
2479                 qla_printk(KERN_ERR, ha,
2480                     "Firmware load failed from binary blob\n");
2481                 blob->fw = NULL;
2482                 blob = NULL;
2483                 goto fw_load_failed;
2484         }
2485         return QLA_SUCCESS;
2486
2487 fw_load_failed:
2488         return QLA_FUNCTION_FAILED;
2489 }
2490
2491 static int
2492 qla82xx_start_firmware(scsi_qla_host_t *vha)
2493 {
2494         int           pcie_cap;
2495         uint16_t      lnk;
2496         struct qla_hw_data *ha = vha->hw;
2497
2498         /* scrub dma mask expansion register */
2499         qla82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555);
2500
2501         /* Overwrite stale initialization register values */
2502         qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
2503         qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
2504
2505         if (qla82xx_load_fw(vha) != QLA_SUCCESS) {
2506                 qla_printk(KERN_INFO, ha,
2507                         "%s: Error trying to start fw!\n", __func__);
2508                 return QLA_FUNCTION_FAILED;
2509         }
2510
2511         /* Handshake with the card before we register the devices. */
2512         if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) {
2513                 qla_printk(KERN_INFO, ha,
2514                         "%s: Error during card handshake!\n", __func__);
2515                 return QLA_FUNCTION_FAILED;
2516         }
2517
2518         /* Negotiated Link width */
2519         pcie_cap = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
2520         pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk);
2521         ha->link_width = (lnk >> 4) & 0x3f;
2522
2523         /* Synchronize with Receive peg */
2524         return qla82xx_check_rcvpeg_state(ha);
2525 }
2526
2527 static inline int
2528 qla2xx_build_scsi_type_6_iocbs(srb_t *sp, struct cmd_type_6 *cmd_pkt,
2529         uint16_t tot_dsds)
2530 {
2531         uint32_t *cur_dsd = NULL;
2532         scsi_qla_host_t *vha;
2533         struct qla_hw_data *ha;
2534         struct scsi_cmnd *cmd;
2535         struct  scatterlist *cur_seg;
2536         uint32_t *dsd_seg;
2537         void *next_dsd;
2538         uint8_t avail_dsds;
2539         uint8_t first_iocb = 1;
2540         uint32_t dsd_list_len;
2541         struct dsd_dma *dsd_ptr;
2542         struct ct6_dsd *ctx;
2543
2544         cmd = sp->cmd;
2545
2546         /* Update entry type to indicate Command Type 3 IOCB */
2547         *((uint32_t *)(&cmd_pkt->entry_type)) =
2548                 __constant_cpu_to_le32(COMMAND_TYPE_6);
2549
2550         /* No data transfer */
2551         if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) {
2552                 cmd_pkt->byte_count = __constant_cpu_to_le32(0);
2553                 return 0;
2554         }
2555
2556         vha = sp->fcport->vha;
2557         ha = vha->hw;
2558
2559         /* Set transfer direction */
2560         if (cmd->sc_data_direction == DMA_TO_DEVICE) {
2561                 cmd_pkt->control_flags =
2562                     __constant_cpu_to_le16(CF_WRITE_DATA);
2563                 ha->qla_stats.output_bytes += scsi_bufflen(cmd);
2564         } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) {
2565                 cmd_pkt->control_flags =
2566                     __constant_cpu_to_le16(CF_READ_DATA);
2567                 ha->qla_stats.input_bytes += scsi_bufflen(cmd);
2568         }
2569
2570         cur_seg = scsi_sglist(cmd);
2571         ctx = sp->ctx;
2572
2573         while (tot_dsds) {
2574                 avail_dsds = (tot_dsds > QLA_DSDS_PER_IOCB) ?
2575                     QLA_DSDS_PER_IOCB : tot_dsds;
2576                 tot_dsds -= avail_dsds;
2577                 dsd_list_len = (avail_dsds + 1) * QLA_DSD_SIZE;
2578
2579                 dsd_ptr = list_first_entry(&ha->gbl_dsd_list,
2580                     struct dsd_dma, list);
2581                 next_dsd = dsd_ptr->dsd_addr;
2582                 list_del(&dsd_ptr->list);
2583                 ha->gbl_dsd_avail--;
2584                 list_add_tail(&dsd_ptr->list, &ctx->dsd_list);
2585                 ctx->dsd_use_cnt++;
2586                 ha->gbl_dsd_inuse++;
2587
2588                 if (first_iocb) {
2589                         first_iocb = 0;
2590                         dsd_seg = (uint32_t *)&cmd_pkt->fcp_data_dseg_address;
2591                         *dsd_seg++ = cpu_to_le32(LSD(dsd_ptr->dsd_list_dma));
2592                         *dsd_seg++ = cpu_to_le32(MSD(dsd_ptr->dsd_list_dma));
2593                         *dsd_seg++ = dsd_list_len;
2594                 } else {
2595                         *cur_dsd++ = cpu_to_le32(LSD(dsd_ptr->dsd_list_dma));
2596                         *cur_dsd++ = cpu_to_le32(MSD(dsd_ptr->dsd_list_dma));
2597                         *cur_dsd++ = dsd_list_len;
2598                 }
2599                 cur_dsd = (uint32_t *)next_dsd;
2600                 while (avail_dsds) {
2601                         dma_addr_t      sle_dma;
2602
2603                         sle_dma = sg_dma_address(cur_seg);
2604                         *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
2605                         *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
2606                         *cur_dsd++ = cpu_to_le32(sg_dma_len(cur_seg));
2607                         cur_seg++;
2608                         avail_dsds--;
2609                 }
2610         }
2611
2612         /* Null termination */
2613         *cur_dsd++ =  0;
2614         *cur_dsd++ = 0;
2615         *cur_dsd++ = 0;
2616         cmd_pkt->control_flags |= CF_DATA_SEG_DESCR_ENABLE;
2617         return 0;
2618 }
2619
2620 /*
2621  * qla82xx_calc_dsd_lists() - Determine number of DSD list required
2622  * for Command Type 6.
2623  *
2624  * @dsds: number of data segment decriptors needed
2625  *
2626  * Returns the number of dsd list needed to store @dsds.
2627  */
2628 inline uint16_t
2629 qla82xx_calc_dsd_lists(uint16_t dsds)
2630 {
2631         uint16_t dsd_lists = 0;
2632
2633         dsd_lists = (dsds/QLA_DSDS_PER_IOCB);
2634         if (dsds % QLA_DSDS_PER_IOCB)
2635                 dsd_lists++;
2636         return dsd_lists;
2637 }
2638
2639 /*
2640  * qla82xx_start_scsi() - Send a SCSI command to the ISP
2641  * @sp: command to send to the ISP
2642  *
2643  * Returns non-zero if a failure occured, else zero.
2644  */
2645 int
2646 qla82xx_start_scsi(srb_t *sp)
2647 {
2648         int             ret, nseg;
2649         unsigned long   flags;
2650         struct scsi_cmnd *cmd;
2651         uint32_t        *clr_ptr;
2652         uint32_t        index;
2653         uint32_t        handle;
2654         uint16_t        cnt;
2655         uint16_t        req_cnt;
2656         uint16_t        tot_dsds;
2657         struct device_reg_82xx __iomem *reg;
2658         uint32_t dbval;
2659         uint32_t *fcp_dl;
2660         uint8_t additional_cdb_len;
2661         struct ct6_dsd *ctx;
2662         struct scsi_qla_host *vha = sp->fcport->vha;
2663         struct qla_hw_data *ha = vha->hw;
2664         struct req_que *req = NULL;
2665         struct rsp_que *rsp = NULL;
2666
2667         /* Setup device pointers. */
2668         ret = 0;
2669         reg = &ha->iobase->isp82;
2670         cmd = sp->cmd;
2671         req = vha->req;
2672         rsp = ha->rsp_q_map[0];
2673
2674         /* So we know we haven't pci_map'ed anything yet */
2675         tot_dsds = 0;
2676
2677         dbval = 0x04 | (ha->portnum << 5);
2678
2679         /* Send marker if required */
2680         if (vha->marker_needed != 0) {
2681                 if (qla2x00_marker(vha, req,
2682                         rsp, 0, 0, MK_SYNC_ALL) != QLA_SUCCESS)
2683                         return QLA_FUNCTION_FAILED;
2684                 vha->marker_needed = 0;
2685         }
2686
2687         /* Acquire ring specific lock */
2688         spin_lock_irqsave(&ha->hardware_lock, flags);
2689
2690         /* Check for room in outstanding command list. */
2691         handle = req->current_outstanding_cmd;
2692         for (index = 1; index < MAX_OUTSTANDING_COMMANDS; index++) {
2693                 handle++;
2694                 if (handle == MAX_OUTSTANDING_COMMANDS)
2695                         handle = 1;
2696                 if (!req->outstanding_cmds[handle])
2697                         break;
2698         }
2699         if (index == MAX_OUTSTANDING_COMMANDS)
2700                 goto queuing_error;
2701
2702         /* Map the sg table so we have an accurate count of sg entries needed */
2703         if (scsi_sg_count(cmd)) {
2704                 nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd),
2705                     scsi_sg_count(cmd), cmd->sc_data_direction);
2706                 if (unlikely(!nseg))
2707                         goto queuing_error;
2708         } else
2709                 nseg = 0;
2710
2711         tot_dsds = nseg;
2712
2713         if (tot_dsds > ql2xshiftctondsd) {
2714                 struct cmd_type_6 *cmd_pkt;
2715                 uint16_t more_dsd_lists = 0;
2716                 struct dsd_dma *dsd_ptr;
2717                 uint16_t i;
2718
2719                 more_dsd_lists = qla82xx_calc_dsd_lists(tot_dsds);
2720                 if ((more_dsd_lists + ha->gbl_dsd_inuse) >= NUM_DSD_CHAIN)
2721                         goto queuing_error;
2722
2723                 if (more_dsd_lists <= ha->gbl_dsd_avail)
2724                         goto sufficient_dsds;
2725                 else
2726                         more_dsd_lists -= ha->gbl_dsd_avail;
2727
2728                 for (i = 0; i < more_dsd_lists; i++) {
2729                         dsd_ptr = kzalloc(sizeof(struct dsd_dma), GFP_ATOMIC);
2730                         if (!dsd_ptr)
2731                                 goto queuing_error;
2732
2733                         dsd_ptr->dsd_addr = dma_pool_alloc(ha->dl_dma_pool,
2734                                 GFP_ATOMIC, &dsd_ptr->dsd_list_dma);
2735                         if (!dsd_ptr->dsd_addr) {
2736                                 kfree(dsd_ptr);
2737                                 goto queuing_error;
2738                         }
2739                         list_add_tail(&dsd_ptr->list, &ha->gbl_dsd_list);
2740                         ha->gbl_dsd_avail++;
2741                 }
2742
2743 sufficient_dsds:
2744                 req_cnt = 1;
2745
2746                 ctx = sp->ctx = mempool_alloc(ha->ctx_mempool, GFP_ATOMIC);
2747                 if (!sp->ctx) {
2748                         DEBUG(printk(KERN_INFO
2749                                 "%s(%ld): failed to allocate"
2750                                 " ctx.\n", __func__, vha->host_no));
2751                         goto queuing_error;
2752                 }
2753                 memset(ctx, 0, sizeof(struct ct6_dsd));
2754                 ctx->fcp_cmnd = dma_pool_alloc(ha->fcp_cmnd_dma_pool,
2755                         GFP_ATOMIC, &ctx->fcp_cmnd_dma);
2756                 if (!ctx->fcp_cmnd) {
2757                         DEBUG2_3(printk("%s(%ld): failed to allocate"
2758                                 " fcp_cmnd.\n", __func__, vha->host_no));
2759                         goto queuing_error_fcp_cmnd;
2760                 }
2761
2762                 /* Initialize the DSD list and dma handle */
2763                 INIT_LIST_HEAD(&ctx->dsd_list);
2764                 ctx->dsd_use_cnt = 0;
2765
2766                 if (cmd->cmd_len > 16) {
2767                         additional_cdb_len = cmd->cmd_len - 16;
2768                         if ((cmd->cmd_len % 4) != 0) {
2769                                 /* SCSI command bigger than 16 bytes must be
2770                                  * multiple of 4
2771                                  */
2772                                 goto queuing_error_fcp_cmnd;
2773                         }
2774                         ctx->fcp_cmnd_len = 12 + cmd->cmd_len + 4;
2775                 } else {
2776                         additional_cdb_len = 0;
2777                         ctx->fcp_cmnd_len = 12 + 16 + 4;
2778                 }
2779
2780                 cmd_pkt = (struct cmd_type_6 *)req->ring_ptr;
2781                 cmd_pkt->handle = MAKE_HANDLE(req->id, handle);
2782
2783                 /* Zero out remaining portion of packet. */
2784                 /*    tagged queuing modifier -- default is TSK_SIMPLE (0). */
2785                 clr_ptr = (uint32_t *)cmd_pkt + 2;
2786                 memset(clr_ptr, 0, REQUEST_ENTRY_SIZE - 8);
2787                 cmd_pkt->dseg_count = cpu_to_le16(tot_dsds);
2788
2789                 /* Set NPORT-ID and LUN number*/
2790                 cmd_pkt->nport_handle = cpu_to_le16(sp->fcport->loop_id);
2791                 cmd_pkt->port_id[0] = sp->fcport->d_id.b.al_pa;
2792                 cmd_pkt->port_id[1] = sp->fcport->d_id.b.area;
2793                 cmd_pkt->port_id[2] = sp->fcport->d_id.b.domain;
2794                 cmd_pkt->vp_index = sp->fcport->vp_idx;
2795
2796                 /* Build IOCB segments */
2797                 if (qla2xx_build_scsi_type_6_iocbs(sp, cmd_pkt, tot_dsds))
2798                         goto queuing_error_fcp_cmnd;
2799
2800                 int_to_scsilun(sp->cmd->device->lun, &cmd_pkt->lun);
2801
2802                 /* build FCP_CMND IU */
2803                 memset(ctx->fcp_cmnd, 0, sizeof(struct fcp_cmnd));
2804                 int_to_scsilun(sp->cmd->device->lun, &ctx->fcp_cmnd->lun);
2805                 ctx->fcp_cmnd->additional_cdb_len = additional_cdb_len;
2806
2807                 if (cmd->sc_data_direction == DMA_TO_DEVICE)
2808                         ctx->fcp_cmnd->additional_cdb_len |= 1;
2809                 else if (cmd->sc_data_direction == DMA_FROM_DEVICE)
2810                         ctx->fcp_cmnd->additional_cdb_len |= 2;
2811
2812                 memcpy(ctx->fcp_cmnd->cdb, cmd->cmnd, cmd->cmd_len);
2813
2814                 fcp_dl = (uint32_t *)(ctx->fcp_cmnd->cdb + 16 +
2815                     additional_cdb_len);
2816                 *fcp_dl = htonl((uint32_t)scsi_bufflen(cmd));
2817
2818                 cmd_pkt->fcp_cmnd_dseg_len = cpu_to_le16(ctx->fcp_cmnd_len);
2819                 cmd_pkt->fcp_cmnd_dseg_address[0] =
2820                     cpu_to_le32(LSD(ctx->fcp_cmnd_dma));
2821                 cmd_pkt->fcp_cmnd_dseg_address[1] =
2822                     cpu_to_le32(MSD(ctx->fcp_cmnd_dma));
2823
2824                 sp->flags |= SRB_FCP_CMND_DMA_VALID;
2825                 cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd));
2826                 /* Set total data segment count. */
2827                 cmd_pkt->entry_count = (uint8_t)req_cnt;
2828                 /* Specify response queue number where
2829                  * completion should happen
2830                  */
2831                 cmd_pkt->entry_status = (uint8_t) rsp->id;
2832         } else {
2833                 struct cmd_type_7 *cmd_pkt;
2834                 req_cnt = qla24xx_calc_iocbs(tot_dsds);
2835                 if (req->cnt < (req_cnt + 2)) {
2836                         cnt = (uint16_t)RD_REG_DWORD_RELAXED(
2837                             &reg->req_q_out[0]);
2838                         if (req->ring_index < cnt)
2839                                 req->cnt = cnt - req->ring_index;
2840                         else
2841                                 req->cnt = req->length -
2842                                         (req->ring_index - cnt);
2843                 }
2844                 if (req->cnt < (req_cnt + 2))
2845                         goto queuing_error;
2846
2847                 cmd_pkt = (struct cmd_type_7 *)req->ring_ptr;
2848                 cmd_pkt->handle = MAKE_HANDLE(req->id, handle);
2849
2850                 /* Zero out remaining portion of packet. */
2851                 /* tagged queuing modifier -- default is TSK_SIMPLE (0).*/
2852                 clr_ptr = (uint32_t *)cmd_pkt + 2;
2853                 memset(clr_ptr, 0, REQUEST_ENTRY_SIZE - 8);
2854                 cmd_pkt->dseg_count = cpu_to_le16(tot_dsds);
2855
2856                 /* Set NPORT-ID and LUN number*/
2857                 cmd_pkt->nport_handle = cpu_to_le16(sp->fcport->loop_id);
2858                 cmd_pkt->port_id[0] = sp->fcport->d_id.b.al_pa;
2859                 cmd_pkt->port_id[1] = sp->fcport->d_id.b.area;
2860                 cmd_pkt->port_id[2] = sp->fcport->d_id.b.domain;
2861                 cmd_pkt->vp_index = sp->fcport->vp_idx;
2862
2863                 int_to_scsilun(sp->cmd->device->lun, &cmd_pkt->lun);
2864                 host_to_fcp_swap((uint8_t *)&cmd_pkt->lun,
2865                         sizeof(cmd_pkt->lun));
2866
2867                 /* Load SCSI command packet. */
2868                 memcpy(cmd_pkt->fcp_cdb, cmd->cmnd, cmd->cmd_len);
2869                 host_to_fcp_swap(cmd_pkt->fcp_cdb, sizeof(cmd_pkt->fcp_cdb));
2870
2871                 cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd));
2872
2873                 /* Build IOCB segments */
2874                 qla24xx_build_scsi_iocbs(sp, cmd_pkt, tot_dsds);
2875
2876                 /* Set total data segment count. */
2877                 cmd_pkt->entry_count = (uint8_t)req_cnt;
2878                 /* Specify response queue number where
2879                  * completion should happen.
2880                  */
2881                 cmd_pkt->entry_status = (uint8_t) rsp->id;
2882
2883         }
2884         /* Build command packet. */
2885         req->current_outstanding_cmd = handle;
2886         req->outstanding_cmds[handle] = sp;
2887         sp->handle = handle;
2888         sp->cmd->host_scribble = (unsigned char *)(unsigned long)handle;
2889         req->cnt -= req_cnt;
2890         wmb();
2891
2892         /* Adjust ring index. */
2893         req->ring_index++;
2894         if (req->ring_index == req->length) {
2895                 req->ring_index = 0;
2896                 req->ring_ptr = req->ring;
2897         } else
2898                 req->ring_ptr++;
2899
2900         sp->flags |= SRB_DMA_VALID;
2901
2902         /* Set chip new ring index. */
2903         /* write, read and verify logic */
2904         dbval = dbval | (req->id << 8) | (req->ring_index << 16);
2905         if (ql2xdbwr)
2906                 qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval);
2907         else {
2908                 WRT_REG_DWORD(
2909                         (unsigned long __iomem *)ha->nxdb_wr_ptr,
2910                         dbval);
2911                 wmb();
2912                 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) {
2913                         WRT_REG_DWORD(
2914                                 (unsigned long __iomem *)ha->nxdb_wr_ptr,
2915                                 dbval);
2916                         wmb();
2917                 }
2918         }
2919
2920         /* Manage unprocessed RIO/ZIO commands in response queue. */
2921         if (vha->flags.process_response_queue &&
2922             rsp->ring_ptr->signature != RESPONSE_PROCESSED)
2923                 qla24xx_process_response_queue(vha, rsp);
2924
2925         spin_unlock_irqrestore(&ha->hardware_lock, flags);
2926         return QLA_SUCCESS;
2927
2928 queuing_error_fcp_cmnd:
2929         dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd, ctx->fcp_cmnd_dma);
2930 queuing_error:
2931         if (tot_dsds)
2932                 scsi_dma_unmap(cmd);
2933
2934         if (sp->ctx) {
2935                 mempool_free(sp->ctx, ha->ctx_mempool);
2936                 sp->ctx = NULL;
2937         }
2938         spin_unlock_irqrestore(&ha->hardware_lock, flags);
2939
2940         return QLA_FUNCTION_FAILED;
2941 }
2942
2943 uint32_t *
2944 qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
2945         uint32_t length)
2946 {
2947         uint32_t i;
2948         uint32_t val;
2949         struct qla_hw_data *ha = vha->hw;
2950
2951         /* Dword reads to flash. */
2952         for (i = 0; i < length/4; i++, faddr += 4) {
2953                 if (qla82xx_rom_fast_read(ha, faddr, &val)) {
2954                         qla_printk(KERN_WARNING, ha,
2955                             "Do ROM fast read failed\n");
2956                         goto done_read;
2957                 }
2958                 dwptr[i] = __constant_cpu_to_le32(val);
2959         }
2960 done_read:
2961         return dwptr;
2962 }
2963
2964 int
2965 qla82xx_unprotect_flash(struct qla_hw_data *ha)
2966 {
2967         int ret;
2968         uint32_t val;
2969
2970         ret = ql82xx_rom_lock_d(ha);
2971         if (ret < 0) {
2972                 qla_printk(KERN_WARNING, ha, "ROM Lock failed\n");
2973                 return ret;
2974         }
2975
2976         ret = qla82xx_read_status_reg(ha, &val);
2977         if (ret < 0)
2978                 goto done_unprotect;
2979
2980         val &= ~(0x7 << 2);
2981         ret = qla82xx_write_status_reg(ha, val);
2982         if (ret < 0) {
2983                 val |= (0x7 << 2);
2984                 qla82xx_write_status_reg(ha, val);
2985         }
2986
2987         if (qla82xx_write_disable_flash(ha) != 0)
2988                 qla_printk(KERN_WARNING, ha, "Write disable failed\n");
2989
2990 done_unprotect:
2991         qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
2992         return ret;
2993 }
2994
2995 int
2996 qla82xx_protect_flash(struct qla_hw_data *ha)
2997 {
2998         int ret;
2999         uint32_t val;
3000
3001         ret = ql82xx_rom_lock_d(ha);
3002         if (ret < 0) {
3003                 qla_printk(KERN_WARNING, ha, "ROM Lock failed\n");
3004                 return ret;
3005         }
3006
3007         ret = qla82xx_read_status_reg(ha, &val);
3008         if (ret < 0)
3009                 goto done_protect;
3010
3011         val |= (0x7 << 2);
3012         /* LOCK all sectors */
3013         ret = qla82xx_write_status_reg(ha, val);
3014         if (ret < 0)
3015                 qla_printk(KERN_WARNING, ha, "Write status register failed\n");
3016
3017         if (qla82xx_write_disable_flash(ha) != 0)
3018                 qla_printk(KERN_WARNING, ha, "Write disable failed\n");
3019 done_protect:
3020         qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
3021         return ret;
3022 }
3023
3024 int
3025 qla82xx_erase_sector(struct qla_hw_data *ha, int addr)
3026 {
3027         int ret = 0;
3028
3029         ret = ql82xx_rom_lock_d(ha);
3030         if (ret < 0) {
3031                 qla_printk(KERN_WARNING, ha, "ROM Lock failed\n");
3032                 return ret;
3033         }
3034
3035         qla82xx_flash_set_write_enable(ha);
3036         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
3037         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
3038         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE);
3039
3040         if (qla82xx_wait_rom_done(ha)) {
3041                 qla_printk(KERN_WARNING, ha,
3042                     "Error waiting for rom done\n");
3043                 ret = -1;
3044                 goto done;
3045         }
3046         ret = qla82xx_flash_wait_write_finish(ha);
3047 done:
3048         qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
3049         return ret;
3050 }
3051
3052 /*
3053  * Address and length are byte address
3054  */
3055 uint8_t *
3056 qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
3057         uint32_t offset, uint32_t length)
3058 {
3059         scsi_block_requests(vha->host);
3060         qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length);
3061         scsi_unblock_requests(vha->host);
3062         return buf;
3063 }
3064
3065 static int
3066 qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr,
3067         uint32_t faddr, uint32_t dwords)
3068 {
3069         int ret;
3070         uint32_t liter;
3071         uint32_t sec_mask, rest_addr;
3072         dma_addr_t optrom_dma;
3073         void *optrom = NULL;
3074         int page_mode = 0;
3075         struct qla_hw_data *ha = vha->hw;
3076
3077         ret = -1;
3078
3079         /* Prepare burst-capable write on supported ISPs. */
3080         if (page_mode && !(faddr & 0xfff) &&
3081             dwords > OPTROM_BURST_DWORDS) {
3082                 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
3083                     &optrom_dma, GFP_KERNEL);
3084                 if (!optrom) {
3085                         qla_printk(KERN_DEBUG, ha,
3086                                 "Unable to allocate memory for optrom "
3087                                 "burst write (%x KB).\n",
3088                                 OPTROM_BURST_SIZE / 1024);
3089                 }
3090         }
3091
3092         rest_addr = ha->fdt_block_size - 1;
3093         sec_mask = ~rest_addr;
3094
3095         ret = qla82xx_unprotect_flash(ha);
3096         if (ret) {
3097                 qla_printk(KERN_WARNING, ha,
3098                         "Unable to unprotect flash for update.\n");
3099                 goto write_done;
3100         }
3101
3102         for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
3103                 /* Are we at the beginning of a sector? */
3104                 if ((faddr & rest_addr) == 0) {
3105
3106                         ret = qla82xx_erase_sector(ha, faddr);
3107                         if (ret) {
3108                                 DEBUG9(qla_printk(KERN_ERR, ha,
3109                                     "Unable to erase sector: "
3110                                     "address=%x.\n", faddr));
3111                                 break;
3112                         }
3113                 }
3114
3115                 /* Go with burst-write. */
3116                 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
3117                         /* Copy data to DMA'ble buffer. */
3118                         memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
3119
3120                         ret = qla2x00_load_ram(vha, optrom_dma,
3121                             (ha->flash_data_off | faddr),
3122                             OPTROM_BURST_DWORDS);
3123                         if (ret != QLA_SUCCESS) {
3124                                 qla_printk(KERN_WARNING, ha,
3125                                     "Unable to burst-write optrom segment "
3126                                     "(%x/%x/%llx).\n", ret,
3127                                     (ha->flash_data_off | faddr),
3128                                     (unsigned long long)optrom_dma);
3129                                 qla_printk(KERN_WARNING, ha,
3130                                     "Reverting to slow-write.\n");
3131
3132                                 dma_free_coherent(&ha->pdev->dev,
3133                                     OPTROM_BURST_SIZE, optrom, optrom_dma);
3134                                 optrom = NULL;
3135                         } else {
3136                                 liter += OPTROM_BURST_DWORDS - 1;
3137                                 faddr += OPTROM_BURST_DWORDS - 1;
3138                                 dwptr += OPTROM_BURST_DWORDS - 1;
3139                                 continue;
3140                         }
3141                 }
3142
3143                 ret = qla82xx_write_flash_dword(ha, faddr,
3144                     cpu_to_le32(*dwptr));
3145                 if (ret) {
3146                         DEBUG9(printk(KERN_DEBUG "%s(%ld) Unable to program"
3147                             "flash address=%x data=%x.\n", __func__,
3148                             ha->host_no, faddr, *dwptr));
3149                         break;
3150                 }
3151         }
3152
3153         ret = qla82xx_protect_flash(ha);
3154         if (ret)
3155                 qla_printk(KERN_WARNING, ha,
3156                     "Unable to protect flash after update.\n");
3157 write_done:
3158         if (optrom)
3159                 dma_free_coherent(&ha->pdev->dev,
3160                     OPTROM_BURST_SIZE, optrom, optrom_dma);
3161         return ret;
3162 }
3163
3164 int
3165 qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
3166         uint32_t offset, uint32_t length)
3167 {
3168         int rval;
3169
3170         /* Suspend HBA. */
3171         scsi_block_requests(vha->host);
3172         rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset,
3173                 length >> 2);
3174         scsi_unblock_requests(vha->host);
3175
3176         /* Convert return ISP82xx to generic */
3177         if (rval)
3178                 rval = QLA_FUNCTION_FAILED;
3179         else
3180                 rval = QLA_SUCCESS;
3181         return rval;
3182 }
3183
3184 void
3185 qla82xx_start_iocbs(srb_t *sp)
3186 {
3187         struct qla_hw_data *ha = sp->fcport->vha->hw;
3188         struct req_que *req = ha->req_q_map[0];
3189         struct device_reg_82xx __iomem *reg;
3190         uint32_t dbval;
3191
3192         /* Adjust ring index. */
3193         req->ring_index++;
3194         if (req->ring_index == req->length) {
3195                 req->ring_index = 0;
3196                 req->ring_ptr = req->ring;
3197         } else
3198                 req->ring_ptr++;
3199
3200         reg = &ha->iobase->isp82;
3201         dbval = 0x04 | (ha->portnum << 5);
3202
3203         dbval = dbval | (req->id << 8) | (req->ring_index << 16);
3204         WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval);
3205         wmb();
3206         while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) {
3207                 WRT_REG_DWORD((unsigned long  __iomem *)ha->nxdb_wr_ptr, dbval);
3208                 wmb();
3209         }
3210 }
3211
3212 /*
3213  * qla82xx_device_bootstrap
3214  *    Initialize device, set DEV_READY, start fw
3215  *
3216  * Note:
3217  *      IDC lock must be held upon entry
3218  *
3219  * Return:
3220  *    Success : 0
3221  *    Failed  : 1
3222  */
3223 static int
3224 qla82xx_device_bootstrap(scsi_qla_host_t *vha)
3225 {
3226         int rval, i, timeout;
3227         uint32_t old_count, count;
3228         struct qla_hw_data *ha = vha->hw;
3229
3230         if (qla82xx_need_reset(ha))
3231                 goto dev_initialize;
3232
3233         old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
3234
3235         for (i = 0; i < 10; i++) {
3236                 timeout = msleep_interruptible(200);
3237                 if (timeout) {
3238                         qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3239                                 QLA82XX_DEV_FAILED);
3240                         return QLA_FUNCTION_FAILED;
3241                 }
3242
3243                 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
3244                 if (count != old_count)
3245                         goto dev_ready;
3246         }
3247
3248 dev_initialize:
3249         /* set to DEV_INITIALIZING */
3250         qla_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
3251         qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING);
3252
3253         /* Driver that sets device state to initializating sets IDC version */
3254         qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION);
3255
3256         qla82xx_idc_unlock(ha);
3257         rval = qla82xx_start_firmware(vha);
3258         qla82xx_idc_lock(ha);
3259
3260         if (rval != QLA_SUCCESS) {
3261                 qla_printk(KERN_INFO, ha, "HW State: FAILED\n");
3262                 qla82xx_clear_drv_active(ha);
3263                 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED);
3264                 return rval;
3265         }
3266
3267 dev_ready:
3268         qla_printk(KERN_INFO, ha, "HW State: READY\n");
3269         qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY);
3270
3271         return QLA_SUCCESS;
3272 }
3273
3274 static void
3275 qla82xx_dev_failed_handler(scsi_qla_host_t *vha)
3276 {
3277         struct qla_hw_data *ha = vha->hw;
3278
3279         /* Disable the board */
3280         qla_printk(KERN_INFO, ha, "Disabling the board\n");
3281
3282         /* Set DEV_FAILED flag to disable timer */
3283         vha->device_flags |= DFLG_DEV_FAILED;
3284         qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3285         qla2x00_mark_all_devices_lost(vha, 0);
3286         vha->flags.online = 0;
3287         vha->flags.init_done = 0;
3288 }
3289
3290 /*
3291  * qla82xx_need_reset_handler
3292  *    Code to start reset sequence
3293  *
3294  * Note:
3295  *      IDC lock must be held upon entry
3296  *
3297  * Return:
3298  *    Success : 0
3299  *    Failed  : 1
3300  */
3301 static void
3302 qla82xx_need_reset_handler(scsi_qla_host_t *vha)
3303 {
3304         uint32_t dev_state, drv_state, drv_active;
3305         unsigned long reset_timeout;
3306         struct qla_hw_data *ha = vha->hw;
3307         struct req_que *req = ha->req_q_map[0];
3308
3309         if (vha->flags.online) {
3310                 qla82xx_idc_unlock(ha);
3311                 qla2x00_abort_isp_cleanup(vha);
3312                 ha->isp_ops->get_flash_version(vha, req->ring);
3313                 ha->isp_ops->nvram_config(vha);
3314                 qla82xx_idc_lock(ha);
3315         }
3316
3317         qla82xx_set_rst_ready(ha);
3318
3319         /* wait for 10 seconds for reset ack from all functions */
3320         reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
3321
3322         drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3323         drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3324
3325         while (drv_state != drv_active) {
3326                 if (time_after_eq(jiffies, reset_timeout)) {
3327                         qla_printk(KERN_INFO, ha,
3328                                 "%s: RESET TIMEOUT!\n", QLA2XXX_DRIVER_NAME);
3329                         break;
3330                 }
3331                 qla82xx_idc_unlock(ha);
3332                 msleep(1000);
3333                 qla82xx_idc_lock(ha);
3334                 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3335                 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3336         }
3337
3338         dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3339         qla_printk(KERN_INFO, ha, "3:Device state is 0x%x = %s\n", dev_state,
3340                 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
3341
3342         /* Force to DEV_COLD unless someone else is starting a reset */
3343         if (dev_state != QLA82XX_DEV_INITIALIZING) {
3344                 qla_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n");
3345                 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD);
3346         }
3347 }
3348
3349 static void
3350 qla82xx_check_fw_alive(scsi_qla_host_t *vha)
3351 {
3352         uint32_t fw_heartbeat_counter, halt_status;
3353         struct qla_hw_data *ha = vha->hw;
3354
3355         fw_heartbeat_counter = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
3356         if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
3357                 vha->seconds_since_last_heartbeat++;
3358                 /* FW not alive after 2 seconds */
3359                 if (vha->seconds_since_last_heartbeat == 2) {
3360                         vha->seconds_since_last_heartbeat = 0;
3361                         halt_status = qla82xx_rd_32(ha,
3362                                 QLA82XX_PEG_HALT_STATUS1);
3363                         if (halt_status & HALT_STATUS_UNRECOVERABLE) {
3364                                 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3365                         } else {
3366                                 qla_printk(KERN_INFO, ha,
3367                                         "scsi(%ld): %s - detect abort needed\n",
3368                                         vha->host_no, __func__);
3369                                 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
3370                         }
3371                         qla2xxx_wake_dpc(vha);
3372                 }
3373         }
3374         vha->fw_heartbeat_counter = fw_heartbeat_counter;
3375 }
3376
3377 /*
3378  * qla82xx_device_state_handler
3379  *      Main state handler
3380  *
3381  * Note:
3382  *      IDC lock must be held upon entry
3383  *
3384  * Return:
3385  *    Success : 0
3386  *    Failed  : 1
3387  */
3388 int
3389 qla82xx_device_state_handler(scsi_qla_host_t *vha)
3390 {
3391         uint32_t dev_state;
3392         int rval = QLA_SUCCESS;
3393         unsigned long dev_init_timeout;
3394         struct qla_hw_data *ha = vha->hw;
3395
3396         qla82xx_idc_lock(ha);
3397         if (!vha->flags.init_done)
3398                 qla82xx_set_drv_active(vha);
3399
3400         dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3401         qla_printk(KERN_INFO, ha, "1:Device state is 0x%x = %s\n", dev_state,
3402                 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
3403
3404         /* wait for 30 seconds for device to go ready */
3405         dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
3406
3407         while (1) {
3408
3409                 if (time_after_eq(jiffies, dev_init_timeout)) {
3410                         DEBUG(qla_printk(KERN_INFO, ha,
3411                                 "%s: device init failed!\n",
3412                                 QLA2XXX_DRIVER_NAME));
3413                         rval = QLA_FUNCTION_FAILED;
3414                         break;
3415                 }
3416                 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3417                 qla_printk(KERN_INFO, ha,
3418                         "2:Device state is 0x%x = %s\n", dev_state,
3419                         dev_state < MAX_STATES ?
3420                         qdev_state[dev_state] : "Unknown");
3421
3422                 switch (dev_state) {
3423                 case QLA82XX_DEV_READY:
3424                         goto exit;
3425                 case QLA82XX_DEV_COLD:
3426                         rval = qla82xx_device_bootstrap(vha);
3427                         goto exit;
3428                 case QLA82XX_DEV_INITIALIZING:
3429                         qla82xx_idc_unlock(ha);
3430                         msleep(1000);
3431                         qla82xx_idc_lock(ha);
3432                         break;
3433                 case QLA82XX_DEV_NEED_RESET:
3434                         if (!ql2xdontresethba)
3435                                 qla82xx_need_reset_handler(vha);
3436                         break;
3437                 case QLA82XX_DEV_NEED_QUIESCENT:
3438                         qla82xx_set_qsnt_ready(ha);
3439                 case QLA82XX_DEV_QUIESCENT:
3440                         qla82xx_idc_unlock(ha);
3441                         msleep(1000);
3442                         qla82xx_idc_lock(ha);
3443                         break;
3444                 case QLA82XX_DEV_FAILED:
3445                         qla82xx_dev_failed_handler(vha);
3446                         rval = QLA_FUNCTION_FAILED;
3447                         goto exit;
3448                 default:
3449                         qla82xx_idc_unlock(ha);
3450                         msleep(1000);
3451                         qla82xx_idc_lock(ha);
3452                 }
3453         }
3454 exit:
3455         qla82xx_idc_unlock(ha);
3456         return rval;
3457 }
3458
3459 void qla82xx_watchdog(scsi_qla_host_t *vha)
3460 {
3461         uint32_t dev_state;
3462         struct qla_hw_data *ha = vha->hw;
3463
3464         dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3465
3466         /* don't poll if reset is going on */
3467         if (!(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
3468                 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) ||
3469                 test_bit(ISP_ABORT_RETRY, &vha->dpc_flags))) {
3470                 if (dev_state == QLA82XX_DEV_NEED_RESET) {
3471                         qla_printk(KERN_WARNING, ha,
3472                                 "%s(): Adapter reset needed!\n", __func__);
3473                         set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
3474                         qla2xxx_wake_dpc(vha);
3475                 } else {
3476                         qla82xx_check_fw_alive(vha);
3477                 }
3478         }
3479 }
3480
3481 int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
3482 {
3483         int rval;
3484         rval = qla82xx_device_state_handler(vha);
3485         return rval;
3486 }
3487
3488 /*
3489  *  qla82xx_abort_isp
3490  *      Resets ISP and aborts all outstanding commands.
3491  *
3492  * Input:
3493  *      ha           = adapter block pointer.
3494  *
3495  * Returns:
3496  *      0 = success
3497  */
3498 int
3499 qla82xx_abort_isp(scsi_qla_host_t *vha)
3500 {
3501         int rval;
3502         struct qla_hw_data *ha = vha->hw;
3503         uint32_t dev_state;
3504
3505         if (vha->device_flags & DFLG_DEV_FAILED) {
3506                 qla_printk(KERN_WARNING, ha,
3507                         "%s(%ld): Device in failed state, "
3508                         "Exiting.\n", __func__, vha->host_no);
3509                 return QLA_SUCCESS;
3510         }
3511
3512         qla82xx_idc_lock(ha);
3513         dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3514         if (dev_state == QLA82XX_DEV_READY) {
3515                 qla_printk(KERN_INFO, ha, "HW State: NEED RESET\n");
3516                 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3517                         QLA82XX_DEV_NEED_RESET);
3518         } else
3519                 qla_printk(KERN_INFO, ha, "HW State: %s\n",
3520                         dev_state < MAX_STATES ?
3521                         qdev_state[dev_state] : "Unknown");
3522         qla82xx_idc_unlock(ha);
3523
3524         rval = qla82xx_device_state_handler(vha);
3525
3526         qla82xx_idc_lock(ha);
3527         qla82xx_clear_rst_ready(ha);
3528         qla82xx_idc_unlock(ha);
3529
3530         if (rval == QLA_SUCCESS)
3531                 qla82xx_restart_isp(vha);
3532
3533         if (rval) {
3534                 vha->flags.online = 1;
3535                 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
3536                         if (ha->isp_abort_cnt == 0) {
3537                                 qla_printk(KERN_WARNING, ha,
3538                                     "ISP error recovery failed - "
3539                                     "board disabled\n");
3540                                 /*
3541                                  * The next call disables the board
3542                                  * completely.
3543                                  */
3544                                 ha->isp_ops->reset_adapter(vha);
3545                                 vha->flags.online = 0;
3546                                 clear_bit(ISP_ABORT_RETRY,
3547                                     &vha->dpc_flags);
3548                                 rval = QLA_SUCCESS;
3549                         } else { /* schedule another ISP abort */
3550                                 ha->isp_abort_cnt--;
3551                                 DEBUG(qla_printk(KERN_INFO, ha,
3552                                     "qla%ld: ISP abort - retry remaining %d\n",
3553                                     vha->host_no, ha->isp_abort_cnt));
3554                                 rval = QLA_FUNCTION_FAILED;
3555                         }
3556                 } else {
3557                         ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
3558                         DEBUG(qla_printk(KERN_INFO, ha,
3559                             "(%ld): ISP error recovery - retrying (%d) "
3560                             "more times\n", vha->host_no, ha->isp_abort_cnt));
3561                         set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3562                         rval = QLA_FUNCTION_FAILED;
3563                 }
3564         }
3565         return rval;
3566 }
3567
3568 /*
3569  *  qla82xx_fcoe_ctx_reset
3570  *      Perform a quick reset and aborts all outstanding commands.
3571  *      This will only perform an FCoE context reset and avoids a full blown
3572  *      chip reset.
3573  *
3574  * Input:
3575  *      ha = adapter block pointer.
3576  *      is_reset_path = flag for identifying the reset path.
3577  *
3578  * Returns:
3579  *      0 = success
3580  */
3581 int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha)
3582 {
3583         int rval = QLA_FUNCTION_FAILED;
3584
3585         if (vha->flags.online) {
3586                 /* Abort all outstanding commands, so as to be requeued later */
3587                 qla2x00_abort_isp_cleanup(vha);
3588         }
3589
3590         /* Stop currently executing firmware.
3591          * This will destroy existing FCoE context at the F/W end.
3592          */
3593         qla2x00_try_to_stop_firmware(vha);
3594
3595         /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */
3596         rval = qla82xx_restart_isp(vha);
3597
3598         return rval;
3599 }
3600
3601 /*
3602  * qla2x00_wait_for_fcoe_ctx_reset
3603  *    Wait till the FCoE context is reset.
3604  *
3605  * Note:
3606  *    Does context switching here.
3607  *    Release SPIN_LOCK (if any) before calling this routine.
3608  *
3609  * Return:
3610  *    Success (fcoe_ctx reset is done) : 0
3611  *    Failed  (fcoe_ctx reset not completed within max loop timout ) : 1
3612  */
3613 int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha)
3614 {
3615         int status = QLA_FUNCTION_FAILED;
3616         unsigned long wait_reset;
3617
3618         wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
3619         while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
3620             test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
3621             && time_before(jiffies, wait_reset)) {
3622
3623                 set_current_state(TASK_UNINTERRUPTIBLE);
3624                 schedule_timeout(HZ);
3625
3626                 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) &&
3627                     !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) {
3628                         status = QLA_SUCCESS;
3629                         break;
3630                 }
3631         }
3632         DEBUG2(printk(KERN_INFO
3633             "%s status=%d\n", __func__, status));
3634
3635         return status;
3636 }