2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2005 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
9 #include <linux/delay.h>
12 qla2xxx_prep_dump(scsi_qla_host_t *ha, struct qla2xxx_fw_dump *fw_dump)
14 fw_dump->fw_major_version = htonl(ha->fw_major_version);
15 fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
16 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
17 fw_dump->fw_attributes = htonl(ha->fw_attributes);
19 fw_dump->vendor = htonl(ha->pdev->vendor);
20 fw_dump->device = htonl(ha->pdev->device);
21 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
22 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
26 qla2xxx_copy_queues(scsi_qla_host_t *ha, void *ptr)
29 memcpy(ptr, ha->request_ring, ha->request_q_length *
33 ptr += ha->request_q_length * sizeof(request_t);
34 memcpy(ptr, ha->response_ring, ha->response_q_length *
37 return ptr + (ha->response_q_length * sizeof(response_t));
41 qla24xx_dump_memory(scsi_qla_host_t *ha, uint32_t *code_ram,
42 uint32_t cram_size, uint32_t *ext_mem, void **nxt)
45 uint32_t cnt, stat, timer, risc_address, ext_mem_cnt;
47 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
50 risc_address = ext_mem_cnt = 0;
51 memset(mb, 0, sizeof(mb));
54 risc_address = 0x20000;
55 WRT_REG_WORD(®->mailbox0, MBC_READ_RAM_EXTENDED);
56 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
58 for (cnt = 0; cnt < cram_size / 4 && rval == QLA_SUCCESS;
59 cnt++, risc_address++) {
60 WRT_REG_WORD(®->mailbox1, LSW(risc_address));
61 WRT_REG_WORD(®->mailbox8, MSW(risc_address));
62 RD_REG_WORD(®->mailbox8);
63 WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT);
65 for (timer = 6000000; timer; timer--) {
66 /* Check for pending interrupts. */
67 stat = RD_REG_DWORD(®->host_status);
68 if (stat & HSRX_RISC_INT) {
71 if (stat == 0x1 || stat == 0x2 ||
72 stat == 0x10 || stat == 0x11) {
73 set_bit(MBX_INTERRUPT,
76 mb[0] = RD_REG_WORD(®->mailbox0);
77 mb[2] = RD_REG_WORD(®->mailbox2);
78 mb[3] = RD_REG_WORD(®->mailbox3);
80 WRT_REG_DWORD(®->hccr,
82 RD_REG_DWORD(®->hccr);
86 /* Clear this intr; it wasn't a mailbox intr */
87 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT);
88 RD_REG_DWORD(®->hccr);
93 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
94 rval = mb[0] & MBS_MASK;
95 code_ram[cnt] = htonl((mb[3] << 16) | mb[2]);
97 rval = QLA_FUNCTION_FAILED;
101 if (rval == QLA_SUCCESS) {
102 /* External Memory. */
103 risc_address = 0x100000;
104 ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1;
105 WRT_REG_WORD(®->mailbox0, MBC_READ_RAM_EXTENDED);
106 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
108 for (cnt = 0; cnt < ext_mem_cnt && rval == QLA_SUCCESS;
109 cnt++, risc_address++) {
110 WRT_REG_WORD(®->mailbox1, LSW(risc_address));
111 WRT_REG_WORD(®->mailbox8, MSW(risc_address));
112 RD_REG_WORD(®->mailbox8);
113 WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT);
115 for (timer = 6000000; timer; timer--) {
116 /* Check for pending interrupts. */
117 stat = RD_REG_DWORD(®->host_status);
118 if (stat & HSRX_RISC_INT) {
121 if (stat == 0x1 || stat == 0x2 ||
122 stat == 0x10 || stat == 0x11) {
123 set_bit(MBX_INTERRUPT,
126 mb[0] = RD_REG_WORD(®->mailbox0);
127 mb[2] = RD_REG_WORD(®->mailbox2);
128 mb[3] = RD_REG_WORD(®->mailbox3);
130 WRT_REG_DWORD(®->hccr,
132 RD_REG_DWORD(®->hccr);
136 /* Clear this intr; it wasn't a mailbox intr */
137 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT);
138 RD_REG_DWORD(®->hccr);
143 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
144 rval = mb[0] & MBS_MASK;
145 ext_mem[cnt] = htonl((mb[3] << 16) | mb[2]);
147 rval = QLA_FUNCTION_FAILED;
151 *nxt = rval == QLA_SUCCESS ? &ext_mem[cnt]: NULL;
156 qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
157 uint32_t count, uint32_t *buf)
159 uint32_t __iomem *dmp_reg;
161 WRT_REG_DWORD(®->iobase_addr, iobase);
162 dmp_reg = ®->iobase_window;
164 *buf++ = htonl(RD_REG_DWORD(dmp_reg++));
170 qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
172 int rval = QLA_SUCCESS;
175 if (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE)
178 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE);
179 for (cnt = 30000; (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0 &&
180 rval == QLA_SUCCESS; cnt--) {
184 rval = QLA_FUNCTION_TIMEOUT;
191 qla24xx_soft_reset(scsi_qla_host_t *ha)
193 int rval = QLA_SUCCESS;
196 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
199 WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
200 for (cnt = 0; cnt < 30000; cnt++) {
201 if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
207 WRT_REG_DWORD(®->ctrl_status,
208 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
209 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
212 /* Wait for firmware to complete NVRAM accesses. */
213 mb0 = (uint32_t) RD_REG_WORD(®->mailbox0);
214 for (cnt = 10000 ; cnt && mb0; cnt--) {
216 mb0 = (uint32_t) RD_REG_WORD(®->mailbox0);
220 /* Wait for soft-reset to complete. */
221 for (cnt = 0; cnt < 30000; cnt++) {
222 if ((RD_REG_DWORD(®->ctrl_status) &
223 CSRX_ISP_SOFT_RESET) == 0)
228 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET);
229 RD_REG_DWORD(®->hccr); /* PCI Posting. */
231 for (cnt = 30000; RD_REG_WORD(®->mailbox0) != 0 &&
232 rval == QLA_SUCCESS; cnt--) {
236 rval = QLA_FUNCTION_TIMEOUT;
243 qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
246 uint16_t __iomem *dmp_reg = ®->u.isp2300.fb_cmd;
249 *buf++ = htons(RD_REG_WORD(dmp_reg++));
253 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
255 * @hardware_locked: Called with the hardware_lock
258 qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
262 uint32_t risc_address;
266 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
267 uint16_t __iomem *dmp_reg;
269 struct qla2300_fw_dump *fw;
270 uint32_t data_ram_cnt;
272 risc_address = data_ram_cnt = 0;
276 if (!hardware_locked)
277 spin_lock_irqsave(&ha->hardware_lock, flags);
280 qla_printk(KERN_WARNING, ha,
281 "No buffer available for dump!!!\n");
282 goto qla2300_fw_dump_failed;
286 qla_printk(KERN_WARNING, ha,
287 "Firmware has been previously dumped (%p) -- ignoring "
288 "request...\n", ha->fw_dump);
289 goto qla2300_fw_dump_failed;
291 fw = &ha->fw_dump->isp.isp23;
292 qla2xxx_prep_dump(ha, ha->fw_dump);
295 fw->hccr = htons(RD_REG_WORD(®->hccr));
298 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
299 if (IS_QLA2300(ha)) {
301 (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 &&
302 rval == QLA_SUCCESS; cnt--) {
306 rval = QLA_FUNCTION_TIMEOUT;
309 RD_REG_WORD(®->hccr); /* PCI Posting. */
313 if (rval == QLA_SUCCESS) {
314 dmp_reg = ®->flash_address;
315 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
316 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
318 dmp_reg = ®->u.isp2300.req_q_in;
319 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
320 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
322 dmp_reg = ®->u.isp2300.mailbox0;
323 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
324 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
326 WRT_REG_WORD(®->ctrl_status, 0x40);
327 qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
329 WRT_REG_WORD(®->ctrl_status, 0x50);
330 qla2xxx_read_window(reg, 48, fw->dma_reg);
332 WRT_REG_WORD(®->ctrl_status, 0x00);
333 dmp_reg = ®->risc_hw;
334 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
335 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
337 WRT_REG_WORD(®->pcr, 0x2000);
338 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
340 WRT_REG_WORD(®->pcr, 0x2200);
341 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
343 WRT_REG_WORD(®->pcr, 0x2400);
344 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
346 WRT_REG_WORD(®->pcr, 0x2600);
347 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
349 WRT_REG_WORD(®->pcr, 0x2800);
350 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
352 WRT_REG_WORD(®->pcr, 0x2A00);
353 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
355 WRT_REG_WORD(®->pcr, 0x2C00);
356 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
358 WRT_REG_WORD(®->pcr, 0x2E00);
359 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
361 WRT_REG_WORD(®->ctrl_status, 0x10);
362 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
364 WRT_REG_WORD(®->ctrl_status, 0x20);
365 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
367 WRT_REG_WORD(®->ctrl_status, 0x30);
368 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
371 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET);
372 for (cnt = 0; cnt < 30000; cnt++) {
373 if ((RD_REG_WORD(®->ctrl_status) &
374 CSR_ISP_SOFT_RESET) == 0)
381 if (!IS_QLA2300(ha)) {
382 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
383 rval == QLA_SUCCESS; cnt--) {
387 rval = QLA_FUNCTION_TIMEOUT;
391 if (rval == QLA_SUCCESS) {
393 risc_address = 0x800;
394 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
395 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
397 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
398 cnt++, risc_address++) {
399 WRT_MAILBOX_REG(ha, reg, 1, (uint16_t)risc_address);
400 WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT);
402 for (timer = 6000000; timer; timer--) {
403 /* Check for pending interrupts. */
404 stat = RD_REG_DWORD(®->u.isp2300.host_status);
405 if (stat & HSR_RISC_INT) {
408 if (stat == 0x1 || stat == 0x2) {
409 set_bit(MBX_INTERRUPT,
412 mb0 = RD_MAILBOX_REG(ha, reg, 0);
413 mb2 = RD_MAILBOX_REG(ha, reg, 2);
415 /* Release mailbox registers. */
416 WRT_REG_WORD(®->semaphore, 0);
417 WRT_REG_WORD(®->hccr,
419 RD_REG_WORD(®->hccr);
421 } else if (stat == 0x10 || stat == 0x11) {
422 set_bit(MBX_INTERRUPT,
425 mb0 = RD_MAILBOX_REG(ha, reg, 0);
426 mb2 = RD_MAILBOX_REG(ha, reg, 2);
428 WRT_REG_WORD(®->hccr,
430 RD_REG_WORD(®->hccr);
434 /* clear this intr; it wasn't a mailbox intr */
435 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
436 RD_REG_WORD(®->hccr);
441 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
442 rval = mb0 & MBS_MASK;
443 fw->risc_ram[cnt] = htons(mb2);
445 rval = QLA_FUNCTION_FAILED;
449 if (rval == QLA_SUCCESS) {
450 /* Get stack SRAM. */
451 risc_address = 0x10000;
452 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_EXTENDED);
453 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
455 for (cnt = 0; cnt < sizeof(fw->stack_ram) / 2 && rval == QLA_SUCCESS;
456 cnt++, risc_address++) {
457 WRT_MAILBOX_REG(ha, reg, 1, LSW(risc_address));
458 WRT_MAILBOX_REG(ha, reg, 8, MSW(risc_address));
459 WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT);
461 for (timer = 6000000; timer; timer--) {
462 /* Check for pending interrupts. */
463 stat = RD_REG_DWORD(®->u.isp2300.host_status);
464 if (stat & HSR_RISC_INT) {
467 if (stat == 0x1 || stat == 0x2) {
468 set_bit(MBX_INTERRUPT,
471 mb0 = RD_MAILBOX_REG(ha, reg, 0);
472 mb2 = RD_MAILBOX_REG(ha, reg, 2);
474 /* Release mailbox registers. */
475 WRT_REG_WORD(®->semaphore, 0);
476 WRT_REG_WORD(®->hccr,
478 RD_REG_WORD(®->hccr);
480 } else if (stat == 0x10 || stat == 0x11) {
481 set_bit(MBX_INTERRUPT,
484 mb0 = RD_MAILBOX_REG(ha, reg, 0);
485 mb2 = RD_MAILBOX_REG(ha, reg, 2);
487 WRT_REG_WORD(®->hccr,
489 RD_REG_WORD(®->hccr);
493 /* clear this intr; it wasn't a mailbox intr */
494 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
495 RD_REG_WORD(®->hccr);
500 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
501 rval = mb0 & MBS_MASK;
502 fw->stack_ram[cnt] = htons(mb2);
504 rval = QLA_FUNCTION_FAILED;
508 if (rval == QLA_SUCCESS) {
510 risc_address = 0x11000;
511 data_ram_cnt = ha->fw_memory_size - risc_address + 1;
512 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_EXTENDED);
513 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
515 for (cnt = 0; cnt < data_ram_cnt && rval == QLA_SUCCESS;
516 cnt++, risc_address++) {
517 WRT_MAILBOX_REG(ha, reg, 1, LSW(risc_address));
518 WRT_MAILBOX_REG(ha, reg, 8, MSW(risc_address));
519 WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT);
521 for (timer = 6000000; timer; timer--) {
522 /* Check for pending interrupts. */
523 stat = RD_REG_DWORD(®->u.isp2300.host_status);
524 if (stat & HSR_RISC_INT) {
527 if (stat == 0x1 || stat == 0x2) {
528 set_bit(MBX_INTERRUPT,
531 mb0 = RD_MAILBOX_REG(ha, reg, 0);
532 mb2 = RD_MAILBOX_REG(ha, reg, 2);
534 /* Release mailbox registers. */
535 WRT_REG_WORD(®->semaphore, 0);
536 WRT_REG_WORD(®->hccr,
538 RD_REG_WORD(®->hccr);
540 } else if (stat == 0x10 || stat == 0x11) {
541 set_bit(MBX_INTERRUPT,
544 mb0 = RD_MAILBOX_REG(ha, reg, 0);
545 mb2 = RD_MAILBOX_REG(ha, reg, 2);
547 WRT_REG_WORD(®->hccr,
549 RD_REG_WORD(®->hccr);
553 /* clear this intr; it wasn't a mailbox intr */
554 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
555 RD_REG_WORD(®->hccr);
560 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
561 rval = mb0 & MBS_MASK;
562 fw->data_ram[cnt] = htons(mb2);
564 rval = QLA_FUNCTION_FAILED;
568 if (rval == QLA_SUCCESS)
569 qla2xxx_copy_queues(ha, &fw->data_ram[cnt]);
571 if (rval != QLA_SUCCESS) {
572 qla_printk(KERN_WARNING, ha,
573 "Failed to dump firmware (%x)!!!\n", rval);
577 qla_printk(KERN_INFO, ha,
578 "Firmware dump saved to temp buffer (%ld/%p).\n",
579 ha->host_no, ha->fw_dump);
583 qla2300_fw_dump_failed:
584 if (!hardware_locked)
585 spin_unlock_irqrestore(&ha->hardware_lock, flags);
589 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
591 * @hardware_locked: Called with the hardware_lock
594 qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
598 uint16_t risc_address;
600 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
601 uint16_t __iomem *dmp_reg;
603 struct qla2100_fw_dump *fw;
609 if (!hardware_locked)
610 spin_lock_irqsave(&ha->hardware_lock, flags);
613 qla_printk(KERN_WARNING, ha,
614 "No buffer available for dump!!!\n");
615 goto qla2100_fw_dump_failed;
619 qla_printk(KERN_WARNING, ha,
620 "Firmware has been previously dumped (%p) -- ignoring "
621 "request...\n", ha->fw_dump);
622 goto qla2100_fw_dump_failed;
624 fw = &ha->fw_dump->isp.isp21;
625 qla2xxx_prep_dump(ha, ha->fw_dump);
628 fw->hccr = htons(RD_REG_WORD(®->hccr));
631 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
632 for (cnt = 30000; (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 &&
633 rval == QLA_SUCCESS; cnt--) {
637 rval = QLA_FUNCTION_TIMEOUT;
639 if (rval == QLA_SUCCESS) {
640 dmp_reg = ®->flash_address;
641 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
642 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
644 dmp_reg = ®->u.isp2100.mailbox0;
645 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
647 dmp_reg = ®->u_end.isp2200.mailbox8;
649 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
652 dmp_reg = ®->u.isp2100.unused_2[0];
653 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
654 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
656 WRT_REG_WORD(®->ctrl_status, 0x00);
657 dmp_reg = ®->risc_hw;
658 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
659 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
661 WRT_REG_WORD(®->pcr, 0x2000);
662 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
664 WRT_REG_WORD(®->pcr, 0x2100);
665 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
667 WRT_REG_WORD(®->pcr, 0x2200);
668 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
670 WRT_REG_WORD(®->pcr, 0x2300);
671 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
673 WRT_REG_WORD(®->pcr, 0x2400);
674 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
676 WRT_REG_WORD(®->pcr, 0x2500);
677 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
679 WRT_REG_WORD(®->pcr, 0x2600);
680 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
682 WRT_REG_WORD(®->pcr, 0x2700);
683 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
685 WRT_REG_WORD(®->ctrl_status, 0x10);
686 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
688 WRT_REG_WORD(®->ctrl_status, 0x20);
689 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
691 WRT_REG_WORD(®->ctrl_status, 0x30);
692 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
695 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET);
698 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
699 rval == QLA_SUCCESS; cnt--) {
703 rval = QLA_FUNCTION_TIMEOUT;
707 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
708 (RD_REG_WORD(®->mctr) & (BIT_1 | BIT_0)) != 0))) {
710 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
712 (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 &&
713 rval == QLA_SUCCESS; cnt--) {
717 rval = QLA_FUNCTION_TIMEOUT;
719 if (rval == QLA_SUCCESS) {
720 /* Set memory configuration and timing. */
722 WRT_REG_WORD(®->mctr, 0xf1);
724 WRT_REG_WORD(®->mctr, 0xf2);
725 RD_REG_WORD(®->mctr); /* PCI Posting. */
728 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC);
732 if (rval == QLA_SUCCESS) {
734 risc_address = 0x1000;
735 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
736 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
738 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
739 cnt++, risc_address++) {
740 WRT_MAILBOX_REG(ha, reg, 1, risc_address);
741 WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT);
743 for (timer = 6000000; timer != 0; timer--) {
744 /* Check for pending interrupts. */
745 if (RD_REG_WORD(®->istatus) & ISR_RISC_INT) {
746 if (RD_REG_WORD(®->semaphore) & BIT_0) {
747 set_bit(MBX_INTERRUPT,
750 mb0 = RD_MAILBOX_REG(ha, reg, 0);
751 mb2 = RD_MAILBOX_REG(ha, reg, 2);
753 WRT_REG_WORD(®->semaphore, 0);
754 WRT_REG_WORD(®->hccr,
756 RD_REG_WORD(®->hccr);
759 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
760 RD_REG_WORD(®->hccr);
765 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
766 rval = mb0 & MBS_MASK;
767 fw->risc_ram[cnt] = htons(mb2);
769 rval = QLA_FUNCTION_FAILED;
773 if (rval == QLA_SUCCESS)
774 qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
776 if (rval != QLA_SUCCESS) {
777 qla_printk(KERN_WARNING, ha,
778 "Failed to dump firmware (%x)!!!\n", rval);
782 qla_printk(KERN_INFO, ha,
783 "Firmware dump saved to temp buffer (%ld/%p).\n",
784 ha->host_no, ha->fw_dump);
788 qla2100_fw_dump_failed:
789 if (!hardware_locked)
790 spin_unlock_irqrestore(&ha->hardware_lock, flags);
794 qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
798 uint32_t risc_address;
800 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
801 uint32_t __iomem *dmp_reg;
803 uint16_t __iomem *mbx_reg;
805 struct qla24xx_fw_dump *fw;
806 uint32_t ext_mem_cnt;
809 risc_address = ext_mem_cnt = 0;
812 if (!hardware_locked)
813 spin_lock_irqsave(&ha->hardware_lock, flags);
816 qla_printk(KERN_WARNING, ha,
817 "No buffer available for dump!!!\n");
818 goto qla24xx_fw_dump_failed;
822 qla_printk(KERN_WARNING, ha,
823 "Firmware has been previously dumped (%p) -- ignoring "
824 "request...\n", ha->fw_dump);
825 goto qla24xx_fw_dump_failed;
827 fw = &ha->fw_dump->isp.isp24;
828 qla2xxx_prep_dump(ha, ha->fw_dump);
830 fw->host_status = htonl(RD_REG_DWORD(®->host_status));
833 rval = qla24xx_pause_risc(reg);
834 if (rval != QLA_SUCCESS)
835 goto qla24xx_fw_dump_failed_0;
837 /* Host interface registers. */
838 dmp_reg = ®->flash_addr;
839 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
840 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
842 /* Disable interrupts. */
843 WRT_REG_DWORD(®->ictrl, 0);
844 RD_REG_DWORD(®->ictrl);
846 /* Shadow registers. */
847 WRT_REG_DWORD(®->iobase_addr, 0x0F70);
848 RD_REG_DWORD(®->iobase_addr);
849 WRT_REG_DWORD(®->iobase_select, 0xB0000000);
850 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata));
852 WRT_REG_DWORD(®->iobase_select, 0xB0100000);
853 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata));
855 WRT_REG_DWORD(®->iobase_select, 0xB0200000);
856 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata));
858 WRT_REG_DWORD(®->iobase_select, 0xB0300000);
859 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata));
861 WRT_REG_DWORD(®->iobase_select, 0xB0400000);
862 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata));
864 WRT_REG_DWORD(®->iobase_select, 0xB0500000);
865 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata));
867 WRT_REG_DWORD(®->iobase_select, 0xB0600000);
868 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata));
870 /* Mailbox registers. */
871 mbx_reg = ®->mailbox0;
872 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
873 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
875 /* Transfer sequence registers. */
876 iter_reg = fw->xseq_gp_reg;
877 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
878 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
879 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
880 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
881 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
882 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
883 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
884 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
886 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
887 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
889 /* Receive sequence registers. */
890 iter_reg = fw->rseq_gp_reg;
891 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
892 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
893 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
894 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
895 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
896 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
897 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
898 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
900 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
901 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
902 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
904 /* Command DMA registers. */
905 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
908 iter_reg = fw->req0_dma_reg;
909 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
910 dmp_reg = ®->iobase_q;
911 for (cnt = 0; cnt < 7; cnt++)
912 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
914 iter_reg = fw->resp0_dma_reg;
915 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
916 dmp_reg = ®->iobase_q;
917 for (cnt = 0; cnt < 7; cnt++)
918 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
920 iter_reg = fw->req1_dma_reg;
921 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
922 dmp_reg = ®->iobase_q;
923 for (cnt = 0; cnt < 7; cnt++)
924 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
926 /* Transmit DMA registers. */
927 iter_reg = fw->xmt0_dma_reg;
928 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
929 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
931 iter_reg = fw->xmt1_dma_reg;
932 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
933 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
935 iter_reg = fw->xmt2_dma_reg;
936 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
937 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
939 iter_reg = fw->xmt3_dma_reg;
940 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
941 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
943 iter_reg = fw->xmt4_dma_reg;
944 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
945 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
947 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
949 /* Receive DMA registers. */
950 iter_reg = fw->rcvt0_data_dma_reg;
951 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
952 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
954 iter_reg = fw->rcvt1_data_dma_reg;
955 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
956 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
958 /* RISC registers. */
959 iter_reg = fw->risc_gp_reg;
960 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
961 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
962 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
963 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
964 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
965 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
966 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
967 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
969 /* Local memory controller registers. */
970 iter_reg = fw->lmc_reg;
971 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
972 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
973 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
974 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
975 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
976 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
977 qla24xx_read_window(reg, 0x3060, 16, iter_reg);
979 /* Fibre Protocol Module registers. */
980 iter_reg = fw->fpm_hdw_reg;
981 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
982 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
983 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
984 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
985 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
986 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
987 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
988 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
989 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
990 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
991 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
992 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
994 /* Frame Buffer registers. */
995 iter_reg = fw->fb_hdw_reg;
996 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
997 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
998 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
999 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1000 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1001 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1002 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1003 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1004 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1005 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1006 qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1008 rval = qla24xx_soft_reset(ha);
1009 if (rval != QLA_SUCCESS)
1010 goto qla24xx_fw_dump_failed_0;
1012 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1014 if (rval != QLA_SUCCESS)
1015 goto qla24xx_fw_dump_failed_0;
1017 nxt = qla2xxx_copy_queues(ha, nxt);
1019 memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size));
1021 qla24xx_fw_dump_failed_0:
1022 if (rval != QLA_SUCCESS) {
1023 qla_printk(KERN_WARNING, ha,
1024 "Failed to dump firmware (%x)!!!\n", rval);
1028 qla_printk(KERN_INFO, ha,
1029 "Firmware dump saved to temp buffer (%ld/%p).\n",
1030 ha->host_no, ha->fw_dump);
1034 qla24xx_fw_dump_failed:
1035 if (!hardware_locked)
1036 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1040 qla25xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
1044 uint32_t risc_address;
1046 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1047 uint32_t __iomem *dmp_reg;
1049 uint16_t __iomem *mbx_reg;
1050 unsigned long flags;
1051 struct qla25xx_fw_dump *fw;
1052 uint32_t ext_mem_cnt;
1055 risc_address = ext_mem_cnt = 0;
1058 if (!hardware_locked)
1059 spin_lock_irqsave(&ha->hardware_lock, flags);
1062 qla_printk(KERN_WARNING, ha,
1063 "No buffer available for dump!!!\n");
1064 goto qla25xx_fw_dump_failed;
1067 if (ha->fw_dumped) {
1068 qla_printk(KERN_WARNING, ha,
1069 "Firmware has been previously dumped (%p) -- ignoring "
1070 "request...\n", ha->fw_dump);
1071 goto qla25xx_fw_dump_failed;
1073 fw = &ha->fw_dump->isp.isp25;
1074 qla2xxx_prep_dump(ha, ha->fw_dump);
1076 fw->host_status = htonl(RD_REG_DWORD(®->host_status));
1079 rval = qla24xx_pause_risc(reg);
1080 if (rval != QLA_SUCCESS)
1081 goto qla25xx_fw_dump_failed_0;
1083 /* Host interface registers. */
1084 dmp_reg = ®->flash_addr;
1085 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1086 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1088 /* Disable interrupts. */
1089 WRT_REG_DWORD(®->ictrl, 0);
1090 RD_REG_DWORD(®->ictrl);
1092 /* Shadow registers. */
1093 WRT_REG_DWORD(®->iobase_addr, 0x0F70);
1094 RD_REG_DWORD(®->iobase_addr);
1095 WRT_REG_DWORD(®->iobase_select, 0xB0000000);
1096 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata));
1098 WRT_REG_DWORD(®->iobase_select, 0xB0100000);
1099 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata));
1101 WRT_REG_DWORD(®->iobase_select, 0xB0200000);
1102 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata));
1104 WRT_REG_DWORD(®->iobase_select, 0xB0300000);
1105 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata));
1107 WRT_REG_DWORD(®->iobase_select, 0xB0400000);
1108 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata));
1110 WRT_REG_DWORD(®->iobase_select, 0xB0500000);
1111 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata));
1113 WRT_REG_DWORD(®->iobase_select, 0xB0600000);
1114 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata));
1116 WRT_REG_DWORD(®->iobase_select, 0xB0700000);
1117 fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata));
1119 WRT_REG_DWORD(®->iobase_select, 0xB0800000);
1120 fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata));
1122 WRT_REG_DWORD(®->iobase_select, 0xB0900000);
1123 fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata));
1125 WRT_REG_DWORD(®->iobase_select, 0xB0A00000);
1126 fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata));
1128 /* RISC I/O register. */
1129 WRT_REG_DWORD(®->iobase_addr, 0x0010);
1130 fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window));
1132 /* Mailbox registers. */
1133 mbx_reg = ®->mailbox0;
1134 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1135 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1137 /* Transfer sequence registers. */
1138 iter_reg = fw->xseq_gp_reg;
1139 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1140 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1141 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1142 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1143 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1144 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1145 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1146 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1148 iter_reg = fw->xseq_0_reg;
1149 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1150 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1151 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1153 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1155 /* Receive sequence registers. */
1156 iter_reg = fw->rseq_gp_reg;
1157 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1158 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1159 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1160 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1161 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1162 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1163 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1164 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1166 iter_reg = fw->rseq_0_reg;
1167 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1168 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1170 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1171 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1173 /* Auxiliary sequence registers. */
1174 iter_reg = fw->aseq_gp_reg;
1175 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1176 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1177 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1178 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1179 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1180 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1181 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1182 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1184 iter_reg = fw->aseq_0_reg;
1185 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1186 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1188 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1189 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1191 /* Command DMA registers. */
1192 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1195 iter_reg = fw->req0_dma_reg;
1196 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1197 dmp_reg = ®->iobase_q;
1198 for (cnt = 0; cnt < 7; cnt++)
1199 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1201 iter_reg = fw->resp0_dma_reg;
1202 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1203 dmp_reg = ®->iobase_q;
1204 for (cnt = 0; cnt < 7; cnt++)
1205 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1207 iter_reg = fw->req1_dma_reg;
1208 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1209 dmp_reg = ®->iobase_q;
1210 for (cnt = 0; cnt < 7; cnt++)
1211 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1213 /* Transmit DMA registers. */
1214 iter_reg = fw->xmt0_dma_reg;
1215 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1216 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1218 iter_reg = fw->xmt1_dma_reg;
1219 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1220 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1222 iter_reg = fw->xmt2_dma_reg;
1223 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1224 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1226 iter_reg = fw->xmt3_dma_reg;
1227 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1228 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1230 iter_reg = fw->xmt4_dma_reg;
1231 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1232 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1234 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1236 /* Receive DMA registers. */
1237 iter_reg = fw->rcvt0_data_dma_reg;
1238 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1239 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1241 iter_reg = fw->rcvt1_data_dma_reg;
1242 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1243 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1245 /* RISC registers. */
1246 iter_reg = fw->risc_gp_reg;
1247 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1248 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1249 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1250 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1251 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1252 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1253 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1254 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1256 /* Local memory controller registers. */
1257 iter_reg = fw->lmc_reg;
1258 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1259 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1260 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1261 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1262 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1263 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1264 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1265 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1267 /* Fibre Protocol Module registers. */
1268 iter_reg = fw->fpm_hdw_reg;
1269 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1270 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1271 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1272 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1273 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1274 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1275 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1276 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1277 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1278 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1279 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1280 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1282 /* Frame Buffer registers. */
1283 iter_reg = fw->fb_hdw_reg;
1284 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1285 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1286 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1287 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1288 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1289 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1290 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1291 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1292 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1293 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1294 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1295 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1297 rval = qla24xx_soft_reset(ha);
1298 if (rval != QLA_SUCCESS)
1299 goto qla25xx_fw_dump_failed_0;
1301 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1303 if (rval != QLA_SUCCESS)
1304 goto qla25xx_fw_dump_failed_0;
1306 nxt = qla2xxx_copy_queues(ha, nxt);
1308 memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size));
1310 qla25xx_fw_dump_failed_0:
1311 if (rval != QLA_SUCCESS) {
1312 qla_printk(KERN_WARNING, ha,
1313 "Failed to dump firmware (%x)!!!\n", rval);
1317 qla_printk(KERN_INFO, ha,
1318 "Firmware dump saved to temp buffer (%ld/%p).\n",
1319 ha->host_no, ha->fw_dump);
1323 qla25xx_fw_dump_failed:
1324 if (!hardware_locked)
1325 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1328 /****************************************************************************/
1329 /* Driver Debug Functions. */
1330 /****************************************************************************/
1333 qla2x00_dump_regs(scsi_qla_host_t *ha)
1336 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1337 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
1338 uint16_t __iomem *mbx_reg;
1340 mbx_reg = IS_FWI2_CAPABLE(ha) ? ®24->mailbox0:
1341 MAILBOX_REG(ha, reg, 0);
1343 printk("Mailbox registers:\n");
1344 for (i = 0; i < 6; i++)
1345 printk("scsi(%ld): mbox %d 0x%04x \n", ha->host_no, i,
1346 RD_REG_WORD(mbx_reg++));
1351 qla2x00_dump_buffer(uint8_t * b, uint32_t size)
1356 printk(" 0 1 2 3 4 5 6 7 8 9 "
1357 "Ah Bh Ch Dh Eh Fh\n");
1358 printk("----------------------------------------"
1359 "----------------------\n");
1361 for (cnt = 0; cnt < size;) {
1363 printk("%02x",(uint32_t) c);
1374 /**************************************************************************
1375 * qla2x00_print_scsi_cmd
1376 * Dumps out info about the scsi cmd and srb.
1378 * cmd : struct scsi_cmnd
1379 **************************************************************************/
1381 qla2x00_print_scsi_cmd(struct scsi_cmnd * cmd)
1384 struct scsi_qla_host *ha;
1387 ha = (struct scsi_qla_host *)cmd->device->host->hostdata;
1389 sp = (srb_t *) cmd->SCp.ptr;
1390 printk("SCSI Command @=0x%p, Handle=0x%p\n", cmd, cmd->host_scribble);
1391 printk(" chan=0x%02x, target=0x%02x, lun=0x%02x, cmd_len=0x%02x\n",
1392 cmd->device->channel, cmd->device->id, cmd->device->lun,
1395 for (i = 0; i < cmd->cmd_len; i++) {
1396 printk("0x%02x ", cmd->cmnd[i]);
1398 printk("\n seg_cnt=%d, allowed=%d, retries=%d\n",
1399 scsi_sg_count(cmd), cmd->allowed, cmd->retries);
1400 printk(" request buffer=0x%p, request buffer len=0x%x\n",
1401 scsi_sglist(cmd), scsi_bufflen(cmd));
1402 printk(" tag=%d, transfersize=0x%x\n",
1403 cmd->tag, cmd->transfersize);
1404 printk(" serial_number=%lx, SP=%p\n", cmd->serial_number, sp);
1405 printk(" data direction=%d\n", cmd->sc_data_direction);
1410 printk(" sp flags=0x%x\n", sp->flags);
1414 qla2x00_dump_pkt(void *pkt)
1417 uint8_t *data = (uint8_t *) pkt;
1419 for (i = 0; i < 64; i++) {
1421 printk("\n%02x: ", i);
1423 printk("%02x ", data[i]);
1428 #if defined(QL_DEBUG_ROUTINES)
1430 * qla2x00_formatted_dump_buffer
1431 * Prints string plus buffer.
1434 * string = Null terminated string (no newline at end).
1435 * buffer = buffer address.
1436 * wd_size = word size 8, 16, 32 or 64 bits
1437 * count = number of words.
1440 qla2x00_formatted_dump_buffer(char *string, uint8_t * buffer,
1441 uint8_t wd_size, uint32_t count)
1447 if (strcmp(string, "") != 0)
1448 printk("%s\n",string);
1452 printk(" 0 1 2 3 4 5 6 7 "
1453 "8 9 Ah Bh Ch Dh Eh Fh\n");
1454 printk("-----------------------------------------"
1455 "-------------------------------------\n");
1457 for (cnt = 1; cnt <= count; cnt++, buffer++) {
1458 printk("%02x",*buffer);
1468 printk(" 0 2 4 6 8 Ah "
1470 printk("-----------------------------------------"
1473 buf16 = (uint16_t *) buffer;
1474 for (cnt = 1; cnt <= count; cnt++, buf16++) {
1475 printk("%4x",*buf16);
1479 else if (*buf16 < 10)
1488 printk(" 0 4 8 Ch\n");
1489 printk("------------------------------------------\n");
1491 buf32 = (uint32_t *) buffer;
1492 for (cnt = 1; cnt <= count; cnt++, buf32++) {
1493 printk("%8x", *buf32);
1497 else if (*buf32 < 10)