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   1 /*
   2  * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    substantially similar to the "NO WARRANTY" disclaimer below
  15  *    ("Disclaimer") and any redistribution must be conditioned upon
  16  *    including a substantially similar Disclaimer requirement for further
  17  *    binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *    of any contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40  #include "pm8001_sas.h"
  41  #include "pm8001_hwi.h"
  42  #include "pm8001_chips.h"
  43  #include "pm8001_ctl.h"
  44
  45 /**
  46  * read_main_config_table - read the configure table and save it.
  47  * @pm8001_ha: our hba card information
  48  */
  49 static void __devinit read_main_config_table(struct pm8001_hba_info *pm8001_ha)
  50 {
  51         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
  52         pm8001_ha->main_cfg_tbl.signature       = pm8001_mr32(address, 0x00);
  53         pm8001_ha->main_cfg_tbl.interface_rev   = pm8001_mr32(address, 0x04);
  54         pm8001_ha->main_cfg_tbl.firmware_rev    = pm8001_mr32(address, 0x08);
  55         pm8001_ha->main_cfg_tbl.max_out_io      = pm8001_mr32(address, 0x0C);
  56         pm8001_ha->main_cfg_tbl.max_sgl         = pm8001_mr32(address, 0x10);
  57         pm8001_ha->main_cfg_tbl.ctrl_cap_flag   = pm8001_mr32(address, 0x14);
  58         pm8001_ha->main_cfg_tbl.gst_offset      = pm8001_mr32(address, 0x18);
  59         pm8001_ha->main_cfg_tbl.inbound_queue_offset =
  60                 pm8001_mr32(address, 0x1C);
  61         pm8001_ha->main_cfg_tbl.outbound_queue_offset =
  62                 pm8001_mr32(address, 0x20);
  63         pm8001_ha->main_cfg_tbl.hda_mode_flag   =
  64                 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
  65
  66         /* read analog Setting offset from the configuration table */
  67         pm8001_ha->main_cfg_tbl.anolog_setup_table_offset =
  68                 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
  69
  70         /* read Error Dump Offset and Length */
  71         pm8001_ha->main_cfg_tbl.fatal_err_dump_offset0 =
  72                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
  73         pm8001_ha->main_cfg_tbl.fatal_err_dump_length0 =
  74                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
  75         pm8001_ha->main_cfg_tbl.fatal_err_dump_offset1 =
  76                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
  77         pm8001_ha->main_cfg_tbl.fatal_err_dump_length1 =
  78                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
  79 }
  80
  81 /**
  82  * read_general_status_table - read the general status table and save it.
  83  * @pm8001_ha: our hba card information
  84  */
  85 static void __devinit
  86 read_general_status_table(struct pm8001_hba_info *pm8001_ha)
  87 {
  88         void __iomem *address = pm8001_ha->general_stat_tbl_addr;
  89         pm8001_ha->gs_tbl.gst_len_mpistate      = pm8001_mr32(address, 0x00);
  90         pm8001_ha->gs_tbl.iq_freeze_state0      = pm8001_mr32(address, 0x04);
  91         pm8001_ha->gs_tbl.iq_freeze_state1      = pm8001_mr32(address, 0x08);
  92         pm8001_ha->gs_tbl.msgu_tcnt             = pm8001_mr32(address, 0x0C);
  93         pm8001_ha->gs_tbl.iop_tcnt              = pm8001_mr32(address, 0x10);
  94         pm8001_ha->gs_tbl.reserved              = pm8001_mr32(address, 0x14);
  95         pm8001_ha->gs_tbl.phy_state[0]  = pm8001_mr32(address, 0x18);
  96         pm8001_ha->gs_tbl.phy_state[1]  = pm8001_mr32(address, 0x1C);
  97         pm8001_ha->gs_tbl.phy_state[2]  = pm8001_mr32(address, 0x20);
  98         pm8001_ha->gs_tbl.phy_state[3]  = pm8001_mr32(address, 0x24);
  99         pm8001_ha->gs_tbl.phy_state[4]  = pm8001_mr32(address, 0x28);
 100         pm8001_ha->gs_tbl.phy_state[5]  = pm8001_mr32(address, 0x2C);
 101         pm8001_ha->gs_tbl.phy_state[6]  = pm8001_mr32(address, 0x30);
 102         pm8001_ha->gs_tbl.phy_state[7]  = pm8001_mr32(address, 0x34);
 103         pm8001_ha->gs_tbl.reserved1             = pm8001_mr32(address, 0x38);
 104         pm8001_ha->gs_tbl.reserved2             = pm8001_mr32(address, 0x3C);
 105         pm8001_ha->gs_tbl.reserved3             = pm8001_mr32(address, 0x40);
 106         pm8001_ha->gs_tbl.recover_err_info[0]   = pm8001_mr32(address, 0x44);
 107         pm8001_ha->gs_tbl.recover_err_info[1]   = pm8001_mr32(address, 0x48);
 108         pm8001_ha->gs_tbl.recover_err_info[2]   = pm8001_mr32(address, 0x4C);
 109         pm8001_ha->gs_tbl.recover_err_info[3]   = pm8001_mr32(address, 0x50);
 110         pm8001_ha->gs_tbl.recover_err_info[4]   = pm8001_mr32(address, 0x54);
 111         pm8001_ha->gs_tbl.recover_err_info[5]   = pm8001_mr32(address, 0x58);
 112         pm8001_ha->gs_tbl.recover_err_info[6]   = pm8001_mr32(address, 0x5C);
 113         pm8001_ha->gs_tbl.recover_err_info[7]   = pm8001_mr32(address, 0x60);
 114 }
 115
 116 /**
 117  * read_inbnd_queue_table - read the inbound queue table and save it.
 118  * @pm8001_ha: our hba card information
 119  */
 120 static void __devinit
 121 read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 122 {
 123         int inbQ_num = 1;
 124         int i;
 125         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 126         for (i = 0; i < inbQ_num; i++) {
 127                 u32 offset = i * 0x24;
 128                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
 129                       get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
 130                 pm8001_ha->inbnd_q_tbl[i].pi_offset =
 131                         pm8001_mr32(address, (offset + 0x18));
 132         }
 133 }
 134
 135 /**
 136  * read_outbnd_queue_table - read the outbound queue table and save it.
 137  * @pm8001_ha: our hba card information
 138  */
 139 static void __devinit
 140 read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 141 {
 142         int outbQ_num = 1;
 143         int i;
 144         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 145         for (i = 0; i < outbQ_num; i++) {
 146                 u32 offset = i * 0x24;
 147                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
 148                       get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
 149                 pm8001_ha->outbnd_q_tbl[i].ci_offset =
 150                         pm8001_mr32(address, (offset + 0x18));
 151         }
 152 }
 153
 154 /**
 155  * init_default_table_values - init the default table.
 156  * @pm8001_ha: our hba card information
 157  */
 158 static void __devinit
 159 init_default_table_values(struct pm8001_hba_info *pm8001_ha)
 160 {
 161         int qn = 1;
 162         int i;
 163         u32 offsetib, offsetob;
 164         void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
 165         void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
 166
 167         pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd                     = 0;
 168         pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3                = 0;
 169         pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7                = 0;
 170         pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3               = 0;
 171         pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7               = 0;
 172         pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3       = 0;
 173         pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7       = 0;
 174         pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3   = 0;
 175         pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7   = 0;
 176         pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3   = 0;
 177         pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7   = 0;
 178
 179         pm8001_ha->main_cfg_tbl.upper_event_log_addr            =
 180                 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
 181         pm8001_ha->main_cfg_tbl.lower_event_log_addr            =
 182                 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
 183         pm8001_ha->main_cfg_tbl.event_log_size  = PM8001_EVENT_LOG_SIZE;
 184         pm8001_ha->main_cfg_tbl.event_log_option                = 0x01;
 185         pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr        =
 186                 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
 187         pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr        =
 188                 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
 189         pm8001_ha->main_cfg_tbl.iop_event_log_size      = PM8001_EVENT_LOG_SIZE;
 190         pm8001_ha->main_cfg_tbl.iop_event_log_option            = 0x01;
 191         pm8001_ha->main_cfg_tbl.fatal_err_interrupt             = 0x01;
 192         for (i = 0; i < qn; i++) {
 193                 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt  =
 194                         0x00000100 | (0x00000040 << 16) | (0x00<<30);
 195                 pm8001_ha->inbnd_q_tbl[i].upper_base_addr       =
 196                         pm8001_ha->memoryMap.region[IB].phys_addr_hi;
 197                 pm8001_ha->inbnd_q_tbl[i].lower_base_addr       =
 198                 pm8001_ha->memoryMap.region[IB].phys_addr_lo;
 199                 pm8001_ha->inbnd_q_tbl[i].base_virt             =
 200                         (u8 *)pm8001_ha->memoryMap.region[IB].virt_ptr;
 201                 pm8001_ha->inbnd_q_tbl[i].total_length          =
 202                         pm8001_ha->memoryMap.region[IB].total_len;
 203                 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr    =
 204                         pm8001_ha->memoryMap.region[CI].phys_addr_hi;
 205                 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr    =
 206                         pm8001_ha->memoryMap.region[CI].phys_addr_lo;
 207                 pm8001_ha->inbnd_q_tbl[i].ci_virt               =
 208                         pm8001_ha->memoryMap.region[CI].virt_ptr;
 209                 offsetib = i * 0x20;
 210                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar            =
 211                         get_pci_bar_index(pm8001_mr32(addressib,
 212                                 (offsetib + 0x14)));
 213                 pm8001_ha->inbnd_q_tbl[i].pi_offset             =
 214                         pm8001_mr32(addressib, (offsetib + 0x18));
 215                 pm8001_ha->inbnd_q_tbl[i].producer_idx          = 0;
 216                 pm8001_ha->inbnd_q_tbl[i].consumer_index        = 0;
 217         }
 218         for (i = 0; i < qn; i++) {
 219                 pm8001_ha->outbnd_q_tbl[i].element_size_cnt     =
 220                         256 | (64 << 16) | (1<<30);
 221                 pm8001_ha->outbnd_q_tbl[i].upper_base_addr      =
 222                         pm8001_ha->memoryMap.region[OB].phys_addr_hi;
 223                 pm8001_ha->outbnd_q_tbl[i].lower_base_addr      =
 224                         pm8001_ha->memoryMap.region[OB].phys_addr_lo;
 225                 pm8001_ha->outbnd_q_tbl[i].base_virt            =
 226                         (u8 *)pm8001_ha->memoryMap.region[OB].virt_ptr;
 227                 pm8001_ha->outbnd_q_tbl[i].total_length         =
 228                         pm8001_ha->memoryMap.region[OB].total_len;
 229                 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr   =
 230                         pm8001_ha->memoryMap.region[PI].phys_addr_hi;
 231                 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr   =
 232                         pm8001_ha->memoryMap.region[PI].phys_addr_lo;
 233                 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay       =
 234                         0 | (0 << 16) | (0 << 24);
 235                 pm8001_ha->outbnd_q_tbl[i].pi_virt              =
 236                         pm8001_ha->memoryMap.region[PI].virt_ptr;
 237                 offsetob = i * 0x24;
 238                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar           =
 239                         get_pci_bar_index(pm8001_mr32(addressob,
 240                         offsetob + 0x14));
 241                 pm8001_ha->outbnd_q_tbl[i].ci_offset            =
 242                         pm8001_mr32(addressob, (offsetob + 0x18));
 243                 pm8001_ha->outbnd_q_tbl[i].consumer_idx         = 0;
 244                 pm8001_ha->outbnd_q_tbl[i].producer_index       = 0;
 245         }
 246 }
 247
 248 /**
 249  * update_main_config_table - update the main default table to the HBA.
 250  * @pm8001_ha: our hba card information
 251  */
 252 static void __devinit
 253 update_main_config_table(struct pm8001_hba_info *pm8001_ha)
 254 {
 255         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 256         pm8001_mw32(address, 0x24,
 257                 pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd);
 258         pm8001_mw32(address, 0x28,
 259                 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3);
 260         pm8001_mw32(address, 0x2C,
 261                 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7);
 262         pm8001_mw32(address, 0x30,
 263                 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3);
 264         pm8001_mw32(address, 0x34,
 265                 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7);
 266         pm8001_mw32(address, 0x38,
 267                 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3);
 268         pm8001_mw32(address, 0x3C,
 269                 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7);
 270         pm8001_mw32(address, 0x40,
 271                 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3);
 272         pm8001_mw32(address, 0x44,
 273                 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7);
 274         pm8001_mw32(address, 0x48,
 275                 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3);
 276         pm8001_mw32(address, 0x4C,
 277                 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7);
 278         pm8001_mw32(address, 0x50,
 279                 pm8001_ha->main_cfg_tbl.upper_event_log_addr);
 280         pm8001_mw32(address, 0x54,
 281                 pm8001_ha->main_cfg_tbl.lower_event_log_addr);
 282         pm8001_mw32(address, 0x58, pm8001_ha->main_cfg_tbl.event_log_size);
 283         pm8001_mw32(address, 0x5C, pm8001_ha->main_cfg_tbl.event_log_option);
 284         pm8001_mw32(address, 0x60,
 285                 pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr);
 286         pm8001_mw32(address, 0x64,
 287                 pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr);
 288         pm8001_mw32(address, 0x68, pm8001_ha->main_cfg_tbl.iop_event_log_size);
 289         pm8001_mw32(address, 0x6C,
 290                 pm8001_ha->main_cfg_tbl.iop_event_log_option);
 291         pm8001_mw32(address, 0x70,
 292                 pm8001_ha->main_cfg_tbl.fatal_err_interrupt);
 293 }
 294
 295 /**
 296  * update_inbnd_queue_table - update the inbound queue table to the HBA.
 297  * @pm8001_ha: our hba card information
 298  */
 299 static void __devinit
 300 update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number)
 301 {
 302         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 303         u16 offset = number * 0x20;
 304         pm8001_mw32(address, offset + 0x00,
 305                 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
 306         pm8001_mw32(address, offset + 0x04,
 307                 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
 308         pm8001_mw32(address, offset + 0x08,
 309                 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
 310         pm8001_mw32(address, offset + 0x0C,
 311                 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
 312         pm8001_mw32(address, offset + 0x10,
 313                 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
 314 }
 315
 316 /**
 317  * update_outbnd_queue_table - update the outbound queue table to the HBA.
 318  * @pm8001_ha: our hba card information
 319  */
 320 static void __devinit
 321 update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number)
 322 {
 323         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 324         u16 offset = number * 0x24;
 325         pm8001_mw32(address, offset + 0x00,
 326                 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
 327         pm8001_mw32(address, offset + 0x04,
 328                 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
 329         pm8001_mw32(address, offset + 0x08,
 330                 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
 331         pm8001_mw32(address, offset + 0x0C,
 332                 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
 333         pm8001_mw32(address, offset + 0x10,
 334                 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
 335         pm8001_mw32(address, offset + 0x1C,
 336                 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
 337 }
 338
 339 /**
 340  * bar4_shift - function is called to shift BAR base address
 341  * @pm8001_ha : our hba card infomation
 342  * @shiftValue : shifting value in memory bar.
 343  */
 344 static u32 bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
 345 {
 346         u32 regVal;
 347         u32 max_wait_count;
 348
 349         /* program the inbound AXI translation Lower Address */
 350         pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
 351
 352         /* confirm the setting is written */
 353         max_wait_count = 1 * 1000 * 1000;  /* 1 sec */
 354         do {
 355                 udelay(1);
 356                 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
 357         } while ((regVal != shiftValue) && (--max_wait_count));
 358
 359         if (!max_wait_count) {
 360                 PM8001_INIT_DBG(pm8001_ha,
 361                         pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW"
 362                         " = 0x%x\n", regVal));
 363                 return -1;
 364         }
 365         return 0;
 366 }
 367
 368 /**
 369  * mpi_set_phys_g3_with_ssc
 370  * @pm8001_ha: our hba card information
 371  * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
 372  */
 373 static void __devinit
 374 mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha, u32 SSCbit)
 375 {
 376         u32 offset;
 377         u32 value;
 378         u32 i;
 379
 380 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
 381 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
 382 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
 383 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
 384 #define PHY_SSC_BIT_SHIFT 13
 385
 386    /*
 387     * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
 388     * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
 389     */
 390         if (-1 == bar4_shift(pm8001_ha, SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR))
 391                 return;
 392         /* set SSC bit of PHY 0 - 3 */
 393         for (i = 0; i < 4; i++) {
 394                 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
 395                 value = pm8001_cr32(pm8001_ha, 2, offset);
 396                 if (SSCbit)
 397                         value = value | (0x00000001 << PHY_SSC_BIT_SHIFT);
 398                 else
 399                         value = value & (~(0x00000001<<PHY_SSC_BIT_SHIFT));
 400                 pm8001_cw32(pm8001_ha, 2, offset, value);
 401         }
 402
 403         /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
 404         if (-1 == bar4_shift(pm8001_ha, SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR))
 405                 return;
 406
 407         /* set SSC bit of PHY 4 - 7 */
 408         for (i = 4; i < 8; i++) {
 409                 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
 410                 value = pm8001_cr32(pm8001_ha, 2, offset);
 411                 if (SSCbit)
 412                         value = value | (0x00000001 << PHY_SSC_BIT_SHIFT);
 413                 else
 414                         value = value & (~(0x00000001<<PHY_SSC_BIT_SHIFT));
 415                 pm8001_cw32(pm8001_ha, 2, offset, value);
 416         }
 417
 418         /*set the shifted destination address to 0x0 to avoid error operation */
 419         bar4_shift(pm8001_ha, 0x0);
 420         return;
 421 }
 422
 423 /**
 424  * mpi_set_open_retry_interval_reg
 425  * @pm8001_ha: our hba card information
 426  * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us.
 427  */
 428 static void __devinit
 429 mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
 430                                 u32 interval)
 431 {
 432         u32 offset;
 433         u32 value;
 434         u32 i;
 435
 436 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
 437 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
 438 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
 439 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
 440 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
 441
 442         value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
 443         /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
 444         if (-1 == bar4_shift(pm8001_ha,
 445                              OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR))
 446                 return;
 447         for (i = 0; i < 4; i++) {
 448                 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
 449                 pm8001_cw32(pm8001_ha, 2, offset, value);
 450         }
 451
 452         if (-1 == bar4_shift(pm8001_ha,
 453                              OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR))
 454                 return;
 455         for (i = 4; i < 8; i++) {
 456                 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
 457                 pm8001_cw32(pm8001_ha, 2, offset, value);
 458         }
 459         /*set the shifted destination address to 0x0 to avoid error operation */
 460         bar4_shift(pm8001_ha, 0x0);
 461         return;
 462 }
 463
 464 /**
 465  * mpi_init_check - check firmware initialization status.
 466  * @pm8001_ha: our hba card information
 467  */
 468 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
 469 {
 470         u32 max_wait_count;
 471         u32 value;
 472         u32 gst_len_mpistate;
 473         /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
 474         table is updated */
 475         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
 476         /* wait until Inbound DoorBell Clear Register toggled */
 477         max_wait_count = 1 * 1000 * 1000;/* 1 sec */
 478         do {
 479                 udelay(1);
 480                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 481                 value &= SPC_MSGU_CFG_TABLE_UPDATE;
 482         } while ((value != 0) && (--max_wait_count));
 483
 484         if (!max_wait_count)
 485                 return -1;
 486         /* check the MPI-State for initialization */
 487         gst_len_mpistate =
 488                 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 489                 GST_GSTLEN_MPIS_OFFSET);
 490         if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
 491                 return -1;
 492         /* check MPI Initialization error */
 493         gst_len_mpistate = gst_len_mpistate >> 16;
 494         if (0x0000 != gst_len_mpistate)
 495                 return -1;
 496         return 0;
 497 }
 498
 499 /**
 500  * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
 501  * @pm8001_ha: our hba card information
 502  */
 503 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
 504 {
 505         u32 value, value1;
 506         u32 max_wait_count;
 507         /* check error state */
 508         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 509         value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
 510         /* check AAP error */
 511         if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
 512                 /* error state */
 513                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 514                 return -1;
 515         }
 516
 517         /* check IOP error */
 518         if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
 519                 /* error state */
 520                 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
 521                 return -1;
 522         }
 523
 524         /* bit 4-31 of scratch pad1 should be zeros if it is not
 525         in error state*/
 526         if (value & SCRATCH_PAD1_STATE_MASK) {
 527                 /* error case */
 528                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 529                 return -1;
 530         }
 531
 532         /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
 533         in error state */
 534         if (value1 & SCRATCH_PAD2_STATE_MASK) {
 535                 /* error case */
 536                 return -1;
 537         }
 538
 539         max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
 540
 541         /* wait until scratch pad 1 and 2 registers in ready state  */
 542         do {
 543                 udelay(1);
 544                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
 545                         & SCRATCH_PAD1_RDY;
 546                 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
 547                         & SCRATCH_PAD2_RDY;
 548                 if ((--max_wait_count) == 0)
 549                         return -1;
 550         } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
 551         return 0;
 552 }
 553
 554 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
 555 {
 556         void __iomem *base_addr;
 557         u32     value;
 558         u32     offset;
 559         u32     pcibar;
 560         u32     pcilogic;
 561
 562         value = pm8001_cr32(pm8001_ha, 0, 0x44);
 563         offset = value & 0x03FFFFFF;
 564         PM8001_INIT_DBG(pm8001_ha,
 565                 pm8001_printk("Scratchpad 0 Offset: %x \n", offset));
 566         pcilogic = (value & 0xFC000000) >> 26;
 567         pcibar = get_pci_bar_index(pcilogic);
 568         PM8001_INIT_DBG(pm8001_ha,
 569                 pm8001_printk("Scratchpad 0 PCI BAR: %d \n", pcibar));
 570         pm8001_ha->main_cfg_tbl_addr = base_addr =
 571                 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
 572         pm8001_ha->general_stat_tbl_addr =
 573                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
 574         pm8001_ha->inbnd_q_tbl_addr =
 575                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
 576         pm8001_ha->outbnd_q_tbl_addr =
 577                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
 578 }
 579
 580 /**
 581  * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
 582  * @pm8001_ha: our hba card information
 583  */
 584 static int __devinit pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
 585 {
 586         /* check the firmware status */
 587         if (-1 == check_fw_ready(pm8001_ha)) {
 588                 PM8001_FAIL_DBG(pm8001_ha,
 589                         pm8001_printk("Firmware is not ready!\n"));
 590                 return -EBUSY;
 591         }
 592
 593         /* Initialize pci space address eg: mpi offset */
 594         init_pci_device_addresses(pm8001_ha);
 595         init_default_table_values(pm8001_ha);
 596         read_main_config_table(pm8001_ha);
 597         read_general_status_table(pm8001_ha);
 598         read_inbnd_queue_table(pm8001_ha);
 599         read_outbnd_queue_table(pm8001_ha);
 600         /* update main config table ,inbound table and outbound table */
 601         update_main_config_table(pm8001_ha);
 602         update_inbnd_queue_table(pm8001_ha, 0);
 603         update_outbnd_queue_table(pm8001_ha, 0);
 604         mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
 605         mpi_set_open_retry_interval_reg(pm8001_ha, 7);
 606         /* notify firmware update finished and check initialization status */
 607         if (0 == mpi_init_check(pm8001_ha)) {
 608                 PM8001_INIT_DBG(pm8001_ha,
 609                         pm8001_printk("MPI initialize successful!\n"));
 610         } else
 611                 return -EBUSY;
 612         /*This register is a 16-bit timer with a resolution of 1us. This is the
 613         timer used for interrupt delay/coalescing in the PCIe Application Layer.
 614         Zero is not a valid value. A value of 1 in the register will cause the
 615         interrupts to be normal. A value greater than 1 will cause coalescing
 616         delays.*/
 617         pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
 618         pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
 619         return 0;
 620 }
 621
 622 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
 623 {
 624         u32 max_wait_count;
 625         u32 value;
 626         u32 gst_len_mpistate;
 627         init_pci_device_addresses(pm8001_ha);
 628         /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
 629         table is stop */
 630         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
 631
 632         /* wait until Inbound DoorBell Clear Register toggled */
 633         max_wait_count = 1 * 1000 * 1000;/* 1 sec */
 634         do {
 635                 udelay(1);
 636                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 637                 value &= SPC_MSGU_CFG_TABLE_RESET;
 638         } while ((value != 0) && (--max_wait_count));
 639
 640         if (!max_wait_count) {
 641                 PM8001_FAIL_DBG(pm8001_ha,
 642                         pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value));
 643                 return -1;
 644         }
 645
 646         /* check the MPI-State for termination in progress */
 647         /* wait until Inbound DoorBell Clear Register toggled */
 648         max_wait_count = 1 * 1000 * 1000;  /* 1 sec */
 649         do {
 650                 udelay(1);
 651                 gst_len_mpistate =
 652                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 653                         GST_GSTLEN_MPIS_OFFSET);
 654                 if (GST_MPI_STATE_UNINIT ==
 655                         (gst_len_mpistate & GST_MPI_STATE_MASK))
 656                         break;
 657         } while (--max_wait_count);
 658         if (!max_wait_count) {
 659                 PM8001_FAIL_DBG(pm8001_ha,
 660                         pm8001_printk(" TIME OUT MPI State = 0x%x\n",
 661                                 gst_len_mpistate & GST_MPI_STATE_MASK));
 662                 return -1;
 663         }
 664         return 0;
 665 }
 666
 667 /**
 668  * soft_reset_ready_check - Function to check FW is ready for soft reset.
 669  * @pm8001_ha: our hba card information
 670  */
 671 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
 672 {
 673         u32 regVal, regVal1, regVal2;
 674         if (mpi_uninit_check(pm8001_ha) != 0) {
 675                 PM8001_FAIL_DBG(pm8001_ha,
 676                         pm8001_printk("MPI state is not ready\n"));
 677                 return -1;
 678         }
 679         /* read the scratch pad 2 register bit 2 */
 680         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
 681                 & SCRATCH_PAD2_FWRDY_RST;
 682         if (regVal == SCRATCH_PAD2_FWRDY_RST) {
 683                 PM8001_INIT_DBG(pm8001_ha,
 684                         pm8001_printk("Firmware is ready for reset .\n"));
 685         } else {
 686         /* Trigger NMI twice via RB6 */
 687                 if (-1 == bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
 688                         PM8001_FAIL_DBG(pm8001_ha,
 689                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 690                                         RB6_ACCESS_REG));
 691                         return -1;
 692                 }
 693                 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
 694                         RB6_MAGIC_NUMBER_RST);
 695                 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
 696                 /* wait for 100 ms */
 697                 mdelay(100);
 698                 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
 699                         SCRATCH_PAD2_FWRDY_RST;
 700                 if (regVal != SCRATCH_PAD2_FWRDY_RST) {
 701                         regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 702                         regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
 703                         PM8001_FAIL_DBG(pm8001_ha,
 704                                 pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1"
 705                                 "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
 706                                 regVal1, regVal2));
 707                         PM8001_FAIL_DBG(pm8001_ha,
 708                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
 709                                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
 710                         PM8001_FAIL_DBG(pm8001_ha,
 711                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
 712                                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
 713                         return -1;
 714                 }
 715         }
 716         return 0;
 717 }
 718
 719 /**
 720  * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
 721  * the FW register status to the originated status.
 722  * @pm8001_ha: our hba card information
 723  * @signature: signature in host scratch pad0 register.
 724  */
 725 static int
 726 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature)
 727 {
 728         u32     regVal, toggleVal;
 729         u32     max_wait_count;
 730         u32     regVal1, regVal2, regVal3;
 731
 732         /* step1: Check FW is ready for soft reset */
 733         if (soft_reset_ready_check(pm8001_ha) != 0) {
 734                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n"));
 735                 return -1;
 736         }
 737
 738         /* step 2: clear NMI status register on AAP1 and IOP, write the same
 739         value to clear */
 740         /* map 0x60000 to BAR4(0x20), BAR2(win) */
 741         if (-1 == bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
 742                 PM8001_FAIL_DBG(pm8001_ha,
 743                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 744                         MBIC_AAP1_ADDR_BASE));
 745                 return -1;
 746         }
 747         regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
 748         PM8001_INIT_DBG(pm8001_ha,
 749                 pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal));
 750         pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
 751         /* map 0x70000 to BAR4(0x20), BAR2(win) */
 752         if (-1 == bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
 753                 PM8001_FAIL_DBG(pm8001_ha,
 754                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 755                         MBIC_IOP_ADDR_BASE));
 756                 return -1;
 757         }
 758         regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
 759         PM8001_INIT_DBG(pm8001_ha,
 760                 pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal));
 761         pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
 762
 763         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
 764         PM8001_INIT_DBG(pm8001_ha,
 765                 pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal));
 766         pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
 767
 768         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
 769         PM8001_INIT_DBG(pm8001_ha,
 770                 pm8001_printk("PCIE - Event Interrupt  = 0x%x\n", regVal));
 771         pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
 772
 773         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
 774         PM8001_INIT_DBG(pm8001_ha,
 775                 pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal));
 776         pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
 777
 778         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
 779         PM8001_INIT_DBG(pm8001_ha,
 780                 pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal));
 781         pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
 782
 783         /* read the scratch pad 1 register bit 2 */
 784         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
 785                 & SCRATCH_PAD1_RST;
 786         toggleVal = regVal ^ SCRATCH_PAD1_RST;
 787
 788         /* set signature in host scratch pad0 register to tell SPC that the
 789         host performs the soft reset */
 790         pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
 791
 792         /* read required registers for confirmming */
 793         /* map 0x0700000 to BAR4(0x20), BAR2(win) */
 794         if (-1 == bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
 795                 PM8001_FAIL_DBG(pm8001_ha,
 796                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 797                         GSM_ADDR_BASE));
 798                 return -1;
 799         }
 800         PM8001_INIT_DBG(pm8001_ha,
 801                 pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and"
 802                 " Reset = 0x%x\n",
 803                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 804
 805         /* step 3: host read GSM Configuration and Reset register */
 806         regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
 807         /* Put those bits to low */
 808         /* GSM XCBI offset = 0x70 0000
 809         0x00 Bit 13 COM_SLV_SW_RSTB 1
 810         0x00 Bit 12 QSSP_SW_RSTB 1
 811         0x00 Bit 11 RAAE_SW_RSTB 1
 812         0x00 Bit 9 RB_1_SW_RSTB 1
 813         0x00 Bit 8 SM_SW_RSTB 1
 814         */
 815         regVal &= ~(0x00003b00);
 816         /* host write GSM Configuration and Reset register */
 817         pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
 818         PM8001_INIT_DBG(pm8001_ha,
 819                 pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM "
 820                 "Configuration and Reset is set to = 0x%x\n",
 821                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 822
 823         /* step 4: */
 824         /* disable GSM - Read Address Parity Check */
 825         regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
 826         PM8001_INIT_DBG(pm8001_ha,
 827                 pm8001_printk("GSM 0x700038 - Read Address Parity Check "
 828                 "Enable = 0x%x\n", regVal1));
 829         pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
 830         PM8001_INIT_DBG(pm8001_ha,
 831                 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
 832                 "is set to = 0x%x\n",
 833                 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
 834
 835         /* disable GSM - Write Address Parity Check */
 836         regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
 837         PM8001_INIT_DBG(pm8001_ha,
 838                 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
 839                 " Enable = 0x%x\n", regVal2));
 840         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
 841         PM8001_INIT_DBG(pm8001_ha,
 842                 pm8001_printk("GSM 0x700040 - Write Address Parity Check "
 843                 "Enable is set to = 0x%x\n",
 844                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
 845
 846         /* disable GSM - Write Data Parity Check */
 847         regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
 848         PM8001_INIT_DBG(pm8001_ha,
 849                 pm8001_printk("GSM 0x300048 - Write Data Parity Check"
 850                 " Enable = 0x%x\n", regVal3));
 851         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
 852         PM8001_INIT_DBG(pm8001_ha,
 853                 pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable"
 854                 "is set to = 0x%x\n",
 855         pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
 856
 857         /* step 5: delay 10 usec */
 858         udelay(10);
 859         /* step 5-b: set GPIO-0 output control to tristate anyway */
 860         if (-1 == bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
 861                 PM8001_INIT_DBG(pm8001_ha,
 862                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 863                                 GPIO_ADDR_BASE));
 864                 return -1;
 865         }
 866         regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
 867                 PM8001_INIT_DBG(pm8001_ha,
 868                                 pm8001_printk("GPIO Output Control Register:"
 869                                 " = 0x%x\n", regVal));
 870         /* set GPIO-0 output control to tri-state */
 871         regVal &= 0xFFFFFFFC;
 872         pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
 873
 874         /* Step 6: Reset the IOP and AAP1 */
 875         /* map 0x00000 to BAR4(0x20), BAR2(win) */
 876         if (-1 == bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
 877                 PM8001_FAIL_DBG(pm8001_ha,
 878                         pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
 879                         SPC_TOP_LEVEL_ADDR_BASE));
 880                 return -1;
 881         }
 882         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 883         PM8001_INIT_DBG(pm8001_ha,
 884                 pm8001_printk("Top Register before resetting IOP/AAP1"
 885                 ":= 0x%x\n", regVal));
 886         regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
 887         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 888
 889         /* step 7: Reset the BDMA/OSSP */
 890         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 891         PM8001_INIT_DBG(pm8001_ha,
 892                 pm8001_printk("Top Register before resetting BDMA/OSSP"
 893                 ": = 0x%x\n", regVal));
 894         regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
 895         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 896
 897         /* step 8: delay 10 usec */
 898         udelay(10);
 899
 900         /* step 9: bring the BDMA and OSSP out of reset */
 901         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 902         PM8001_INIT_DBG(pm8001_ha,
 903                 pm8001_printk("Top Register before bringing up BDMA/OSSP"
 904                 ":= 0x%x\n", regVal));
 905         regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
 906         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 907
 908         /* step 10: delay 10 usec */
 909         udelay(10);
 910
 911         /* step 11: reads and sets the GSM Configuration and Reset Register */
 912         /* map 0x0700000 to BAR4(0x20), BAR2(win) */
 913         if (-1 == bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
 914                 PM8001_FAIL_DBG(pm8001_ha,
 915                         pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
 916                         GSM_ADDR_BASE));
 917                 return -1;
 918         }
 919         PM8001_INIT_DBG(pm8001_ha,
 920                 pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and "
 921                 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 922         regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
 923         /* Put those bits to high */
 924         /* GSM XCBI offset = 0x70 0000
 925         0x00 Bit 13 COM_SLV_SW_RSTB 1
 926         0x00 Bit 12 QSSP_SW_RSTB 1
 927         0x00 Bit 11 RAAE_SW_RSTB 1
 928         0x00 Bit 9   RB_1_SW_RSTB 1
 929         0x00 Bit 8   SM_SW_RSTB 1
 930         */
 931         regVal |= (GSM_CONFIG_RESET_VALUE);
 932         pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
 933         PM8001_INIT_DBG(pm8001_ha,
 934                 pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM"
 935                 " Configuration and Reset is set to = 0x%x\n",
 936                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 937
 938         /* step 12: Restore GSM - Read Address Parity Check */
 939         regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
 940         /* just for debugging */
 941         PM8001_INIT_DBG(pm8001_ha,
 942                 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
 943                 " = 0x%x\n", regVal));
 944         pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
 945         PM8001_INIT_DBG(pm8001_ha,
 946                 pm8001_printk("GSM 0x700038 - Read Address Parity"
 947                 " Check Enable is set to = 0x%x\n",
 948                 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
 949         /* Restore GSM - Write Address Parity Check */
 950         regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
 951         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
 952         PM8001_INIT_DBG(pm8001_ha,
 953                 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
 954                 " Enable is set to = 0x%x\n",
 955                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
 956         /* Restore GSM - Write Data Parity Check */
 957         regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
 958         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
 959         PM8001_INIT_DBG(pm8001_ha,
 960                 pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable"
 961                 "is set to = 0x%x\n",
 962                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
 963
 964         /* step 13: bring the IOP and AAP1 out of reset */
 965         /* map 0x00000 to BAR4(0x20), BAR2(win) */
 966         if (-1 == bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
 967                 PM8001_FAIL_DBG(pm8001_ha,
 968                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 969                         SPC_TOP_LEVEL_ADDR_BASE));
 970                 return -1;
 971         }
 972         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 973         regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
 974         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 975
 976         /* step 14: delay 10 usec - Normal Mode */
 977         udelay(10);
 978         /* check Soft Reset Normal mode or Soft Reset HDA mode */
 979         if (signature == SPC_SOFT_RESET_SIGNATURE) {
 980                 /* step 15 (Normal Mode): wait until scratch pad1 register
 981                 bit 2 toggled */
 982                 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
 983                 do {
 984                         udelay(1);
 985                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
 986                                 SCRATCH_PAD1_RST;
 987                 } while ((regVal != toggleVal) && (--max_wait_count));
 988
 989                 if (!max_wait_count) {
 990                         regVal = pm8001_cr32(pm8001_ha, 0,
 991                                 MSGU_SCRATCH_PAD_1);
 992                         PM8001_FAIL_DBG(pm8001_ha,
 993                                 pm8001_printk("TIMEOUT : ToggleVal 0x%x,"
 994                                 "MSGU_SCRATCH_PAD1 = 0x%x\n",
 995                                 toggleVal, regVal));
 996                         PM8001_FAIL_DBG(pm8001_ha,
 997                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
 998                                 pm8001_cr32(pm8001_ha, 0,
 999                                 MSGU_SCRATCH_PAD_0)));
1000                         PM8001_FAIL_DBG(pm8001_ha,
1001                                 pm8001_printk("SCRATCH_PAD2 value = 0x%x\n",
1002                                 pm8001_cr32(pm8001_ha, 0,
1003                                 MSGU_SCRATCH_PAD_2)));
1004                         PM8001_FAIL_DBG(pm8001_ha,
1005                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1006                                 pm8001_cr32(pm8001_ha, 0,
1007                                 MSGU_SCRATCH_PAD_3)));
1008                         return -1;
1009                 }
1010
1011                 /* step 16 (Normal) - Clear ODMR and ODCR */
1012                 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1013                 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1014
1015                 /* step 17 (Normal Mode): wait for the FW and IOP to get
1016                 ready - 1 sec timeout */
1017                 /* Wait for the SPC Configuration Table to be ready */
1018                 if (check_fw_ready(pm8001_ha) == -1) {
1019                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1020                         /* return error if MPI Configuration Table not ready */
1021                         PM8001_INIT_DBG(pm8001_ha,
1022                                 pm8001_printk("FW not ready SCRATCH_PAD1"
1023                                 " = 0x%x\n", regVal));
1024                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1025                         /* return error if MPI Configuration Table not ready */
1026                         PM8001_INIT_DBG(pm8001_ha,
1027                                 pm8001_printk("FW not ready SCRATCH_PAD2"
1028                                 " = 0x%x\n", regVal));
1029                         PM8001_INIT_DBG(pm8001_ha,
1030                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1031                                 pm8001_cr32(pm8001_ha, 0,
1032                                 MSGU_SCRATCH_PAD_0)));
1033                         PM8001_INIT_DBG(pm8001_ha,
1034                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1035                                 pm8001_cr32(pm8001_ha, 0,
1036                                 MSGU_SCRATCH_PAD_3)));
1037                         return -1;
1038                 }
1039         }
1040
1041         PM8001_INIT_DBG(pm8001_ha,
1042                 pm8001_printk("SPC soft reset Complete\n"));
1043         return 0;
1044 }
1045
1046 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1047 {
1048         u32 i;
1049         u32 regVal;
1050         PM8001_INIT_DBG(pm8001_ha,
1051                 pm8001_printk("chip reset start\n"));
1052
1053         /* do SPC chip reset. */
1054         regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1055         regVal &= ~(SPC_REG_RESET_DEVICE);
1056         pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1057
1058         /* delay 10 usec */
1059         udelay(10);
1060
1061         /* bring chip reset out of reset */
1062         regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1063         regVal |= SPC_REG_RESET_DEVICE;
1064         pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1065
1066         /* delay 10 usec */
1067         udelay(10);
1068
1069         /* wait for 20 msec until the firmware gets reloaded */
1070         i = 20;
1071         do {
1072                 mdelay(1);
1073         } while ((--i) != 0);
1074
1075         PM8001_INIT_DBG(pm8001_ha,
1076                 pm8001_printk("chip reset finished\n"));
1077 }
1078
1079 /**
1080  * pm8001_chip_iounmap - which maped when initilized.
1081  * @pm8001_ha: our hba card information
1082  */
1083 static void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
1084 {
1085         s8 bar, logical = 0;
1086         for (bar = 0; bar < 6; bar++) {
1087                 /*
1088                 ** logical BARs for SPC:
1089                 ** bar 0 and 1 - logical BAR0
1090                 ** bar 2 and 3 - logical BAR1
1091                 ** bar4 - logical BAR2
1092                 ** bar5 - logical BAR3
1093                 ** Skip the appropriate assignments:
1094                 */
1095                 if ((bar == 1) || (bar == 3))
1096                         continue;
1097                 if (pm8001_ha->io_mem[logical].memvirtaddr) {
1098                         iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1099                         logical++;
1100                 }
1101         }
1102 }
1103
1104 /**
1105  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1106  * @pm8001_ha: our hba card information
1107  */
1108 static void
1109 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1110 {
1111         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1112         pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1113 }
1114
1115  /**
1116   * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1117   * @pm8001_ha: our hba card information
1118   */
1119 static void
1120 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1121 {
1122         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1123 }
1124
1125 /**
1126  * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1127  * @pm8001_ha: our hba card information
1128  */
1129 static void
1130 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1131         u32 int_vec_idx)
1132 {
1133         u32 msi_index;
1134         u32 value;
1135         msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1136         msi_index += MSIX_TABLE_BASE;
1137         pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1138         value = (1 << int_vec_idx);
1139         pm8001_cw32(pm8001_ha, 0,  MSGU_ODCR, value);
1140
1141 }
1142
1143 /**
1144  * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1145  * @pm8001_ha: our hba card information
1146  */
1147 static void
1148 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1149         u32 int_vec_idx)
1150 {
1151         u32 msi_index;
1152         msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1153         msi_index += MSIX_TABLE_BASE;
1154         pm8001_cw32(pm8001_ha, 0,  msi_index, MSIX_INTERRUPT_DISABLE);
1155
1156 }
1157 /**
1158  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1159  * @pm8001_ha: our hba card information
1160  */
1161 static void
1162 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1163 {
1164 #ifdef PM8001_USE_MSIX
1165         pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1166         return;
1167 #endif
1168         pm8001_chip_intx_interrupt_enable(pm8001_ha);
1169
1170 }
1171
1172 /**
1173  * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1174  * @pm8001_ha: our hba card information
1175  */
1176 static void
1177 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1178 {
1179 #ifdef PM8001_USE_MSIX
1180         pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1181         return;
1182 #endif
1183         pm8001_chip_intx_interrupt_disable(pm8001_ha);
1184
1185 }
1186
1187 /**
1188  * mpi_msg_free_get- get the free message buffer for transfer inbound queue.
1189  * @circularQ: the inbound queue  we want to transfer to HBA.
1190  * @messageSize: the message size of this transfer, normally it is 64 bytes
1191  * @messagePtr: the pointer to message.
1192  */
1193 static u32 mpi_msg_free_get(struct inbound_queue_table *circularQ,
1194                             u16 messageSize, void **messagePtr)
1195 {
1196         u32 offset, consumer_index;
1197         struct mpi_msg_hdr *msgHeader;
1198         u8 bcCount = 1; /* only support single buffer */
1199
1200         /* Checks is the requested message size can be allocated in this queue*/
1201         if (messageSize > 64) {
1202                 *messagePtr = NULL;
1203                 return -1;
1204         }
1205
1206         /* Stores the new consumer index */
1207         consumer_index = pm8001_read_32(circularQ->ci_virt);
1208         circularQ->consumer_index = cpu_to_le32(consumer_index);
1209         if (((circularQ->producer_idx + bcCount) % 256) ==
1210                 circularQ->consumer_index) {
1211                 *messagePtr = NULL;
1212                 return -1;
1213         }
1214         /* get memory IOMB buffer address */
1215         offset = circularQ->producer_idx * 64;
1216         /* increment to next bcCount element */
1217         circularQ->producer_idx = (circularQ->producer_idx + bcCount) % 256;
1218         /* Adds that distance to the base of the region virtual address plus
1219         the message header size*/
1220         msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
1221         *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1222         return 0;
1223 }
1224
1225 /**
1226  * mpi_build_cmd- build the message queue for transfer, update the PI to FW
1227  * to tell the fw to get this message from IOMB.
1228  * @pm8001_ha: our hba card information
1229  * @circularQ: the inbound queue we want to transfer to HBA.
1230  * @opCode: the operation code represents commands which LLDD and fw recognized.
1231  * @payload: the command payload of each operation command.
1232  */
1233 static u32 mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
1234                          struct inbound_queue_table *circularQ,
1235                          u32 opCode, void *payload)
1236 {
1237         u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
1238         u32 responseQueue = 0;
1239         void *pMessage;
1240
1241         if (mpi_msg_free_get(circularQ, 64, &pMessage) < 0) {
1242                 PM8001_IO_DBG(pm8001_ha,
1243                         pm8001_printk("No free mpi buffer \n"));
1244                 return -1;
1245         }
1246
1247         /*Copy to the payload*/
1248         memcpy(pMessage, payload, (64 - sizeof(struct mpi_msg_hdr)));
1249
1250         /*Build the header*/
1251         Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1252                 | ((responseQueue & 0x3F) << 16)
1253                 | ((category & 0xF) << 12) | (opCode & 0xFFF));
1254
1255         pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1256         /*Update the PI to the firmware*/
1257         pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1258                 circularQ->pi_offset, circularQ->producer_idx);
1259         PM8001_IO_DBG(pm8001_ha,
1260                 pm8001_printk("after PI= %d CI= %d \n", circularQ->producer_idx,
1261                 circularQ->consumer_index));
1262         return 0;
1263 }
1264
1265 static u32 mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha,
1266                             struct outbound_queue_table *circularQ, u8 bc)
1267 {
1268         u32 producer_index;
1269         /* free the circular queue buffer elements associated with the message*/
1270         circularQ->consumer_idx = (circularQ->consumer_idx + bc) % 256;
1271         /* update the CI of outbound queue */
1272         pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1273                 circularQ->consumer_idx);
1274         /* Update the producer index from SPC*/
1275         producer_index = pm8001_read_32(circularQ->pi_virt);
1276         circularQ->producer_index = cpu_to_le32(producer_index);
1277         PM8001_IO_DBG(pm8001_ha,
1278                 pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx,
1279                 circularQ->producer_index));
1280         return 0;
1281 }
1282
1283 /**
1284  * mpi_msg_consume- get the MPI message from  outbound queue message table.
1285  * @pm8001_ha: our hba card information
1286  * @circularQ: the outbound queue  table.
1287  * @messagePtr1: the message contents of this outbound message.
1288  * @pBC: the message size.
1289  */
1290 static u32 mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
1291                            struct outbound_queue_table *circularQ,
1292                            void **messagePtr1, u8 *pBC)
1293 {
1294         struct mpi_msg_hdr      *msgHeader;
1295         __le32  msgHeader_tmp;
1296         u32 header_tmp;
1297         do {
1298                 /* If there are not-yet-delivered messages ... */
1299                 if (circularQ->producer_index != circularQ->consumer_idx) {
1300                         PM8001_IO_DBG(pm8001_ha,
1301                                 pm8001_printk("process an IOMB\n"));
1302                         /*Get the pointer to the circular queue buffer element*/
1303                         msgHeader = (struct mpi_msg_hdr *)
1304                                 (circularQ->base_virt +
1305                                 circularQ->consumer_idx * 64);
1306                         /* read header */
1307                         header_tmp = pm8001_read_32(msgHeader);
1308                         msgHeader_tmp = cpu_to_le32(header_tmp);
1309                         if (0 != (msgHeader_tmp & 0x80000000)) {
1310                                 if (OPC_OUB_SKIP_ENTRY !=
1311                                         (msgHeader_tmp & 0xfff)) {
1312                                         *messagePtr1 =
1313                                                 ((u8 *)msgHeader) +
1314                                                 sizeof(struct mpi_msg_hdr);
1315                                         *pBC = (u8)((msgHeader_tmp >> 24) &
1316                                                 0x1f);
1317                                         PM8001_IO_DBG(pm8001_ha,
1318                                                 pm8001_printk("mpi_msg_consume"
1319                                                 ": CI=%d PI=%d msgHeader=%x\n",
1320                                                 circularQ->consumer_idx,
1321                                                 circularQ->producer_index,
1322                                                 msgHeader_tmp));
1323                                         return MPI_IO_STATUS_SUCCESS;
1324                                 } else {
1325                                         u32 producer_index;
1326                                         void *pi_virt = circularQ->pi_virt;
1327                                         /* free the circular queue buffer
1328                                         elements associated with the message*/
1329                                         circularQ->consumer_idx =
1330                                                 (circularQ->consumer_idx +
1331                                                 ((msgHeader_tmp >> 24) & 0x1f))
1332                                                 % 256;
1333                                         /* update the CI of outbound queue */
1334                                         pm8001_cw32(pm8001_ha,
1335                                                 circularQ->ci_pci_bar,
1336                                                 circularQ->ci_offset,
1337                                                 circularQ->consumer_idx);
1338                                         /* Update the producer index from SPC */
1339                                         producer_index =
1340                                                 pm8001_read_32(pi_virt);
1341                                         circularQ->producer_index =
1342                                                 cpu_to_le32(producer_index);
1343                                 }
1344                         } else
1345                                 return MPI_IO_STATUS_FAIL;
1346                 }
1347         } while (circularQ->producer_index != circularQ->consumer_idx);
1348         /* while we don't have any more not-yet-delivered message */
1349         /* report empty */
1350         return MPI_IO_STATUS_BUSY;
1351 }
1352
1353 static void pm8001_work_queue(struct work_struct *work)
1354 {
1355         struct delayed_work *dw = container_of(work, struct delayed_work, work);
1356         struct pm8001_wq *wq = container_of(dw, struct pm8001_wq, work_q);
1357         struct pm8001_device *pm8001_dev;
1358         struct domain_device    *dev;
1359
1360         switch (wq->handler) {
1361         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1362                 pm8001_dev = wq->data;
1363                 dev = pm8001_dev->sas_device;
1364                 pm8001_I_T_nexus_reset(dev);
1365                 break;
1366         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1367                 pm8001_dev = wq->data;
1368                 dev = pm8001_dev->sas_device;
1369                 pm8001_I_T_nexus_reset(dev);
1370                 break;
1371         case IO_DS_IN_ERROR:
1372                 pm8001_dev = wq->data;
1373                 dev = pm8001_dev->sas_device;
1374                 pm8001_I_T_nexus_reset(dev);
1375                 break;
1376         case IO_DS_NON_OPERATIONAL:
1377                 pm8001_dev = wq->data;
1378                 dev = pm8001_dev->sas_device;
1379                 pm8001_I_T_nexus_reset(dev);
1380                 break;
1381         }
1382         list_del(&wq->entry);
1383         kfree(wq);
1384 }
1385
1386 static int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
1387                                int handler)
1388 {
1389         struct pm8001_wq *wq;
1390         int ret = 0;
1391
1392         wq = kmalloc(sizeof(struct pm8001_wq), GFP_ATOMIC);
1393         if (wq) {
1394                 wq->pm8001_ha = pm8001_ha;
1395                 wq->data = data;
1396                 wq->handler = handler;
1397                 INIT_DELAYED_WORK(&wq->work_q, pm8001_work_queue);
1398                 list_add_tail(&wq->entry, &pm8001_ha->wq_list);
1399                 schedule_delayed_work(&wq->work_q, 0);
1400         } else
1401                 ret = -ENOMEM;
1402
1403         return ret;
1404 }
1405
1406 /**
1407  * mpi_ssp_completion- process the event that FW response to the SSP request.
1408  * @pm8001_ha: our hba card information
1409  * @piomb: the message contents of this outbound message.
1410  *
1411  * When FW has completed a ssp request for example a IO request, after it has
1412  * filled the SG data with the data, it will trigger this event represent
1413  * that he has finished the job,please check the coresponding buffer.
1414  * So we will tell the caller who maybe waiting the result to tell upper layer
1415  * that the task has been finished.
1416  */
1417 static int
1418 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1419 {
1420         struct sas_task *t;
1421         struct pm8001_ccb_info *ccb;
1422         unsigned long flags;
1423         u32 status;
1424         u32 param;
1425         u32 tag;
1426         struct ssp_completion_resp *psspPayload;
1427         struct task_status_struct *ts;
1428         struct ssp_response_iu *iu;
1429         struct pm8001_device *pm8001_dev;
1430         psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1431         status = le32_to_cpu(psspPayload->status);
1432         tag = le32_to_cpu(psspPayload->tag);
1433         ccb = &pm8001_ha->ccb_info[tag];
1434         pm8001_dev = ccb->device;
1435         param = le32_to_cpu(psspPayload->param);
1436
1437         PM8001_IO_DBG(pm8001_ha, pm8001_printk("OPC_OUB_SSP_COMP\n"));
1438         t = ccb->task;
1439
1440         if (status)
1441                 PM8001_FAIL_DBG(pm8001_ha,
1442                         pm8001_printk("sas IO status 0x%x\n", status));
1443         if (unlikely(!t || !t->lldd_task || !t->dev))
1444                 return -1;
1445         ts = &t->task_status;
1446         switch (status) {
1447         case IO_SUCCESS:
1448                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS"
1449                         ",param = %d \n", param));
1450                 if (param == 0) {
1451                         ts->resp = SAS_TASK_COMPLETE;
1452                         ts->stat = SAM_GOOD;
1453                 } else {
1454                         ts->resp = SAS_TASK_COMPLETE;
1455                         ts->stat = SAS_PROTO_RESPONSE;
1456                         ts->residual = param;
1457                         iu = &psspPayload->ssp_resp_iu;
1458                         sas_ssp_task_response(pm8001_ha->dev, t, iu);
1459                 }
1460                 if (pm8001_dev)
1461                         pm8001_dev->running_req--;
1462                 break;
1463         case IO_ABORTED:
1464                 PM8001_IO_DBG(pm8001_ha,
1465                         pm8001_printk("IO_ABORTED IOMB Tag \n"));
1466                 ts->resp = SAS_TASK_COMPLETE;
1467                 ts->stat = SAS_ABORTED_TASK;
1468                 break;
1469         case IO_UNDERFLOW:
1470                 /* SSP Completion with error */
1471                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW"
1472                         ",param = %d \n", param));
1473                 ts->resp = SAS_TASK_COMPLETE;
1474                 ts->stat = SAS_DATA_UNDERRUN;
1475                 ts->residual = param;
1476                 if (pm8001_dev)
1477                         pm8001_dev->running_req--;
1478                 break;
1479         case IO_NO_DEVICE:
1480                 PM8001_IO_DBG(pm8001_ha,
1481                         pm8001_printk("IO_NO_DEVICE\n"));
1482                 ts->resp = SAS_TASK_UNDELIVERED;
1483                 ts->stat = SAS_PHY_DOWN;
1484                 break;
1485         case IO_XFER_ERROR_BREAK:
1486                 PM8001_IO_DBG(pm8001_ha,
1487                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1488                 ts->resp = SAS_TASK_COMPLETE;
1489                 ts->stat = SAS_OPEN_REJECT;
1490                 break;
1491         case IO_XFER_ERROR_PHY_NOT_READY:
1492                 PM8001_IO_DBG(pm8001_ha,
1493                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1494                 ts->resp = SAS_TASK_COMPLETE;
1495                 ts->stat = SAS_OPEN_REJECT;
1496                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1497                 break;
1498         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1499                 PM8001_IO_DBG(pm8001_ha,
1500                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1501                 ts->resp = SAS_TASK_COMPLETE;
1502                 ts->stat = SAS_OPEN_REJECT;
1503                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1504                 break;
1505         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1506                 PM8001_IO_DBG(pm8001_ha,
1507                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1508                 ts->resp = SAS_TASK_COMPLETE;
1509                 ts->stat = SAS_OPEN_REJECT;
1510                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1511                 break;
1512         case IO_OPEN_CNX_ERROR_BREAK:
1513                 PM8001_IO_DBG(pm8001_ha,
1514                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1515                 ts->resp = SAS_TASK_COMPLETE;
1516                 ts->stat = SAS_OPEN_REJECT;
1517                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
1518                 break;
1519         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1520                 PM8001_IO_DBG(pm8001_ha,
1521                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1522                 ts->resp = SAS_TASK_COMPLETE;
1523                 ts->stat = SAS_OPEN_REJECT;
1524                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1525                 if (!t->uldd_task)
1526                         pm8001_handle_event(pm8001_ha,
1527                                 pm8001_dev,
1528                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1529                 break;
1530         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1531                 PM8001_IO_DBG(pm8001_ha,
1532                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1533                 ts->resp = SAS_TASK_COMPLETE;
1534                 ts->stat = SAS_OPEN_REJECT;
1535                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1536                 break;
1537         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1538                 PM8001_IO_DBG(pm8001_ha,
1539                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1540                         "NOT_SUPPORTED\n"));
1541                 ts->resp = SAS_TASK_COMPLETE;
1542                 ts->stat = SAS_OPEN_REJECT;
1543                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1544                 break;
1545         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1546                 PM8001_IO_DBG(pm8001_ha,
1547                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1548                 ts->resp = SAS_TASK_UNDELIVERED;
1549                 ts->stat = SAS_OPEN_REJECT;
1550                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1551                 break;
1552         case IO_XFER_ERROR_NAK_RECEIVED:
1553                 PM8001_IO_DBG(pm8001_ha,
1554                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1555                 ts->resp = SAS_TASK_COMPLETE;
1556                 ts->stat = SAS_OPEN_REJECT;
1557                 break;
1558         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1559                 PM8001_IO_DBG(pm8001_ha,
1560                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1561                 ts->resp = SAS_TASK_COMPLETE;
1562                 ts->stat = SAS_NAK_R_ERR;
1563                 break;
1564         case IO_XFER_ERROR_DMA:
1565                 PM8001_IO_DBG(pm8001_ha,
1566                 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1567                 ts->resp = SAS_TASK_COMPLETE;
1568                 ts->stat = SAS_OPEN_REJECT;
1569                 break;
1570         case IO_XFER_OPEN_RETRY_TIMEOUT:
1571                 PM8001_IO_DBG(pm8001_ha,
1572                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1573                 ts->resp = SAS_TASK_COMPLETE;
1574                 ts->stat = SAS_OPEN_REJECT;
1575                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1576                 break;
1577         case IO_XFER_ERROR_OFFSET_MISMATCH:
1578                 PM8001_IO_DBG(pm8001_ha,
1579                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1580                 ts->resp = SAS_TASK_COMPLETE;
1581                 ts->stat = SAS_OPEN_REJECT;
1582                 break;
1583         case IO_PORT_IN_RESET:
1584                 PM8001_IO_DBG(pm8001_ha,
1585                         pm8001_printk("IO_PORT_IN_RESET\n"));
1586                 ts->resp = SAS_TASK_COMPLETE;
1587                 ts->stat = SAS_OPEN_REJECT;
1588                 break;
1589         case IO_DS_NON_OPERATIONAL:
1590                 PM8001_IO_DBG(pm8001_ha,
1591                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1592                 ts->resp = SAS_TASK_COMPLETE;
1593                 ts->stat = SAS_OPEN_REJECT;
1594                 if (!t->uldd_task)
1595                         pm8001_handle_event(pm8001_ha,
1596                                 pm8001_dev,
1597                                 IO_DS_NON_OPERATIONAL);
1598                 break;
1599         case IO_DS_IN_RECOVERY:
1600                 PM8001_IO_DBG(pm8001_ha,
1601                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
1602                 ts->resp = SAS_TASK_COMPLETE;
1603                 ts->stat = SAS_OPEN_REJECT;
1604                 break;
1605         case IO_TM_TAG_NOT_FOUND:
1606                 PM8001_IO_DBG(pm8001_ha,
1607                         pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1608                 ts->resp = SAS_TASK_COMPLETE;
1609                 ts->stat = SAS_OPEN_REJECT;
1610                 break;
1611         case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1612                 PM8001_IO_DBG(pm8001_ha,
1613                         pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1614                 ts->resp = SAS_TASK_COMPLETE;
1615                 ts->stat = SAS_OPEN_REJECT;
1616                 break;
1617         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1618                 PM8001_IO_DBG(pm8001_ha,
1619                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1620                 ts->resp = SAS_TASK_COMPLETE;
1621                 ts->stat = SAS_OPEN_REJECT;
1622                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1623         default:
1624                 PM8001_IO_DBG(pm8001_ha,
1625                         pm8001_printk("Unknown status 0x%x\n", status));
1626                 /* not allowed case. Therefore, return failed status */
1627                 ts->resp = SAS_TASK_COMPLETE;
1628                 ts->stat = SAS_OPEN_REJECT;
1629                 break;
1630         }
1631         PM8001_IO_DBG(pm8001_ha,
1632                 pm8001_printk("scsi_satus = %x \n ",
1633                 psspPayload->ssp_resp_iu.status));
1634         spin_lock_irqsave(&t->task_state_lock, flags);
1635         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1636         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1637         t->task_state_flags |= SAS_TASK_STATE_DONE;
1638         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1639                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1640                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
1641                         " io_status 0x%x resp 0x%x "
1642                         "stat 0x%x but aborted by upper layer!\n",
1643                         t, status, ts->resp, ts->stat));
1644                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1645         } else {
1646                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1647                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1648                 mb();/* in order to force CPU ordering */
1649                 t->task_done(t);
1650         }
1651         return 0;
1652 }
1653
1654 /*See the comments for mpi_ssp_completion */
1655 static int mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1656 {
1657         struct sas_task *t;
1658         unsigned long flags;
1659         struct task_status_struct *ts;
1660         struct pm8001_ccb_info *ccb;
1661         struct pm8001_device *pm8001_dev;
1662         struct ssp_event_resp *psspPayload =
1663                 (struct ssp_event_resp *)(piomb + 4);
1664         u32 event = le32_to_cpu(psspPayload->event);
1665         u32 tag = le32_to_cpu(psspPayload->tag);
1666         u32 port_id = le32_to_cpu(psspPayload->port_id);
1667         u32 dev_id = le32_to_cpu(psspPayload->device_id);
1668
1669         ccb = &pm8001_ha->ccb_info[tag];
1670         t = ccb->task;
1671         pm8001_dev = ccb->device;
1672         if (event)
1673                 PM8001_FAIL_DBG(pm8001_ha,
1674                         pm8001_printk("sas IO status 0x%x\n", event));
1675         if (unlikely(!t || !t->lldd_task || !t->dev))
1676                 return -1;
1677         ts = &t->task_status;
1678         PM8001_IO_DBG(pm8001_ha,
1679                 pm8001_printk("port_id = %x,device_id = %x\n",
1680                 port_id, dev_id));
1681         switch (event) {
1682         case IO_OVERFLOW:
1683                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1684                 ts->resp = SAS_TASK_COMPLETE;
1685                 ts->stat = SAS_DATA_OVERRUN;
1686                 ts->residual = 0;
1687                 if (pm8001_dev)
1688                         pm8001_dev->running_req--;
1689                 break;
1690         case IO_XFER_ERROR_BREAK:
1691                 PM8001_IO_DBG(pm8001_ha,
1692                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1693                 ts->resp = SAS_TASK_COMPLETE;
1694                 ts->stat = SAS_INTERRUPTED;
1695                 break;
1696         case IO_XFER_ERROR_PHY_NOT_READY:
1697                 PM8001_IO_DBG(pm8001_ha,
1698                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1699                 ts->resp = SAS_TASK_COMPLETE;
1700                 ts->stat = SAS_OPEN_REJECT;
1701                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1702                 break;
1703         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1704                 PM8001_IO_DBG(pm8001_ha,
1705                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
1706                         "_SUPPORTED\n"));
1707                 ts->resp = SAS_TASK_COMPLETE;
1708                 ts->stat = SAS_OPEN_REJECT;
1709                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1710                 break;
1711         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1712                 PM8001_IO_DBG(pm8001_ha,
1713                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1714                 ts->resp = SAS_TASK_COMPLETE;
1715                 ts->stat = SAS_OPEN_REJECT;
1716                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1717                 break;
1718         case IO_OPEN_CNX_ERROR_BREAK:
1719                 PM8001_IO_DBG(pm8001_ha,
1720                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1721                 ts->resp = SAS_TASK_COMPLETE;
1722                 ts->stat = SAS_OPEN_REJECT;
1723                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
1724                 break;
1725         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1726                 PM8001_IO_DBG(pm8001_ha,
1727                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1728                 ts->resp = SAS_TASK_COMPLETE;
1729                 ts->stat = SAS_OPEN_REJECT;
1730                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1731                 if (!t->uldd_task)
1732                         pm8001_handle_event(pm8001_ha,
1733                                 pm8001_dev,
1734                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1735                 break;
1736         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1737                 PM8001_IO_DBG(pm8001_ha,
1738                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1739                 ts->resp = SAS_TASK_COMPLETE;
1740                 ts->stat = SAS_OPEN_REJECT;
1741                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1742                 break;
1743         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1744                 PM8001_IO_DBG(pm8001_ha,
1745                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1746                         "NOT_SUPPORTED\n"));
1747                 ts->resp = SAS_TASK_COMPLETE;
1748                 ts->stat = SAS_OPEN_REJECT;
1749                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1750                 break;
1751         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1752                 PM8001_IO_DBG(pm8001_ha,
1753                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1754                 ts->resp = SAS_TASK_COMPLETE;
1755                 ts->stat = SAS_OPEN_REJECT;
1756                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1757                 break;
1758         case IO_XFER_ERROR_NAK_RECEIVED:
1759                 PM8001_IO_DBG(pm8001_ha,
1760                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1761                 ts->resp = SAS_TASK_COMPLETE;
1762                 ts->stat = SAS_OPEN_REJECT;
1763                 break;
1764         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1765                 PM8001_IO_DBG(pm8001_ha,
1766                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1767                 ts->resp = SAS_TASK_COMPLETE;
1768                 ts->stat = SAS_NAK_R_ERR;
1769                 break;
1770         case IO_XFER_OPEN_RETRY_TIMEOUT:
1771                 PM8001_IO_DBG(pm8001_ha,
1772                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1773                 ts->resp = SAS_TASK_COMPLETE;
1774                 ts->stat = SAS_OPEN_REJECT;
1775                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1776                 break;
1777         case IO_XFER_ERROR_UNEXPECTED_PHASE:
1778                 PM8001_IO_DBG(pm8001_ha,
1779                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
1780                 ts->resp = SAS_TASK_COMPLETE;
1781                 ts->stat = SAS_DATA_OVERRUN;
1782                 break;
1783         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
1784                 PM8001_IO_DBG(pm8001_ha,
1785                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
1786                 ts->resp = SAS_TASK_COMPLETE;
1787                 ts->stat = SAS_DATA_OVERRUN;
1788                 break;
1789         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
1790                 PM8001_IO_DBG(pm8001_ha,
1791                        pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
1792                 ts->resp = SAS_TASK_COMPLETE;
1793                 ts->stat = SAS_DATA_OVERRUN;
1794                 break;
1795         case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
1796                 PM8001_IO_DBG(pm8001_ha,
1797                 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
1798                 ts->resp = SAS_TASK_COMPLETE;
1799                 ts->stat = SAS_DATA_OVERRUN;
1800                 break;
1801         case IO_XFER_ERROR_OFFSET_MISMATCH:
1802                 PM8001_IO_DBG(pm8001_ha,
1803                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1804                 ts->resp = SAS_TASK_COMPLETE;
1805                 ts->stat = SAS_DATA_OVERRUN;
1806                 break;
1807         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
1808                 PM8001_IO_DBG(pm8001_ha,
1809                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
1810                 ts->resp = SAS_TASK_COMPLETE;
1811                 ts->stat = SAS_DATA_OVERRUN;
1812                 break;
1813         case IO_XFER_CMD_FRAME_ISSUED:
1814                 PM8001_IO_DBG(pm8001_ha,
1815                         pm8001_printk("  IO_XFER_CMD_FRAME_ISSUED\n"));
1816                 return 0;
1817         default:
1818                 PM8001_IO_DBG(pm8001_ha,
1819                         pm8001_printk("Unknown status 0x%x\n", event));
1820                 /* not allowed case. Therefore, return failed status */
1821                 ts->resp = SAS_TASK_COMPLETE;
1822                 ts->stat = SAS_DATA_OVERRUN;
1823                 break;
1824         }
1825         spin_lock_irqsave(&t->task_state_lock, flags);
1826         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1827         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1828         t->task_state_flags |= SAS_TASK_STATE_DONE;
1829         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1830                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1831                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
1832                         " event 0x%x resp 0x%x "
1833                         "stat 0x%x but aborted by upper layer!\n",
1834                         t, event, ts->resp, ts->stat));
1835                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1836         } else {
1837                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1838                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1839                 mb();/* in order to force CPU ordering */
1840                 t->task_done(t);
1841         }
1842         return 0;
1843 }
1844
1845 /*See the comments for mpi_ssp_completion */
1846 static int
1847 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1848 {
1849         struct sas_task *t;
1850         struct pm8001_ccb_info *ccb;
1851         unsigned long flags;
1852         u32 param;
1853         u32 status;
1854         u32 tag;
1855         struct sata_completion_resp *psataPayload;
1856         struct task_status_struct *ts;
1857         struct ata_task_resp *resp ;
1858         u32 *sata_resp;
1859         struct pm8001_device *pm8001_dev;
1860
1861         psataPayload = (struct sata_completion_resp *)(piomb + 4);
1862         status = le32_to_cpu(psataPayload->status);
1863         tag = le32_to_cpu(psataPayload->tag);
1864
1865         ccb = &pm8001_ha->ccb_info[tag];
1866         param = le32_to_cpu(psataPayload->param);
1867         t = ccb->task;
1868         ts = &t->task_status;
1869         pm8001_dev = ccb->device;
1870         if (status)
1871                 PM8001_FAIL_DBG(pm8001_ha,
1872                         pm8001_printk("sata IO status 0x%x\n", status));
1873         if (unlikely(!t || !t->lldd_task || !t->dev))
1874                 return -1;
1875
1876         switch (status) {
1877         case IO_SUCCESS:
1878                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
1879                 if (param == 0) {
1880                         ts->resp = SAS_TASK_COMPLETE;
1881                         ts->stat = SAM_GOOD;
1882                 } else {
1883                         u8 len;
1884                         ts->resp = SAS_TASK_COMPLETE;
1885                         ts->stat = SAS_PROTO_RESPONSE;
1886                         ts->residual = param;
1887                         PM8001_IO_DBG(pm8001_ha,
1888                                 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
1889                                 param));
1890                         sata_resp = &psataPayload->sata_resp[0];
1891                         resp = (struct ata_task_resp *)ts->buf;
1892                         if (t->ata_task.dma_xfer == 0 &&
1893                         t->data_dir == PCI_DMA_FROMDEVICE) {
1894                                 len = sizeof(struct pio_setup_fis);
1895                                 PM8001_IO_DBG(pm8001_ha,
1896                                 pm8001_printk("PIO read len = %d\n", len));
1897                         } else if (t->ata_task.use_ncq) {
1898                                 len = sizeof(struct set_dev_bits_fis);
1899                                 PM8001_IO_DBG(pm8001_ha,
1900                                         pm8001_printk("FPDMA len = %d\n", len));
1901                         } else {
1902                                 len = sizeof(struct dev_to_host_fis);
1903                                 PM8001_IO_DBG(pm8001_ha,
1904                                 pm8001_printk("other len = %d\n", len));
1905                         }
1906                         if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
1907                                 resp->frame_len = len;
1908                                 memcpy(&resp->ending_fis[0], sata_resp, len);
1909                                 ts->buf_valid_size = sizeof(*resp);
1910                         } else
1911                                 PM8001_IO_DBG(pm8001_ha,
1912                                         pm8001_printk("response to large \n"));
1913                 }
1914                 if (pm8001_dev)
1915                         pm8001_dev->running_req--;
1916                 break;
1917         case IO_ABORTED:
1918                 PM8001_IO_DBG(pm8001_ha,
1919                         pm8001_printk("IO_ABORTED IOMB Tag \n"));
1920                 ts->resp = SAS_TASK_COMPLETE;
1921                 ts->stat = SAS_ABORTED_TASK;
1922                 if (pm8001_dev)
1923                         pm8001_dev->running_req--;
1924                 break;
1925                 /* following cases are to do cases */
1926         case IO_UNDERFLOW:
1927                 /* SATA Completion with error */
1928                 PM8001_IO_DBG(pm8001_ha,
1929                         pm8001_printk("IO_UNDERFLOW param = %d\n", param));
1930                 ts->resp = SAS_TASK_COMPLETE;
1931                 ts->stat = SAS_DATA_UNDERRUN;
1932                 ts->residual =  param;
1933                 if (pm8001_dev)
1934                         pm8001_dev->running_req--;
1935                 break;
1936         case IO_NO_DEVICE:
1937                 PM8001_IO_DBG(pm8001_ha,
1938                         pm8001_printk("IO_NO_DEVICE\n"));
1939                 ts->resp = SAS_TASK_UNDELIVERED;
1940                 ts->stat = SAS_PHY_DOWN;
1941                 break;
1942         case IO_XFER_ERROR_BREAK:
1943                 PM8001_IO_DBG(pm8001_ha,
1944                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1945                 ts->resp = SAS_TASK_COMPLETE;
1946                 ts->stat = SAS_INTERRUPTED;
1947                 break;
1948         case IO_XFER_ERROR_PHY_NOT_READY:
1949                 PM8001_IO_DBG(pm8001_ha,
1950                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1951                 ts->resp = SAS_TASK_COMPLETE;
1952                 ts->stat = SAS_OPEN_REJECT;
1953                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1954                 break;
1955         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1956                 PM8001_IO_DBG(pm8001_ha,
1957                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
1958                         "_SUPPORTED\n"));
1959                 ts->resp = SAS_TASK_COMPLETE;
1960                 ts->stat = SAS_OPEN_REJECT;
1961                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1962                 break;
1963         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1964                 PM8001_IO_DBG(pm8001_ha,
1965                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1966                 ts->resp = SAS_TASK_COMPLETE;
1967                 ts->stat = SAS_OPEN_REJECT;
1968                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1969                 break;
1970         case IO_OPEN_CNX_ERROR_BREAK:
1971                 PM8001_IO_DBG(pm8001_ha,
1972                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1973                 ts->resp = SAS_TASK_COMPLETE;
1974                 ts->stat = SAS_OPEN_REJECT;
1975                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
1976                 break;
1977         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1978                 PM8001_IO_DBG(pm8001_ha,
1979                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1980                 ts->resp = SAS_TASK_COMPLETE;
1981                 ts->stat = SAS_DEV_NO_RESPONSE;
1982                 if (!t->uldd_task) {
1983                         pm8001_handle_event(pm8001_ha,
1984                                 pm8001_dev,
1985                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1986                         ts->resp = SAS_TASK_UNDELIVERED;
1987                         ts->stat = SAS_QUEUE_FULL;
1988                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1989                         mb();/*in order to force CPU ordering*/
1990                         t->task_done(t);
1991                         return 0;
1992                 }
1993                 break;
1994         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1995                 PM8001_IO_DBG(pm8001_ha,
1996                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1997                 ts->resp = SAS_TASK_UNDELIVERED;
1998                 ts->stat = SAS_OPEN_REJECT;
1999                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2000                 if (!t->uldd_task) {
2001                         pm8001_handle_event(pm8001_ha,
2002                                 pm8001_dev,
2003                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2004                         ts->resp = SAS_TASK_UNDELIVERED;
2005                         ts->stat = SAS_QUEUE_FULL;
2006                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2007                         mb();/*ditto*/
2008                         t->task_done(t);
2009                         return 0;
2010                 }
2011                 break;
2012         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2013                 PM8001_IO_DBG(pm8001_ha,
2014                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2015                         "NOT_SUPPORTED\n"));
2016                 ts->resp = SAS_TASK_COMPLETE;
2017                 ts->stat = SAS_OPEN_REJECT;
2018                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2019                 break;
2020         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2021                 PM8001_IO_DBG(pm8001_ha,
2022                         pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES"
2023                         "_BUSY\n"));
2024                 ts->resp = SAS_TASK_COMPLETE;
2025                 ts->stat = SAS_DEV_NO_RESPONSE;
2026                 if (!t->uldd_task) {
2027                         pm8001_handle_event(pm8001_ha,
2028                                 pm8001_dev,
2029                                 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2030                         ts->resp = SAS_TASK_UNDELIVERED;
2031                         ts->stat = SAS_QUEUE_FULL;
2032                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2033                         mb();/* ditto*/
2034                         t->task_done(t);
2035                         return 0;
2036                 }
2037                 break;
2038         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2039                 PM8001_IO_DBG(pm8001_ha,
2040                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2041                 ts->resp = SAS_TASK_COMPLETE;
2042                 ts->stat = SAS_OPEN_REJECT;
2043                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2044                 break;
2045         case IO_XFER_ERROR_NAK_RECEIVED:
2046                 PM8001_IO_DBG(pm8001_ha,
2047                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2048                 ts->resp = SAS_TASK_COMPLETE;
2049                 ts->stat = SAS_NAK_R_ERR;
2050                 break;
2051         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2052                 PM8001_IO_DBG(pm8001_ha,
2053                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2054                 ts->resp = SAS_TASK_COMPLETE;
2055                 ts->stat = SAS_NAK_R_ERR;
2056                 break;
2057         case IO_XFER_ERROR_DMA:
2058                 PM8001_IO_DBG(pm8001_ha,
2059                         pm8001_printk("IO_XFER_ERROR_DMA\n"));
2060                 ts->resp = SAS_TASK_COMPLETE;
2061                 ts->stat = SAS_ABORTED_TASK;
2062                 break;
2063         case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2064                 PM8001_IO_DBG(pm8001_ha,
2065                         pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2066                 ts->resp = SAS_TASK_UNDELIVERED;
2067                 ts->stat = SAS_DEV_NO_RESPONSE;
2068                 break;
2069         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2070                 PM8001_IO_DBG(pm8001_ha,
2071                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2072                 ts->resp = SAS_TASK_COMPLETE;
2073                 ts->stat = SAS_DATA_UNDERRUN;
2074                 break;
2075         case IO_XFER_OPEN_RETRY_TIMEOUT:
2076                 PM8001_IO_DBG(pm8001_ha,
2077                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2078                 ts->resp = SAS_TASK_COMPLETE;
2079                 ts->stat = SAS_OPEN_TO;
2080                 break;
2081         case IO_PORT_IN_RESET:
2082                 PM8001_IO_DBG(pm8001_ha,
2083                         pm8001_printk("IO_PORT_IN_RESET\n"));
2084                 ts->resp = SAS_TASK_COMPLETE;
2085                 ts->stat = SAS_DEV_NO_RESPONSE;
2086                 break;
2087         case IO_DS_NON_OPERATIONAL:
2088                 PM8001_IO_DBG(pm8001_ha,
2089                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2090                 ts->resp = SAS_TASK_COMPLETE;
2091                 ts->stat = SAS_DEV_NO_RESPONSE;
2092                 if (!t->uldd_task) {
2093                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2094                                     IO_DS_NON_OPERATIONAL);
2095                         ts->resp = SAS_TASK_UNDELIVERED;
2096                         ts->stat = SAS_QUEUE_FULL;
2097                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2098                         mb();/*ditto*/
2099                         t->task_done(t);
2100                         return 0;
2101                 }
2102                 break;
2103         case IO_DS_IN_RECOVERY:
2104                 PM8001_IO_DBG(pm8001_ha,
2105                         pm8001_printk("  IO_DS_IN_RECOVERY\n"));
2106                 ts->resp = SAS_TASK_COMPLETE;
2107                 ts->stat = SAS_DEV_NO_RESPONSE;
2108                 break;
2109         case IO_DS_IN_ERROR:
2110                 PM8001_IO_DBG(pm8001_ha,
2111                         pm8001_printk("IO_DS_IN_ERROR\n"));
2112                 ts->resp = SAS_TASK_COMPLETE;
2113                 ts->stat = SAS_DEV_NO_RESPONSE;
2114                 if (!t->uldd_task) {
2115                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2116                                     IO_DS_IN_ERROR);
2117                         ts->resp = SAS_TASK_UNDELIVERED;
2118                         ts->stat = SAS_QUEUE_FULL;
2119                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2120                         mb();/*ditto*/
2121                         t->task_done(t);
2122                         return 0;
2123                 }
2124                 break;
2125         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2126                 PM8001_IO_DBG(pm8001_ha,
2127                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2128                 ts->resp = SAS_TASK_COMPLETE;
2129                 ts->stat = SAS_OPEN_REJECT;
2130                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2131         default:
2132                 PM8001_IO_DBG(pm8001_ha,
2133                         pm8001_printk("Unknown status 0x%x\n", status));
2134                 /* not allowed case. Therefore, return failed status */
2135                 ts->resp = SAS_TASK_COMPLETE;
2136                 ts->stat = SAS_DEV_NO_RESPONSE;
2137                 break;
2138         }
2139         spin_lock_irqsave(&t->task_state_lock, flags);
2140         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2141         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2142         t->task_state_flags |= SAS_TASK_STATE_DONE;
2143         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2144                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2145                 PM8001_FAIL_DBG(pm8001_ha,
2146                         pm8001_printk("task 0x%p done with io_status 0x%x"
2147                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2148                         t, status, ts->resp, ts->stat));
2149                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2150         } else {
2151                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2152                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2153                 mb();/* ditto */
2154                 t->task_done(t);
2155         }
2156         return 0;
2157 }
2158
2159 /*See the comments for mpi_ssp_completion */
2160 static int mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2161 {
2162         struct sas_task *t;
2163         unsigned long flags;
2164         struct task_status_struct *ts;
2165         struct pm8001_ccb_info *ccb;
2166         struct pm8001_device *pm8001_dev;
2167         struct sata_event_resp *psataPayload =
2168                 (struct sata_event_resp *)(piomb + 4);
2169         u32 event = le32_to_cpu(psataPayload->event);
2170         u32 tag = le32_to_cpu(psataPayload->tag);
2171         u32 port_id = le32_to_cpu(psataPayload->port_id);
2172         u32 dev_id = le32_to_cpu(psataPayload->device_id);
2173
2174         ccb = &pm8001_ha->ccb_info[tag];
2175         t = ccb->task;
2176         pm8001_dev = ccb->device;
2177         if (event)
2178                 PM8001_FAIL_DBG(pm8001_ha,
2179                         pm8001_printk("sata IO status 0x%x\n", event));
2180         if (unlikely(!t || !t->lldd_task || !t->dev))
2181                 return -1;
2182         ts = &t->task_status;
2183         PM8001_IO_DBG(pm8001_ha,
2184                 pm8001_printk("port_id = %x,device_id = %x\n",
2185                 port_id, dev_id));
2186         switch (event) {
2187         case IO_OVERFLOW:
2188                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2189                 ts->resp = SAS_TASK_COMPLETE;
2190                 ts->stat = SAS_DATA_OVERRUN;
2191                 ts->residual = 0;
2192                 if (pm8001_dev)
2193                         pm8001_dev->running_req--;
2194                 break;
2195         case IO_XFER_ERROR_BREAK:
2196                 PM8001_IO_DBG(pm8001_ha,
2197                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2198                 ts->resp = SAS_TASK_COMPLETE;
2199                 ts->stat = SAS_INTERRUPTED;
2200                 break;
2201         case IO_XFER_ERROR_PHY_NOT_READY:
2202                 PM8001_IO_DBG(pm8001_ha,
2203                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2204                 ts->resp = SAS_TASK_COMPLETE;
2205                 ts->stat = SAS_OPEN_REJECT;
2206                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2207                 break;
2208         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2209                 PM8001_IO_DBG(pm8001_ha,
2210                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2211                         "_SUPPORTED\n"));
2212                 ts->resp = SAS_TASK_COMPLETE;
2213                 ts->stat = SAS_OPEN_REJECT;
2214                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2215                 break;
2216         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2217                 PM8001_IO_DBG(pm8001_ha,
2218                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2219                 ts->resp = SAS_TASK_COMPLETE;
2220                 ts->stat = SAS_OPEN_REJECT;
2221                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2222                 break;
2223         case IO_OPEN_CNX_ERROR_BREAK:
2224                 PM8001_IO_DBG(pm8001_ha,
2225                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2226                 ts->resp = SAS_TASK_COMPLETE;
2227                 ts->stat = SAS_OPEN_REJECT;
2228                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2229                 break;
2230         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2231                 PM8001_IO_DBG(pm8001_ha,
2232                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2233                 ts->resp = SAS_TASK_UNDELIVERED;
2234                 ts->stat = SAS_DEV_NO_RESPONSE;
2235                 if (!t->uldd_task) {
2236                         pm8001_handle_event(pm8001_ha,
2237                                 pm8001_dev,
2238                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2239                         ts->resp = SAS_TASK_COMPLETE;
2240                         ts->stat = SAS_QUEUE_FULL;
2241                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2242                         mb();/*ditto*/
2243                         t->task_done(t);
2244                         return 0;
2245                 }
2246                 break;
2247         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2248                 PM8001_IO_DBG(pm8001_ha,
2249                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2250                 ts->resp = SAS_TASK_UNDELIVERED;
2251                 ts->stat = SAS_OPEN_REJECT;
2252                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2253                 break;
2254         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2255                 PM8001_IO_DBG(pm8001_ha,
2256                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2257                         "NOT_SUPPORTED\n"));
2258                 ts->resp = SAS_TASK_COMPLETE;
2259                 ts->stat = SAS_OPEN_REJECT;
2260                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2261                 break;
2262         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2263                 PM8001_IO_DBG(pm8001_ha,
2264                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2265                 ts->resp = SAS_TASK_COMPLETE;
2266                 ts->stat = SAS_OPEN_REJECT;
2267                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2268                 break;
2269         case IO_XFER_ERROR_NAK_RECEIVED:
2270                 PM8001_IO_DBG(pm8001_ha,
2271                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2272                 ts->resp = SAS_TASK_COMPLETE;
2273                 ts->stat = SAS_NAK_R_ERR;
2274                 break;
2275         case IO_XFER_ERROR_PEER_ABORTED:
2276                 PM8001_IO_DBG(pm8001_ha,
2277                         pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2278                 ts->resp = SAS_TASK_COMPLETE;
2279                 ts->stat = SAS_NAK_R_ERR;
2280                 break;
2281         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2282                 PM8001_IO_DBG(pm8001_ha,
2283                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2284                 ts->resp = SAS_TASK_COMPLETE;
2285                 ts->stat = SAS_DATA_UNDERRUN;
2286                 break;
2287         case IO_XFER_OPEN_RETRY_TIMEOUT:
2288                 PM8001_IO_DBG(pm8001_ha,
2289                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2290                 ts->resp = SAS_TASK_COMPLETE;
2291                 ts->stat = SAS_OPEN_TO;
2292                 break;
2293         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2294                 PM8001_IO_DBG(pm8001_ha,
2295                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2296                 ts->resp = SAS_TASK_COMPLETE;
2297                 ts->stat = SAS_OPEN_TO;
2298                 break;
2299         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2300                 PM8001_IO_DBG(pm8001_ha,
2301                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2302                 ts->resp = SAS_TASK_COMPLETE;
2303                 ts->stat = SAS_OPEN_TO;
2304                 break;
2305         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2306                 PM8001_IO_DBG(pm8001_ha,
2307                        pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2308                 ts->resp = SAS_TASK_COMPLETE;
2309                 ts->stat = SAS_OPEN_TO;
2310                 break;
2311         case IO_XFER_ERROR_OFFSET_MISMATCH:
2312                 PM8001_IO_DBG(pm8001_ha,
2313                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2314                 ts->resp = SAS_TASK_COMPLETE;
2315                 ts->stat = SAS_OPEN_TO;
2316                 break;
2317         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2318                 PM8001_IO_DBG(pm8001_ha,
2319                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2320                 ts->resp = SAS_TASK_COMPLETE;
2321                 ts->stat = SAS_OPEN_TO;
2322                 break;
2323         case IO_XFER_CMD_FRAME_ISSUED:
2324                 PM8001_IO_DBG(pm8001_ha,
2325                         pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2326                 break;
2327         case IO_XFER_PIO_SETUP_ERROR:
2328                 PM8001_IO_DBG(pm8001_ha,
2329                         pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2330                 ts->resp = SAS_TASK_COMPLETE;
2331                 ts->stat = SAS_OPEN_TO;
2332                 break;
2333         default:
2334                 PM8001_IO_DBG(pm8001_ha,
2335                         pm8001_printk("Unknown status 0x%x\n", event));
2336                 /* not allowed case. Therefore, return failed status */
2337                 ts->resp = SAS_TASK_COMPLETE;
2338                 ts->stat = SAS_OPEN_TO;
2339                 break;
2340         }
2341         spin_lock_irqsave(&t->task_state_lock, flags);
2342         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2343         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2344         t->task_state_flags |= SAS_TASK_STATE_DONE;
2345         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2346                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2347                 PM8001_FAIL_DBG(pm8001_ha,
2348                         pm8001_printk("task 0x%p done with io_status 0x%x"
2349                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2350                         t, event, ts->resp, ts->stat));
2351                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2352         } else {
2353                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2354                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2355                 mb();/* in order to force CPU ordering */
2356                 t->task_done(t);
2357         }
2358         return 0;
2359 }
2360
2361 /*See the comments for mpi_ssp_completion */
2362 static int
2363 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2364 {
2365         u32 param;
2366         struct sas_task *t;
2367         struct pm8001_ccb_info *ccb;
2368         unsigned long flags;
2369         u32 status;
2370         u32 tag;
2371         struct smp_completion_resp *psmpPayload;
2372         struct task_status_struct *ts;
2373         struct pm8001_device *pm8001_dev;
2374
2375         psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2376         status = le32_to_cpu(psmpPayload->status);
2377         tag = le32_to_cpu(psmpPayload->tag);
2378
2379         ccb = &pm8001_ha->ccb_info[tag];
2380         param = le32_to_cpu(psmpPayload->param);
2381         t = ccb->task;
2382         ts = &t->task_status;
2383         pm8001_dev = ccb->device;
2384         if (status)
2385                 PM8001_FAIL_DBG(pm8001_ha,
2386                         pm8001_printk("smp IO status 0x%x\n", status));
2387         if (unlikely(!t || !t->lldd_task || !t->dev))
2388                 return -1;
2389
2390         switch (status) {
2391         case IO_SUCCESS:
2392                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2393                 ts->resp = SAS_TASK_COMPLETE;
2394                 ts->stat = SAM_GOOD;
2395         if (pm8001_dev)
2396                         pm8001_dev->running_req--;
2397                 break;
2398         case IO_ABORTED:
2399                 PM8001_IO_DBG(pm8001_ha,
2400                         pm8001_printk("IO_ABORTED IOMB\n"));
2401                 ts->resp = SAS_TASK_COMPLETE;
2402                 ts->stat = SAS_ABORTED_TASK;
2403                 if (pm8001_dev)
2404                         pm8001_dev->running_req--;
2405                 break;
2406         case IO_OVERFLOW:
2407                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2408                 ts->resp = SAS_TASK_COMPLETE;
2409                 ts->stat = SAS_DATA_OVERRUN;
2410                 ts->residual = 0;
2411                 if (pm8001_dev)
2412                         pm8001_dev->running_req--;
2413                 break;
2414         case IO_NO_DEVICE:
2415                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2416                 ts->resp = SAS_TASK_COMPLETE;
2417                 ts->stat = SAS_PHY_DOWN;
2418                 break;
2419         case IO_ERROR_HW_TIMEOUT:
2420                 PM8001_IO_DBG(pm8001_ha,
2421                         pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2422                 ts->resp = SAS_TASK_COMPLETE;
2423                 ts->stat = SAM_BUSY;
2424                 break;
2425         case IO_XFER_ERROR_BREAK:
2426                 PM8001_IO_DBG(pm8001_ha,
2427                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2428                 ts->resp = SAS_TASK_COMPLETE;
2429                 ts->stat = SAM_BUSY;
2430                 break;
2431         case IO_XFER_ERROR_PHY_NOT_READY:
2432                 PM8001_IO_DBG(pm8001_ha,
2433                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2434                 ts->resp = SAS_TASK_COMPLETE;
2435                 ts->stat = SAM_BUSY;
2436                 break;
2437         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2438                 PM8001_IO_DBG(pm8001_ha,
2439                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2440                 ts->resp = SAS_TASK_COMPLETE;
2441                 ts->stat = SAS_OPEN_REJECT;
2442                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2443                 break;
2444         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2445                 PM8001_IO_DBG(pm8001_ha,
2446                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2447                 ts->resp = SAS_TASK_COMPLETE;
2448                 ts->stat = SAS_OPEN_REJECT;
2449                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2450                 break;
2451         case IO_OPEN_CNX_ERROR_BREAK:
2452                 PM8001_IO_DBG(pm8001_ha,
2453                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2454                 ts->resp = SAS_TASK_COMPLETE;
2455                 ts->stat = SAS_OPEN_REJECT;
2456                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2457                 break;
2458         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2459                 PM8001_IO_DBG(pm8001_ha,
2460                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2461                 ts->resp = SAS_TASK_COMPLETE;
2462                 ts->stat = SAS_OPEN_REJECT;
2463                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2464                 pm8001_handle_event(pm8001_ha,
2465                                 pm8001_dev,
2466                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2467                 break;
2468         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2469                 PM8001_IO_DBG(pm8001_ha,
2470                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2471                 ts->resp = SAS_TASK_COMPLETE;
2472                 ts->stat = SAS_OPEN_REJECT;
2473                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2474                 break;
2475         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2476                 PM8001_IO_DBG(pm8001_ha,
2477                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2478                         "NOT_SUPPORTED\n"));
2479                 ts->resp = SAS_TASK_COMPLETE;
2480                 ts->stat = SAS_OPEN_REJECT;
2481                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2482                 break;
2483         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2484                 PM8001_IO_DBG(pm8001_ha,
2485                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2486                 ts->resp = SAS_TASK_COMPLETE;
2487                 ts->stat = SAS_OPEN_REJECT;
2488                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2489                 break;
2490         case IO_XFER_ERROR_RX_FRAME:
2491                 PM8001_IO_DBG(pm8001_ha,
2492                         pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2493                 ts->resp = SAS_TASK_COMPLETE;
2494                 ts->stat = SAS_DEV_NO_RESPONSE;
2495                 break;
2496         case IO_XFER_OPEN_RETRY_TIMEOUT:
2497                 PM8001_IO_DBG(pm8001_ha,
2498                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2499                 ts->resp = SAS_TASK_COMPLETE;
2500                 ts->stat = SAS_OPEN_REJECT;
2501                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2502                 break;
2503         case IO_ERROR_INTERNAL_SMP_RESOURCE:
2504                 PM8001_IO_DBG(pm8001_ha,
2505                         pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2506                 ts->resp = SAS_TASK_COMPLETE;
2507                 ts->stat = SAS_QUEUE_FULL;
2508                 break;
2509         case IO_PORT_IN_RESET:
2510                 PM8001_IO_DBG(pm8001_ha,
2511                         pm8001_printk("IO_PORT_IN_RESET\n"));
2512                 ts->resp = SAS_TASK_COMPLETE;
2513                 ts->stat = SAS_OPEN_REJECT;
2514                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2515                 break;
2516         case IO_DS_NON_OPERATIONAL:
2517                 PM8001_IO_DBG(pm8001_ha,
2518                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2519                 ts->resp = SAS_TASK_COMPLETE;
2520                 ts->stat = SAS_DEV_NO_RESPONSE;
2521                 break;
2522         case IO_DS_IN_RECOVERY:
2523                 PM8001_IO_DBG(pm8001_ha,
2524                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
2525                 ts->resp = SAS_TASK_COMPLETE;
2526                 ts->stat = SAS_OPEN_REJECT;
2527                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2528                 break;
2529         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2530                 PM8001_IO_DBG(pm8001_ha,
2531                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2532                 ts->resp = SAS_TASK_COMPLETE;
2533                 ts->stat = SAS_OPEN_REJECT;
2534                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2535                 break;
2536         default:
2537                 PM8001_IO_DBG(pm8001_ha,
2538                         pm8001_printk("Unknown status 0x%x\n", status));
2539                 ts->resp = SAS_TASK_COMPLETE;
2540                 ts->stat = SAS_DEV_NO_RESPONSE;
2541                 /* not allowed case. Therefore, return failed status */
2542                 break;
2543         }
2544         spin_lock_irqsave(&t->task_state_lock, flags);
2545         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2546         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2547         t->task_state_flags |= SAS_TASK_STATE_DONE;
2548         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2549                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2550                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2551                         " io_status 0x%x resp 0x%x "
2552                         "stat 0x%x but aborted by upper layer!\n",
2553                         t, status, ts->resp, ts->stat));
2554                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2555         } else {
2556                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2557                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2558                 mb();/* in order to force CPU ordering */
2559                 t->task_done(t);
2560         }
2561         return 0;
2562 }
2563
2564 static void
2565 mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2566 {
2567         struct set_dev_state_resp *pPayload =
2568                 (struct set_dev_state_resp *)(piomb + 4);
2569         u32 tag = le32_to_cpu(pPayload->tag);
2570         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2571         struct pm8001_device *pm8001_dev = ccb->device;
2572         u32 status = le32_to_cpu(pPayload->status);
2573         u32 device_id = le32_to_cpu(pPayload->device_id);
2574         u8 pds = le32_to_cpu(pPayload->pds_nds) | PDS_BITS;
2575         u8 nds = le32_to_cpu(pPayload->pds_nds) | NDS_BITS;
2576         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state "
2577                 "from 0x%x to 0x%x status = 0x%x!\n",
2578                 device_id, pds, nds, status));
2579         complete(pm8001_dev->setds_completion);
2580         ccb->task = NULL;
2581         ccb->ccb_tag = 0xFFFFFFFF;
2582         pm8001_ccb_free(pm8001_ha, tag);
2583 }
2584
2585 static void
2586 mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2587 {
2588         struct get_nvm_data_resp *pPayload =
2589                 (struct get_nvm_data_resp *)(piomb + 4);
2590         u32 tag = le32_to_cpu(pPayload->tag);
2591         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2592         u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
2593         complete(pm8001_ha->nvmd_completion);
2594         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n"));
2595         if ((dlen_status & NVMD_STAT) != 0) {
2596                 PM8001_FAIL_DBG(pm8001_ha,
2597                         pm8001_printk("Set nvm data error!\n"));
2598                 return;
2599         }
2600         ccb->task = NULL;
2601         ccb->ccb_tag = 0xFFFFFFFF;
2602         pm8001_ccb_free(pm8001_ha, tag);
2603 }
2604
2605 static void
2606 mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2607 {
2608         struct fw_control_ex    *fw_control_context;
2609         struct get_nvm_data_resp *pPayload =
2610                 (struct get_nvm_data_resp *)(piomb + 4);
2611         u32 tag = le32_to_cpu(pPayload->tag);
2612         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2613         u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
2614         u32 ir_tds_bn_dps_das_nvm =
2615                 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
2616         void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
2617         fw_control_context = ccb->fw_control_context;
2618
2619         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n"));
2620         if ((dlen_status & NVMD_STAT) != 0) {
2621                 PM8001_FAIL_DBG(pm8001_ha,
2622                         pm8001_printk("Get nvm data error!\n"));
2623                 complete(pm8001_ha->nvmd_completion);
2624                 return;
2625         }
2626
2627         if (ir_tds_bn_dps_das_nvm & IPMode) {
2628                 /* indirect mode - IR bit set */
2629                 PM8001_MSG_DBG(pm8001_ha,
2630                         pm8001_printk("Get NVMD success, IR=1\n"));
2631                 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
2632                         if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
2633                                 memcpy(pm8001_ha->sas_addr,
2634                                       ((u8 *)virt_addr + 4),
2635                                        SAS_ADDR_SIZE);
2636                                 PM8001_MSG_DBG(pm8001_ha,
2637                                         pm8001_printk("Get SAS address"
2638                                         " from VPD successfully!\n"));
2639                         }
2640                 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
2641                         || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
2642                         ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
2643                                 ;
2644                 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
2645                         || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
2646                         ;
2647                 } else {
2648                         /* Should not be happened*/
2649                         PM8001_MSG_DBG(pm8001_ha,
2650                                 pm8001_printk("(IR=1)Wrong Device type 0x%x\n",
2651                                 ir_tds_bn_dps_das_nvm));
2652                 }
2653         } else /* direct mode */{
2654                 PM8001_MSG_DBG(pm8001_ha,
2655                         pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n",
2656                         (dlen_status & NVMD_LEN) >> 24));
2657         }
2658         memcpy((void *)(fw_control_context->usrAddr),
2659                 (void *)(pm8001_ha->memoryMap.region[NVMD].virt_ptr),
2660                 fw_control_context->len);
2661         complete(pm8001_ha->nvmd_completion);
2662         ccb->task = NULL;
2663         ccb->ccb_tag = 0xFFFFFFFF;
2664         pm8001_ccb_free(pm8001_ha, tag);
2665 }
2666
2667 static int mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
2668 {
2669         struct local_phy_ctl_resp *pPayload =
2670                 (struct local_phy_ctl_resp *)(piomb + 4);
2671         u32 status = le32_to_cpu(pPayload->status);
2672         u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
2673         u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
2674         if (status != 0) {
2675                 PM8001_MSG_DBG(pm8001_ha,
2676                         pm8001_printk("%x phy execute %x phy op failed! \n",
2677                         phy_id, phy_op));
2678         } else
2679                 PM8001_MSG_DBG(pm8001_ha,
2680                         pm8001_printk("%x phy execute %x phy op success! \n",
2681                         phy_id, phy_op));
2682         return 0;
2683 }
2684
2685 /**
2686  * pm8001_bytes_dmaed - one of the interface function communication with libsas
2687  * @pm8001_ha: our hba card information
2688  * @i: which phy that received the event.
2689  *
2690  * when HBA driver received the identify done event or initiate FIS received
2691  * event(for SATA), it will invoke this function to notify the sas layer that
2692  * the sas toplogy has formed, please discover the the whole sas domain,
2693  * while receive a broadcast(change) primitive just tell the sas
2694  * layer to discover the changed domain rather than the whole domain.
2695  */
2696 static void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
2697 {
2698         struct pm8001_phy *phy = &pm8001_ha->phy[i];
2699         struct asd_sas_phy *sas_phy = &phy->sas_phy;
2700         struct sas_ha_struct *sas_ha;
2701         if (!phy->phy_attached)
2702                 return;
2703
2704         sas_ha = pm8001_ha->sas;
2705         if (sas_phy->phy) {
2706                 struct sas_phy *sphy = sas_phy->phy;
2707                 sphy->negotiated_linkrate = sas_phy->linkrate;
2708                 sphy->minimum_linkrate = phy->minimum_linkrate;
2709                 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
2710                 sphy->maximum_linkrate = phy->maximum_linkrate;
2711                 sphy->maximum_linkrate_hw = phy->maximum_linkrate;
2712         }
2713
2714         if (phy->phy_type & PORT_TYPE_SAS) {
2715                 struct sas_identify_frame *id;
2716                 id = (struct sas_identify_frame *)phy->frame_rcvd;
2717                 id->dev_type = phy->identify.device_type;
2718                 id->initiator_bits = SAS_PROTOCOL_ALL;
2719                 id->target_bits = phy->identify.target_port_protocols;
2720         } else if (phy->phy_type & PORT_TYPE_SATA) {
2721                 /*Nothing*/
2722         }
2723         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i));
2724
2725         sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
2726         pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED);
2727 }
2728
2729 /* Get the link rate speed  */
2730 static void get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
2731 {
2732         struct sas_phy *sas_phy = phy->sas_phy.phy;
2733
2734         switch (link_rate) {
2735         case PHY_SPEED_60:
2736                 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
2737                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
2738                 break;
2739         case PHY_SPEED_30:
2740                 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
2741                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
2742                 break;
2743         case PHY_SPEED_15:
2744                 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
2745                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
2746                 break;
2747         }
2748         sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
2749         sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
2750         sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
2751         sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
2752         sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
2753 }
2754
2755 /**
2756  * asd_get_attached_sas_addr -- extract/generate attached SAS address
2757  * @phy: pointer to asd_phy
2758  * @sas_addr: pointer to buffer where the SAS address is to be written
2759  *
2760  * This function extracts the SAS address from an IDENTIFY frame
2761  * received.  If OOB is SATA, then a SAS address is generated from the
2762  * HA tables.
2763  *
2764  * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
2765  * buffer.
2766  */
2767 static void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
2768         u8 *sas_addr)
2769 {
2770         if (phy->sas_phy.frame_rcvd[0] == 0x34
2771                 && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
2772                 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
2773                 /* FIS device-to-host */
2774                 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
2775                 addr += phy->sas_phy.id;
2776                 *(__be64 *)sas_addr = cpu_to_be64(addr);
2777         } else {
2778                 struct sas_identify_frame *idframe =
2779                         (void *) phy->sas_phy.frame_rcvd;
2780                 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
2781         }
2782 }
2783
2784 /**
2785  * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
2786  * @pm8001_ha: our hba card information
2787  * @Qnum: the outbound queue message number.
2788  * @SEA: source of event to ack
2789  * @port_id: port id.
2790  * @phyId: phy id.
2791  * @param0: parameter 0.
2792  * @param1: parameter 1.
2793  */
2794 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
2795         u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
2796 {
2797         struct hw_event_ack_req  payload;
2798         u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
2799
2800         struct inbound_queue_table *circularQ;
2801
2802         memset((u8 *)&payload, 0, sizeof(payload));
2803         circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
2804         payload.tag = 1;
2805         payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
2806                 ((phyId & 0x0F) << 4) | (port_id & 0x0F));
2807         payload.param0 = cpu_to_le32(param0);
2808         payload.param1 = cpu_to_le32(param1);
2809         mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
2810 }
2811
2812 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
2813         u32 phyId, u32 phy_op);
2814
2815 /**
2816  * hw_event_sas_phy_up -FW tells me a SAS phy up event.
2817  * @pm8001_ha: our hba card information
2818  * @piomb: IO message buffer
2819  */
2820 static void
2821 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2822 {
2823         struct hw_event_resp *pPayload =
2824                 (struct hw_event_resp *)(piomb + 4);
2825         u32 lr_evt_status_phyid_portid =
2826                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
2827         u8 link_rate =
2828                 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
2829         u8 phy_id =
2830                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
2831         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2832         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2833         unsigned long flags;
2834         u8 deviceType = pPayload->sas_identify.dev_type;
2835
2836         PM8001_MSG_DBG(pm8001_ha,
2837                 pm8001_printk("HW_EVENT_SAS_PHY_UP \n"));
2838
2839         switch (deviceType) {
2840         case SAS_PHY_UNUSED:
2841                 PM8001_MSG_DBG(pm8001_ha,
2842                         pm8001_printk("device type no device.\n"));
2843                 break;
2844         case SAS_END_DEVICE:
2845                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
2846                 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
2847                         PHY_NOTIFY_ENABLE_SPINUP);
2848                 get_lrate_mode(phy, link_rate);
2849                 break;
2850         case SAS_EDGE_EXPANDER_DEVICE:
2851                 PM8001_MSG_DBG(pm8001_ha,
2852                         pm8001_printk("expander device.\n"));
2853                 get_lrate_mode(phy, link_rate);
2854                 break;
2855         case SAS_FANOUT_EXPANDER_DEVICE:
2856                 PM8001_MSG_DBG(pm8001_ha,
2857                         pm8001_printk("fanout expander device.\n"));
2858                 get_lrate_mode(phy, link_rate);
2859                 break;
2860         default:
2861                 PM8001_MSG_DBG(pm8001_ha,
2862                         pm8001_printk("unkown device type(%x)\n", deviceType));
2863                 break;
2864         }
2865         phy->phy_type |= PORT_TYPE_SAS;
2866         phy->identify.device_type = deviceType;
2867         phy->phy_attached = 1;
2868         if (phy->identify.device_type == SAS_END_DEV)
2869                 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
2870         else if (phy->identify.device_type != NO_DEVICE)
2871                 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
2872         phy->sas_phy.oob_mode = SAS_OOB_MODE;
2873         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2874         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2875         memcpy(phy->frame_rcvd, &pPayload->sas_identify,
2876                 sizeof(struct sas_identify_frame)-4);
2877         phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
2878         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2879         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2880         if (pm8001_ha->flags == PM8001F_RUN_TIME)
2881                 mdelay(200);/*delay a moment to wait disk to spinup*/
2882         pm8001_bytes_dmaed(pm8001_ha, phy_id);
2883 }
2884
2885 /**
2886  * hw_event_sata_phy_up -FW tells me a SATA phy up event.
2887  * @pm8001_ha: our hba card information
2888  * @piomb: IO message buffer
2889  */
2890 static void
2891 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2892 {
2893         struct hw_event_resp *pPayload =
2894                 (struct hw_event_resp *)(piomb + 4);
2895         u32 lr_evt_status_phyid_portid =
2896                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
2897         u8 link_rate =
2898                 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
2899         u8 phy_id =
2900                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
2901         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2902         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2903         unsigned long flags;
2904         get_lrate_mode(phy, link_rate);
2905         phy->phy_type |= PORT_TYPE_SATA;
2906         phy->phy_attached = 1;
2907         phy->sas_phy.oob_mode = SATA_OOB_MODE;
2908         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2909         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2910         memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
2911                 sizeof(struct dev_to_host_fis));
2912         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
2913         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
2914         phy->identify.device_type = SATA_DEV;
2915         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2916         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2917         pm8001_bytes_dmaed(pm8001_ha, phy_id);
2918 }
2919
2920 /**
2921  * hw_event_phy_down -we should notify the libsas the phy is down.
2922  * @pm8001_ha: our hba card information
2923  * @piomb: IO message buffer
2924  */
2925 static void
2926 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
2927 {
2928         struct hw_event_resp *pPayload =
2929                 (struct hw_event_resp *)(piomb + 4);
2930         u32 lr_evt_status_phyid_portid =
2931                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
2932         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
2933         u8 phy_id =
2934                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
2935         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
2936         u8 portstate = (u8)(npip_portstate & 0x0000000F);
2937
2938         switch (portstate) {
2939         case PORT_VALID:
2940                 break;
2941         case PORT_INVALID:
2942                 PM8001_MSG_DBG(pm8001_ha,
2943                         pm8001_printk(" PortInvalid portID %d \n", port_id));
2944                 PM8001_MSG_DBG(pm8001_ha,
2945                         pm8001_printk(" Last phy Down and port invalid\n"));
2946                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
2947                         port_id, phy_id, 0, 0);
2948                 break;
2949         case PORT_IN_RESET:
2950                 PM8001_MSG_DBG(pm8001_ha,
2951                         pm8001_printk(" PortInReset portID %d \n", port_id));
2952                 break;
2953         case PORT_NOT_ESTABLISHED:
2954                 PM8001_MSG_DBG(pm8001_ha,
2955                         pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
2956                 break;
2957         case PORT_LOSTCOMM:
2958                 PM8001_MSG_DBG(pm8001_ha,
2959                         pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
2960                 PM8001_MSG_DBG(pm8001_ha,
2961                         pm8001_printk(" Last phy Down and port invalid\n"));
2962                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
2963                         port_id, phy_id, 0, 0);
2964                 break;
2965         default:
2966                 PM8001_MSG_DBG(pm8001_ha,
2967                         pm8001_printk(" phy Down and(default) = %x\n",
2968                         portstate));
2969                 break;
2970
2971         }
2972 }
2973
2974 /**
2975  * mpi_reg_resp -process register device ID response.
2976  * @pm8001_ha: our hba card information
2977  * @piomb: IO message buffer
2978  *
2979  * when sas layer find a device it will notify LLDD, then the driver register
2980  * the domain device to FW, this event is the return device ID which the FW
2981  * has assigned, from now,inter-communication with FW is no longer using the
2982  * SAS address, use device ID which FW assigned.
2983  */
2984 static int mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2985 {
2986         u32 status;
2987         u32 device_id;
2988         u32 htag;
2989         struct pm8001_ccb_info *ccb;
2990         struct pm8001_device *pm8001_dev;
2991         struct dev_reg_resp *registerRespPayload =
2992                 (struct dev_reg_resp *)(piomb + 4);
2993
2994         htag = le32_to_cpu(registerRespPayload->tag);
2995         ccb = &pm8001_ha->ccb_info[registerRespPayload->tag];
2996         pm8001_dev = ccb->device;
2997         status = le32_to_cpu(registerRespPayload->status);
2998         device_id = le32_to_cpu(registerRespPayload->device_id);
2999         PM8001_MSG_DBG(pm8001_ha,
3000                 pm8001_printk(" register device is status = %d\n", status));
3001         switch (status) {
3002         case DEVREG_SUCCESS:
3003                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n"));
3004                 pm8001_dev->device_id = device_id;
3005                 break;
3006         case DEVREG_FAILURE_OUT_OF_RESOURCE:
3007                 PM8001_MSG_DBG(pm8001_ha,
3008                         pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n"));
3009                 break;
3010         case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3011                 PM8001_MSG_DBG(pm8001_ha,
3012                    pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n"));
3013                 break;
3014         case DEVREG_FAILURE_INVALID_PHY_ID:
3015                 PM8001_MSG_DBG(pm8001_ha,
3016                         pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n"));
3017                 break;
3018         case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3019                 PM8001_MSG_DBG(pm8001_ha,
3020                    pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n"));
3021                 break;
3022         case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3023                 PM8001_MSG_DBG(pm8001_ha,
3024                         pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n"));
3025                 break;
3026         case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3027                 PM8001_MSG_DBG(pm8001_ha,
3028                         pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n"));
3029                 break;
3030         case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3031                 PM8001_MSG_DBG(pm8001_ha,
3032                        pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n"));
3033                 break;
3034         default:
3035                 PM8001_MSG_DBG(pm8001_ha,
3036                  pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_UNSORPORTED\n"));
3037                 break;
3038         }
3039         complete(pm8001_dev->dcompletion);
3040         ccb->task = NULL;
3041         ccb->ccb_tag = 0xFFFFFFFF;
3042         pm8001_ccb_free(pm8001_ha, htag);
3043         return 0;
3044 }
3045
3046 static int mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3047 {
3048         u32 status;
3049         u32 device_id;
3050         struct dev_reg_resp *registerRespPayload =
3051                 (struct dev_reg_resp *)(piomb + 4);
3052
3053         status = le32_to_cpu(registerRespPayload->status);
3054         device_id = le32_to_cpu(registerRespPayload->device_id);
3055         if (status != 0)
3056                 PM8001_MSG_DBG(pm8001_ha,
3057                         pm8001_printk(" deregister device failed ,status = %x"
3058                         ", device_id = %x\n", status, device_id));
3059         return 0;
3060 }
3061
3062 static int
3063 mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3064 {
3065         u32 status;
3066         struct fw_control_ex    fw_control_context;
3067         struct fw_flash_Update_resp *ppayload =
3068                 (struct fw_flash_Update_resp *)(piomb + 4);
3069         u32 tag = le32_to_cpu(ppayload->tag);
3070         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3071         status = le32_to_cpu(ppayload->status);
3072         memcpy(&fw_control_context,
3073                 ccb->fw_control_context,
3074                 sizeof(fw_control_context));
3075         switch (status) {
3076         case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3077                 PM8001_MSG_DBG(pm8001_ha,
3078                 pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n"));
3079                 break;
3080         case FLASH_UPDATE_IN_PROGRESS:
3081                 PM8001_MSG_DBG(pm8001_ha,
3082                         pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n"));
3083                 break;
3084         case FLASH_UPDATE_HDR_ERR:
3085                 PM8001_MSG_DBG(pm8001_ha,
3086                         pm8001_printk(": FLASH_UPDATE_HDR_ERR\n"));
3087                 break;
3088         case FLASH_UPDATE_OFFSET_ERR:
3089                 PM8001_MSG_DBG(pm8001_ha,
3090                         pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n"));
3091                 break;
3092         case FLASH_UPDATE_CRC_ERR:
3093                 PM8001_MSG_DBG(pm8001_ha,
3094                         pm8001_printk(": FLASH_UPDATE_CRC_ERR\n"));
3095                 break;
3096         case FLASH_UPDATE_LENGTH_ERR:
3097                 PM8001_MSG_DBG(pm8001_ha,
3098                         pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n"));
3099                 break;
3100         case FLASH_UPDATE_HW_ERR:
3101                 PM8001_MSG_DBG(pm8001_ha,
3102                         pm8001_printk(": FLASH_UPDATE_HW_ERR\n"));
3103                 break;
3104         case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3105                 PM8001_MSG_DBG(pm8001_ha,
3106                         pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n"));
3107                 break;
3108         case FLASH_UPDATE_DISABLED:
3109                 PM8001_MSG_DBG(pm8001_ha,
3110                         pm8001_printk(": FLASH_UPDATE_DISABLED\n"));
3111                 break;
3112         default:
3113                 PM8001_MSG_DBG(pm8001_ha,
3114                         pm8001_printk("No matched status = %d\n", status));
3115                 break;
3116         }
3117         ccb->fw_control_context->fw_control->retcode = status;
3118         pci_free_consistent(pm8001_ha->pdev,
3119                         fw_control_context.len,
3120                         fw_control_context.virtAddr,
3121                         fw_control_context.phys_addr);
3122         complete(pm8001_ha->nvmd_completion);
3123         ccb->task = NULL;
3124         ccb->ccb_tag = 0xFFFFFFFF;
3125         pm8001_ccb_free(pm8001_ha, tag);
3126         return 0;
3127 }
3128
3129 static int
3130 mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
3131 {
3132         u32 status;
3133         int i;
3134         struct general_event_resp *pPayload =
3135                 (struct general_event_resp *)(piomb + 4);
3136         status = le32_to_cpu(pPayload->status);
3137         PM8001_MSG_DBG(pm8001_ha,
3138                 pm8001_printk(" status = 0x%x\n", status));
3139         for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3140                 PM8001_MSG_DBG(pm8001_ha,
3141                         pm8001_printk("inb_IOMB_payload[0x%x] 0x%x, \n", i,
3142                         pPayload->inb_IOMB_payload[i]));
3143         return 0;
3144 }
3145
3146 static int
3147 mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3148 {
3149         struct sas_task *t;
3150         struct pm8001_ccb_info *ccb;
3151         unsigned long flags;
3152         u32 status ;
3153         u32 tag, scp;
3154         struct task_status_struct *ts;
3155
3156         struct task_abort_resp *pPayload =
3157                 (struct task_abort_resp *)(piomb + 4);
3158         ccb = &pm8001_ha->ccb_info[pPayload->tag];
3159         t = ccb->task;
3160         ts = &t->task_status;
3161
3162         if (t == NULL)
3163                 return -1;
3164
3165         status = le32_to_cpu(pPayload->status);
3166         tag = le32_to_cpu(pPayload->tag);
3167         scp = le32_to_cpu(pPayload->scp);
3168         PM8001_IO_DBG(pm8001_ha,
3169                 pm8001_printk(" status = 0x%x\n", status));
3170         if (status != 0)
3171                 PM8001_FAIL_DBG(pm8001_ha,
3172                         pm8001_printk("task abort failed tag = 0x%x,"
3173                         " scp= 0x%x\n", tag, scp));
3174         switch (status) {
3175         case IO_SUCCESS:
3176                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
3177                 ts->resp = SAS_TASK_COMPLETE;
3178                 ts->stat = SAM_GOOD;
3179                 break;
3180         case IO_NOT_VALID:
3181                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n"));
3182                 ts->resp = TMF_RESP_FUNC_FAILED;
3183                 break;
3184         }
3185         spin_lock_irqsave(&t->task_state_lock, flags);
3186         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3187         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3188         t->task_state_flags |= SAS_TASK_STATE_DONE;
3189         spin_unlock_irqrestore(&t->task_state_lock, flags);
3190         pm8001_ccb_task_free(pm8001_ha, t, ccb, pPayload->tag);
3191         mb();
3192         t->task_done(t);
3193         return 0;
3194 }
3195
3196 /**
3197  * mpi_hw_event -The hw event has come.
3198  * @pm8001_ha: our hba card information
3199  * @piomb: IO message buffer
3200  */
3201 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb)
3202 {
3203         unsigned long flags;
3204         struct hw_event_resp *pPayload =
3205                 (struct hw_event_resp *)(piomb + 4);
3206         u32 lr_evt_status_phyid_portid =
3207                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3208         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3209         u8 phy_id =
3210                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3211         u16 eventType =
3212                 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3213         u8 status =
3214                 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3215         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3216         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3217         struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3218         PM8001_MSG_DBG(pm8001_ha,
3219                 pm8001_printk("outbound queue HW event & event type : "));
3220         switch (eventType) {
3221         case HW_EVENT_PHY_START_STATUS:
3222                 PM8001_MSG_DBG(pm8001_ha,
3223                 pm8001_printk("HW_EVENT_PHY_START_STATUS"
3224                         " status = %x\n", status));
3225                 if (status == 0) {
3226                         phy->phy_state = 1;
3227                         if (pm8001_ha->flags == PM8001F_RUN_TIME)
3228                                 complete(phy->enable_completion);
3229                 }
3230                 break;
3231         case HW_EVENT_SAS_PHY_UP:
3232                 PM8001_MSG_DBG(pm8001_ha,
3233                         pm8001_printk("HW_EVENT_PHY_START_STATUS \n"));
3234                 hw_event_sas_phy_up(pm8001_ha, piomb);
3235                 break;
3236         case HW_EVENT_SATA_PHY_UP:
3237                 PM8001_MSG_DBG(pm8001_ha,
3238                         pm8001_printk("HW_EVENT_SATA_PHY_UP \n"));
3239                 hw_event_sata_phy_up(pm8001_ha, piomb);
3240                 break;
3241         case HW_EVENT_PHY_STOP_STATUS:
3242                 PM8001_MSG_DBG(pm8001_ha,
3243                         pm8001_printk("HW_EVENT_PHY_STOP_STATUS "
3244                         "status = %x\n", status));
3245                 if (status == 0)
3246                         phy->phy_state = 0;
3247                 break;
3248         case HW_EVENT_SATA_SPINUP_HOLD:
3249                 PM8001_MSG_DBG(pm8001_ha,
3250                         pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD \n"));
3251                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3252                 break;
3253         case HW_EVENT_PHY_DOWN:
3254                 PM8001_MSG_DBG(pm8001_ha,
3255                         pm8001_printk("HW_EVENT_PHY_DOWN \n"));
3256                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3257                 phy->phy_attached = 0;
3258                 phy->phy_state = 0;
3259                 hw_event_phy_down(pm8001_ha, piomb);
3260                 break;
3261         case HW_EVENT_PORT_INVALID:
3262                 PM8001_MSG_DBG(pm8001_ha,
3263                         pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3264                 sas_phy_disconnected(sas_phy);
3265                 phy->phy_attached = 0;
3266                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3267                 break;
3268         /* the broadcast change primitive received, tell the LIBSAS this event
3269         to revalidate the sas domain*/
3270         case HW_EVENT_BROADCAST_CHANGE:
3271                 PM8001_MSG_DBG(pm8001_ha,
3272                         pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3273                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3274                         port_id, phy_id, 1, 0);
3275                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3276                 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3277                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3278                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3279                 break;
3280         case HW_EVENT_PHY_ERROR:
3281                 PM8001_MSG_DBG(pm8001_ha,
3282                         pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3283                 sas_phy_disconnected(&phy->sas_phy);
3284                 phy->phy_attached = 0;
3285                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3286                 break;
3287         case HW_EVENT_BROADCAST_EXP:
3288                 PM8001_MSG_DBG(pm8001_ha,
3289                         pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3290                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3291                 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3292                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3293                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3294                 break;
3295         case HW_EVENT_LINK_ERR_INVALID_DWORD:
3296                 PM8001_MSG_DBG(pm8001_ha,
3297                         pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3298                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3299                         HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3300                 sas_phy_disconnected(sas_phy);
3301                 phy->phy_attached = 0;
3302                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3303                 break;
3304         case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3305                 PM8001_MSG_DBG(pm8001_ha,
3306                         pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3307                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3308                         HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3309                         port_id, phy_id, 0, 0);
3310                 sas_phy_disconnected(sas_phy);
3311                 phy->phy_attached = 0;
3312                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3313                 break;
3314         case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3315                 PM8001_MSG_DBG(pm8001_ha,
3316                         pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3317                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3318                         HW_EVENT_LINK_ERR_CODE_VIOLATION,
3319                         port_id, phy_id, 0, 0);
3320                 sas_phy_disconnected(sas_phy);
3321                 phy->phy_attached = 0;
3322                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3323                 break;
3324         case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3325                 PM8001_MSG_DBG(pm8001_ha,
3326                       pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3327                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3328                         HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3329                         port_id, phy_id, 0, 0);
3330                 sas_phy_disconnected(sas_phy);
3331                 phy->phy_attached = 0;
3332                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3333                 break;
3334         case HW_EVENT_MALFUNCTION:
3335                 PM8001_MSG_DBG(pm8001_ha,
3336                         pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3337                 break;
3338         case HW_EVENT_BROADCAST_SES:
3339                 PM8001_MSG_DBG(pm8001_ha,
3340                         pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3341                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3342                 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3343                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3344                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3345                 break;
3346         case HW_EVENT_INBOUND_CRC_ERROR:
3347                 PM8001_MSG_DBG(pm8001_ha,
3348                         pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3349                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3350                         HW_EVENT_INBOUND_CRC_ERROR,
3351                         port_id, phy_id, 0, 0);
3352                 break;
3353         case HW_EVENT_HARD_RESET_RECEIVED:
3354                 PM8001_MSG_DBG(pm8001_ha,
3355                         pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3356                 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3357                 break;
3358         case HW_EVENT_ID_FRAME_TIMEOUT:
3359                 PM8001_MSG_DBG(pm8001_ha,
3360                         pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3361                 sas_phy_disconnected(sas_phy);
3362                 phy->phy_attached = 0;
3363                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3364                 break;
3365         case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3366                 PM8001_MSG_DBG(pm8001_ha,
3367                         pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED \n"));
3368                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3369                         HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3370                         port_id, phy_id, 0, 0);
3371                 sas_phy_disconnected(sas_phy);
3372                 phy->phy_attached = 0;
3373                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3374                 break;
3375         case HW_EVENT_PORT_RESET_TIMER_TMO:
3376                 PM8001_MSG_DBG(pm8001_ha,
3377                         pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO \n"));
3378                 sas_phy_disconnected(sas_phy);
3379                 phy->phy_attached = 0;
3380                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3381                 break;
3382         case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3383                 PM8001_MSG_DBG(pm8001_ha,
3384                         pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO \n"));
3385                 sas_phy_disconnected(sas_phy);
3386                 phy->phy_attached = 0;
3387                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3388                 break;
3389         case HW_EVENT_PORT_RECOVER:
3390                 PM8001_MSG_DBG(pm8001_ha,
3391                         pm8001_printk("HW_EVENT_PORT_RECOVER \n"));
3392                 break;
3393         case HW_EVENT_PORT_RESET_COMPLETE:
3394                 PM8001_MSG_DBG(pm8001_ha,
3395                         pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE \n"));
3396                 break;
3397         case EVENT_BROADCAST_ASYNCH_EVENT:
3398                 PM8001_MSG_DBG(pm8001_ha,
3399                         pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3400                 break;
3401         default:
3402                 PM8001_MSG_DBG(pm8001_ha,
3403                         pm8001_printk("Unknown event type = %x\n", eventType));
3404                 break;
3405         }
3406         return 0;
3407 }
3408
3409 /**
3410  * process_one_iomb - process one outbound Queue memory block
3411  * @pm8001_ha: our hba card information
3412  * @piomb: IO message buffer
3413  */
3414 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3415 {
3416         u32 pHeader = (u32)*(u32 *)piomb;
3417         u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
3418
3419         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:\n"));
3420
3421         switch (opc) {
3422         case OPC_OUB_ECHO:
3423                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO \n"));
3424                 break;
3425         case OPC_OUB_HW_EVENT:
3426                 PM8001_MSG_DBG(pm8001_ha,
3427                         pm8001_printk("OPC_OUB_HW_EVENT \n"));
3428                 mpi_hw_event(pm8001_ha, piomb);
3429                 break;
3430         case OPC_OUB_SSP_COMP:
3431                 PM8001_MSG_DBG(pm8001_ha,
3432                         pm8001_printk("OPC_OUB_SSP_COMP \n"));
3433                 mpi_ssp_completion(pm8001_ha, piomb);
3434                 break;
3435         case OPC_OUB_SMP_COMP:
3436                 PM8001_MSG_DBG(pm8001_ha,
3437                         pm8001_printk("OPC_OUB_SMP_COMP \n"));
3438                 mpi_smp_completion(pm8001_ha, piomb);
3439                 break;
3440         case OPC_OUB_LOCAL_PHY_CNTRL:
3441                 PM8001_MSG_DBG(pm8001_ha,
3442                         pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3443                 mpi_local_phy_ctl(pm8001_ha, piomb);
3444                 break;
3445         case OPC_OUB_DEV_REGIST:
3446                 PM8001_MSG_DBG(pm8001_ha,
3447                         pm8001_printk("OPC_OUB_DEV_REGIST \n"));
3448                 mpi_reg_resp(pm8001_ha, piomb);
3449                 break;
3450         case OPC_OUB_DEREG_DEV:
3451                 PM8001_MSG_DBG(pm8001_ha,
3452                         pm8001_printk("unresgister the deviece \n"));
3453                 mpi_dereg_resp(pm8001_ha, piomb);
3454                 break;
3455         case OPC_OUB_GET_DEV_HANDLE:
3456                 PM8001_MSG_DBG(pm8001_ha,
3457                         pm8001_printk("OPC_OUB_GET_DEV_HANDLE \n"));
3458                 break;
3459         case OPC_OUB_SATA_COMP:
3460                 PM8001_MSG_DBG(pm8001_ha,
3461                         pm8001_printk("OPC_OUB_SATA_COMP \n"));
3462                 mpi_sata_completion(pm8001_ha, piomb);
3463                 break;
3464         case OPC_OUB_SATA_EVENT:
3465                 PM8001_MSG_DBG(pm8001_ha,
3466                         pm8001_printk("OPC_OUB_SATA_EVENT \n"));
3467                 mpi_sata_event(pm8001_ha, piomb);
3468                 break;
3469         case OPC_OUB_SSP_EVENT:
3470                 PM8001_MSG_DBG(pm8001_ha,
3471                         pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3472                 mpi_ssp_event(pm8001_ha, piomb);
3473                 break;
3474         case OPC_OUB_DEV_HANDLE_ARRIV:
3475                 PM8001_MSG_DBG(pm8001_ha,
3476                         pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3477                 /*This is for target*/
3478                 break;
3479         case OPC_OUB_SSP_RECV_EVENT:
3480                 PM8001_MSG_DBG(pm8001_ha,
3481                         pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3482                 /*This is for target*/
3483                 break;
3484         case OPC_OUB_DEV_INFO:
3485                 PM8001_MSG_DBG(pm8001_ha,
3486                         pm8001_printk("OPC_OUB_DEV_INFO\n"));
3487                 break;
3488         case OPC_OUB_FW_FLASH_UPDATE:
3489                 PM8001_MSG_DBG(pm8001_ha,
3490                         pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3491                 mpi_fw_flash_update_resp(pm8001_ha, piomb);
3492                 break;
3493         case OPC_OUB_GPIO_RESPONSE:
3494                 PM8001_MSG_DBG(pm8001_ha,
3495                         pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3496                 break;
3497         case OPC_OUB_GPIO_EVENT:
3498                 PM8001_MSG_DBG(pm8001_ha,
3499                         pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3500                 break;
3501         case OPC_OUB_GENERAL_EVENT:
3502                 PM8001_MSG_DBG(pm8001_ha,
3503                         pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3504                 mpi_general_event(pm8001_ha, piomb);
3505                 break;
3506         case OPC_OUB_SSP_ABORT_RSP:
3507                 PM8001_MSG_DBG(pm8001_ha,
3508                         pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3509                 mpi_task_abort_resp(pm8001_ha, piomb);
3510                 break;
3511         case OPC_OUB_SATA_ABORT_RSP:
3512                 PM8001_MSG_DBG(pm8001_ha,
3513                         pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3514                 mpi_task_abort_resp(pm8001_ha, piomb);
3515                 break;
3516         case OPC_OUB_SAS_DIAG_MODE_START_END:
3517                 PM8001_MSG_DBG(pm8001_ha,
3518                         pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3519                 break;
3520         case OPC_OUB_SAS_DIAG_EXECUTE:
3521                 PM8001_MSG_DBG(pm8001_ha,
3522                         pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3523                 break;
3524         case OPC_OUB_GET_TIME_STAMP:
3525                 PM8001_MSG_DBG(pm8001_ha,
3526                         pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3527                 break;
3528         case OPC_OUB_SAS_HW_EVENT_ACK:
3529                 PM8001_MSG_DBG(pm8001_ha,
3530                         pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3531                 break;
3532         case OPC_OUB_PORT_CONTROL:
3533                 PM8001_MSG_DBG(pm8001_ha,
3534                         pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3535                 break;
3536         case OPC_OUB_SMP_ABORT_RSP:
3537                 PM8001_MSG_DBG(pm8001_ha,
3538                         pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3539                 mpi_task_abort_resp(pm8001_ha, piomb);
3540                 break;
3541         case OPC_OUB_GET_NVMD_DATA:
3542                 PM8001_MSG_DBG(pm8001_ha,
3543                         pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3544                 mpi_get_nvmd_resp(pm8001_ha, piomb);
3545                 break;
3546         case OPC_OUB_SET_NVMD_DATA:
3547                 PM8001_MSG_DBG(pm8001_ha,
3548                         pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3549                 mpi_set_nvmd_resp(pm8001_ha, piomb);
3550                 break;
3551         case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3552                 PM8001_MSG_DBG(pm8001_ha,
3553                         pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3554                 break;
3555         case OPC_OUB_SET_DEVICE_STATE:
3556                 PM8001_MSG_DBG(pm8001_ha,
3557                         pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3558                 mpi_set_dev_state_resp(pm8001_ha, piomb);
3559                 break;
3560         case OPC_OUB_GET_DEVICE_STATE:
3561                 PM8001_MSG_DBG(pm8001_ha,
3562                         pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3563                 break;
3564         case OPC_OUB_SET_DEV_INFO:
3565                 PM8001_MSG_DBG(pm8001_ha,
3566                         pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3567                 break;
3568         case OPC_OUB_SAS_RE_INITIALIZE:
3569                 PM8001_MSG_DBG(pm8001_ha,
3570                         pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n"));
3571                 break;
3572         default:
3573                 PM8001_MSG_DBG(pm8001_ha,
3574                         pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n",
3575                         opc));
3576                 break;
3577         }
3578 }
3579
3580 static int process_oq(struct pm8001_hba_info *pm8001_ha)
3581 {
3582         struct outbound_queue_table *circularQ;
3583         void *pMsg1 = NULL;
3584         u8 bc = 0;
3585         u32 ret = MPI_IO_STATUS_FAIL, processedMsgCount = 0;
3586
3587         circularQ = &pm8001_ha->outbnd_q_tbl[0];
3588         do {
3589                 ret = mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3590                 if (MPI_IO_STATUS_SUCCESS == ret) {
3591                         /* process the outbound message */
3592                         process_one_iomb(pm8001_ha, (void *)((u8 *)pMsg1 - 4));
3593                         /* free the message from the outbound circular buffer */
3594                         mpi_msg_free_set(pm8001_ha, circularQ, bc);
3595                         processedMsgCount++;
3596                 }
3597                 if (MPI_IO_STATUS_BUSY == ret) {
3598                         u32 producer_idx;
3599                         /* Update the producer index from SPC */
3600                         producer_idx = pm8001_read_32(circularQ->pi_virt);
3601                         circularQ->producer_index = cpu_to_le32(producer_idx);
3602                         if (circularQ->producer_index ==
3603                                 circularQ->consumer_idx)
3604                                 /* OQ is empty */
3605                                 break;
3606                 }
3607         } while (100 > processedMsgCount);/*end message processing if hit the
3608         count*/
3609         return ret;
3610 }
3611
3612 /* PCI_DMA_... to our direction translation. */
3613 static const u8 data_dir_flags[] = {
3614         [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3615         [PCI_DMA_TODEVICE]      = DATA_DIR_OUT,/* OUTBOUND */
3616         [PCI_DMA_FROMDEVICE]    = DATA_DIR_IN,/* INBOUND */
3617         [PCI_DMA_NONE]          = DATA_DIR_NONE,/* NO TRANSFER */
3618 };
3619 static void
3620 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
3621 {
3622         int i;
3623         struct scatterlist *sg;
3624         struct pm8001_prd *buf_prd = prd;
3625
3626         for_each_sg(scatter, sg, nr, i) {
3627                 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
3628                 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
3629                 buf_prd->im_len.e = 0;
3630                 buf_prd++;
3631         }
3632 }
3633
3634 static void build_smp_cmd(u32 deviceID, u32 hTag, struct smp_req *psmp_cmd)
3635 {
3636         psmp_cmd->tag = cpu_to_le32(hTag);
3637         psmp_cmd->device_id = cpu_to_le32(deviceID);
3638         psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3639 }
3640
3641 /**
3642  * pm8001_chip_smp_req - send a SMP task to FW
3643  * @pm8001_ha: our hba card information.
3644  * @ccb: the ccb information this request used.
3645  */
3646 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3647         struct pm8001_ccb_info *ccb)
3648 {
3649         int elem, rc;
3650         struct sas_task *task = ccb->task;
3651         struct domain_device *dev = task->dev;
3652         struct pm8001_device *pm8001_dev = dev->lldd_dev;
3653         struct scatterlist *sg_req, *sg_resp;
3654         u32 req_len, resp_len;
3655         struct smp_req smp_cmd;
3656         u32 opc;
3657         struct inbound_queue_table *circularQ;
3658
3659         memset(&smp_cmd, 0, sizeof(smp_cmd));
3660         /*
3661          * DMA-map SMP request, response buffers
3662          */
3663         sg_req = &task->smp_task.smp_req;
3664         elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
3665         if (!elem)
3666                 return -ENOMEM;
3667         req_len = sg_dma_len(sg_req);
3668
3669         sg_resp = &task->smp_task.smp_resp;
3670         elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
3671         if (!elem) {
3672                 rc = -ENOMEM;
3673                 goto err_out;
3674         }
3675         resp_len = sg_dma_len(sg_resp);
3676         /* must be in dwords */
3677         if ((req_len & 0x3) || (resp_len & 0x3)) {
3678                 rc = -EINVAL;
3679                 goto err_out_2;
3680         }
3681
3682         opc = OPC_INB_SMP_REQUEST;
3683         circularQ = &pm8001_ha->inbnd_q_tbl[0];
3684         smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
3685         smp_cmd.long_smp_req.long_req_addr =
3686                 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
3687         smp_cmd.long_smp_req.long_req_size =
3688                 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
3689         smp_cmd.long_smp_req.long_resp_addr =
3690                 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
3691         smp_cmd.long_smp_req.long_resp_size =
3692                 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
3693         build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
3694         mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd);
3695         return 0;
3696
3697 err_out_2:
3698         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
3699                         PCI_DMA_FROMDEVICE);
3700 err_out:
3701         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
3702                         PCI_DMA_TODEVICE);
3703         return rc;
3704 }
3705
3706 /**
3707  * pm8001_chip_ssp_io_req - send a SSP task to FW
3708  * @pm8001_ha: our hba card information.
3709  * @ccb: the ccb information this request used.
3710  */
3711 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
3712         struct pm8001_ccb_info *ccb)
3713 {
3714         struct sas_task *task = ccb->task;
3715         struct domain_device *dev = task->dev;
3716         struct pm8001_device *pm8001_dev = dev->lldd_dev;
3717         struct ssp_ini_io_start_req ssp_cmd;
3718         u32 tag = ccb->ccb_tag;
3719         __le64 phys_addr;
3720         struct inbound_queue_table *circularQ;
3721         u32 opc = OPC_INB_SSPINIIOSTART;
3722         memset(&ssp_cmd, 0, sizeof(ssp_cmd));
3723         memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
3724         ssp_cmd.dir_m_tlr = data_dir_flags[task->data_dir] << 8 | 0x0;/*0 for
3725         SAS 1.1 compatible TLR*/
3726         ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3727         ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
3728         ssp_cmd.tag = cpu_to_le32(tag);
3729         if (task->ssp_task.enable_first_burst)
3730                 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
3731         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
3732         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
3733         memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cdb, 16);
3734         circularQ = &pm8001_ha->inbnd_q_tbl[0];
3735
3736         /* fill in PRD (scatter/gather) table, if any */
3737         if (task->num_scatter > 1) {
3738                 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
3739                 phys_addr = cpu_to_le64(ccb->ccb_dma_handle +
3740                                 offsetof(struct pm8001_ccb_info, buf_prd[0]));
3741                 ssp_cmd.addr_low = lower_32_bits(phys_addr);
3742                 ssp_cmd.addr_high = upper_32_bits(phys_addr);
3743                 ssp_cmd.esgl = cpu_to_le32(1<<31);
3744         } else if (task->num_scatter == 1) {
3745                 __le64 dma_addr = cpu_to_le64(sg_dma_address(task->scatter));
3746                 ssp_cmd.addr_low = lower_32_bits(dma_addr);
3747                 ssp_cmd.addr_high = upper_32_bits(dma_addr);
3748                 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
3749                 ssp_cmd.esgl = 0;
3750         } else if (task->num_scatter == 0) {
3751                 ssp_cmd.addr_low = 0;
3752                 ssp_cmd.addr_high = 0;
3753                 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
3754                 ssp_cmd.esgl = 0;
3755         }
3756         mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd);
3757         return 0;
3758 }
3759
3760 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
3761         struct pm8001_ccb_info *ccb)
3762 {
3763         struct sas_task *task = ccb->task;
3764         struct domain_device *dev = task->dev;
3765         struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
3766         u32 tag = ccb->ccb_tag;
3767         struct sata_start_req sata_cmd;
3768         u32 hdr_tag, ncg_tag = 0;
3769         __le64 phys_addr;
3770         u32 ATAP = 0x0;
3771         u32 dir;
3772         struct inbound_queue_table *circularQ;
3773         u32  opc = OPC_INB_SATA_HOST_OPSTART;
3774         memset(&sata_cmd, 0, sizeof(sata_cmd));
3775         circularQ = &pm8001_ha->inbnd_q_tbl[0];
3776         if (task->data_dir == PCI_DMA_NONE) {
3777                 ATAP = 0x04;  /* no data*/
3778                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data \n"));
3779         } else if (likely(!task->ata_task.device_control_reg_update)) {
3780                 if (task->ata_task.dma_xfer) {
3781                         ATAP = 0x06; /* DMA */
3782                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA \n"));
3783                 } else {
3784                         ATAP = 0x05; /* PIO*/
3785                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO \n"));
3786                 }
3787                 if (task->ata_task.use_ncq &&
3788                         dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
3789                         ATAP = 0x07; /* FPDMA */
3790                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA \n"));
3791                 }
3792         }
3793         if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag))
3794                 ncg_tag = cpu_to_le32(hdr_tag);
3795         dir = data_dir_flags[task->data_dir] << 8;
3796         sata_cmd.tag = cpu_to_le32(tag);
3797         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
3798         sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3799         sata_cmd.ncqtag_atap_dir_m =
3800                 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
3801         sata_cmd.sata_fis = task->ata_task.fis;
3802         if (likely(!task->ata_task.device_control_reg_update))
3803                 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
3804         sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
3805         /* fill in PRD (scatter/gather) table, if any */
3806         if (task->num_scatter > 1) {
3807                 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
3808                 phys_addr = cpu_to_le64(ccb->ccb_dma_handle +
3809                                 offsetof(struct pm8001_ccb_info, buf_prd[0]));
3810                 sata_cmd.addr_low = lower_32_bits(phys_addr);
3811                 sata_cmd.addr_high = upper_32_bits(phys_addr);
3812                 sata_cmd.esgl = cpu_to_le32(1 << 31);
3813         } else if (task->num_scatter == 1) {
3814                 __le64 dma_addr = cpu_to_le64(sg_dma_address(task->scatter));
3815                 sata_cmd.addr_low = lower_32_bits(dma_addr);
3816                 sata_cmd.addr_high = upper_32_bits(dma_addr);
3817                 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
3818                 sata_cmd.esgl = 0;
3819         } else if (task->num_scatter == 0) {
3820                 sata_cmd.addr_low = 0;
3821                 sata_cmd.addr_high = 0;
3822                 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
3823                 sata_cmd.esgl = 0;
3824         }
3825         mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd);
3826         return 0;
3827 }
3828
3829 /**
3830  * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
3831  * @pm8001_ha: our hba card information.
3832  * @num: the inbound queue number
3833  * @phy_id: the phy id which we wanted to start up.
3834  */
3835 static int
3836 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
3837 {
3838         struct phy_start_req payload;
3839         struct inbound_queue_table *circularQ;
3840         u32 tag = 0x01;
3841         u32 opcode = OPC_INB_PHYSTART;
3842         circularQ = &pm8001_ha->inbnd_q_tbl[0];
3843         memset(&payload, 0, sizeof(payload));
3844         payload.tag = cpu_to_le32(tag);
3845         /*
3846          ** [0:7]   PHY Identifier
3847          ** [8:11]  link rate 1.5G, 3G, 6G
3848          ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
3849          ** [14]    0b disable spin up hold; 1b enable spin up hold
3850          */
3851         payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
3852                 LINKMODE_AUTO | LINKRATE_15 |
3853                 LINKRATE_30 | LINKRATE_60 | phy_id);
3854         payload.sas_identify.dev_type = SAS_END_DEV;
3855         payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
3856         memcpy(payload.sas_identify.sas_addr,
3857                 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
3858         payload.sas_identify.phy_id = phy_id;
3859         mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload);
3860         return 0;
3861 }
3862
3863 /**
3864  * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
3865  * @pm8001_ha: our hba card information.
3866  * @num: the inbound queue number
3867  * @phy_id: the phy id which we wanted to start up.
3868  */
3869 static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
3870         u8 phy_id)
3871 {
3872         struct phy_stop_req payload;
3873         struct inbound_queue_table *circularQ;
3874         u32 tag = 0x01;
3875         u32 opcode = OPC_INB_PHYSTOP;
3876         circularQ = &pm8001_ha->inbnd_q_tbl[0];
3877         memset(&payload, 0, sizeof(payload));
3878         payload.tag = cpu_to_le32(tag);
3879         payload.phy_id = cpu_to_le32(phy_id);
3880         mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload);
3881         return 0;
3882 }
3883
3884 /**
3885  * see comments on mpi_reg_resp.
3886  */
3887 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
3888         struct pm8001_device *pm8001_dev, u32 flag)
3889 {
3890         struct reg_dev_req payload;
3891         u32     opc;
3892         u32 stp_sspsmp_sata = 0x4;
3893         struct inbound_queue_table *circularQ;
3894         u32 linkrate, phy_id;
3895         u32 rc, tag = 0xdeadbeef;
3896         struct pm8001_ccb_info *ccb;
3897         u8 retryFlag = 0x1;
3898         u16 firstBurstSize = 0;
3899         u16 ITNT = 2000;
3900         struct domain_device *dev = pm8001_dev->sas_device;
3901         struct domain_device *parent_dev = dev->parent;
3902         circularQ = &pm8001_ha->inbnd_q_tbl[0];
3903
3904         memset(&payload, 0, sizeof(payload));
3905         rc = pm8001_tag_alloc(pm8001_ha, &tag);
3906         if (rc)
3907                 return rc;
3908         ccb = &pm8001_ha->ccb_info[tag];
3909         ccb->device = pm8001_dev;
3910         ccb->ccb_tag = tag;
3911         payload.tag = cpu_to_le32(tag);
3912         if (flag == 1)
3913                 stp_sspsmp_sata = 0x02; /*direct attached sata */
3914         else {
3915                 if (pm8001_dev->dev_type == SATA_DEV)
3916                         stp_sspsmp_sata = 0x00; /* stp*/
3917                 else if (pm8001_dev->dev_type == SAS_END_DEV ||
3918                         pm8001_dev->dev_type == EDGE_DEV ||
3919                         pm8001_dev->dev_type == FANOUT_DEV)
3920                         stp_sspsmp_sata = 0x01; /*ssp or smp*/
3921         }
3922         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
3923                 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
3924         else
3925                 phy_id = pm8001_dev->attached_phy;
3926         opc = OPC_INB_REG_DEV;
3927         linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
3928                         pm8001_dev->sas_device->linkrate : dev->port->linkrate;
3929         payload.phyid_portid =
3930                 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) |
3931                 ((phy_id & 0x0F) << 4));
3932         payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
3933                 ((linkrate & 0x0F) * 0x1000000) |
3934                 ((stp_sspsmp_sata & 0x03) * 0x10000000));
3935         payload.firstburstsize_ITNexustimeout =
3936                 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
3937         memcpy(&payload.sas_addr_hi, pm8001_dev->sas_device->sas_addr,
3938                 SAS_ADDR_SIZE);
3939         mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
3940         return 0;
3941 }
3942
3943 /**
3944  * see comments on mpi_reg_resp.
3945  */
3946 static int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
3947         u32 device_id)
3948 {
3949         struct dereg_dev_req payload;
3950         u32 opc = OPC_INB_DEREG_DEV_HANDLE;
3951         struct inbound_queue_table *circularQ;
3952
3953         circularQ = &pm8001_ha->inbnd_q_tbl[0];
3954         memset((u8 *)&payload, 0, sizeof(payload));
3955         payload.tag = 1;
3956         payload.device_id = cpu_to_le32(device_id);
3957         PM8001_MSG_DBG(pm8001_ha,
3958                 pm8001_printk("unregister device device_id = %d\n", device_id));
3959         mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
3960         return 0;
3961 }
3962
3963 /**
3964  * pm8001_chip_phy_ctl_req - support the local phy operation
3965  * @pm8001_ha: our hba card information.
3966  * @num: the inbound queue number
3967  * @phy_id: the phy id which we wanted to operate
3968  * @phy_op:
3969  */
3970 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3971         u32 phyId, u32 phy_op)
3972 {
3973         struct local_phy_ctl_req payload;
3974         struct inbound_queue_table *circularQ;
3975         u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
3976         memset((u8 *)&payload, 0, sizeof(payload));
3977         circularQ = &pm8001_ha->inbnd_q_tbl[0];
3978         payload.tag = 1;
3979         payload.phyop_phyid =
3980                 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
3981         mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
3982         return 0;
3983 }
3984
3985 static u32 pm8001_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
3986 {
3987         u32 value;
3988 #ifdef PM8001_USE_MSIX
3989         return 1;
3990 #endif
3991         value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
3992         if (value)
3993                 return 1;
3994         return 0;
3995
3996 }
3997
3998 /**
3999  * pm8001_chip_isr - PM8001 isr handler.
4000  * @pm8001_ha: our hba card information.
4001  * @irq: irq number.
4002  * @stat: stat.
4003  */
4004 static void
4005 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha)
4006 {
4007         pm8001_chip_interrupt_disable(pm8001_ha);
4008         process_oq(pm8001_ha);
4009         pm8001_chip_interrupt_enable(pm8001_ha);
4010 }
4011
4012 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
4013         u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag)
4014 {
4015         struct task_abort_req task_abort;
4016         struct inbound_queue_table *circularQ;
4017
4018         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4019         memset(&task_abort, 0, sizeof(task_abort));
4020         if (ABORT_SINGLE == (flag & ABORT_MASK)) {
4021                 task_abort.abort_all = 0;
4022                 task_abort.device_id = cpu_to_le32(dev_id);
4023                 task_abort.tag_to_abort = cpu_to_le32(task_tag);
4024                 task_abort.tag = cpu_to_le32(cmd_tag);
4025         } else if (ABORT_ALL == (flag & ABORT_MASK)) {
4026                 task_abort.abort_all = cpu_to_le32(1);
4027                 task_abort.device_id = cpu_to_le32(dev_id);
4028                 task_abort.tag = cpu_to_le32(cmd_tag);
4029         }
4030         mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort);
4031         return 0;
4032 }
4033
4034 /**
4035  * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4036  * @task: the task we wanted to aborted.
4037  * @flag: the abort flag.
4038  */
4039 static int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
4040         struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag)
4041 {
4042         u32 opc, device_id;
4043         int rc = TMF_RESP_FUNC_FAILED;
4044         PM8001_IO_DBG(pm8001_ha, pm8001_printk("Abort tag[%x]", task_tag));
4045         if (pm8001_dev->dev_type == SAS_END_DEV)
4046                 opc = OPC_INB_SSP_ABORT;
4047         else if (pm8001_dev->dev_type == SATA_DEV)
4048                 opc = OPC_INB_SATA_ABORT;
4049         else
4050                 opc = OPC_INB_SMP_ABORT;/* SMP */
4051         device_id = pm8001_dev->device_id;
4052         rc = send_task_abort(pm8001_ha, opc, device_id, flag,
4053                 task_tag, cmd_tag);
4054         if (rc != TMF_RESP_FUNC_COMPLETE)
4055                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc));
4056         return rc;
4057 }
4058
4059 /**
4060  * pm8001_chip_ssp_tm_req - built the task managment command.
4061  * @pm8001_ha: our hba card information.
4062  * @ccb: the ccb information.
4063  * @tmf: task management function.
4064  */
4065 static int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
4066         struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
4067 {
4068         struct sas_task *task = ccb->task;
4069         struct domain_device *dev = task->dev;
4070         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4071         u32 opc = OPC_INB_SSPINITMSTART;
4072         struct inbound_queue_table *circularQ;
4073         struct ssp_ini_tm_start_req sspTMCmd;
4074
4075         memset(&sspTMCmd, 0, sizeof(sspTMCmd));
4076         sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4077         sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed);
4078         sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
4079         sspTMCmd.ds_ads_m = cpu_to_le32(1 << 2);
4080         memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
4081         sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
4082         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4083         mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd);
4084         return 0;
4085 }
4086
4087 static int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4088         void *payload)
4089 {
4090         u32 opc = OPC_INB_GET_NVMD_DATA;
4091         u32 nvmd_type;
4092         u32 rc;
4093         u32 tag;
4094         struct pm8001_ccb_info *ccb;
4095         struct inbound_queue_table *circularQ;
4096         struct get_nvm_data_req nvmd_req;
4097         struct fw_control_ex *fw_control_context;
4098         struct pm8001_ioctl_payload *ioctl_payload = payload;
4099
4100         nvmd_type = ioctl_payload->minor_function;
4101         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4102         fw_control_context->usrAddr = (u8 *)&ioctl_payload->func_specific[0];
4103         fw_control_context->len = ioctl_payload->length;
4104         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4105         memset(&nvmd_req, 0, sizeof(nvmd_req));
4106         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4107         if (rc)
4108                 return rc;
4109         ccb = &pm8001_ha->ccb_info[tag];
4110         ccb->ccb_tag = tag;
4111         ccb->fw_control_context = fw_control_context;
4112         nvmd_req.tag = cpu_to_le32(tag);
4113
4114         switch (nvmd_type) {
4115         case TWI_DEVICE: {
4116                 u32 twi_addr, twi_page_size;
4117                 twi_addr = 0xa8;
4118                 twi_page_size = 2;
4119
4120                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4121                         twi_page_size << 8 | TWI_DEVICE);
4122                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4123                 nvmd_req.resp_addr_hi =
4124                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4125                 nvmd_req.resp_addr_lo =
4126                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4127                 break;
4128         }
4129         case C_SEEPROM: {
4130                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4131                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4132                 nvmd_req.resp_addr_hi =
4133                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4134                 nvmd_req.resp_addr_lo =
4135                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4136                 break;
4137         }
4138         case VPD_FLASH: {
4139                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4140                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4141                 nvmd_req.resp_addr_hi =
4142                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4143                 nvmd_req.resp_addr_lo =
4144                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4145                 break;
4146         }
4147         case EXPAN_ROM: {
4148                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4149                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4150                 nvmd_req.resp_addr_hi =
4151                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4152                 nvmd_req.resp_addr_lo =
4153                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4154                 break;
4155         }
4156         default:
4157                 break;
4158         }
4159         mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req);
4160         return 0;
4161 }
4162
4163 static int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4164         void *payload)
4165 {
4166         u32 opc = OPC_INB_SET_NVMD_DATA;
4167         u32 nvmd_type;
4168         u32 rc;
4169         u32 tag;
4170         struct pm8001_ccb_info *ccb;
4171         struct inbound_queue_table *circularQ;
4172         struct set_nvm_data_req nvmd_req;
4173         struct fw_control_ex *fw_control_context;
4174         struct pm8001_ioctl_payload *ioctl_payload = payload;
4175
4176         nvmd_type = ioctl_payload->minor_function;
4177         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4178         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4179         memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
4180                 ioctl_payload->func_specific,
4181                 ioctl_payload->length);
4182         memset(&nvmd_req, 0, sizeof(nvmd_req));
4183         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4184         if (rc)
4185                 return rc;
4186         ccb = &pm8001_ha->ccb_info[tag];
4187         ccb->fw_control_context = fw_control_context;
4188         ccb->ccb_tag = tag;
4189         nvmd_req.tag = cpu_to_le32(tag);
4190         switch (nvmd_type) {
4191         case TWI_DEVICE: {
4192                 u32 twi_addr, twi_page_size;
4193                 twi_addr = 0xa8;
4194                 twi_page_size = 2;
4195                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4196                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4197                         twi_page_size << 8 | TWI_DEVICE);
4198                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4199                 nvmd_req.resp_addr_hi =
4200                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4201                 nvmd_req.resp_addr_lo =
4202                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4203                 break;
4204         }
4205         case C_SEEPROM:
4206                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4207                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4208                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4209                 nvmd_req.resp_addr_hi =
4210                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4211                 nvmd_req.resp_addr_lo =
4212                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4213                 break;
4214         case VPD_FLASH:
4215                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4216                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4217                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4218                 nvmd_req.resp_addr_hi =
4219                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4220                 nvmd_req.resp_addr_lo =
4221                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4222                 break;
4223         case EXPAN_ROM:
4224                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4225                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4226                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4227                 nvmd_req.resp_addr_hi =
4228                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4229                 nvmd_req.resp_addr_lo =
4230                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4231                 break;
4232         default:
4233                 break;
4234         }
4235         mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req);
4236         return 0;
4237 }
4238
4239 /**
4240  * pm8001_chip_fw_flash_update_build - support the firmware update operation
4241  * @pm8001_ha: our hba card information.
4242  * @fw_flash_updata_info: firmware flash update param
4243  */
4244 static int
4245 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
4246         void *fw_flash_updata_info, u32 tag)
4247 {
4248         struct fw_flash_Update_req payload;
4249         struct fw_flash_updata_info *info;
4250         struct inbound_queue_table *circularQ;
4251         u32 opc = OPC_INB_FW_FLASH_UPDATE;
4252
4253         memset((u8 *)&payload, 0, sizeof(struct fw_flash_Update_req));
4254         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4255         info = fw_flash_updata_info;
4256         payload.tag = cpu_to_le32(tag);
4257         payload.cur_image_len = cpu_to_le32(info->cur_image_len);
4258         payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
4259         payload.total_image_len = cpu_to_le32(info->total_image_len);
4260         payload.len = info->sgl.im_len.len ;
4261         payload.sgl_addr_lo = lower_32_bits(info->sgl.addr);
4262         payload.sgl_addr_hi = upper_32_bits(info->sgl.addr);
4263         mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4264         return 0;
4265 }
4266
4267 static int
4268 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
4269         void *payload)
4270 {
4271         struct fw_flash_updata_info flash_update_info;
4272         struct fw_control_info *fw_control;
4273         struct fw_control_ex *fw_control_context;
4274         u32 rc;
4275         u32 tag;
4276         struct pm8001_ccb_info *ccb;
4277         void *buffer = NULL;
4278         dma_addr_t phys_addr;
4279         u32 phys_addr_hi;
4280         u32 phys_addr_lo;
4281         struct pm8001_ioctl_payload *ioctl_payload = payload;
4282
4283         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4284         fw_control = (struct fw_control_info *)&ioctl_payload->func_specific[0];
4285         if (fw_control->len != 0) {
4286                 if (pm8001_mem_alloc(pm8001_ha->pdev,
4287                         (void **)&buffer,
4288                         &phys_addr,
4289                         &phys_addr_hi,
4290                         &phys_addr_lo,
4291                         fw_control->len, 0) != 0) {
4292                                 PM8001_FAIL_DBG(pm8001_ha,
4293                                         pm8001_printk("Mem alloc failure\n"));
4294                                 return -ENOMEM;
4295                 }
4296         }
4297         memset((void *)buffer, 0, fw_control->len);
4298         memcpy((void *)buffer, fw_control->buffer, fw_control->len);
4299         flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
4300         flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
4301         flash_update_info.sgl.im_len.e = 0;
4302         flash_update_info.cur_image_offset = fw_control->offset;
4303         flash_update_info.cur_image_len = fw_control->len;
4304         flash_update_info.total_image_len = fw_control->size;
4305         fw_control_context->fw_control = fw_control;
4306         fw_control_context->virtAddr = buffer;
4307         fw_control_context->len = fw_control->len;
4308         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4309         if (rc)
4310                 return rc;
4311         ccb = &pm8001_ha->ccb_info[tag];
4312         ccb->fw_control_context = fw_control_context;
4313         ccb->ccb_tag = tag;
4314         pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info, tag);
4315         return 0;
4316 }
4317
4318 static int
4319 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
4320         struct pm8001_device *pm8001_dev, u32 state)
4321 {
4322         struct set_dev_state_req payload;
4323         struct inbound_queue_table *circularQ;
4324         struct pm8001_ccb_info *ccb;
4325         u32 rc;
4326         u32 tag;
4327         u32 opc = OPC_INB_SET_DEVICE_STATE;
4328         memset((u8 *)&payload, 0, sizeof(payload));
4329         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4330         if (rc)
4331                 return -1;
4332         ccb = &pm8001_ha->ccb_info[tag];
4333         ccb->ccb_tag = tag;
4334         ccb->device = pm8001_dev;
4335         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4336         payload.tag = cpu_to_le32(tag);
4337         payload.device_id = cpu_to_le32(pm8001_dev->device_id);
4338         payload.nds = cpu_to_le32(state);
4339         mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4340         return 0;
4341
4342 }
4343
4344 const struct pm8001_dispatch pm8001_8001_dispatch = {
4345         .name                   = "pmc8001",
4346         .chip_init              = pm8001_chip_init,
4347         .chip_soft_rst          = pm8001_chip_soft_rst,
4348         .chip_rst               = pm8001_hw_chip_rst,
4349         .chip_iounmap           = pm8001_chip_iounmap,
4350         .isr                    = pm8001_chip_isr,
4351         .is_our_interupt        = pm8001_chip_is_our_interupt,
4352         .isr_process_oq         = process_oq,
4353         .interrupt_enable       = pm8001_chip_interrupt_enable,
4354         .interrupt_disable      = pm8001_chip_interrupt_disable,
4355         .make_prd               = pm8001_chip_make_sg,
4356         .smp_req                = pm8001_chip_smp_req,
4357         .ssp_io_req             = pm8001_chip_ssp_io_req,
4358         .sata_req               = pm8001_chip_sata_req,
4359         .phy_start_req          = pm8001_chip_phy_start_req,
4360         .phy_stop_req           = pm8001_chip_phy_stop_req,
4361         .reg_dev_req            = pm8001_chip_reg_dev_req,
4362         .dereg_dev_req          = pm8001_chip_dereg_dev_req,
4363         .phy_ctl_req            = pm8001_chip_phy_ctl_req,
4364         .task_abort             = pm8001_chip_abort_task,
4365         .ssp_tm_req             = pm8001_chip_ssp_tm_req,
4366         .get_nvmd_req           = pm8001_chip_get_nvmd_req,
4367         .set_nvmd_req           = pm8001_chip_set_nvmd_req,
4368         .fw_flash_update_req    = pm8001_chip_fw_flash_update_req,
4369         .set_dev_state_req      = pm8001_chip_set_dev_state_req,
4370 };
4371