1 /************************************************************************
3 * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
4 * Intel Corporation: Storage RAID Controllers *
7 * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
8 * Copyright (C) 2002-04 Intel Corporation *
9 * Copyright (C) 2003-06 Adaptec Inc. *
10 * <achim_leubner@adaptec.com> *
13 * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
14 * Johannes Dinner <johannes_dinner@adaptec.com> *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published *
18 * by the Free Software Foundation; either version 2 of the License, *
19 * or (at your option) any later version. *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
26 * You should have received a copy of the GNU General Public License *
27 * along with this kernel; if not, write to the Free Software *
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
30 * Linux kernel 2.6.x supported *
32 ************************************************************************/
34 /* All GDT Disk Array Controllers are fully supported by this driver.
35 * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
36 * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
37 * list of all controller types.
39 * If you have one or more GDT3000/3020 EISA controllers with
40 * controller BIOS disabled, you have to set the IRQ values with the
41 * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
42 * the IRQ values for the EISA controllers.
44 * After the optional list of IRQ values, other possible
45 * command line options are:
46 * disable:Y disable driver
47 * disable:N enable driver
48 * reserve_mode:0 reserve no drives for the raw service
49 * reserve_mode:1 reserve all not init., removable drives
50 * reserve_mode:2 reserve all not init. drives
51 * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
52 * h- controller no., b- channel no.,
53 * t- target ID, l- LUN
54 * reverse_scan:Y reverse scan order for PCI controllers
55 * reverse_scan:N scan PCI controllers like BIOS
56 * max_ids:x x - target ID count per channel (1..MAXID)
57 * rescan:Y rescan all channels/IDs
58 * rescan:N use all devices found until now
59 * virt_ctr:Y map every channel to a virtual controller
60 * virt_ctr:N use multi channel support
61 * hdr_channel:x x - number of virtual bus for host drives
62 * shared_access:Y disable driver reserve/release protocol to
63 * access a shared resource from several nodes,
64 * appropriate controller firmware required
65 * shared_access:N enable driver reserve/release protocol
66 * probe_eisa_isa:Y scan for EISA/ISA controllers
67 * probe_eisa_isa:N do not scan for EISA/ISA controllers
68 * force_dma32:Y use only 32 bit DMA mode
69 * force_dma32:N use 64 bit DMA mode, if supported
71 * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
72 * max_ids:127,rescan:N,virt_ctr:N,hdr_channel:0,
73 * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
74 * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
76 * When loading the gdth driver as a module, the same options are available.
77 * You can set the IRQs with "IRQ=...". However, the syntax to specify the
78 * options changes slightly. You must replace all ',' between options
79 * with ' ' and all ':' with '=' and you must use
80 * '1' in place of 'Y' and '0' in place of 'N'.
82 * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
83 * max_ids=127 rescan=0 virt_ctr=0 hdr_channel=0 shared_access=0
84 * probe_eisa_isa=0 force_dma32=0"
85 * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
88 /* The meaning of the Scsi_Pointer members in this driver is as follows:
90 * this_residual: Command priority
91 * buffer: phys. DMA sense buffer
92 * dma_handle: phys. DMA buffer (kernel >= 2.4.0)
93 * buffers_residual: Timeout value
94 * Status: Command status (gdth_do_cmd()), DMA mem. mappings
95 * Message: Additional info (gdth_do_cmd()), DMA direction
96 * have_data_in: Flag for gdth_wait_completion()
97 * sent_command: Opcode special command
98 * phase: Service/parameter/return code special command
102 /* interrupt coalescing */
103 /* #define INT_COAL */
106 #define GDTH_STATISTICS
108 #include <linux/module.h>
110 #include <linux/version.h>
111 #include <linux/kernel.h>
112 #include <linux/types.h>
113 #include <linux/pci.h>
114 #include <linux/string.h>
115 #include <linux/ctype.h>
116 #include <linux/ioport.h>
117 #include <linux/delay.h>
118 #include <linux/interrupt.h>
119 #include <linux/in.h>
120 #include <linux/proc_fs.h>
121 #include <linux/time.h>
122 #include <linux/timer.h>
123 #include <linux/dma-mapping.h>
126 #include <linux/mc146818rtc.h>
128 #include <linux/reboot.h>
131 #include <asm/system.h>
133 #include <asm/uaccess.h>
134 #include <linux/spinlock.h>
135 #include <linux/blkdev.h>
138 #include <scsi/scsi_host.h>
141 static void gdth_delay(int milliseconds);
142 static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
143 static irqreturn_t gdth_interrupt(int irq, void *dev_id);
144 static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp);
145 static int gdth_async_event(int hanum);
146 static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
148 static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority);
149 static void gdth_next(int hanum);
150 static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b);
151 static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp);
152 static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
153 ushort idx, gdth_evt_data *evt);
154 static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
155 static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
157 static void gdth_clear_events(void);
159 static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
160 char *buffer,ushort count);
161 static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp);
162 static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive);
164 static void gdth_enable_int(int hanum);
165 static int gdth_get_status(unchar *pIStatus,int irq);
166 static int gdth_test_busy(int hanum);
167 static int gdth_get_cmd_index(int hanum);
168 static void gdth_release_event(int hanum);
169 static int gdth_wait(int hanum,int index,ulong32 time);
170 static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
171 ulong64 p2,ulong64 p3);
172 static int gdth_search_drives(int hanum);
173 static int gdth_analyse_hdrive(int hanum, ushort hdrive);
175 static const char *gdth_ctr_name(int hanum);
177 static int gdth_open(struct inode *inode, struct file *filep);
178 static int gdth_close(struct inode *inode, struct file *filep);
179 static int gdth_ioctl(struct inode *inode, struct file *filep,
180 unsigned int cmd, unsigned long arg);
182 static void gdth_flush(int hanum);
183 static int gdth_halt(struct notifier_block *nb, ulong event, void *buf);
184 static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
185 static void gdth_scsi_done(struct scsi_cmnd *scp);
187 static int gdth_isa_probe_one(struct scsi_host_template *, ulong32);
190 static int gdth_eisa_probe_one(struct scsi_host_template *, ushort);
193 static int gdth_pci_probe_one(struct scsi_host_template *, gdth_pci_str *, int);
197 static unchar DebugState = DEBUG_GDTH;
200 #define MAX_SERBUF 160
201 static void ser_init(void);
202 static void ser_puts(char *str);
203 static void ser_putc(char c);
204 static int ser_printk(const char *fmt, ...);
205 static char strbuf[MAX_SERBUF+1];
207 #define COM_BASE 0x2f8
209 #define COM_BASE 0x3f8
211 static void ser_init()
213 unsigned port=COM_BASE;
217 /* 19200 Baud, if 9600: outb(12,port) */
227 static void ser_puts(char *str)
232 for (ptr=str;*ptr;++ptr)
236 static void ser_putc(char c)
238 unsigned port=COM_BASE;
240 while ((inb(port+5) & 0x20)==0);
244 while ((inb(port+5) & 0x20)==0);
249 static int ser_printk(const char *fmt, ...)
255 i = vsprintf(strbuf,fmt,args);
261 #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
262 #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
263 #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
265 #else /* !__SERIAL__ */
266 #define TRACE(a) {if (DebugState==1) {printk a;}}
267 #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
268 #define TRACE3(a) {if (DebugState!=0) {printk a;}}
277 #ifdef GDTH_STATISTICS
278 static ulong32 max_rq=0, max_index=0, max_sg=0;
280 static ulong32 max_int_coal=0;
282 static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
283 static struct timer_list gdth_timer;
286 #define PTR2USHORT(a) (ushort)(ulong)(a)
287 #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
288 #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
290 #define NUMDATA(a) ( (gdth_num_str *)((a)->hostdata))
291 #define HADATA(a) (&((gdth_ext_str *)((a)->hostdata))->haext)
292 #define CMDDATA(a) (&((gdth_ext_str *)((a)->hostdata))->cmdext)
294 #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
297 static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
300 static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
302 static unchar gdth_polling; /* polling if TRUE */
303 static unchar gdth_from_wait = FALSE; /* gdth_wait() */
304 static int wait_index,wait_hanum; /* gdth_wait() */
305 static int gdth_ctr_count = 0; /* controller count */
306 static int gdth_ctr_vcount = 0; /* virt. ctr. count */
307 static int gdth_ctr_released = 0; /* gdth_release() */
308 static struct Scsi_Host *gdth_ctr_tab[MAXHA]; /* controller table */
309 static struct Scsi_Host *gdth_ctr_vtab[MAXHA*MAXBUS]; /* virt. ctr. table */
310 static unchar gdth_write_through = FALSE; /* write through */
311 static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
316 #define DIN 1 /* IN data direction */
317 #define DOU 2 /* OUT data direction */
318 #define DNO DIN /* no data transfer */
319 #define DUN DIN /* unknown data direction */
320 static unchar gdth_direction_tab[0x100] = {
321 DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
322 DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
323 DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
324 DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
325 DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
326 DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
327 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
328 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
329 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
330 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
331 DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
332 DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
333 DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
334 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
335 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
336 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
339 /* LILO and modprobe/insmod parameters */
340 /* IRQ list for GDT3000/3020 EISA controllers */
341 static int irq[MAXHA] __initdata =
342 {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
343 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
344 /* disable driver flag */
345 static int disable __initdata = 0;
347 static int reserve_mode = 1;
349 static int reserve_list[MAX_RES_ARGS] =
350 {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
351 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
352 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
353 /* scan order for PCI controllers */
354 static int reverse_scan = 0;
355 /* virtual channel for the host drives */
356 static int hdr_channel = 0;
357 /* max. IDs per channel */
358 static int max_ids = MAXID;
360 static int rescan = 0;
361 /* map channels to virtual controllers */
362 static int virt_ctr = 0;
364 static int shared_access = 1;
365 /* enable support for EISA and ISA controllers */
366 static int probe_eisa_isa = 0;
367 /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
368 static int force_dma32 = 0;
370 /* parameters for modprobe/insmod */
371 module_param_array(irq, int, NULL, 0);
372 module_param(disable, int, 0);
373 module_param(reserve_mode, int, 0);
374 module_param_array(reserve_list, int, NULL, 0);
375 module_param(reverse_scan, int, 0);
376 module_param(hdr_channel, int, 0);
377 module_param(max_ids, int, 0);
378 module_param(rescan, int, 0);
379 module_param(virt_ctr, int, 0);
380 module_param(shared_access, int, 0);
381 module_param(probe_eisa_isa, int, 0);
382 module_param(force_dma32, int, 0);
383 MODULE_AUTHOR("Achim Leubner");
384 MODULE_LICENSE("GPL");
386 /* ioctl interface */
387 static const struct file_operations gdth_fops = {
390 .release = gdth_close,
393 #define GDTH_MAGIC 0xc2e7c389 /* I got it from /dev/urandom */
394 #define IS_GDTH_INTERNAL_CMD(scp) (scp->underflow == GDTH_MAGIC)
396 #include "gdth_proc.h"
397 #include "gdth_proc.c"
399 /* notifier block to get a notify on system shutdown/halt/reboot */
400 static struct notifier_block gdth_notifier = {
403 static int notifier_disabled = 0;
405 static void gdth_delay(int milliseconds)
407 if (milliseconds == 0) {
410 mdelay(milliseconds);
414 static void gdth_scsi_done(struct scsi_cmnd *scp)
416 TRACE2(("gdth_scsi_done()\n"));
418 if (IS_GDTH_INTERNAL_CMD(scp))
419 complete((struct completion *)scp->request);
424 int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
425 int timeout, u32 *info)
428 DECLARE_COMPLETION_ONSTACK(wait);
431 scp = kzalloc(sizeof(*scp), GFP_KERNEL);
436 /* use request field to save the ptr. to completion struct. */
437 scp->request = (struct request *)&wait;
438 scp->timeout_per_command = timeout*HZ;
439 scp->request_buffer = gdtcmd;
441 memcpy(scp->cmnd, cmnd, 12);
442 scp->SCp.this_residual = IOCTL_PRI; /* priority */
443 scp->underflow = GDTH_MAGIC;
444 gdth_queuecommand(scp, NULL);
445 wait_for_completion(&wait);
447 rval = scp->SCp.Status;
449 *info = scp->SCp.Message;
454 int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
455 int timeout, u32 *info)
457 struct scsi_device *sdev = scsi_get_host_dev(shost);
458 int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
460 scsi_free_host_dev(sdev);
464 static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
466 *cyls = size /HEADS/SECS;
467 if (*cyls <= MAXCYLS) {
470 } else { /* too high for 64*32 */
471 *cyls = size /MEDHEADS/MEDSECS;
472 if (*cyls <= MAXCYLS) {
475 } else { /* too high for 127*63 */
476 *cyls = size /BIGHEADS/BIGSECS;
483 /* controller search and initialization functions */
485 static int __init gdth_search_eisa(ushort eisa_adr)
489 TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
490 id = inl(eisa_adr+ID0REG);
491 if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
492 if ((inb(eisa_adr+EISAREG) & 8) == 0)
493 return 0; /* not EISA configured */
496 if (id == GDT3_ID) /* GDT3000 */
501 #endif /* CONFIG_EISA */
504 static int __init gdth_search_isa(ulong32 bios_adr)
509 TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
510 if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
513 if (id == GDT2_ID) /* GDT2000 */
518 #endif /* CONFIG_ISA */
521 static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
522 ushort vendor, ushort dev);
524 static int __init gdth_search_pci(gdth_pci_str *pcistr)
528 TRACE(("gdth_search_pci()\n"));
531 for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
532 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
533 for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
534 device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
535 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
536 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
537 PCI_DEVICE_ID_VORTEX_GDTNEWRX);
538 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
539 PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
540 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
541 PCI_DEVICE_ID_INTEL_SRC);
542 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
543 PCI_DEVICE_ID_INTEL_SRC_XSCALE);
547 /* Vortex only makes RAID controllers.
548 * We do not really want to specify all 550 ids here, so wildcard match.
550 static struct pci_device_id gdthtable[] __maybe_unused = {
551 {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
552 {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
553 {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
556 MODULE_DEVICE_TABLE(pci,gdthtable);
558 static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
559 ushort vendor, ushort device)
561 ulong base0, base1, base2;
562 struct pci_dev *pdev;
564 TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
565 *cnt, vendor, device));
568 while ((pdev = pci_find_device(vendor, device, pdev))
570 if (pci_enable_device(pdev))
574 /* GDT PCI controller found, resources are already in pdev */
575 pcistr[*cnt].pdev = pdev;
576 pcistr[*cnt].irq = pdev->irq;
577 base0 = pci_resource_flags(pdev, 0);
578 base1 = pci_resource_flags(pdev, 1);
579 base2 = pci_resource_flags(pdev, 2);
580 if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
581 device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
582 if (!(base0 & IORESOURCE_MEM))
584 pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
585 } else { /* GDT6110, GDT6120, .. */
586 if (!(base0 & IORESOURCE_MEM) ||
587 !(base2 & IORESOURCE_MEM) ||
588 !(base1 & IORESOURCE_IO))
590 pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
591 pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
592 pcistr[*cnt].io = pci_resource_start(pdev, 1);
594 TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
595 pcistr[*cnt].pdev->bus->number,
596 PCI_SLOT(pcistr[*cnt].pdev->devfn),
597 pcistr[*cnt].irq, pcistr[*cnt].dpmem));
602 static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
607 TRACE(("gdth_sort_pci() cnt %d\n",cnt));
613 for (i = 0; i < cnt-1; ++i) {
615 if ((pcistr[i].pdev->bus->number > pcistr[i+1].pdev->bus->number) ||
616 (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
617 PCI_SLOT(pcistr[i].pdev->devfn) >
618 PCI_SLOT(pcistr[i+1].pdev->devfn))) {
620 pcistr[i] = pcistr[i+1];
625 if ((pcistr[i].pdev->bus->number < pcistr[i+1].pdev->bus->number) ||
626 (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
627 PCI_SLOT(pcistr[i].pdev->devfn) <
628 PCI_SLOT(pcistr[i+1].pdev->devfn))) {
630 pcistr[i] = pcistr[i+1];
638 #endif /* CONFIG_PCI */
641 static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
644 unchar prot_ver,eisacf,i,irq_found;
646 TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
648 /* disable board interrupts, deinitialize services */
649 outb(0xff,eisa_adr+EDOORREG);
650 outb(0x00,eisa_adr+EDENABREG);
651 outb(0x00,eisa_adr+EINTENABREG);
653 outb(0xff,eisa_adr+LDOORREG);
654 retries = INIT_RETRIES;
656 while (inb(eisa_adr+EDOORREG) != 0xff) {
657 if (--retries == 0) {
658 printk("GDT-EISA: Initialization error (DEINIT failed)\n");
662 TRACE2(("wait for DEINIT: retries=%d\n",retries));
664 prot_ver = inb(eisa_adr+MAILBOXREG);
665 outb(0xff,eisa_adr+EDOORREG);
666 if (prot_ver != PROTOCOL_VERSION) {
667 printk("GDT-EISA: Illegal protocol version\n");
671 ha->brd_phys = (ulong32)eisa_adr >> 12;
673 outl(0,eisa_adr+MAILBOXREG);
674 outl(0,eisa_adr+MAILBOXREG+4);
675 outl(0,eisa_adr+MAILBOXREG+8);
676 outl(0,eisa_adr+MAILBOXREG+12);
679 if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
680 ha->oem_id = OEM_ID_ICP;
683 outl(1,eisa_adr+MAILBOXREG+8);
684 outb(0xfe,eisa_adr+LDOORREG);
685 retries = INIT_RETRIES;
687 while (inb(eisa_adr+EDOORREG) != 0xfe) {
688 if (--retries == 0) {
689 printk("GDT-EISA: Initialization error (get IRQ failed)\n");
694 ha->irq = inb(eisa_adr+MAILBOXREG);
695 outb(0xff,eisa_adr+EDOORREG);
696 TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
697 /* check the result */
699 TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
700 for (i = 0, irq_found = FALSE;
701 i < MAXHA && irq[i] != 0xff; ++i) {
702 if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
710 printk("GDT-EISA: Can not detect controller IRQ,\n");
711 printk("Use IRQ setting from command line (IRQ = %d)\n",
714 printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
715 printk("the controller BIOS or use command line parameters\n");
720 eisacf = inb(eisa_adr+EISAREG) & 7;
721 if (eisacf > 4) /* level triggered */
723 ha->irq = gdth_irq_tab[eisacf];
724 ha->oem_id = OEM_ID_ICP;
729 ha->dma64_support = 0;
732 #endif /* CONFIG_EISA */
735 static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
737 register gdt2_dpram_str __iomem *dp2_ptr;
739 unchar irq_drq,prot_ver;
742 TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
744 ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
745 if (ha->brd == NULL) {
746 printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
750 writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
751 /* reset interface area */
752 memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
753 if (readl(&dp2_ptr->u) != 0) {
754 printk("GDT-ISA: Initialization error (DPMEM write error)\n");
759 /* disable board interrupts, read DRQ and IRQ */
760 writeb(0xff, &dp2_ptr->io.irqdel);
761 writeb(0x00, &dp2_ptr->io.irqen);
762 writeb(0x00, &dp2_ptr->u.ic.S_Status);
763 writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
765 irq_drq = readb(&dp2_ptr->io.rq);
766 for (i=0; i<3; ++i) {
767 if ((irq_drq & 1)==0)
771 ha->drq = gdth_drq_tab[i];
773 irq_drq = readb(&dp2_ptr->io.rq) >> 3;
774 for (i=1; i<5; ++i) {
775 if ((irq_drq & 1)==0)
779 ha->irq = gdth_irq_tab[i];
781 /* deinitialize services */
782 writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
783 writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
784 writeb(0, &dp2_ptr->io.event);
785 retries = INIT_RETRIES;
787 while (readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
788 if (--retries == 0) {
789 printk("GDT-ISA: Initialization error (DEINIT failed)\n");
795 prot_ver = (unchar)readl(&dp2_ptr->u.ic.S_Info[0]);
796 writeb(0, &dp2_ptr->u.ic.Status);
797 writeb(0xff, &dp2_ptr->io.irqdel);
798 if (prot_ver != PROTOCOL_VERSION) {
799 printk("GDT-ISA: Illegal protocol version\n");
804 ha->oem_id = OEM_ID_ICP;
806 ha->ic_all_size = sizeof(dp2_ptr->u);
808 ha->brd_phys = bios_adr >> 4;
810 /* special request to controller BIOS */
811 writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
812 writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
813 writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
814 writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
815 writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
816 writeb(0, &dp2_ptr->io.event);
817 retries = INIT_RETRIES;
819 while (readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
820 if (--retries == 0) {
821 printk("GDT-ISA: Initialization error\n");
827 writeb(0, &dp2_ptr->u.ic.Status);
828 writeb(0xff, &dp2_ptr->io.irqdel);
830 ha->dma64_support = 0;
833 #endif /* CONFIG_ISA */
836 static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
838 register gdt6_dpram_str __iomem *dp6_ptr;
839 register gdt6c_dpram_str __iomem *dp6c_ptr;
840 register gdt6m_dpram_str __iomem *dp6m_ptr;
844 int i, found = FALSE;
846 TRACE(("gdth_init_pci()\n"));
848 if (pcistr->pdev->vendor == PCI_VENDOR_ID_INTEL)
849 ha->oem_id = OEM_ID_INTEL;
851 ha->oem_id = OEM_ID_ICP;
852 ha->brd_phys = (pcistr->pdev->bus->number << 8) | (pcistr->pdev->devfn & 0xf8);
853 ha->stype = (ulong32)pcistr->pdev->device;
854 ha->irq = pcistr->irq;
855 ha->pdev = pcistr->pdev;
857 if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
858 TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
859 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
860 if (ha->brd == NULL) {
861 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
864 /* check and reset interface area */
866 writel(DPMEM_MAGIC, &dp6_ptr->u);
867 if (readl(&dp6_ptr->u) != DPMEM_MAGIC) {
868 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
871 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
873 ha->brd = ioremap(i, sizeof(ushort));
874 if (ha->brd == NULL) {
875 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
878 if (readw(ha->brd) != 0xffff) {
879 TRACE2(("init_pci_old() address 0x%x busy\n", i));
883 pci_write_config_dword(pcistr->pdev,
884 PCI_BASE_ADDRESS_0, i);
885 ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
886 if (ha->brd == NULL) {
887 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
891 writel(DPMEM_MAGIC, &dp6_ptr->u);
892 if (readl(&dp6_ptr->u) == DPMEM_MAGIC) {
893 printk("GDT-PCI: Use free address at 0x%x\n", i);
899 printk("GDT-PCI: No free address found!\n");
904 memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
905 if (readl(&dp6_ptr->u) != 0) {
906 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
911 /* disable board interrupts, deinit services */
912 writeb(0xff, &dp6_ptr->io.irqdel);
913 writeb(0x00, &dp6_ptr->io.irqen);
914 writeb(0x00, &dp6_ptr->u.ic.S_Status);
915 writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
917 writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
918 writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
919 writeb(0, &dp6_ptr->io.event);
920 retries = INIT_RETRIES;
922 while (readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
923 if (--retries == 0) {
924 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
930 prot_ver = (unchar)readl(&dp6_ptr->u.ic.S_Info[0]);
931 writeb(0, &dp6_ptr->u.ic.S_Status);
932 writeb(0xff, &dp6_ptr->io.irqdel);
933 if (prot_ver != PROTOCOL_VERSION) {
934 printk("GDT-PCI: Illegal protocol version\n");
940 ha->ic_all_size = sizeof(dp6_ptr->u);
942 /* special command to controller BIOS */
943 writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
944 writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
945 writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
946 writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
947 writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
948 writeb(0, &dp6_ptr->io.event);
949 retries = INIT_RETRIES;
951 while (readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
952 if (--retries == 0) {
953 printk("GDT-PCI: Initialization error\n");
959 writeb(0, &dp6_ptr->u.ic.S_Status);
960 writeb(0xff, &dp6_ptr->io.irqdel);
962 ha->dma64_support = 0;
964 } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
965 ha->plx = (gdt6c_plx_regs *)pcistr->io;
966 TRACE2(("init_pci_new() dpmem %lx irq %d\n",
967 pcistr->dpmem,ha->irq));
968 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
969 if (ha->brd == NULL) {
970 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
974 /* check and reset interface area */
976 writel(DPMEM_MAGIC, &dp6c_ptr->u);
977 if (readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
978 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
981 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
983 ha->brd = ioremap(i, sizeof(ushort));
984 if (ha->brd == NULL) {
985 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
988 if (readw(ha->brd) != 0xffff) {
989 TRACE2(("init_pci_plx() address 0x%x busy\n", i));
993 pci_write_config_dword(pcistr->pdev,
994 PCI_BASE_ADDRESS_2, i);
995 ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
996 if (ha->brd == NULL) {
997 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1001 writel(DPMEM_MAGIC, &dp6c_ptr->u);
1002 if (readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
1003 printk("GDT-PCI: Use free address at 0x%x\n", i);
1009 printk("GDT-PCI: No free address found!\n");
1014 memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
1015 if (readl(&dp6c_ptr->u) != 0) {
1016 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
1021 /* disable board interrupts, deinit services */
1022 outb(0x00,PTR2USHORT(&ha->plx->control1));
1023 outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
1025 writeb(0x00, &dp6c_ptr->u.ic.S_Status);
1026 writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
1028 writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
1029 writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
1031 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1033 retries = INIT_RETRIES;
1035 while (readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
1036 if (--retries == 0) {
1037 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1043 prot_ver = (unchar)readl(&dp6c_ptr->u.ic.S_Info[0]);
1044 writeb(0, &dp6c_ptr->u.ic.Status);
1045 if (prot_ver != PROTOCOL_VERSION) {
1046 printk("GDT-PCI: Illegal protocol version\n");
1051 ha->type = GDT_PCINEW;
1052 ha->ic_all_size = sizeof(dp6c_ptr->u);
1054 /* special command to controller BIOS */
1055 writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
1056 writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
1057 writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
1058 writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
1059 writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
1061 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1063 retries = INIT_RETRIES;
1065 while (readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
1066 if (--retries == 0) {
1067 printk("GDT-PCI: Initialization error\n");
1073 writeb(0, &dp6c_ptr->u.ic.S_Status);
1075 ha->dma64_support = 0;
1078 TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
1079 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
1080 if (ha->brd == NULL) {
1081 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1085 /* manipulate config. space to enable DPMEM, start RP controller */
1086 pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
1088 pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
1089 if (pci_resource_start(pcistr->pdev, 8) == 1UL)
1090 pci_resource_start(pcistr->pdev, 8) = 0UL;
1092 pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
1094 pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
1095 pci_resource_start(pcistr->pdev, 8));
1099 /* Ensure that it is safe to access the non HW portions of DPMEM.
1100 * Aditional check needed for Xscale based RAID controllers */
1101 while( ((int)readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
1104 /* check and reset interface area */
1105 writel(DPMEM_MAGIC, &dp6m_ptr->u);
1106 if (readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
1107 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1110 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1112 ha->brd = ioremap(i, sizeof(ushort));
1113 if (ha->brd == NULL) {
1114 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1117 if (readw(ha->brd) != 0xffff) {
1118 TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
1122 pci_write_config_dword(pcistr->pdev,
1123 PCI_BASE_ADDRESS_0, i);
1124 ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
1125 if (ha->brd == NULL) {
1126 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1130 writel(DPMEM_MAGIC, &dp6m_ptr->u);
1131 if (readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
1132 printk("GDT-PCI: Use free address at 0x%x\n", i);
1138 printk("GDT-PCI: No free address found!\n");
1143 memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
1145 /* disable board interrupts, deinit services */
1146 writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
1147 &dp6m_ptr->i960r.edoor_en_reg);
1148 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1149 writeb(0x00, &dp6m_ptr->u.ic.S_Status);
1150 writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
1152 writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
1153 writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
1154 writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1155 retries = INIT_RETRIES;
1157 while (readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
1158 if (--retries == 0) {
1159 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1165 prot_ver = (unchar)readl(&dp6m_ptr->u.ic.S_Info[0]);
1166 writeb(0, &dp6m_ptr->u.ic.S_Status);
1167 if (prot_ver != PROTOCOL_VERSION) {
1168 printk("GDT-PCI: Illegal protocol version\n");
1173 ha->type = GDT_PCIMPR;
1174 ha->ic_all_size = sizeof(dp6m_ptr->u);
1176 /* special command to controller BIOS */
1177 writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
1178 writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
1179 writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
1180 writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
1181 writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
1182 writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1183 retries = INIT_RETRIES;
1185 while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
1186 if (--retries == 0) {
1187 printk("GDT-PCI: Initialization error\n");
1193 writeb(0, &dp6m_ptr->u.ic.S_Status);
1195 /* read FW version to detect 64-bit DMA support */
1196 writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
1197 writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1198 retries = INIT_RETRIES;
1200 while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
1201 if (--retries == 0) {
1202 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1208 prot_ver = (unchar)(readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
1209 writeb(0, &dp6m_ptr->u.ic.S_Status);
1210 if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
1211 ha->dma64_support = 0;
1213 ha->dma64_support = 1;
1218 #endif /* CONFIG_PCI */
1220 /* controller protocol functions */
1222 static void __init gdth_enable_int(int hanum)
1226 gdt2_dpram_str __iomem *dp2_ptr;
1227 gdt6_dpram_str __iomem *dp6_ptr;
1228 gdt6m_dpram_str __iomem *dp6m_ptr;
1230 TRACE(("gdth_enable_int() hanum %d\n",hanum));
1231 ha = HADATA(gdth_ctr_tab[hanum]);
1232 spin_lock_irqsave(&ha->smp_lock, flags);
1234 if (ha->type == GDT_EISA) {
1235 outb(0xff, ha->bmic + EDOORREG);
1236 outb(0xff, ha->bmic + EDENABREG);
1237 outb(0x01, ha->bmic + EINTENABREG);
1238 } else if (ha->type == GDT_ISA) {
1240 writeb(1, &dp2_ptr->io.irqdel);
1241 writeb(0, &dp2_ptr->u.ic.Cmd_Index);
1242 writeb(1, &dp2_ptr->io.irqen);
1243 } else if (ha->type == GDT_PCI) {
1245 writeb(1, &dp6_ptr->io.irqdel);
1246 writeb(0, &dp6_ptr->u.ic.Cmd_Index);
1247 writeb(1, &dp6_ptr->io.irqen);
1248 } else if (ha->type == GDT_PCINEW) {
1249 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
1250 outb(0x03, PTR2USHORT(&ha->plx->control1));
1251 } else if (ha->type == GDT_PCIMPR) {
1253 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1254 writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
1255 &dp6m_ptr->i960r.edoor_en_reg);
1257 spin_unlock_irqrestore(&ha->smp_lock, flags);
1261 static int gdth_get_status(unchar *pIStatus,int irq)
1263 register gdth_ha_str *ha;
1266 TRACE(("gdth_get_status() irq %d ctr_count %d\n",
1267 irq,gdth_ctr_count));
1270 for (i=0; i<gdth_ctr_count; ++i) {
1271 ha = HADATA(gdth_ctr_tab[i]);
1272 if (ha->irq != (unchar)irq) /* check IRQ */
1274 if (ha->type == GDT_EISA)
1275 *pIStatus = inb((ushort)ha->bmic + EDOORREG);
1276 else if (ha->type == GDT_ISA)
1278 readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1279 else if (ha->type == GDT_PCI)
1281 readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1282 else if (ha->type == GDT_PCINEW)
1283 *pIStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
1284 else if (ha->type == GDT_PCIMPR)
1286 readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
1289 return i; /* board found */
1295 static int gdth_test_busy(int hanum)
1297 register gdth_ha_str *ha;
1298 register int gdtsema0 = 0;
1300 TRACE(("gdth_test_busy() hanum %d\n",hanum));
1302 ha = HADATA(gdth_ctr_tab[hanum]);
1303 if (ha->type == GDT_EISA)
1304 gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
1305 else if (ha->type == GDT_ISA)
1306 gdtsema0 = (int)readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1307 else if (ha->type == GDT_PCI)
1308 gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1309 else if (ha->type == GDT_PCINEW)
1310 gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
1311 else if (ha->type == GDT_PCIMPR)
1313 (int)readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1315 return (gdtsema0 & 1);
1319 static int gdth_get_cmd_index(int hanum)
1321 register gdth_ha_str *ha;
1324 TRACE(("gdth_get_cmd_index() hanum %d\n",hanum));
1326 ha = HADATA(gdth_ctr_tab[hanum]);
1327 for (i=0; i<GDTH_MAXCMDS; ++i) {
1328 if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
1329 ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
1330 ha->cmd_tab[i].service = ha->pccb->Service;
1331 ha->pccb->CommandIndex = (ulong32)i+2;
1339 static void gdth_set_sema0(int hanum)
1341 register gdth_ha_str *ha;
1343 TRACE(("gdth_set_sema0() hanum %d\n",hanum));
1345 ha = HADATA(gdth_ctr_tab[hanum]);
1346 if (ha->type == GDT_EISA) {
1347 outb(1, ha->bmic + SEMA0REG);
1348 } else if (ha->type == GDT_ISA) {
1349 writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1350 } else if (ha->type == GDT_PCI) {
1351 writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1352 } else if (ha->type == GDT_PCINEW) {
1353 outb(1, PTR2USHORT(&ha->plx->sema0_reg));
1354 } else if (ha->type == GDT_PCIMPR) {
1355 writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1360 static void gdth_copy_command(int hanum)
1362 register gdth_ha_str *ha;
1363 register gdth_cmd_str *cmd_ptr;
1364 register gdt6m_dpram_str __iomem *dp6m_ptr;
1365 register gdt6c_dpram_str __iomem *dp6c_ptr;
1366 gdt6_dpram_str __iomem *dp6_ptr;
1367 gdt2_dpram_str __iomem *dp2_ptr;
1368 ushort cp_count,dp_offset,cmd_no;
1370 TRACE(("gdth_copy_command() hanum %d\n",hanum));
1372 ha = HADATA(gdth_ctr_tab[hanum]);
1373 cp_count = ha->cmd_len;
1374 dp_offset= ha->cmd_offs_dpmem;
1375 cmd_no = ha->cmd_cnt;
1379 if (ha->type == GDT_EISA)
1380 return; /* no DPMEM, no copy */
1382 /* set cpcount dword aligned */
1384 cp_count += (4 - (cp_count & 3));
1386 ha->cmd_offs_dpmem += cp_count;
1388 /* set offset and service, copy command to DPMEM */
1389 if (ha->type == GDT_ISA) {
1391 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1392 &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
1393 writew((ushort)cmd_ptr->Service,
1394 &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
1395 memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1396 } else if (ha->type == GDT_PCI) {
1398 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1399 &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
1400 writew((ushort)cmd_ptr->Service,
1401 &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
1402 memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1403 } else if (ha->type == GDT_PCINEW) {
1405 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1406 &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
1407 writew((ushort)cmd_ptr->Service,
1408 &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
1409 memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1410 } else if (ha->type == GDT_PCIMPR) {
1412 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1413 &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
1414 writew((ushort)cmd_ptr->Service,
1415 &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
1416 memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1421 static void gdth_release_event(int hanum)
1423 register gdth_ha_str *ha;
1425 TRACE(("gdth_release_event() hanum %d\n",hanum));
1426 ha = HADATA(gdth_ctr_tab[hanum]);
1428 #ifdef GDTH_STATISTICS
1431 for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
1432 if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
1435 if (max_index < i) {
1437 TRACE3(("GDT: max_index = %d\n",(ushort)i));
1442 if (ha->pccb->OpCode == GDT_INIT)
1443 ha->pccb->Service |= 0x80;
1445 if (ha->type == GDT_EISA) {
1446 if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
1447 outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
1448 outb(ha->pccb->Service, ha->bmic + LDOORREG);
1449 } else if (ha->type == GDT_ISA) {
1450 writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
1451 } else if (ha->type == GDT_PCI) {
1452 writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
1453 } else if (ha->type == GDT_PCINEW) {
1454 outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
1455 } else if (ha->type == GDT_PCIMPR) {
1456 writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
1461 static int gdth_wait(int hanum,int index,ulong32 time)
1464 int answer_found = FALSE;
1466 TRACE(("gdth_wait() hanum %d index %d time %d\n",hanum,index,time));
1468 ha = HADATA(gdth_ctr_tab[hanum]);
1470 return 1; /* no wait required */
1472 gdth_from_wait = TRUE;
1474 gdth_interrupt((int)ha->irq,ha);
1475 if (wait_hanum==hanum && wait_index==index) {
1476 answer_found = TRUE;
1481 gdth_from_wait = FALSE;
1483 while (gdth_test_busy(hanum))
1486 return (answer_found);
1490 static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
1491 ulong64 p2,ulong64 p3)
1493 register gdth_ha_str *ha;
1494 register gdth_cmd_str *cmd_ptr;
1497 TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
1499 ha = HADATA(gdth_ctr_tab[hanum]);
1501 memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
1504 for (retries = INIT_RETRIES;;) {
1505 cmd_ptr->Service = service;
1506 cmd_ptr->RequestBuffer = INTERNAL_CMND;
1507 if (!(index=gdth_get_cmd_index(hanum))) {
1508 TRACE(("GDT: No free command index found\n"));
1511 gdth_set_sema0(hanum);
1512 cmd_ptr->OpCode = opcode;
1513 cmd_ptr->BoardNode = LOCALBOARD;
1514 if (service == CACHESERVICE) {
1515 if (opcode == GDT_IOCTL) {
1516 cmd_ptr->u.ioctl.subfunc = p1;
1517 cmd_ptr->u.ioctl.channel = (ulong32)p2;
1518 cmd_ptr->u.ioctl.param_size = (ushort)p3;
1519 cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
1521 if (ha->cache_feat & GDT_64BIT) {
1522 cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
1523 cmd_ptr->u.cache64.BlockNo = p2;
1525 cmd_ptr->u.cache.DeviceNo = (ushort)p1;
1526 cmd_ptr->u.cache.BlockNo = (ulong32)p2;
1529 } else if (service == SCSIRAWSERVICE) {
1530 if (ha->raw_feat & GDT_64BIT) {
1531 cmd_ptr->u.raw64.direction = p1;
1532 cmd_ptr->u.raw64.bus = (unchar)p2;
1533 cmd_ptr->u.raw64.target = (unchar)p3;
1534 cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
1536 cmd_ptr->u.raw.direction = p1;
1537 cmd_ptr->u.raw.bus = (unchar)p2;
1538 cmd_ptr->u.raw.target = (unchar)p3;
1539 cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
1541 } else if (service == SCREENSERVICE) {
1542 if (opcode == GDT_REALTIME) {
1543 *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
1544 *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
1545 *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
1548 ha->cmd_len = sizeof(gdth_cmd_str);
1549 ha->cmd_offs_dpmem = 0;
1551 gdth_copy_command(hanum);
1552 gdth_release_event(hanum);
1554 if (!gdth_wait(hanum,index,INIT_TIMEOUT)) {
1555 printk("GDT: Initialization error (timeout service %d)\n",service);
1558 if (ha->status != S_BSY || --retries == 0)
1563 return (ha->status != S_OK ? 0:1);
1567 /* search for devices */
1569 static int __init gdth_search_drives(int hanum)
1571 register gdth_ha_str *ha;
1574 ulong32 bus_no, drv_cnt, drv_no, j;
1575 gdth_getch_str *chn;
1576 gdth_drlist_str *drl;
1577 gdth_iochan_str *ioc;
1578 gdth_raw_iochan_str *iocr;
1579 gdth_arcdl_str *alst;
1580 gdth_alist_str *alst2;
1581 gdth_oem_str_ioctl *oemstr;
1583 gdth_perf_modes *pmod;
1591 TRACE(("gdth_search_drives() hanum %d\n",hanum));
1592 ha = HADATA(gdth_ctr_tab[hanum]);
1595 /* initialize controller services, at first: screen service */
1596 ha->screen_feat = 0;
1598 ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_X_INIT_SCR,0,0,0);
1600 ha->screen_feat = GDT_64BIT;
1602 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1603 ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_INIT,0,0,0);
1605 printk("GDT-HA %d: Initialization error screen service (code %d)\n",
1609 TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
1612 /* read realtime clock info, send to controller */
1613 /* 1. wait for the falling edge of update flag */
1614 spin_lock_irqsave(&rtc_lock, flags);
1615 for (j = 0; j < 1000000; ++j)
1616 if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
1618 for (j = 0; j < 1000000; ++j)
1619 if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
1623 for (j = 0; j < 12; ++j)
1624 rtc[j] = CMOS_READ(j);
1625 } while (rtc[0] != CMOS_READ(0));
1626 spin_unlock_irqrestore(&rtc_lock, flags);
1627 TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
1628 *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
1629 /* 3. send to controller firmware */
1630 gdth_internal_cmd(hanum,SCREENSERVICE,GDT_REALTIME, *(ulong32 *)&rtc[0],
1631 *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
1634 /* unfreeze all IOs */
1635 gdth_internal_cmd(hanum,CACHESERVICE,GDT_UNFREEZE_IO,0,0,0);
1637 /* initialize cache service */
1640 ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INIT_HOST,LINUX_OS,0,0);
1642 ha->cache_feat = GDT_64BIT;
1644 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1645 ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_INIT,LINUX_OS,0,0);
1647 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
1651 TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
1652 cdev_cnt = (ushort)ha->info;
1653 ha->fw_vers = ha->service;
1656 if (ha->type == GDT_PCIMPR) {
1657 /* set perf. modes */
1658 pmod = (gdth_perf_modes *)ha->pscratch;
1660 pmod->st_mode = 1; /* enable one status buffer */
1661 *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
1662 pmod->st_buff_indx1 = COALINDEX;
1663 pmod->st_buff_addr2 = 0;
1664 pmod->st_buff_u_addr2 = 0;
1665 pmod->st_buff_indx2 = 0;
1666 pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
1667 pmod->cmd_mode = 0; // disable all cmd buffers
1668 pmod->cmd_buff_addr1 = 0;
1669 pmod->cmd_buff_u_addr1 = 0;
1670 pmod->cmd_buff_indx1 = 0;
1671 pmod->cmd_buff_addr2 = 0;
1672 pmod->cmd_buff_u_addr2 = 0;
1673 pmod->cmd_buff_indx2 = 0;
1674 pmod->cmd_buff_size = 0;
1675 pmod->reserved1 = 0;
1676 pmod->reserved2 = 0;
1677 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,SET_PERF_MODES,
1678 INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
1679 printk("GDT-HA %d: Interrupt coalescing activated\n", hanum);
1684 /* detect number of buses - try new IOCTL */
1685 iocr = (gdth_raw_iochan_str *)ha->pscratch;
1686 iocr->hdr.version = 0xffffffff;
1687 iocr->hdr.list_entries = MAXBUS;
1688 iocr->hdr.first_chan = 0;
1689 iocr->hdr.last_chan = MAXBUS-1;
1690 iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
1691 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_RAW_DESC,
1692 INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
1693 TRACE2(("IOCHAN_RAW_DESC supported!\n"));
1694 ha->bus_cnt = iocr->hdr.chan_count;
1695 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1696 if (iocr->list[bus_no].proc_id < MAXID)
1697 ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
1699 ha->bus_id[bus_no] = 0xff;
1703 chn = (gdth_getch_str *)ha->pscratch;
1704 for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
1705 chn->channel_no = bus_no;
1706 if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
1707 SCSI_CHAN_CNT | L_CTRL_PATTERN,
1708 IO_CHANNEL | INVALID_CHANNEL,
1709 sizeof(gdth_getch_str))) {
1711 printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
1717 if (chn->siop_id < MAXID)
1718 ha->bus_id[bus_no] = chn->siop_id;
1720 ha->bus_id[bus_no] = 0xff;
1722 ha->bus_cnt = (unchar)bus_no;
1724 TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
1726 /* read cache configuration */
1727 if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_INFO,
1728 INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
1729 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
1733 ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
1734 TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
1735 ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
1736 ha->cpar.write_back,ha->cpar.block_size));
1738 /* read board info and features */
1739 ha->more_proc = FALSE;
1740 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_INFO,
1741 INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
1742 memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
1743 sizeof(gdth_binfo_str));
1744 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_FEATURES,
1745 INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
1746 TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
1747 ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
1748 ha->more_proc = TRUE;
1751 TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
1752 strcpy(ha->binfo.type_string, gdth_ctr_name(hanum));
1754 TRACE2(("Controller name: %s\n",ha->binfo.type_string));
1756 /* read more informations */
1757 if (ha->more_proc) {
1758 /* physical drives, channel addresses */
1759 ioc = (gdth_iochan_str *)ha->pscratch;
1760 ioc->hdr.version = 0xffffffff;
1761 ioc->hdr.list_entries = MAXBUS;
1762 ioc->hdr.first_chan = 0;
1763 ioc->hdr.last_chan = MAXBUS-1;
1764 ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
1765 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_DESC,
1766 INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
1767 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1768 ha->raw[bus_no].address = ioc->list[bus_no].address;
1769 ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
1772 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1773 ha->raw[bus_no].address = IO_CHANNEL;
1774 ha->raw[bus_no].local_no = bus_no;
1777 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1778 chn = (gdth_getch_str *)ha->pscratch;
1779 chn->channel_no = ha->raw[bus_no].local_no;
1780 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
1781 SCSI_CHAN_CNT | L_CTRL_PATTERN,
1782 ha->raw[bus_no].address | INVALID_CHANNEL,
1783 sizeof(gdth_getch_str))) {
1784 ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
1785 TRACE2(("Channel %d: %d phys. drives\n",
1786 bus_no,chn->drive_cnt));
1788 if (ha->raw[bus_no].pdev_cnt > 0) {
1789 drl = (gdth_drlist_str *)ha->pscratch;
1790 drl->sc_no = ha->raw[bus_no].local_no;
1791 drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
1792 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
1793 SCSI_DR_LIST | L_CTRL_PATTERN,
1794 ha->raw[bus_no].address | INVALID_CHANNEL,
1795 sizeof(gdth_drlist_str))) {
1796 for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
1797 ha->raw[bus_no].id_list[j] = drl->sc_list[j];
1799 ha->raw[bus_no].pdev_cnt = 0;
1804 /* logical drives */
1805 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_CNT,
1806 INVALID_CHANNEL,sizeof(ulong32))) {
1807 drv_cnt = *(ulong32 *)ha->pscratch;
1808 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_LIST,
1809 INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
1810 for (j = 0; j < drv_cnt; ++j) {
1811 drv_no = ((ulong32 *)ha->pscratch)[j];
1812 if (drv_no < MAX_LDRIVES) {
1813 ha->hdr[drv_no].is_logdrv = TRUE;
1814 TRACE2(("Drive %d is log. drive\n",drv_no));
1818 alst = (gdth_arcdl_str *)ha->pscratch;
1819 alst->entries_avail = MAX_LDRIVES;
1820 alst->first_entry = 0;
1821 alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
1822 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
1823 ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
1824 INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
1825 (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
1826 for (j = 0; j < alst->entries_init; ++j) {
1827 ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
1828 ha->hdr[j].is_master = alst->list[j].is_master;
1829 ha->hdr[j].is_parity = alst->list[j].is_parity;
1830 ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
1831 ha->hdr[j].master_no = alst->list[j].cd_handle;
1833 } else if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
1834 ARRAY_DRV_LIST | LA_CTRL_PATTERN,
1835 0, 35 * sizeof(gdth_alist_str))) {
1836 for (j = 0; j < 35; ++j) {
1837 alst2 = &((gdth_alist_str *)ha->pscratch)[j];
1838 ha->hdr[j].is_arraydrv = alst2->is_arrayd;
1839 ha->hdr[j].is_master = alst2->is_master;
1840 ha->hdr[j].is_parity = alst2->is_parity;
1841 ha->hdr[j].is_hotfix = alst2->is_hotfix;
1842 ha->hdr[j].master_no = alst2->cd_handle;
1848 /* initialize raw service */
1851 ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_X_INIT_RAW,0,0,0);
1853 ha->raw_feat = GDT_64BIT;
1855 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1856 ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_INIT,0,0,0);
1858 printk("GDT-HA %d: Initialization error raw service (code %d)\n",
1862 TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
1864 /* set/get features raw service (scatter/gather) */
1865 if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_SET_FEAT,SCATTER_GATHER,
1867 TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
1868 if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_GET_FEAT,0,0,0)) {
1869 TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
1871 ha->raw_feat |= (ushort)ha->info;
1875 /* set/get features cache service (equal to raw service) */
1876 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_SET_FEAT,0,
1877 SCATTER_GATHER,0)) {
1878 TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
1879 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_GET_FEAT,0,0,0)) {
1880 TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
1882 ha->cache_feat |= (ushort)ha->info;
1886 /* reserve drives for raw service */
1887 if (reserve_mode != 0) {
1888 gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE_ALL,
1889 reserve_mode == 1 ? 1 : 3, 0, 0);
1890 TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
1893 for (i = 0; i < MAX_RES_ARGS; i += 4) {
1894 if (reserve_list[i] == hanum && reserve_list[i+1] < ha->bus_cnt &&
1895 reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
1896 TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
1897 reserve_list[i], reserve_list[i+1],
1898 reserve_list[i+2], reserve_list[i+3]));
1899 if (!gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE,0,
1900 reserve_list[i+1], reserve_list[i+2] |
1901 (reserve_list[i+3] << 8))) {
1902 printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
1908 /* Determine OEM string using IOCTL */
1909 oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
1910 oemstr->params.ctl_version = 0x01;
1911 oemstr->params.buffer_size = sizeof(oemstr->text);
1912 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
1913 CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
1914 sizeof(gdth_oem_str_ioctl))) {
1915 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
1916 printk("GDT-HA %d: Vendor: %s Name: %s\n",
1917 hanum,oemstr->text.oem_company_name,ha->binfo.type_string);
1918 /* Save the Host Drive inquiry data */
1919 strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
1920 sizeof(ha->oem_name));
1922 /* Old method, based on PCI ID */
1923 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
1924 printk("GDT-HA %d: Name: %s\n",
1925 hanum,ha->binfo.type_string);
1926 if (ha->oem_id == OEM_ID_INTEL)
1927 strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
1929 strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
1932 /* scanning for host drives */
1933 for (i = 0; i < cdev_cnt; ++i)
1934 gdth_analyse_hdrive(hanum,i);
1936 TRACE(("gdth_search_drives() OK\n"));
1940 static int gdth_analyse_hdrive(int hanum,ushort hdrive)
1942 register gdth_ha_str *ha;
1944 int drv_hds, drv_secs;
1946 TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n",hanum,hdrive));
1947 if (hdrive >= MAX_HDRIVES)
1949 ha = HADATA(gdth_ctr_tab[hanum]);
1951 if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_INFO,hdrive,0,0))
1953 ha->hdr[hdrive].present = TRUE;
1954 ha->hdr[hdrive].size = ha->info;
1956 /* evaluate mapping (sectors per head, heads per cylinder) */
1957 ha->hdr[hdrive].size &= ~SECS32;
1958 if (ha->info2 == 0) {
1959 gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
1961 drv_hds = ha->info2 & 0xff;
1962 drv_secs = (ha->info2 >> 8) & 0xff;
1963 drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
1965 ha->hdr[hdrive].heads = (unchar)drv_hds;
1966 ha->hdr[hdrive].secs = (unchar)drv_secs;
1968 ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
1970 if (ha->cache_feat & GDT_64BIT) {
1971 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INFO,hdrive,0,0)
1972 && ha->info2 != 0) {
1973 ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
1976 TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
1977 hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
1979 /* get informations about device */
1980 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_DEVTYPE,hdrive,0,0)) {
1981 TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
1983 ha->hdr[hdrive].devtype = (ushort)ha->info;
1987 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_CLUST_INFO,hdrive,0,0)) {
1988 TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
1991 ha->hdr[hdrive].cluster_type = (unchar)ha->info;
1994 /* R/W attributes */
1995 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_RW_ATTRIBS,hdrive,0,0)) {
1996 TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
1998 ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
2005 /* command queueing/sending functions */
2007 static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority)
2009 register gdth_ha_str *ha;
2010 register Scsi_Cmnd *pscp;
2011 register Scsi_Cmnd *nscp;
2015 TRACE(("gdth_putq() priority %d\n",priority));
2016 ha = HADATA(gdth_ctr_tab[hanum]);
2017 spin_lock_irqsave(&ha->smp_lock, flags);
2019 if (!IS_GDTH_INTERNAL_CMD(scp)) {
2020 scp->SCp.this_residual = (int)priority;
2021 b = virt_ctr ? NUMDATA(scp->device->host)->busnum:scp->device->channel;
2022 t = scp->device->id;
2023 if (priority >= DEFAULT_PRI) {
2024 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
2025 (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) {
2026 TRACE2(("gdth_putq(): locked IO ->update_timeout()\n"));
2027 scp->SCp.buffers_residual = gdth_update_timeout(hanum, scp, 0);
2032 if (ha->req_first==NULL) {
2033 ha->req_first = scp; /* queue was empty */
2034 scp->SCp.ptr = NULL;
2035 } else { /* queue not empty */
2036 pscp = ha->req_first;
2037 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2038 /* priority: 0-highest,..,0xff-lowest */
2039 while (nscp && (unchar)nscp->SCp.this_residual <= priority) {
2041 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2043 pscp->SCp.ptr = (char *)scp;
2044 scp->SCp.ptr = (char *)nscp;
2046 spin_unlock_irqrestore(&ha->smp_lock, flags);
2048 #ifdef GDTH_STATISTICS
2050 for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
2052 if (max_rq < flags) {
2054 TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
2059 static void gdth_next(int hanum)
2061 register gdth_ha_str *ha;
2062 register Scsi_Cmnd *pscp;
2063 register Scsi_Cmnd *nscp;
2064 unchar b, t, l, firsttime;
2065 unchar this_cmd, next_cmd;
2069 TRACE(("gdth_next() hanum %d\n",hanum));
2070 ha = HADATA(gdth_ctr_tab[hanum]);
2072 spin_lock_irqsave(&ha->smp_lock, flags);
2074 ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
2075 this_cmd = firsttime = TRUE;
2076 next_cmd = gdth_polling ? FALSE:TRUE;
2079 for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
2080 if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
2081 pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2082 if (!IS_GDTH_INTERNAL_CMD(nscp)) {
2084 NUMDATA(nscp->device->host)->busnum : nscp->device->channel;
2085 t = nscp->device->id;
2086 l = nscp->device->lun;
2087 if (nscp->SCp.this_residual >= DEFAULT_PRI) {
2088 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
2089 (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
2096 if (gdth_test_busy(hanum)) { /* controller busy ? */
2097 TRACE(("gdth_next() controller %d busy !\n",hanum));
2098 if (!gdth_polling) {
2099 spin_unlock_irqrestore(&ha->smp_lock, flags);
2102 while (gdth_test_busy(hanum))
2108 if (!IS_GDTH_INTERNAL_CMD(nscp)) {
2109 if (nscp->SCp.phase == -1) {
2110 nscp->SCp.phase = CACHESERVICE; /* default: cache svc. */
2111 if (nscp->cmnd[0] == TEST_UNIT_READY) {
2112 TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
2114 /* TEST_UNIT_READY -> set scan mode */
2115 if ((ha->scan_mode & 0x0f) == 0) {
2116 if (b == 0 && t == 0 && l == 0) {
2118 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2120 } else if ((ha->scan_mode & 0x0f) == 1) {
2121 if (b == 0 && ((t == 0 && l == 1) ||
2122 (t == 1 && l == 0))) {
2123 nscp->SCp.sent_command = GDT_SCAN_START;
2124 nscp->SCp.phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
2126 ha->scan_mode = 0x12;
2127 TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
2130 ha->scan_mode &= 0x10;
2131 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2133 } else if (ha->scan_mode == 0x12) {
2134 if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
2135 nscp->SCp.phase = SCSIRAWSERVICE;
2136 nscp->SCp.sent_command = GDT_SCAN_END;
2137 ha->scan_mode &= 0x10;
2138 TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
2143 if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
2144 nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
2145 (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
2146 /* always GDT_CLUST_INFO! */
2147 nscp->SCp.sent_command = GDT_CLUST_INFO;
2152 if (nscp->SCp.sent_command != -1) {
2153 if ((nscp->SCp.phase & 0xff) == CACHESERVICE) {
2154 if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2157 } else if ((nscp->SCp.phase & 0xff) == SCSIRAWSERVICE) {
2158 if (!(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
2162 memset((char*)nscp->sense_buffer,0,16);
2163 nscp->sense_buffer[0] = 0x70;
2164 nscp->sense_buffer[2] = NOT_READY;
2165 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2166 if (!nscp->SCp.have_data_in)
2167 nscp->SCp.have_data_in++;
2169 gdth_scsi_done(nscp);
2171 } else if (IS_GDTH_INTERNAL_CMD(nscp)) {
2172 if (!(cmd_index=gdth_special_cmd(hanum,nscp)))
2175 } else if (b != ha->virt_bus) {
2176 if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
2177 !(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
2180 ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
2181 } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
2182 TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
2183 nscp->cmnd[0], b, t, l));
2184 nscp->result = DID_BAD_TARGET << 16;
2185 if (!nscp->SCp.have_data_in)
2186 nscp->SCp.have_data_in++;
2188 gdth_scsi_done(nscp);
2190 switch (nscp->cmnd[0]) {
2191 case TEST_UNIT_READY:
2198 case SERVICE_ACTION_IN:
2199 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2200 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2201 nscp->cmnd[4],nscp->cmnd[5]));
2202 if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
2203 /* return UNIT_ATTENTION */
2204 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2206 ha->hdr[t].media_changed = FALSE;
2207 memset((char*)nscp->sense_buffer,0,16);
2208 nscp->sense_buffer[0] = 0x70;
2209 nscp->sense_buffer[2] = UNIT_ATTENTION;
2210 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2211 if (!nscp->SCp.have_data_in)
2212 nscp->SCp.have_data_in++;
2214 gdth_scsi_done(nscp);
2215 } else if (gdth_internal_cache_cmd(hanum, nscp))
2216 gdth_scsi_done(nscp);
2219 case ALLOW_MEDIUM_REMOVAL:
2220 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2221 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2222 nscp->cmnd[4],nscp->cmnd[5]));
2223 if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
2224 TRACE(("Prevent r. nonremov. drive->do nothing\n"));
2225 nscp->result = DID_OK << 16;
2226 nscp->sense_buffer[0] = 0;
2227 if (!nscp->SCp.have_data_in)
2228 nscp->SCp.have_data_in++;
2230 gdth_scsi_done(nscp);
2232 nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
2233 TRACE(("Prevent/allow r. %d rem. drive %d\n",
2234 nscp->cmnd[4],nscp->cmnd[3]));
2235 if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2242 TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
2243 "RESERVE" : "RELEASE"));
2244 if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2254 if (ha->hdr[t].media_changed) {
2255 /* return UNIT_ATTENTION */
2256 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2258 ha->hdr[t].media_changed = FALSE;
2259 memset((char*)nscp->sense_buffer,0,16);
2260 nscp->sense_buffer[0] = 0x70;
2261 nscp->sense_buffer[2] = UNIT_ATTENTION;
2262 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2263 if (!nscp->SCp.have_data_in)
2264 nscp->SCp.have_data_in++;
2266 gdth_scsi_done(nscp);
2267 } else if (!(cmd_index=gdth_fill_cache_cmd(hanum, nscp, t)))
2272 TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
2273 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2274 nscp->cmnd[4],nscp->cmnd[5]));
2275 printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
2276 hanum, nscp->cmnd[0]);
2277 nscp->result = DID_ABORT << 16;
2278 if (!nscp->SCp.have_data_in)
2279 nscp->SCp.have_data_in++;
2281 gdth_scsi_done(nscp);
2288 if (nscp == ha->req_first)
2289 ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
2291 pscp->SCp.ptr = nscp->SCp.ptr;
2296 if (ha->cmd_cnt > 0) {
2297 gdth_release_event(hanum);
2301 spin_unlock_irqrestore(&ha->smp_lock, flags);
2303 if (gdth_polling && ha->cmd_cnt > 0) {
2304 if (!gdth_wait(hanum,cmd_index,POLL_TIMEOUT))
2305 printk("GDT-HA %d: Command %d timed out !\n",
2310 static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
2311 char *buffer,ushort count)
2315 struct scatterlist *sl;
2319 cpcount = count<=(ushort)scp->request_bufflen ? count:(ushort)scp->request_bufflen;
2320 ha = HADATA(gdth_ctr_tab[hanum]);
2323 sl = (struct scatterlist *)scp->request_buffer;
2324 for (i=0,cpsum=0; i<scp->use_sg; ++i,++sl) {
2325 unsigned long flags;
2326 cpnow = (ushort)sl->length;
2327 TRACE(("copy_internal() now %d sum %d count %d %d\n",
2328 cpnow,cpsum,cpcount,(ushort)scp->bufflen));
2329 if (cpsum+cpnow > cpcount)
2330 cpnow = cpcount - cpsum;
2333 printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
2337 local_irq_save(flags);
2338 address = kmap_atomic(sl->page, KM_BIO_SRC_IRQ) + sl->offset;
2339 memcpy(address,buffer,cpnow);
2340 flush_dcache_page(sl->page);
2341 kunmap_atomic(address, KM_BIO_SRC_IRQ);
2342 local_irq_restore(flags);
2343 if (cpsum == cpcount)
2348 TRACE(("copy_internal() count %d\n",cpcount));
2349 memcpy((char*)scp->request_buffer,buffer,cpcount);
2353 static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp)
2355 register gdth_ha_str *ha;
2358 gdth_rdcap_data rdc;
2360 gdth_modep_data mpd;
2362 ha = HADATA(gdth_ctr_tab[hanum]);
2363 t = scp->device->id;
2364 TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
2367 scp->result = DID_OK << 16;
2368 scp->sense_buffer[0] = 0;
2370 switch (scp->cmnd[0]) {
2371 case TEST_UNIT_READY:
2374 TRACE2(("Test/Verify/Start hdrive %d\n",t));
2378 TRACE2(("Inquiry hdrive %d devtype %d\n",
2379 t,ha->hdr[t].devtype));
2380 inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
2381 /* you can here set all disks to removable, if you want to do
2382 a flush using the ALLOW_MEDIUM_REMOVAL command */
2383 inq.modif_rmb = 0x00;
2384 if ((ha->hdr[t].devtype & 1) ||
2385 (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
2386 inq.modif_rmb = 0x80;
2390 strcpy(inq.vendor,ha->oem_name);
2391 sprintf(inq.product,"Host Drive #%02d",t);
2392 strcpy(inq.revision," ");
2393 gdth_copy_internal_data(hanum,scp,(char*)&inq,sizeof(gdth_inq_data));
2397 TRACE2(("Request sense hdrive %d\n",t));
2398 sd.errorcode = 0x70;
2403 gdth_copy_internal_data(hanum,scp,(char*)&sd,sizeof(gdth_sense_data));
2407 TRACE2(("Mode sense hdrive %d\n",t));
2408 memset((char*)&mpd,0,sizeof(gdth_modep_data));
2409 mpd.hd.data_length = sizeof(gdth_modep_data);
2410 mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
2411 mpd.hd.bd_length = sizeof(mpd.bd);
2412 mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
2413 mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
2414 mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
2415 gdth_copy_internal_data(hanum,scp,(char*)&mpd,sizeof(gdth_modep_data));
2419 TRACE2(("Read capacity hdrive %d\n",t));
2420 if (ha->hdr[t].size > (ulong64)0xffffffff)
2421 rdc.last_block_no = 0xffffffff;
2423 rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
2424 rdc.block_length = cpu_to_be32(SECTOR_SIZE);
2425 gdth_copy_internal_data(hanum,scp,(char*)&rdc,sizeof(gdth_rdcap_data));
2428 case SERVICE_ACTION_IN:
2429 if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
2430 (ha->cache_feat & GDT_64BIT)) {
2431 gdth_rdcap16_data rdc16;
2433 TRACE2(("Read capacity (16) hdrive %d\n",t));
2434 rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
2435 rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
2436 gdth_copy_internal_data(hanum,scp,(char*)&rdc16,sizeof(gdth_rdcap16_data));
2438 scp->result = DID_ABORT << 16;
2443 TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
2447 if (!scp->SCp.have_data_in)
2448 scp->SCp.have_data_in++;
2455 static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive)
2457 register gdth_ha_str *ha;
2458 register gdth_cmd_str *cmdp;
2459 struct scatterlist *sl;
2460 ulong32 cnt, blockcnt;
2461 ulong64 no, blockno;
2462 dma_addr_t phys_addr;
2463 int i, cmd_index, read_write, sgcnt, mode64;
2467 ha = HADATA(gdth_ctr_tab[hanum]);
2469 TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
2470 scp->cmnd[0],scp->cmd_len,hdrive));
2472 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2475 mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
2476 /* test for READ_16, WRITE_16 if !mode64 ? ---
2477 not required, should not occur due to error return on
2480 cmdp->Service = CACHESERVICE;
2481 cmdp->RequestBuffer = scp;
2482 /* search free command index */
2483 if (!(cmd_index=gdth_get_cmd_index(hanum))) {
2484 TRACE(("GDT: No free command index found\n"));
2487 /* if it's the first command, set command semaphore */
2488 if (ha->cmd_cnt == 0)
2489 gdth_set_sema0(hanum);
2493 if (scp->SCp.sent_command != -1)
2494 cmdp->OpCode = scp->SCp.sent_command; /* special cache cmd. */
2495 else if (scp->cmnd[0] == RESERVE)
2496 cmdp->OpCode = GDT_RESERVE_DRV;
2497 else if (scp->cmnd[0] == RELEASE)
2498 cmdp->OpCode = GDT_RELEASE_DRV;
2499 else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
2500 if (scp->cmnd[4] & 1) /* prevent ? */
2501 cmdp->OpCode = GDT_MOUNT;
2502 else if (scp->cmnd[3] & 1) /* removable drive ? */
2503 cmdp->OpCode = GDT_UNMOUNT;
2505 cmdp->OpCode = GDT_FLUSH;
2506 } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
2507 scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
2510 if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
2511 (ha->cache_feat & GDT_WR_THROUGH)))
2512 cmdp->OpCode = GDT_WRITE_THR;
2514 cmdp->OpCode = GDT_WRITE;
2517 cmdp->OpCode = GDT_READ;
2520 cmdp->BoardNode = LOCALBOARD;
2522 cmdp->u.cache64.DeviceNo = hdrive;
2523 cmdp->u.cache64.BlockNo = 1;
2524 cmdp->u.cache64.sg_canz = 0;
2526 cmdp->u.cache.DeviceNo = hdrive;
2527 cmdp->u.cache.BlockNo = 1;
2528 cmdp->u.cache.sg_canz = 0;
2532 if (scp->cmd_len == 16) {
2533 memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
2534 blockno = be64_to_cpu(no);
2535 memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
2536 blockcnt = be32_to_cpu(cnt);
2537 } else if (scp->cmd_len == 10) {
2538 memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
2539 blockno = be32_to_cpu(no);
2540 memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
2541 blockcnt = be16_to_cpu(cnt);
2543 memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
2544 blockno = be32_to_cpu(no) & 0x001fffffUL;
2545 blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
2548 cmdp->u.cache64.BlockNo = blockno;
2549 cmdp->u.cache64.BlockCnt = blockcnt;
2551 cmdp->u.cache.BlockNo = (ulong32)blockno;
2552 cmdp->u.cache.BlockCnt = blockcnt;
2556 sl = (struct scatterlist *)scp->request_buffer;
2557 sgcnt = scp->use_sg;
2558 scp->SCp.Status = GDTH_MAP_SG;
2559 scp->SCp.Message = (read_write == 1 ?
2560 PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
2561 sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
2563 cmdp->u.cache64.DestAddr= (ulong64)-1;
2564 cmdp->u.cache64.sg_canz = sgcnt;
2565 for (i=0; i<sgcnt; ++i,++sl) {
2566 cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
2567 #ifdef GDTH_DMA_STATISTICS
2568 if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
2573 cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
2576 cmdp->u.cache.DestAddr= 0xffffffff;
2577 cmdp->u.cache.sg_canz = sgcnt;
2578 for (i=0; i<sgcnt; ++i,++sl) {
2579 cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
2580 #ifdef GDTH_DMA_STATISTICS
2583 cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
2587 #ifdef GDTH_STATISTICS
2588 if (max_sg < (ulong32)sgcnt) {
2589 max_sg = (ulong32)sgcnt;
2590 TRACE3(("GDT: max_sg = %d\n",max_sg));
2594 } else if (scp->request_bufflen) {
2595 scp->SCp.Status = GDTH_MAP_SINGLE;
2596 scp->SCp.Message = (read_write == 1 ?
2597 PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
2598 page = virt_to_page(scp->request_buffer);
2599 offset = (ulong)scp->request_buffer & ~PAGE_MASK;
2600 phys_addr = pci_map_page(ha->pdev,page,offset,
2601 scp->request_bufflen,scp->SCp.Message);
2602 scp->SCp.dma_handle = phys_addr;
2604 if (ha->cache_feat & SCATTER_GATHER) {
2605 cmdp->u.cache64.DestAddr = (ulong64)-1;
2606 cmdp->u.cache64.sg_canz = 1;
2607 cmdp->u.cache64.sg_lst[0].sg_ptr = phys_addr;
2608 cmdp->u.cache64.sg_lst[0].sg_len = scp->request_bufflen;
2609 cmdp->u.cache64.sg_lst[1].sg_len = 0;
2611 cmdp->u.cache64.DestAddr = phys_addr;
2612 cmdp->u.cache64.sg_canz= 0;
2615 if (ha->cache_feat & SCATTER_GATHER) {
2616 cmdp->u.cache.DestAddr = 0xffffffff;
2617 cmdp->u.cache.sg_canz = 1;
2618 cmdp->u.cache.sg_lst[0].sg_ptr = phys_addr;
2619 cmdp->u.cache.sg_lst[0].sg_len = scp->request_bufflen;
2620 cmdp->u.cache.sg_lst[1].sg_len = 0;
2622 cmdp->u.cache.DestAddr = phys_addr;
2623 cmdp->u.cache.sg_canz= 0;
2628 /* evaluate command size, check space */
2630 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2631 cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
2632 cmdp->u.cache64.sg_lst[0].sg_ptr,
2633 cmdp->u.cache64.sg_lst[0].sg_len));
2634 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2635 cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
2636 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
2637 (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
2639 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2640 cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
2641 cmdp->u.cache.sg_lst[0].sg_ptr,
2642 cmdp->u.cache.sg_lst[0].sg_len));
2643 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2644 cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
2645 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
2646 (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
2648 if (ha->cmd_len & 3)
2649 ha->cmd_len += (4 - (ha->cmd_len & 3));
2651 if (ha->cmd_cnt > 0) {
2652 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
2654 TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
2655 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
2661 gdth_copy_command(hanum);
2665 static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b)
2667 register gdth_ha_str *ha;
2668 register gdth_cmd_str *cmdp;
2669 struct scatterlist *sl;
2671 dma_addr_t phys_addr, sense_paddr;
2672 int cmd_index, sgcnt, mode64;
2677 ha = HADATA(gdth_ctr_tab[hanum]);
2678 t = scp->device->id;
2679 l = scp->device->lun;
2681 TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
2682 scp->cmnd[0],b,t,l));
2684 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2687 mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
2689 cmdp->Service = SCSIRAWSERVICE;
2690 cmdp->RequestBuffer = scp;
2691 /* search free command index */
2692 if (!(cmd_index=gdth_get_cmd_index(hanum))) {
2693 TRACE(("GDT: No free command index found\n"));
2696 /* if it's the first command, set command semaphore */
2697 if (ha->cmd_cnt == 0)
2698 gdth_set_sema0(hanum);
2701 if (scp->SCp.sent_command != -1) {
2702 cmdp->OpCode = scp->SCp.sent_command; /* special raw cmd. */
2703 cmdp->BoardNode = LOCALBOARD;
2705 cmdp->u.raw64.direction = (scp->SCp.phase >> 8);
2706 TRACE2(("special raw cmd 0x%x param 0x%x\n",
2707 cmdp->OpCode, cmdp->u.raw64.direction));
2708 /* evaluate command size */
2709 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
2711 cmdp->u.raw.direction = (scp->SCp.phase >> 8);
2712 TRACE2(("special raw cmd 0x%x param 0x%x\n",
2713 cmdp->OpCode, cmdp->u.raw.direction));
2714 /* evaluate command size */
2715 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
2719 page = virt_to_page(scp->sense_buffer);
2720 offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
2721 sense_paddr = pci_map_page(ha->pdev,page,offset,
2722 16,PCI_DMA_FROMDEVICE);
2723 *(ulong32 *)&scp->SCp.buffer = (ulong32)sense_paddr;
2724 /* high part, if 64bit */
2725 *(ulong32 *)&scp->host_scribble = (ulong32)((ulong64)sense_paddr >> 32);
2726 cmdp->OpCode = GDT_WRITE; /* always */
2727 cmdp->BoardNode = LOCALBOARD;
2729 cmdp->u.raw64.reserved = 0;
2730 cmdp->u.raw64.mdisc_time = 0;
2731 cmdp->u.raw64.mcon_time = 0;
2732 cmdp->u.raw64.clen = scp->cmd_len;
2733 cmdp->u.raw64.target = t;
2734 cmdp->u.raw64.lun = l;
2735 cmdp->u.raw64.bus = b;
2736 cmdp->u.raw64.priority = 0;
2737 cmdp->u.raw64.sdlen = scp->request_bufflen;
2738 cmdp->u.raw64.sense_len = 16;
2739 cmdp->u.raw64.sense_data = sense_paddr;
2740 cmdp->u.raw64.direction =
2741 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
2742 memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
2743 cmdp->u.raw64.sg_ranz = 0;
2745 cmdp->u.raw.reserved = 0;
2746 cmdp->u.raw.mdisc_time = 0;
2747 cmdp->u.raw.mcon_time = 0;
2748 cmdp->u.raw.clen = scp->cmd_len;
2749 cmdp->u.raw.target = t;
2750 cmdp->u.raw.lun = l;
2751 cmdp->u.raw.bus = b;
2752 cmdp->u.raw.priority = 0;
2753 cmdp->u.raw.link_p = 0;
2754 cmdp->u.raw.sdlen = scp->request_bufflen;
2755 cmdp->u.raw.sense_len = 16;
2756 cmdp->u.raw.sense_data = sense_paddr;
2757 cmdp->u.raw.direction =
2758 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
2759 memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
2760 cmdp->u.raw.sg_ranz = 0;
2764 sl = (struct scatterlist *)scp->request_buffer;
2765 sgcnt = scp->use_sg;
2766 scp->SCp.Status = GDTH_MAP_SG;
2767 scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
2768 sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
2770 cmdp->u.raw64.sdata = (ulong64)-1;
2771 cmdp->u.raw64.sg_ranz = sgcnt;
2772 for (i=0; i<sgcnt; ++i,++sl) {
2773 cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
2774 #ifdef GDTH_DMA_STATISTICS
2775 if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
2780 cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
2783 cmdp->u.raw.sdata = 0xffffffff;
2784 cmdp->u.raw.sg_ranz = sgcnt;
2785 for (i=0; i<sgcnt; ++i,++sl) {
2786 cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
2787 #ifdef GDTH_DMA_STATISTICS
2790 cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
2794 #ifdef GDTH_STATISTICS
2795 if (max_sg < sgcnt) {
2797 TRACE3(("GDT: max_sg = %d\n",sgcnt));
2801 } else if (scp->request_bufflen) {
2802 scp->SCp.Status = GDTH_MAP_SINGLE;
2803 scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
2804 page = virt_to_page(scp->request_buffer);
2805 offset = (ulong)scp->request_buffer & ~PAGE_MASK;
2806 phys_addr = pci_map_page(ha->pdev,page,offset,
2807 scp->request_bufflen,scp->SCp.Message);
2808 scp->SCp.dma_handle = phys_addr;
2811 if (ha->raw_feat & SCATTER_GATHER) {
2812 cmdp->u.raw64.sdata = (ulong64)-1;
2813 cmdp->u.raw64.sg_ranz= 1;
2814 cmdp->u.raw64.sg_lst[0].sg_ptr = phys_addr;
2815 cmdp->u.raw64.sg_lst[0].sg_len = scp->request_bufflen;
2816 cmdp->u.raw64.sg_lst[1].sg_len = 0;
2818 cmdp->u.raw64.sdata = phys_addr;
2819 cmdp->u.raw64.sg_ranz= 0;
2822 if (ha->raw_feat & SCATTER_GATHER) {
2823 cmdp->u.raw.sdata = 0xffffffff;
2824 cmdp->u.raw.sg_ranz= 1;
2825 cmdp->u.raw.sg_lst[0].sg_ptr = phys_addr;
2826 cmdp->u.raw.sg_lst[0].sg_len = scp->request_bufflen;
2827 cmdp->u.raw.sg_lst[1].sg_len = 0;
2829 cmdp->u.raw.sdata = phys_addr;
2830 cmdp->u.raw.sg_ranz= 0;
2835 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2836 cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
2837 cmdp->u.raw64.sg_lst[0].sg_ptr,
2838 cmdp->u.raw64.sg_lst[0].sg_len));
2839 /* evaluate command size */
2840 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
2841 (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
2843 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2844 cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
2845 cmdp->u.raw.sg_lst[0].sg_ptr,
2846 cmdp->u.raw.sg_lst[0].sg_len));
2847 /* evaluate command size */
2848 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
2849 (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
2853 if (ha->cmd_len & 3)
2854 ha->cmd_len += (4 - (ha->cmd_len & 3));
2856 if (ha->cmd_cnt > 0) {
2857 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
2859 TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
2860 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
2866 gdth_copy_command(hanum);
2870 static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp)
2872 register gdth_ha_str *ha;
2873 register gdth_cmd_str *cmdp;
2876 ha = HADATA(gdth_ctr_tab[hanum]);
2878 TRACE2(("gdth_special_cmd(): "));
2880 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2883 memcpy( cmdp, scp->request_buffer, sizeof(gdth_cmd_str));
2884 cmdp->RequestBuffer = scp;
2886 /* search free command index */
2887 if (!(cmd_index=gdth_get_cmd_index(hanum))) {
2888 TRACE(("GDT: No free command index found\n"));
2892 /* if it's the first command, set command semaphore */
2893 if (ha->cmd_cnt == 0)
2894 gdth_set_sema0(hanum);
2896 /* evaluate command size, check space */
2897 if (cmdp->OpCode == GDT_IOCTL) {
2898 TRACE2(("IOCTL\n"));
2900 GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
2901 } else if (cmdp->Service == CACHESERVICE) {
2902 TRACE2(("cache command %d\n",cmdp->OpCode));
2903 if (ha->cache_feat & GDT_64BIT)
2905 GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
2908 GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
2909 } else if (cmdp->Service == SCSIRAWSERVICE) {
2910 TRACE2(("raw command %d\n",cmdp->OpCode));
2911 if (ha->raw_feat & GDT_64BIT)
2913 GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
2916 GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
2919 if (ha->cmd_len & 3)
2920 ha->cmd_len += (4 - (ha->cmd_len & 3));
2922 if (ha->cmd_cnt > 0) {
2923 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
2925 TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
2926 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
2932 gdth_copy_command(hanum);
2937 /* Controller event handling functions */
2938 static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
2939 ushort idx, gdth_evt_data *evt)
2944 /* no GDTH_LOCK_HA() ! */
2945 TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
2946 if (source == 0) /* no source -> no event */
2949 if (ebuffer[elastidx].event_source == source &&
2950 ebuffer[elastidx].event_idx == idx &&
2951 ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
2952 !memcmp((char *)&ebuffer[elastidx].event_data.eu,
2953 (char *)&evt->eu, evt->size)) ||
2954 (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
2955 !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
2956 (char *)&evt->event_string)))) {
2957 e = &ebuffer[elastidx];
2958 do_gettimeofday(&tv);
2959 e->last_stamp = tv.tv_sec;
2962 if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
2964 if (elastidx == MAX_EVENTS)
2966 if (elastidx == eoldidx) { /* reached mark ? */
2968 if (eoldidx == MAX_EVENTS)
2972 e = &ebuffer[elastidx];
2973 e->event_source = source;
2975 do_gettimeofday(&tv);
2976 e->first_stamp = e->last_stamp = tv.tv_sec;
2978 e->event_data = *evt;
2984 static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
2990 TRACE2(("gdth_read_event() handle %d\n", handle));
2991 spin_lock_irqsave(&ha->smp_lock, flags);
2996 estr->event_source = 0;
2998 if (eindex >= MAX_EVENTS) {
2999 spin_unlock_irqrestore(&ha->smp_lock, flags);
3002 e = &ebuffer[eindex];
3003 if (e->event_source != 0) {
3004 if (eindex != elastidx) {
3005 if (++eindex == MAX_EVENTS)
3010 memcpy(estr, e, sizeof(gdth_evt_str));
3012 spin_unlock_irqrestore(&ha->smp_lock, flags);
3016 static void gdth_readapp_event(gdth_ha_str *ha,
3017 unchar application, gdth_evt_str *estr)
3022 unchar found = FALSE;
3024 TRACE2(("gdth_readapp_event() app. %d\n", application));
3025 spin_lock_irqsave(&ha->smp_lock, flags);
3028 e = &ebuffer[eindex];
3029 if (e->event_source == 0)
3031 if ((e->application & application) == 0) {
3032 e->application |= application;
3036 if (eindex == elastidx)
3038 if (++eindex == MAX_EVENTS)
3042 memcpy(estr, e, sizeof(gdth_evt_str));
3044 estr->event_source = 0;
3045 spin_unlock_irqrestore(&ha->smp_lock, flags);
3048 static void gdth_clear_events(void)
3050 TRACE(("gdth_clear_events()"));
3052 eoldidx = elastidx = 0;
3053 ebuffer[0].event_source = 0;
3057 /* SCSI interface functions */
3059 static irqreturn_t gdth_interrupt(int irq,void *dev_id)
3061 gdth_ha_str *ha2 = (gdth_ha_str *)dev_id;
3062 register gdth_ha_str *ha;
3063 gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
3064 gdt6_dpram_str __iomem *dp6_ptr;
3065 gdt2_dpram_str __iomem *dp2_ptr;
3072 int coalesced = FALSE;
3074 gdth_coal_status *pcs = NULL;
3075 int act_int_coal = 0;
3078 TRACE(("gdth_interrupt() IRQ %d\n",irq));
3080 /* if polling and not from gdth_wait() -> return */
3082 if (!gdth_from_wait) {
3088 spin_lock_irqsave(&ha2->smp_lock, flags);
3091 /* search controller */
3092 if ((hanum = gdth_get_status(&IStatus,irq)) == -1) {
3093 /* spurious interrupt */
3095 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3098 ha = HADATA(gdth_ctr_tab[hanum]);
3100 #ifdef GDTH_STATISTICS
3105 /* See if the fw is returning coalesced status */
3106 if (IStatus == COALINDEX) {
3107 /* Coalesced status. Setup the initial status
3108 buffer pointer and flags */
3109 pcs = ha->coal_stat;
3116 /* For coalesced requests all status
3117 information is found in the status buffer */
3118 IStatus = (unchar)(pcs->status & 0xff);
3122 if (ha->type == GDT_EISA) {
3123 if (IStatus & 0x80) { /* error flag */
3125 ha->status = inw(ha->bmic + MAILBOXREG+8);
3126 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3127 } else /* no error */
3129 ha->info = inl(ha->bmic + MAILBOXREG+12);
3130 ha->service = inw(ha->bmic + MAILBOXREG+10);
3131 ha->info2 = inl(ha->bmic + MAILBOXREG+4);
3133 outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
3134 outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
3135 } else if (ha->type == GDT_ISA) {
3137 if (IStatus & 0x80) { /* error flag */
3139 ha->status = readw(&dp2_ptr->u.ic.Status);
3140 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3141 } else /* no error */
3143 ha->info = readl(&dp2_ptr->u.ic.Info[0]);
3144 ha->service = readw(&dp2_ptr->u.ic.Service);
3145 ha->info2 = readl(&dp2_ptr->u.ic.Info[1]);
3147 writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
3148 writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
3149 writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
3150 } else if (ha->type == GDT_PCI) {
3152 if (IStatus & 0x80) { /* error flag */
3154 ha->status = readw(&dp6_ptr->u.ic.Status);
3155 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3156 } else /* no error */
3158 ha->info = readl(&dp6_ptr->u.ic.Info[0]);
3159 ha->service = readw(&dp6_ptr->u.ic.Service);
3160 ha->info2 = readl(&dp6_ptr->u.ic.Info[1]);
3162 writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
3163 writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
3164 writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
3165 } else if (ha->type == GDT_PCINEW) {
3166 if (IStatus & 0x80) { /* error flag */
3168 ha->status = inw(PTR2USHORT(&ha->plx->status));
3169 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3172 ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
3173 ha->service = inw(PTR2USHORT(&ha->plx->service));
3174 ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
3176 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
3177 outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
3178 } else if (ha->type == GDT_PCIMPR) {
3180 if (IStatus & 0x80) { /* error flag */
3184 ha->status = pcs->ext_status & 0xffff;
3187 ha->status = readw(&dp6m_ptr->i960r.status);
3188 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3189 } else /* no error */
3192 /* get information */
3194 ha->info = pcs->info0;
3195 ha->info2 = pcs->info1;
3196 ha->service = (pcs->ext_status >> 16) & 0xffff;
3200 ha->info = readl(&dp6m_ptr->i960r.info[0]);
3201 ha->service = readw(&dp6m_ptr->i960r.service);
3202 ha->info2 = readl(&dp6m_ptr->i960r.info[1]);
3205 if (IStatus == ASYNCINDEX) {
3206 if (ha->service != SCREENSERVICE &&
3207 (ha->fw_vers & 0xff) >= 0x1a) {
3208 ha->dvr.severity = readb
3209 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
3210 for (i = 0; i < 256; ++i) {
3211 ha->dvr.event_string[i] = readb
3212 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
3213 if (ha->dvr.event_string[i] == 0)
3219 /* Make sure that non coalesced interrupts get cleared
3220 before being handled by gdth_async_event/gdth_sync_event */
3224 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3225 writeb(0, &dp6m_ptr->i960r.sema1_reg);
3228 TRACE2(("gdth_interrupt() unknown controller type\n"));
3230 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3234 TRACE(("gdth_interrupt() index %d stat %d info %d\n",
3235 IStatus,ha->status,ha->info));
3237 if (gdth_from_wait) {
3239 wait_index = (int)IStatus;
3242 if (IStatus == ASYNCINDEX) {
3243 TRACE2(("gdth_interrupt() async. event\n"));
3244 gdth_async_event(hanum);
3246 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3251 if (IStatus == SPEZINDEX) {
3252 TRACE2(("Service unknown or not initialized !\n"));
3253 ha->dvr.size = sizeof(ha->dvr.eu.driver);
3254 ha->dvr.eu.driver.ionode = hanum;
3255 gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
3257 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3260 scp = ha->cmd_tab[IStatus-2].cmnd;
3261 Service = ha->cmd_tab[IStatus-2].service;
3262 ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
3263 if (scp == UNUSED_CMND) {
3264 TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
3265 ha->dvr.size = sizeof(ha->dvr.eu.driver);
3266 ha->dvr.eu.driver.ionode = hanum;
3267 ha->dvr.eu.driver.index = IStatus;
3268 gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
3270 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3273 if (scp == INTERNAL_CMND) {
3274 TRACE(("gdth_interrupt() answer to internal command\n"));
3276 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3280 TRACE(("gdth_interrupt() sync. status\n"));
3281 rval = gdth_sync_event(hanum,Service,IStatus,scp);
3283 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3285 gdth_putq(hanum,scp,scp->SCp.this_residual);
3286 } else if (rval == 1) {
3287 gdth_scsi_done(scp);
3292 /* go to the next status in the status buffer */
3294 #ifdef GDTH_STATISTICS
3296 if (act_int_coal > max_int_coal) {
3297 max_int_coal = act_int_coal;
3298 printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
3301 /* see if there is another status */
3302 if (pcs->status == 0)
3303 /* Stop the coalesce loop */
3308 /* coalescing only for new GDT_PCIMPR controllers available */
3309 if (ha->type == GDT_PCIMPR && coalesced) {
3310 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3311 writeb(0, &dp6m_ptr->i960r.sema1_reg);
3319 static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp)
3321 register gdth_ha_str *ha;
3326 ha = HADATA(gdth_ctr_tab[hanum]);
3328 TRACE(("gdth_sync_event() serv %d status %d\n",
3329 service,ha->status));
3331 if (service == SCREENSERVICE) {
3333 TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
3334 msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
3335 if (msg->msg_len > MSGLEN+1)
3336 msg->msg_len = MSGLEN+1;
3338 if (!(msg->msg_answer && msg->msg_ext)) {
3339 msg->msg_text[msg->msg_len] = '\0';
3340 printk("%s",msg->msg_text);
3343 if (msg->msg_ext && !msg->msg_answer) {
3344 while (gdth_test_busy(hanum))
3346 cmdp->Service = SCREENSERVICE;
3347 cmdp->RequestBuffer = SCREEN_CMND;
3348 gdth_get_cmd_index(hanum);
3349 gdth_set_sema0(hanum);
3350 cmdp->OpCode = GDT_READ;
3351 cmdp->BoardNode = LOCALBOARD;
3352 cmdp->u.screen.reserved = 0;
3353 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3354 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3355 ha->cmd_offs_dpmem = 0;
3356 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3359 gdth_copy_command(hanum);
3360 gdth_release_event(hanum);
3364 if (msg->msg_answer && msg->msg_alen) {
3365 /* default answers (getchar() not possible) */
3366 if (msg->msg_alen == 1) {
3369 msg->msg_text[0] = 0;
3373 msg->msg_text[0] = 1;
3374 msg->msg_text[1] = 0;
3377 msg->msg_answer = 0;
3378 while (gdth_test_busy(hanum))
3380 cmdp->Service = SCREENSERVICE;
3381 cmdp->RequestBuffer = SCREEN_CMND;
3382 gdth_get_cmd_index(hanum);
3383 gdth_set_sema0(hanum);
3384 cmdp->OpCode = GDT_WRITE;
3385 cmdp->BoardNode = LOCALBOARD;
3386 cmdp->u.screen.reserved = 0;
3387 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3388 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3389 ha->cmd_offs_dpmem = 0;
3390 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3393 gdth_copy_command(hanum);
3394 gdth_release_event(hanum);
3400 b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
3401 t = scp->device->id;
3402 if (scp->SCp.sent_command == -1 && b != ha->virt_bus) {
3403 ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
3405 /* cache or raw service */
3406 if (ha->status == S_BSY) {
3407 TRACE2(("Controller busy -> retry !\n"));
3408 if (scp->SCp.sent_command == GDT_MOUNT)
3409 scp->SCp.sent_command = GDT_CLUST_INFO;
3413 if (scp->SCp.Status == GDTH_MAP_SG)
3414 pci_unmap_sg(ha->pdev,scp->request_buffer,
3415 scp->use_sg,scp->SCp.Message);
3416 else if (scp->SCp.Status == GDTH_MAP_SINGLE)
3417 pci_unmap_page(ha->pdev,scp->SCp.dma_handle,
3418 scp->request_bufflen,scp->SCp.Message);
3419 if (scp->SCp.buffer) {
3421 addr = (dma_addr_t)*(ulong32 *)&scp->SCp.buffer;
3422 if (scp->host_scribble)
3423 addr += (dma_addr_t)
3424 ((ulong64)(*(ulong32 *)&scp->host_scribble) << 32);
3425 pci_unmap_page(ha->pdev,addr,16,PCI_DMA_FROMDEVICE);
3428 if (ha->status == S_OK) {
3429 scp->SCp.Status = S_OK;
3430 scp->SCp.Message = ha->info;
3431 if (scp->SCp.sent_command != -1) {
3432 TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
3433 scp->SCp.sent_command));
3434 /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
3435 if (scp->SCp.sent_command == GDT_CLUST_INFO) {
3436 ha->hdr[t].cluster_type = (unchar)ha->info;
3437 if (!(ha->hdr[t].cluster_type &
3439 /* NOT MOUNTED -> MOUNT */
3440 scp->SCp.sent_command = GDT_MOUNT;
3441 if (ha->hdr[t].cluster_type &
3443 /* cluster drive RESERVED (on the other node) */
3444 scp->SCp.phase = -2; /* reservation conflict */
3447 scp->SCp.sent_command = -1;
3450 if (scp->SCp.sent_command == GDT_MOUNT) {
3451 ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
3452 ha->hdr[t].media_changed = TRUE;
3453 } else if (scp->SCp.sent_command == GDT_UNMOUNT) {
3454 ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
3455 ha->hdr[t].media_changed = TRUE;
3457 scp->SCp.sent_command = -1;
3460 scp->SCp.this_residual = HIGH_PRI;
3463 /* RESERVE/RELEASE ? */
3464 if (scp->cmnd[0] == RESERVE) {
3465 ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
3466 } else if (scp->cmnd[0] == RELEASE) {
3467 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3469 scp->result = DID_OK << 16;
3470 scp->sense_buffer[0] = 0;
3473 scp->SCp.Status = ha->status;
3474 scp->SCp.Message = ha->info;
3476 if (scp->SCp.sent_command != -1) {
3477 TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
3478 scp->SCp.sent_command, ha->status));
3479 if (scp->SCp.sent_command == GDT_SCAN_START ||
3480 scp->SCp.sent_command == GDT_SCAN_END) {
3481 scp->SCp.sent_command = -1;
3483 scp->SCp.this_residual = HIGH_PRI;
3486 memset((char*)scp->sense_buffer,0,16);
3487 scp->sense_buffer[0] = 0x70;
3488 scp->sense_buffer[2] = NOT_READY;
3489 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3490 } else if (service == CACHESERVICE) {
3491 if (ha->status == S_CACHE_UNKNOWN &&
3492 (ha->hdr[t].cluster_type &
3493 CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
3494 /* bus reset -> force GDT_CLUST_INFO */
3495 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3497 memset((char*)scp->sense_buffer,0,16);
3498 if (ha->status == (ushort)S_CACHE_RESERV) {
3499 scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
3501 scp->sense_buffer[0] = 0x70;
3502 scp->sense_buffer[2] = NOT_READY;
3503 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3505 if (!IS_GDTH_INTERNAL_CMD(scp)) {
3506 ha->dvr.size = sizeof(ha->dvr.eu.sync);
3507 ha->dvr.eu.sync.ionode = hanum;
3508 ha->dvr.eu.sync.service = service;
3509 ha->dvr.eu.sync.status = ha->status;
3510 ha->dvr.eu.sync.info = ha->info;
3511 ha->dvr.eu.sync.hostdrive = t;
3512 if (ha->status >= 0x8000)
3513 gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
3515 gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
3518 /* sense buffer filled from controller firmware (DMA) */
3519 if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
3520 scp->result = DID_BAD_TARGET << 16;
3522 scp->result = (DID_OK << 16) | ha->info;
3526 if (!scp->SCp.have_data_in)
3527 scp->SCp.have_data_in++;
3535 static char *async_cache_tab[] = {
3536 /* 0*/ "\011\000\002\002\002\004\002\006\004"
3537 "GDT HA %u, service %u, async. status %u/%lu unknown",
3538 /* 1*/ "\011\000\002\002\002\004\002\006\004"
3539 "GDT HA %u, service %u, async. status %u/%lu unknown",
3540 /* 2*/ "\005\000\002\006\004"
3541 "GDT HA %u, Host Drive %lu not ready",
3542 /* 3*/ "\005\000\002\006\004"
3543 "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3544 /* 4*/ "\005\000\002\006\004"
3545 "GDT HA %u, mirror update on Host Drive %lu failed",
3546 /* 5*/ "\005\000\002\006\004"
3547 "GDT HA %u, Mirror Drive %lu failed",
3548 /* 6*/ "\005\000\002\006\004"
3549 "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3550 /* 7*/ "\005\000\002\006\004"
3551 "GDT HA %u, Host Drive %lu write protected",
3552 /* 8*/ "\005\000\002\006\004"
3553 "GDT HA %u, media changed in Host Drive %lu",
3554 /* 9*/ "\005\000\002\006\004"
3555 "GDT HA %u, Host Drive %lu is offline",
3556 /*10*/ "\005\000\002\006\004"
3557 "GDT HA %u, media change of Mirror Drive %lu",
3558 /*11*/ "\005\000\002\006\004"
3559 "GDT HA %u, Mirror Drive %lu is write protected",
3560 /*12*/ "\005\000\002\006\004"
3561 "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
3562 /*13*/ "\007\000\002\006\002\010\002"
3563 "GDT HA %u, Array Drive %u: Cache Drive %u failed",
3564 /*14*/ "\005\000\002\006\002"
3565 "GDT HA %u, Array Drive %u: FAIL state entered",
3566 /*15*/ "\005\000\002\006\002"
3567 "GDT HA %u, Array Drive %u: error",
3568 /*16*/ "\007\000\002\006\002\010\002"
3569 "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
3570 /*17*/ "\005\000\002\006\002"
3571 "GDT HA %u, Array Drive %u: parity build failed",
3572 /*18*/ "\005\000\002\006\002"
3573 "GDT HA %u, Array Drive %u: drive rebuild failed",
3574 /*19*/ "\005\000\002\010\002"
3575 "GDT HA %u, Test of Hot Fix %u failed",
3576 /*20*/ "\005\000\002\006\002"
3577 "GDT HA %u, Array Drive %u: drive build finished successfully",
3578 /*21*/ "\005\000\002\006\002"
3579 "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
3580 /*22*/ "\007\000\002\006\002\010\002"
3581 "GDT HA %u, Array Drive %u: Hot Fix %u activated",
3582 /*23*/ "\005\000\002\006\002"
3583 "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
3584 /*24*/ "\005\000\002\010\002"
3585 "GDT HA %u, mirror update on Cache Drive %u completed",
3586 /*25*/ "\005\000\002\010\002"
3587 "GDT HA %u, mirror update on Cache Drive %lu failed",
3588 /*26*/ "\005\000\002\006\002"
3589 "GDT HA %u, Array Drive %u: drive rebuild started",
3590 /*27*/ "\005\000\002\012\001"
3591 "GDT HA %u, Fault bus %u: SHELF OK detected",
3592 /*28*/ "\005\000\002\012\001"
3593 "GDT HA %u, Fault bus %u: SHELF not OK detected",
3594 /*29*/ "\007\000\002\012\001\013\001"
3595 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
3596 /*30*/ "\007\000\002\012\001\013\001"
3597 "GDT HA %u, Fault bus %u, ID %u: new disk detected",
3598 /*31*/ "\007\000\002\012\001\013\001"
3599 "GDT HA %u, Fault bus %u, ID %u: old disk detected",
3600 /*32*/ "\007\000\002\012\001\013\001"
3601 "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
3602 /*33*/ "\007\000\002\012\001\013\001"
3603 "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
3604 /*34*/ "\011\000\002\012\001\013\001\006\004"
3605 "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
3606 /*35*/ "\007\000\002\012\001\013\001"
3607 "GDT HA %u, Fault bus %u, ID %u: disk write protected",
3608 /*36*/ "\007\000\002\012\001\013\001"
3609 "GDT HA %u, Fault bus %u, ID %u: disk not available",
3610 /*37*/ "\007\000\002\012\001\006\004"
3611 "GDT HA %u, Fault bus %u: swap detected (%lu)",
3612 /*38*/ "\007\000\002\012\001\013\001"
3613 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
3614 /*39*/ "\007\000\002\012\001\013\001"
3615 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
3616 /*40*/ "\007\000\002\012\001\013\001"
3617 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
3618 /*41*/ "\007\000\002\012\001\013\001"
3619 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
3620 /*42*/ "\005\000\002\006\002"
3621 "GDT HA %u, Array Drive %u: drive build started",
3622 /*43*/ "\003\000\002"
3623 "GDT HA %u, DRAM parity error detected",
3624 /*44*/ "\005\000\002\006\002"
3625 "GDT HA %u, Mirror Drive %u: update started",
3626 /*45*/ "\007\000\002\006\002\010\002"
3627 "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
3628 /*46*/ "\005\000\002\006\002"
3629 "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
3630 /*47*/ "\005\000\002\006\002"
3631 "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
3632 /*48*/ "\005\000\002\006\002"
3633 "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
3634 /*49*/ "\005\000\002\006\002"
3635 "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
3636 /*50*/ "\007\000\002\012\001\013\001"
3637 "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
3638 /*51*/ "\005\000\002\006\002"
3639 "GDT HA %u, Array Drive %u: expand started",
3640 /*52*/ "\005\000\002\006\002"
3641 "GDT HA %u, Array Drive %u: expand finished successfully",
3642 /*53*/ "\005\000\002\006\002"
3643 "GDT HA %u, Array Drive %u: expand failed",
3644 /*54*/ "\003\000\002"
3645 "GDT HA %u, CPU temperature critical",
3646 /*55*/ "\003\000\002"
3647 "GDT HA %u, CPU temperature OK",
3648 /*56*/ "\005\000\002\006\004"
3649 "GDT HA %u, Host drive %lu created",
3650 /*57*/ "\005\000\002\006\002"
3651 "GDT HA %u, Array Drive %u: expand restarted",
3652 /*58*/ "\005\000\002\006\002"
3653 "GDT HA %u, Array Drive %u: expand stopped",
3654 /*59*/ "\005\000\002\010\002"
3655 "GDT HA %u, Mirror Drive %u: drive build quited",
3656 /*60*/ "\005\000\002\006\002"
3657 "GDT HA %u, Array Drive %u: parity build quited",
3658 /*61*/ "\005\000\002\006\002"
3659 "GDT HA %u, Array Drive %u: drive rebuild quited",
3660 /*62*/ "\005\000\002\006\002"
3661 "GDT HA %u, Array Drive %u: parity verify started",
3662 /*63*/ "\005\000\002\006\002"
3663 "GDT HA %u, Array Drive %u: parity verify done",
3664 /*64*/ "\005\000\002\006\002"
3665 "GDT HA %u, Array Drive %u: parity verify failed",
3666 /*65*/ "\005\000\002\006\002"
3667 "GDT HA %u, Array Drive %u: parity error detected",
3668 /*66*/ "\005\000\002\006\002"
3669 "GDT HA %u, Array Drive %u: parity verify quited",
3670 /*67*/ "\005\000\002\006\002"
3671 "GDT HA %u, Host Drive %u reserved",
3672 /*68*/ "\005\000\002\006\002"
3673 "GDT HA %u, Host Drive %u mounted and released",
3674 /*69*/ "\005\000\002\006\002"
3675 "GDT HA %u, Host Drive %u released",
3676 /*70*/ "\003\000\002"
3677 "GDT HA %u, DRAM error detected and corrected with ECC",
3678 /*71*/ "\003\000\002"
3679 "GDT HA %u, Uncorrectable DRAM error detected with ECC",
3680 /*72*/ "\011\000\002\012\001\013\001\014\001"
3681 "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
3682 /*73*/ "\005\000\002\006\002"
3683 "GDT HA %u, Host drive %u resetted locally",
3684 /*74*/ "\005\000\002\006\002"
3685 "GDT HA %u, Host drive %u resetted remotely",
3686 /*75*/ "\003\000\002"
3687 "GDT HA %u, async. status 75 unknown",
3691 static int gdth_async_event(int hanum)
3697 ha = HADATA(gdth_ctr_tab[hanum]);
3699 TRACE2(("gdth_async_event() ha %d serv %d\n",
3700 hanum,ha->service));
3702 if (ha->service == SCREENSERVICE) {
3703 if (ha->status == MSG_REQUEST) {
3704 while (gdth_test_busy(hanum))
3706 cmdp->Service = SCREENSERVICE;
3707 cmdp->RequestBuffer = SCREEN_CMND;
3708 cmd_index = gdth_get_cmd_index(hanum);
3709 gdth_set_sema0(hanum);
3710 cmdp->OpCode = GDT_READ;
3711 cmdp->BoardNode = LOCALBOARD;
3712 cmdp->u.screen.reserved = 0;
3713 cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
3714 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3715 ha->cmd_offs_dpmem = 0;
3716 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3719 gdth_copy_command(hanum);
3720 if (ha->type == GDT_EISA)
3721 printk("[EISA slot %d] ",(ushort)ha->brd_phys);
3722 else if (ha->type == GDT_ISA)
3723 printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
3725 printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
3726 (ushort)((ha->brd_phys>>3)&0x1f));
3727 gdth_release_event(hanum);
3731 if (ha->type == GDT_PCIMPR &&
3732 (ha->fw_vers & 0xff) >= 0x1a) {
3734 ha->dvr.eu.async.ionode = hanum;
3735 ha->dvr.eu.async.status = ha->status;
3736 /* severity and event_string already set! */
3738 ha->dvr.size = sizeof(ha->dvr.eu.async);
3739 ha->dvr.eu.async.ionode = hanum;
3740 ha->dvr.eu.async.service = ha->service;
3741 ha->dvr.eu.async.status = ha->status;
3742 ha->dvr.eu.async.info = ha->info;
3743 *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
3745 gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
3746 gdth_log_event( &ha->dvr, NULL );
3748 /* new host drive from expand? */
3749 if (ha->service == CACHESERVICE && ha->status == 56) {
3750 TRACE2(("gdth_async_event(): new host drive %d created\n",
3752 /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
3758 static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
3760 gdth_stackframe stack;
3764 TRACE2(("gdth_log_event()\n"));
3765 if (dvr->size == 0) {
3766 if (buffer == NULL) {
3767 printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
3769 sprintf(buffer,"Adapter %d: %s\n",
3770 dvr->eu.async.ionode,dvr->event_string);
3772 } else if (dvr->eu.async.service == CACHESERVICE &&
3773 INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
3774 TRACE2(("GDT: Async. event cache service, event no.: %d\n",
3775 dvr->eu.async.status));
3777 f = async_cache_tab[dvr->eu.async.status];
3779 /* i: parameter to push, j: stack element to fill */
3780 for (j=0,i=1; i < f[0]; i+=2) {
3783 stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
3786 stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
3789 stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
3796 if (buffer == NULL) {
3797 printk(&f[(int)f[0]],stack);
3800 sprintf(buffer,&f[(int)f[0]],stack);
3804 if (buffer == NULL) {
3805 printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
3806 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
3808 sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
3809 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
3814 #ifdef GDTH_STATISTICS
3815 static void gdth_timeout(ulong data)
3823 ha = HADATA(gdth_ctr_tab[hanum]);
3824 spin_lock_irqsave(&ha->smp_lock, flags);
3826 for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
3827 if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
3830 for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
3833 TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
3834 act_ints, act_ios, act_stats, act_rq));
3835 act_ints = act_ios = 0;
3837 gdth_timer.expires = jiffies + 30 * HZ;
3838 add_timer(&gdth_timer);
3839 spin_unlock_irqrestore(&ha->smp_lock, flags);
3843 static void __init internal_setup(char *str,int *ints)
3846 char *cur_str, *argv;
3848 TRACE2(("internal_setup() str %s ints[0] %d\n",
3849 str ? str:"NULL", ints ? ints[0]:0));
3851 /* read irq[] from ints[] */
3857 for (i = 0; i < argc; ++i)
3862 /* analyse string */
3864 while (argv && (cur_str = strchr(argv, ':'))) {
3865 int val = 0, c = *++cur_str;
3867 if (c == 'n' || c == 'N')
3869 else if (c == 'y' || c == 'Y')
3872 val = (int)simple_strtoul(cur_str, NULL, 0);
3874 if (!strncmp(argv, "disable:", 8))
3876 else if (!strncmp(argv, "reserve_mode:", 13))
3878 else if (!strncmp(argv, "reverse_scan:", 13))
3880 else if (!strncmp(argv, "hdr_channel:", 12))
3882 else if (!strncmp(argv, "max_ids:", 8))
3884 else if (!strncmp(argv, "rescan:", 7))
3886 else if (!strncmp(argv, "virt_ctr:", 9))
3888 else if (!strncmp(argv, "shared_access:", 14))
3889 shared_access = val;
3890 else if (!strncmp(argv, "probe_eisa_isa:", 15))
3891 probe_eisa_isa = val;
3892 else if (!strncmp(argv, "reserve_list:", 13)) {
3893 reserve_list[0] = val;
3894 for (i = 1; i < MAX_RES_ARGS; i++) {
3895 cur_str = strchr(cur_str, ',');
3898 if (!isdigit((int)*++cur_str)) {
3903 (int)simple_strtoul(cur_str, NULL, 0);
3911 if ((argv = strchr(argv, ',')))
3916 int __init option_setup(char *str)
3922 TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
3924 while (cur && isdigit(*cur) && i <= MAXHA) {
3925 ints[i++] = simple_strtoul(cur, NULL, 0);
3926 if ((cur = strchr(cur, ',')) != NULL) cur++;
3930 internal_setup(cur, ints);
3935 static int __init gdth_detect(struct scsi_host_template *shtp)
3938 printk("GDT: This driver contains debugging information !! Trace level = %d\n",
3940 printk(" Destination of debugging information: ");
3943 printk("Serial port COM2\n");
3945 printk("Serial port COM1\n");
3948 printk("Console\n");
3953 TRACE(("gdth_detect()\n"));
3956 printk("GDT-HA: Controller driver disabled from command line !\n");
3960 printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",GDTH_VERSION_STR);
3961 /* initializations */
3962 gdth_polling = TRUE;
3963 gdth_clear_events();
3965 /* As default we do not probe for EISA or ISA controllers */
3966 if (probe_eisa_isa) {
3967 /* scanning for controllers, at first: ISA controller */
3970 for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
3971 isa_bios += 0x8000UL) {
3972 if (gdth_ctr_count >= MAXHA)
3974 gdth_isa_probe_one(shtp, isa_bios);
3980 for (eisa_slot = 0x1000; eisa_slot <= 0x8000; eisa_slot += 0x1000) {
3981 if (gdth_ctr_count >= MAXHA)
3983 gdth_eisa_probe_one(shtp, eisa_slot);
3990 /* scanning for PCI controllers */
3992 gdth_pci_str pcistr[MAXHA];
3995 cnt = gdth_search_pci(pcistr);
3996 printk("GDT-HA: Found %d PCI Storage RAID Controllers\n",cnt);
3997 gdth_sort_pci(pcistr,cnt);
3998 for (ctr = 0; ctr < cnt; ++ctr) {
3999 if (gdth_ctr_count >= MAXHA)
4001 gdth_pci_probe_one(shtp, pcistr, ctr);
4004 #endif /* CONFIG_PCI */
4006 TRACE2(("gdth_detect() %d controller detected\n",gdth_ctr_count));
4007 if (gdth_ctr_count > 0) {
4008 #ifdef GDTH_STATISTICS
4009 TRACE2(("gdth_detect(): Initializing timer !\n"));
4010 init_timer(&gdth_timer);
4011 gdth_timer.expires = jiffies + HZ;
4012 gdth_timer.data = 0L;
4013 gdth_timer.function = gdth_timeout;
4014 add_timer(&gdth_timer);
4016 major = register_chrdev(0,"gdth",&gdth_fops);
4017 notifier_disabled = 0;
4018 register_reboot_notifier(&gdth_notifier);
4020 gdth_polling = FALSE;
4021 return gdth_ctr_vcount;
4024 static int gdth_release(struct Scsi_Host *shp)
4029 TRACE2(("gdth_release()\n"));
4030 if (NUMDATA(shp)->busnum == 0) {
4031 hanum = NUMDATA(shp)->hanum;
4032 ha = HADATA(gdth_ctr_tab[hanum]);
4034 scsi_free_host_dev(ha->sdev);
4040 free_irq(shp->irq,ha);
4043 if (shp->dma_channel != 0xff) {
4044 free_dma(shp->dma_channel);
4049 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
4050 MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
4053 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4054 ha->pscratch, ha->scratch_phys);
4056 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4057 ha->pmsg, ha->msg_phys);
4059 pci_unmap_single(ha->pdev,ha->ccb_phys,
4060 sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
4061 gdth_ctr_released++;
4062 TRACE2(("gdth_release(): HA %d of %d\n",
4063 gdth_ctr_released, gdth_ctr_count));
4065 if (gdth_ctr_released == gdth_ctr_count) {
4066 #ifdef GDTH_STATISTICS
4067 del_timer(&gdth_timer);
4069 unregister_chrdev(major,"gdth");
4070 unregister_reboot_notifier(&gdth_notifier);
4074 scsi_unregister(shp);
4079 static const char *gdth_ctr_name(int hanum)
4083 TRACE2(("gdth_ctr_name()\n"));
4085 ha = HADATA(gdth_ctr_tab[hanum]);
4087 if (ha->type == GDT_EISA) {
4088 switch (ha->stype) {
4090 return("GDT3000/3020");
4092 return("GDT3000A/3020A/3050A");
4094 return("GDT3000B/3010A");
4096 } else if (ha->type == GDT_ISA) {
4097 return("GDT2000/2020");
4098 } else if (ha->type == GDT_PCI) {
4099 switch (ha->pdev->device) {
4100 case PCI_DEVICE_ID_VORTEX_GDT60x0:
4101 return("GDT6000/6020/6050");
4102 case PCI_DEVICE_ID_VORTEX_GDT6000B:
4103 return("GDT6000B/6010");
4106 /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
4111 static const char *gdth_info(struct Scsi_Host *shp)
4116 TRACE2(("gdth_info()\n"));
4117 hanum = NUMDATA(shp)->hanum;
4118 ha = HADATA(gdth_ctr_tab[hanum]);
4120 return ((const char *)ha->binfo.type_string);
4123 static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
4131 TRACE2(("gdth_eh_bus_reset()\n"));
4133 hanum = NUMDATA(scp->device->host)->hanum;
4134 b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
4135 ha = HADATA(gdth_ctr_tab[hanum]);
4137 /* clear command tab */
4138 spin_lock_irqsave(&ha->smp_lock, flags);
4139 for (i = 0; i < GDTH_MAXCMDS; ++i) {
4140 cmnd = ha->cmd_tab[i].cmnd;
4141 if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
4142 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4144 spin_unlock_irqrestore(&ha->smp_lock, flags);
4146 if (b == ha->virt_bus) {
4148 for (i = 0; i < MAX_HDRIVES; ++i) {
4149 if (ha->hdr[i].present) {
4150 spin_lock_irqsave(&ha->smp_lock, flags);
4151 gdth_polling = TRUE;
4152 while (gdth_test_busy(hanum))
4154 if (gdth_internal_cmd(hanum, CACHESERVICE,
4155 GDT_CLUST_RESET, i, 0, 0))
4156 ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
4157 gdth_polling = FALSE;
4158 spin_unlock_irqrestore(&ha->smp_lock, flags);
4163 spin_lock_irqsave(&ha->smp_lock, flags);
4164 for (i = 0; i < MAXID; ++i)
4165 ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
4166 gdth_polling = TRUE;
4167 while (gdth_test_busy(hanum))
4169 gdth_internal_cmd(hanum, SCSIRAWSERVICE, GDT_RESET_BUS,
4170 BUS_L2P(ha,b), 0, 0);
4171 gdth_polling = FALSE;
4172 spin_unlock_irqrestore(&ha->smp_lock, flags);
4177 static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
4182 struct scsi_device *sd;
4187 hanum = NUMDATA(sd->host)->hanum;
4188 b = virt_ctr ? NUMDATA(sd->host)->busnum : sd->channel;
4190 TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", hanum, b, t));
4191 ha = HADATA(gdth_ctr_tab[hanum]);
4193 if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
4194 /* raw device or host drive without mapping information */
4195 TRACE2(("Evaluate mapping\n"));
4196 gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
4198 ip[0] = ha->hdr[t].heads;
4199 ip[1] = ha->hdr[t].secs;
4200 ip[2] = capacity / ip[0] / ip[1];
4203 TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
4204 ip[0],ip[1],ip[2]));
4209 static int gdth_queuecommand(struct scsi_cmnd *scp,
4210 void (*done)(struct scsi_cmnd *))
4215 TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
4217 scp->scsi_done = done;
4218 scp->SCp.have_data_in = 1;
4219 scp->SCp.phase = -1;
4220 scp->SCp.sent_command = -1;
4221 scp->SCp.Status = GDTH_MAP_NONE;
4222 scp->SCp.buffer = (struct scatterlist *)NULL;
4224 hanum = NUMDATA(scp->device->host)->hanum;
4225 #ifdef GDTH_STATISTICS
4229 priority = DEFAULT_PRI;
4230 if (IS_GDTH_INTERNAL_CMD(scp))
4231 priority = scp->SCp.this_residual;
4233 gdth_update_timeout(hanum, scp, scp->timeout_per_command * 6);
4235 gdth_putq( hanum, scp, priority );
4241 static int gdth_open(struct inode *inode, struct file *filep)
4246 for (i = 0; i < gdth_ctr_count; i++) {
4247 ha = HADATA(gdth_ctr_tab[i]);
4249 ha->sdev = scsi_get_host_dev(gdth_ctr_tab[i]);
4252 TRACE(("gdth_open()\n"));
4256 static int gdth_close(struct inode *inode, struct file *filep)
4258 TRACE(("gdth_close()\n"));
4262 static int ioc_event(void __user *arg)
4264 gdth_ioctl_event evt;
4268 if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)) ||
4269 evt.ionode >= gdth_ctr_count)
4271 ha = HADATA(gdth_ctr_tab[evt.ionode]);
4273 if (evt.erase == 0xff) {
4274 if (evt.event.event_source == ES_TEST)
4275 evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
4276 else if (evt.event.event_source == ES_DRIVER)
4277 evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
4278 else if (evt.event.event_source == ES_SYNC)
4279 evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
4281 evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
4282 spin_lock_irqsave(&ha->smp_lock, flags);
4283 gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
4284 &evt.event.event_data);
4285 spin_unlock_irqrestore(&ha->smp_lock, flags);
4286 } else if (evt.erase == 0xfe) {
4287 gdth_clear_events();
4288 } else if (evt.erase == 0) {
4289 evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
4291 gdth_readapp_event(ha, evt.erase, &evt.event);
4293 if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
4298 static int ioc_lockdrv(void __user *arg)
4300 gdth_ioctl_lockdrv ldrv;
4305 if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)) ||
4306 ldrv.ionode >= gdth_ctr_count)
4308 ha = HADATA(gdth_ctr_tab[ldrv.ionode]);
4310 for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
4312 if (j >= MAX_HDRIVES || !ha->hdr[j].present)
4315 spin_lock_irqsave(&ha->smp_lock, flags);
4316 ha->hdr[j].lock = 1;
4317 spin_unlock_irqrestore(&ha->smp_lock, flags);
4318 gdth_wait_completion(ldrv.ionode, ha->bus_cnt, j);
4319 gdth_stop_timeout(ldrv.ionode, ha->bus_cnt, j);
4321 spin_lock_irqsave(&ha->smp_lock, flags);
4322 ha->hdr[j].lock = 0;
4323 spin_unlock_irqrestore(&ha->smp_lock, flags);
4324 gdth_start_timeout(ldrv.ionode, ha->bus_cnt, j);
4325 gdth_next(ldrv.ionode);
4331 static int ioc_resetdrv(void __user *arg, char *cmnd)
4333 gdth_ioctl_reset res;
4339 if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
4340 res.ionode >= gdth_ctr_count || res.number >= MAX_HDRIVES)
4343 ha = HADATA(gdth_ctr_tab[hanum]);
4345 if (!ha->hdr[res.number].present)
4347 memset(&cmd, 0, sizeof(gdth_cmd_str));
4348 cmd.Service = CACHESERVICE;
4349 cmd.OpCode = GDT_CLUST_RESET;
4350 if (ha->cache_feat & GDT_64BIT)
4351 cmd.u.cache64.DeviceNo = res.number;
4353 cmd.u.cache.DeviceNo = res.number;
4355 rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
4360 if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
4365 static int ioc_general(void __user *arg, char *cmnd)
4367 gdth_ioctl_general gen;
4374 if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)) ||
4375 gen.ionode >= gdth_ctr_count)
4378 ha = HADATA(gdth_ctr_tab[hanum]);
4379 if (gen.data_len + gen.sense_len != 0) {
4380 if (!(buf = gdth_ioctl_alloc(hanum, gen.data_len + gen.sense_len,
4383 if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
4384 gen.data_len + gen.sense_len)) {
4385 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
4389 if (gen.command.OpCode == GDT_IOCTL) {
4390 gen.command.u.ioctl.p_param = paddr;
4391 } else if (gen.command.Service == CACHESERVICE) {
4392 if (ha->cache_feat & GDT_64BIT) {
4393 /* copy elements from 32-bit IOCTL structure */
4394 gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
4395 gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
4396 gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
4398 if (ha->cache_feat & SCATTER_GATHER) {
4399 gen.command.u.cache64.DestAddr = (ulong64)-1;
4400 gen.command.u.cache64.sg_canz = 1;
4401 gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
4402 gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
4403 gen.command.u.cache64.sg_lst[1].sg_len = 0;
4405 gen.command.u.cache64.DestAddr = paddr;
4406 gen.command.u.cache64.sg_canz = 0;
4409 if (ha->cache_feat & SCATTER_GATHER) {
4410 gen.command.u.cache.DestAddr = 0xffffffff;
4411 gen.command.u.cache.sg_canz = 1;
4412 gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
4413 gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
4414 gen.command.u.cache.sg_lst[1].sg_len = 0;
4416 gen.command.u.cache.DestAddr = paddr;
4417 gen.command.u.cache.sg_canz = 0;
4420 } else if (gen.command.Service == SCSIRAWSERVICE) {
4421 if (ha->raw_feat & GDT_64BIT) {
4422 /* copy elements from 32-bit IOCTL structure */
4424 gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
4425 gen.command.u.raw64.bus = gen.command.u.raw.bus;
4426 gen.command.u.raw64.lun = gen.command.u.raw.lun;
4427 gen.command.u.raw64.target = gen.command.u.raw.target;
4428 memcpy(cmd, gen.command.u.raw.cmd, 16);
4429 memcpy(gen.command.u.raw64.cmd, cmd, 16);
4430 gen.command.u.raw64.clen = gen.command.u.raw.clen;
4431 gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
4432 gen.command.u.raw64.direction = gen.command.u.raw.direction;
4434 if (ha->raw_feat & SCATTER_GATHER) {
4435 gen.command.u.raw64.sdata = (ulong64)-1;
4436 gen.command.u.raw64.sg_ranz = 1;
4437 gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
4438 gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
4439 gen.command.u.raw64.sg_lst[1].sg_len = 0;
4441 gen.command.u.raw64.sdata = paddr;
4442 gen.command.u.raw64.sg_ranz = 0;
4444 gen.command.u.raw64.sense_data = paddr + gen.data_len;
4446 if (ha->raw_feat & SCATTER_GATHER) {
4447 gen.command.u.raw.sdata = 0xffffffff;
4448 gen.command.u.raw.sg_ranz = 1;
4449 gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
4450 gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
4451 gen.command.u.raw.sg_lst[1].sg_len = 0;
4453 gen.command.u.raw.sdata = paddr;
4454 gen.command.u.raw.sg_ranz = 0;
4456 gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
4459 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
4464 rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
4469 if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
4470 gen.data_len + gen.sense_len)) {
4471 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
4474 if (copy_to_user(arg, &gen,
4475 sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
4476 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
4479 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
4483 static int ioc_hdrlist(void __user *arg, char *cmnd)
4485 gdth_ioctl_rescan *rsc;
4489 int hanum, rc = -ENOMEM;
4490 u32 cluster_type = 0;
4492 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
4493 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
4497 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
4498 rsc->ionode >= gdth_ctr_count) {
4502 hanum = rsc->ionode;
4503 ha = HADATA(gdth_ctr_tab[hanum]);
4504 memset(cmd, 0, sizeof(gdth_cmd_str));
4506 for (i = 0; i < MAX_HDRIVES; ++i) {
4507 if (!ha->hdr[i].present) {
4508 rsc->hdr_list[i].bus = 0xff;
4511 rsc->hdr_list[i].bus = ha->virt_bus;
4512 rsc->hdr_list[i].target = i;
4513 rsc->hdr_list[i].lun = 0;
4514 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
4515 if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
4516 cmd->Service = CACHESERVICE;
4517 cmd->OpCode = GDT_CLUST_INFO;
4518 if (ha->cache_feat & GDT_64BIT)
4519 cmd->u.cache64.DeviceNo = i;
4521 cmd->u.cache.DeviceNo = i;
4522 if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
4523 rsc->hdr_list[i].cluster_type = cluster_type;
4527 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
4538 static int ioc_rescan(void __user *arg, char *cmnd)
4540 gdth_ioctl_rescan *rsc;
4542 ushort i, status, hdr_cnt;
4544 int hanum, cyls, hds, secs;
4549 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
4550 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
4554 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
4555 rsc->ionode >= gdth_ctr_count) {
4559 hanum = rsc->ionode;
4560 ha = HADATA(gdth_ctr_tab[hanum]);
4561 memset(cmd, 0, sizeof(gdth_cmd_str));
4563 if (rsc->flag == 0) {
4564 /* old method: re-init. cache service */
4565 cmd->Service = CACHESERVICE;
4566 if (ha->cache_feat & GDT_64BIT) {
4567 cmd->OpCode = GDT_X_INIT_HOST;
4568 cmd->u.cache64.DeviceNo = LINUX_OS;
4570 cmd->OpCode = GDT_INIT;
4571 cmd->u.cache.DeviceNo = LINUX_OS;
4574 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4576 hdr_cnt = (status == S_OK ? (ushort)info : 0);
4582 for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
4583 cmd->Service = CACHESERVICE;
4584 cmd->OpCode = GDT_INFO;
4585 if (ha->cache_feat & GDT_64BIT)
4586 cmd->u.cache64.DeviceNo = i;
4588 cmd->u.cache.DeviceNo = i;
4590 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4592 spin_lock_irqsave(&ha->smp_lock, flags);
4593 rsc->hdr_list[i].bus = ha->virt_bus;
4594 rsc->hdr_list[i].target = i;
4595 rsc->hdr_list[i].lun = 0;
4596 if (status != S_OK) {
4597 ha->hdr[i].present = FALSE;
4599 ha->hdr[i].present = TRUE;
4600 ha->hdr[i].size = info;
4601 /* evaluate mapping */
4602 ha->hdr[i].size &= ~SECS32;
4603 gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
4604 ha->hdr[i].heads = hds;
4605 ha->hdr[i].secs = secs;
4607 ha->hdr[i].size = cyls * hds * secs;
4609 spin_unlock_irqrestore(&ha->smp_lock, flags);
4613 /* extended info, if GDT_64BIT, for drives > 2 TB */
4614 /* but we need ha->info2, not yet stored in scp->SCp */
4616 /* devtype, cluster info, R/W attribs */
4617 cmd->Service = CACHESERVICE;
4618 cmd->OpCode = GDT_DEVTYPE;
4619 if (ha->cache_feat & GDT_64BIT)
4620 cmd->u.cache64.DeviceNo = i;
4622 cmd->u.cache.DeviceNo = i;
4624 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4626 spin_lock_irqsave(&ha->smp_lock, flags);
4627 ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
4628 spin_unlock_irqrestore(&ha->smp_lock, flags);
4630 cmd->Service = CACHESERVICE;
4631 cmd->OpCode = GDT_CLUST_INFO;
4632 if (ha->cache_feat & GDT_64BIT)
4633 cmd->u.cache64.DeviceNo = i;
4635 cmd->u.cache.DeviceNo = i;
4637 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4639 spin_lock_irqsave(&ha->smp_lock, flags);
4640 ha->hdr[i].cluster_type =
4641 ((status == S_OK && !shared_access) ? (ushort)info : 0);
4642 spin_unlock_irqrestore(&ha->smp_lock, flags);
4643 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
4645 cmd->Service = CACHESERVICE;
4646 cmd->OpCode = GDT_RW_ATTRIBS;
4647 if (ha->cache_feat & GDT_64BIT)
4648 cmd->u.cache64.DeviceNo = i;
4650 cmd->u.cache.DeviceNo = i;
4652 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4654 spin_lock_irqsave(&ha->smp_lock, flags);
4655 ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
4656 spin_unlock_irqrestore(&ha->smp_lock, flags);
4659 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
4670 static int gdth_ioctl(struct inode *inode, struct file *filep,
4671 unsigned int cmd, unsigned long arg)
4676 char cmnd[MAX_COMMAND_SIZE];
4677 void __user *argp = (void __user *)arg;
4679 memset(cmnd, 0xff, 12);
4681 TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
4684 case GDTIOCTL_CTRCNT:
4686 int cnt = gdth_ctr_count;
4687 if (put_user(cnt, (int __user *)argp))
4692 case GDTIOCTL_DRVERS:
4694 int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
4695 if (put_user(ver, (int __user *)argp))
4700 case GDTIOCTL_OSVERS:
4702 gdth_ioctl_osvers osv;
4704 osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
4705 osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
4706 osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
4707 if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
4712 case GDTIOCTL_CTRTYPE:
4714 gdth_ioctl_ctrtype ctrt;
4716 if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
4717 ctrt.ionode >= gdth_ctr_count)
4719 ha = HADATA(gdth_ctr_tab[ctrt.ionode]);
4720 if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
4721 ctrt.type = (unchar)((ha->stype>>20) - 0x10);
4723 if (ha->type != GDT_PCIMPR) {
4724 ctrt.type = (unchar)((ha->stype<<4) + 6);
4727 (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
4728 if (ha->stype >= 0x300)
4729 ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
4731 ctrt.ext_type = 0x6000 | ha->stype;
4733 ctrt.device_id = ha->pdev->device;
4734 ctrt.sub_device_id = ha->pdev->subsystem_device;
4736 ctrt.info = ha->brd_phys;
4737 ctrt.oem_id = ha->oem_id;
4738 if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
4743 case GDTIOCTL_GENERAL:
4744 return ioc_general(argp, cmnd);
4746 case GDTIOCTL_EVENT:
4747 return ioc_event(argp);
4749 case GDTIOCTL_LOCKDRV:
4750 return ioc_lockdrv(argp);
4752 case GDTIOCTL_LOCKCHN:
4754 gdth_ioctl_lockchn lchn;
4757 if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
4758 lchn.ionode >= gdth_ctr_count)
4760 ha = HADATA(gdth_ctr_tab[lchn.ionode]);
4763 if (i < ha->bus_cnt) {
4765 spin_lock_irqsave(&ha->smp_lock, flags);
4766 ha->raw[i].lock = 1;
4767 spin_unlock_irqrestore(&ha->smp_lock, flags);
4768 for (j = 0; j < ha->tid_cnt; ++j) {
4769 gdth_wait_completion(lchn.ionode, i, j);
4770 gdth_stop_timeout(lchn.ionode, i, j);
4773 spin_lock_irqsave(&ha->smp_lock, flags);
4774 ha->raw[i].lock = 0;
4775 spin_unlock_irqrestore(&ha->smp_lock, flags);
4776 for (j = 0; j < ha->tid_cnt; ++j) {
4777 gdth_start_timeout(lchn.ionode, i, j);
4778 gdth_next(lchn.ionode);
4785 case GDTIOCTL_RESCAN:
4786 return ioc_rescan(argp, cmnd);
4788 case GDTIOCTL_HDRLIST:
4789 return ioc_hdrlist(argp, cmnd);
4791 case GDTIOCTL_RESET_BUS:
4793 gdth_ioctl_reset res;
4796 if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
4797 res.ionode >= gdth_ctr_count)
4800 ha = HADATA(gdth_ctr_tab[hanum]);
4802 scp = kzalloc(sizeof(*scp), GFP_KERNEL);
4805 scp->device = ha->sdev;
4808 scp->device->channel = virt_ctr ? 0 : res.number;
4809 rval = gdth_eh_bus_reset(scp);
4810 res.status = (rval == SUCCESS ? S_OK : S_GENERR);
4813 if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
4818 case GDTIOCTL_RESET_DRV:
4819 return ioc_resetdrv(argp, cmnd);
4829 static void gdth_flush(int hanum)
4833 gdth_cmd_str gdtcmd;
4834 char cmnd[MAX_COMMAND_SIZE];
4835 memset(cmnd, 0xff, MAX_COMMAND_SIZE);
4837 TRACE2(("gdth_flush() hanum %d\n",hanum));
4838 ha = HADATA(gdth_ctr_tab[hanum]);
4840 for (i = 0; i < MAX_HDRIVES; ++i) {
4841 if (ha->hdr[i].present) {
4842 gdtcmd.BoardNode = LOCALBOARD;
4843 gdtcmd.Service = CACHESERVICE;
4844 gdtcmd.OpCode = GDT_FLUSH;
4845 if (ha->cache_feat & GDT_64BIT) {
4846 gdtcmd.u.cache64.DeviceNo = i;
4847 gdtcmd.u.cache64.BlockNo = 1;
4848 gdtcmd.u.cache64.sg_canz = 0;
4850 gdtcmd.u.cache.DeviceNo = i;
4851 gdtcmd.u.cache.BlockNo = 1;
4852 gdtcmd.u.cache.sg_canz = 0;
4854 TRACE2(("gdth_flush(): flush ha %d drive %d\n", hanum, i));
4856 gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 30, NULL);
4861 /* shutdown routine */
4862 static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
4866 gdth_cmd_str gdtcmd;
4867 char cmnd[MAX_COMMAND_SIZE];
4870 if (notifier_disabled)
4873 TRACE2(("gdth_halt() event %d\n",(int)event));
4874 if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
4877 notifier_disabled = 1;
4878 printk("GDT-HA: Flushing all host drives .. ");
4879 for (hanum = 0; hanum < gdth_ctr_count; ++hanum) {
4883 /* controller reset */
4884 memset(cmnd, 0xff, MAX_COMMAND_SIZE);
4885 gdtcmd.BoardNode = LOCALBOARD;
4886 gdtcmd.Service = CACHESERVICE;
4887 gdtcmd.OpCode = GDT_RESET;
4888 TRACE2(("gdth_halt(): reset controller %d\n", hanum));
4889 gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 10, NULL);
4894 #ifdef GDTH_STATISTICS
4895 del_timer(&gdth_timer);
4901 static int gdth_slave_configure(struct scsi_device *sdev)
4903 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
4904 sdev->skip_ms_page_3f = 1;
4905 sdev->skip_ms_page_8 = 1;
4909 static struct scsi_host_template driver_template = {
4910 .proc_name = "gdth",
4911 .proc_info = gdth_proc_info,
4912 .name = "GDT SCSI Disk Array Controller",
4913 .detect = gdth_detect,
4914 .release = gdth_release,
4916 .queuecommand = gdth_queuecommand,
4917 .eh_bus_reset_handler = gdth_eh_bus_reset,
4918 .bios_param = gdth_bios_param,
4919 .can_queue = GDTH_MAXCMDS,
4920 .slave_configure = gdth_slave_configure,
4922 .sg_tablesize = GDTH_MAXSG,
4923 .cmd_per_lun = GDTH_MAXC_P_L,
4924 .unchecked_isa_dma = 1,
4925 .use_clustering = ENABLE_CLUSTERING,
4929 static int gdth_isa_probe_one(struct scsi_host_template *shtp, ulong32 isa_bios)
4931 struct Scsi_Host *shp;
4933 dma_addr_t scratch_dma_handle = 0;
4934 int error, hanum, i;
4937 if (!gdth_search_isa(isa_bios))
4940 shp = scsi_register(shtp, sizeof(gdth_ext_str));
4946 if (!gdth_init_isa(isa_bios,ha))
4949 /* controller found and initialized */
4950 printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
4951 isa_bios, ha->irq, ha->drq);
4953 error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
4955 printk("GDT-ISA: Unable to allocate IRQ\n");
4959 error = request_dma(ha->drq, "gdth");
4961 printk("GDT-ISA: Unable to allocate DMA channel\n");
4965 set_dma_mode(ha->drq,DMA_MODE_CASCADE);
4966 enable_dma(ha->drq);
4967 shp->unchecked_isa_dma = 1;
4969 shp->dma_channel = ha->drq;
4970 hanum = gdth_ctr_count;
4971 gdth_ctr_tab[gdth_ctr_count++] = shp;
4972 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4974 NUMDATA(shp)->hanum = (ushort)hanum;
4975 NUMDATA(shp)->busnum= 0;
4977 ha->pccb = CMDDATA(shp);
4983 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4984 &scratch_dma_handle);
4986 goto out_dec_counters;
4987 ha->scratch_phys = scratch_dma_handle;
4989 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4990 &scratch_dma_handle);
4992 goto out_free_pscratch;
4993 ha->msg_phys = scratch_dma_handle;
4996 ha->coal_stat = pci_alloc_consistent(ha->pdev,
4997 sizeof(gdth_coal_status) * MAXOFFSETS,
4998 &scratch_dma_handle);
5001 ha->coal_stat_phys = scratch_dma_handle;
5004 ha->scratch_busy = FALSE;
5005 ha->req_first = NULL;
5006 ha->tid_cnt = MAX_HDRIVES;
5007 if (max_ids > 0 && max_ids < ha->tid_cnt)
5008 ha->tid_cnt = max_ids;
5009 for (i = 0; i < GDTH_MAXCMDS; ++i)
5010 ha->cmd_tab[i].cmnd = UNUSED_CMND;
5011 ha->scan_mode = rescan ? 0x10 : 0;
5014 if (!gdth_search_drives(hanum)) {
5015 printk("GDT-ISA: Error during device scan\n");
5016 goto out_free_coal_stat;
5019 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
5020 hdr_channel = ha->bus_cnt;
5021 ha->virt_bus = hdr_channel;
5023 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
5024 shp->max_cmd_len = 16;
5026 shp->max_id = ha->tid_cnt;
5027 shp->max_lun = MAXLUN;
5028 shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
5031 /* register addit. SCSI channels as virtual controllers */
5032 for (b = 1; b < ha->bus_cnt + 1; ++b) {
5033 shp = scsi_register(shtp,sizeof(gdth_num_str));
5034 shp->unchecked_isa_dma = 1;
5036 shp->dma_channel = ha->drq;
5037 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
5038 NUMDATA(shp)->hanum = (ushort)hanum;
5039 NUMDATA(shp)->busnum = b;
5043 spin_lock_init(&ha->smp_lock);
5044 gdth_enable_int(hanum);
5050 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
5051 ha->coal_stat, ha->coal_stat_phys);
5054 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
5055 ha->pmsg, ha->msg_phys);
5057 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
5058 ha->pscratch, ha->scratch_phys);
5063 free_irq(ha->irq, ha);
5065 scsi_unregister(shp);
5068 #endif /* CONFIG_ISA */
5071 static int gdth_eisa_probe_one(struct scsi_host_template *shtp,
5074 struct Scsi_Host *shp;
5076 dma_addr_t scratch_dma_handle = 0;
5077 int error, hanum, i;
5080 if (!gdth_search_eisa(eisa_slot))
5083 shp = scsi_register(shtp,sizeof(gdth_ext_str));
5089 if (!gdth_init_eisa(eisa_slot,ha))
5092 /* controller found and initialized */
5093 printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
5094 eisa_slot >> 12, ha->irq);
5096 error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
5098 printk("GDT-EISA: Unable to allocate IRQ\n");
5102 shp->unchecked_isa_dma = 0;
5104 shp->dma_channel = 0xff;
5105 hanum = gdth_ctr_count;
5106 gdth_ctr_tab[gdth_ctr_count++] = shp;
5107 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
5109 NUMDATA(shp)->hanum = (ushort)hanum;
5110 NUMDATA(shp)->busnum= 0;
5111 TRACE2(("EISA detect Bus 0: hanum %d\n",
5112 NUMDATA(shp)->hanum));
5114 ha->pccb = CMDDATA(shp);
5120 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
5121 &scratch_dma_handle);
5124 ha->scratch_phys = scratch_dma_handle;
5126 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
5127 &scratch_dma_handle);
5129 goto out_free_pscratch;
5130 ha->msg_phys = scratch_dma_handle;
5133 ha->coal_stat = pci_alloc_consistent(ha->pdev,
5134 sizeof(gdth_coal_status) * MAXOFFSETS,
5135 &scratch_dma_handle);
5138 ha->coal_stat_phys = scratch_dma_handle;
5141 ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
5142 sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
5144 goto out_free_coal_stat;
5146 ha->scratch_busy = FALSE;
5147 ha->req_first = NULL;
5148 ha->tid_cnt = MAX_HDRIVES;
5149 if (max_ids > 0 && max_ids < ha->tid_cnt)
5150 ha->tid_cnt = max_ids;
5151 for (i = 0; i < GDTH_MAXCMDS; ++i)
5152 ha->cmd_tab[i].cmnd = UNUSED_CMND;
5153 ha->scan_mode = rescan ? 0x10 : 0;
5155 if (!gdth_search_drives(hanum)) {
5156 printk("GDT-EISA: Error during device scan\n");
5158 goto out_free_ccb_phys;
5161 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
5162 hdr_channel = ha->bus_cnt;
5163 ha->virt_bus = hdr_channel;
5165 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
5166 shp->max_cmd_len = 16;
5168 shp->max_id = ha->tid_cnt;
5169 shp->max_lun = MAXLUN;
5170 shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
5173 /* register addit. SCSI channels as virtual controllers */
5174 for (b = 1; b < ha->bus_cnt + 1; ++b) {
5175 shp = scsi_register(shtp,sizeof(gdth_num_str));
5176 shp->unchecked_isa_dma = 0;
5178 shp->dma_channel = 0xff;
5179 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
5180 NUMDATA(shp)->hanum = (ushort)hanum;
5181 NUMDATA(shp)->busnum = b;
5185 spin_lock_init(&ha->smp_lock);
5186 gdth_enable_int(hanum);
5190 pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
5191 PCI_DMA_BIDIRECTIONAL);
5194 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
5195 ha->coal_stat, ha->coal_stat_phys);
5198 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
5199 ha->pmsg, ha->msg_phys);
5201 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
5202 ha->pscratch, ha->scratch_phys);
5204 free_irq(ha->irq, ha);
5208 scsi_unregister(shp);
5211 #endif /* CONFIG_EISA */
5214 static int gdth_pci_probe_one(struct scsi_host_template *shtp,
5215 gdth_pci_str *pcistr, int ctr)
5217 struct Scsi_Host *shp;
5219 dma_addr_t scratch_dma_handle = 0;
5220 int error, hanum, i;
5223 shp = scsi_register(shtp,sizeof(gdth_ext_str));
5229 if (!gdth_init_pci(&pcistr[ctr],ha))
5232 /* controller found and initialized */
5233 printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
5234 pcistr[ctr].pdev->bus->number,
5235 PCI_SLOT(pcistr[ctr].pdev->devfn),
5238 error = request_irq(ha->irq, gdth_interrupt,
5239 IRQF_DISABLED|IRQF_SHARED, "gdth", ha);
5241 printk("GDT-PCI: Unable to allocate IRQ\n");
5245 shp->unchecked_isa_dma = 0;
5247 shp->dma_channel = 0xff;
5248 hanum = gdth_ctr_count;
5249 gdth_ctr_tab[gdth_ctr_count++] = shp;
5250 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
5252 NUMDATA(shp)->hanum = (ushort)hanum;
5253 NUMDATA(shp)->busnum= 0;
5255 ha->pccb = CMDDATA(shp);
5260 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
5261 &scratch_dma_handle);
5264 ha->scratch_phys = scratch_dma_handle;
5266 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
5267 &scratch_dma_handle);
5269 goto out_free_pscratch;
5270 ha->msg_phys = scratch_dma_handle;
5273 ha->coal_stat = pci_alloc_consistent(ha->pdev,
5274 sizeof(gdth_coal_status) * MAXOFFSETS,
5275 &scratch_dma_handle);
5278 ha->coal_stat_phys = scratch_dma_handle;
5281 ha->scratch_busy = FALSE;
5282 ha->req_first = NULL;
5283 ha->tid_cnt = pcistr[ctr].pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
5284 if (max_ids > 0 && max_ids < ha->tid_cnt)
5285 ha->tid_cnt = max_ids;
5286 for (i = 0; i < GDTH_MAXCMDS; ++i)
5287 ha->cmd_tab[i].cmnd = UNUSED_CMND;
5288 ha->scan_mode = rescan ? 0x10 : 0;
5291 if (!gdth_search_drives(hanum)) {
5292 printk("GDT-PCI %d: Error during device scan\n", hanum);
5293 goto out_free_coal_stat;
5296 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
5297 hdr_channel = ha->bus_cnt;
5298 ha->virt_bus = hdr_channel;
5300 /* 64-bit DMA only supported from FW >= x.43 */
5301 if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) ||
5302 !ha->dma64_support) {
5303 if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
5304 printk(KERN_WARNING "GDT-PCI %d: "
5305 "Unable to set 32-bit DMA\n", hanum);
5306 goto out_free_coal_stat;
5309 shp->max_cmd_len = 16;
5310 if (!pci_set_dma_mask(pcistr[ctr].pdev, DMA_64BIT_MASK)) {
5311 printk("GDT-PCI %d: 64-bit DMA enabled\n", hanum);
5312 } else if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
5313 printk(KERN_WARNING "GDT-PCI %d: "
5314 "Unable to set 64/32-bit DMA\n", hanum);
5315 goto out_free_coal_stat;
5319 shp->max_id = ha->tid_cnt;
5320 shp->max_lun = MAXLUN;
5321 shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
5324 /* register addit. SCSI channels as virtual controllers */
5325 for (b = 1; b < ha->bus_cnt + 1; ++b) {
5326 shp = scsi_register(shtp,sizeof(gdth_num_str));
5327 shp->unchecked_isa_dma = 0;
5329 shp->dma_channel = 0xff;
5330 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
5331 NUMDATA(shp)->hanum = (ushort)hanum;
5332 NUMDATA(shp)->busnum = b;
5336 spin_lock_init(&ha->smp_lock);
5337 gdth_enable_int(hanum);
5342 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
5343 ha->coal_stat, ha->coal_stat_phys);
5346 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
5347 ha->pmsg, ha->msg_phys);
5349 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
5350 ha->pscratch, ha->scratch_phys);
5352 free_irq(ha->irq, ha);
5356 scsi_unregister(shp);
5359 #endif /* CONFIG_PCI */
5361 #include "scsi_module.c"
5363 __setup("gdth=", option_setup);