2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "1.2"
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
59 AHCI_CMD_SLOT_SZ = 32 * 32,
61 AHCI_CMD_TBL_HDR = 0x80,
62 AHCI_CMD_TBL_CDB = 0x40,
63 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
64 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
66 AHCI_IRQ_ON_SG = (1 << 31),
67 AHCI_CMD_ATAPI = (1 << 5),
68 AHCI_CMD_WRITE = (1 << 6),
69 AHCI_CMD_RESET = (1 << 8),
70 AHCI_CMD_CLR_BUSY = (1 << 10),
72 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
76 /* global controller registers */
77 HOST_CAP = 0x00, /* host capabilities */
78 HOST_CTL = 0x04, /* global host control */
79 HOST_IRQ_STAT = 0x08, /* interrupt status */
80 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
81 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
84 HOST_RESET = (1 << 0), /* reset controller; self-clear */
85 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
86 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
89 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
90 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
92 /* registers for each SATA port */
93 PORT_LST_ADDR = 0x00, /* command list DMA addr */
94 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
95 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
96 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
97 PORT_IRQ_STAT = 0x10, /* interrupt status */
98 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
99 PORT_CMD = 0x18, /* port command */
100 PORT_TFDATA = 0x20, /* taskfile data */
101 PORT_SIG = 0x24, /* device TF signature */
102 PORT_CMD_ISSUE = 0x38, /* command issue */
103 PORT_SCR = 0x28, /* SATA phy register block */
104 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
105 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
106 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
107 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
109 /* PORT_IRQ_{STAT,MASK} bits */
110 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
111 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
112 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
113 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
114 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
115 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
116 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
117 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
119 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
120 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
121 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
122 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
123 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
124 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
125 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
126 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
127 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
129 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
131 PORT_IRQ_HBUS_DATA_ERR |
133 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
134 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
135 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
136 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
137 PORT_IRQ_D2H_REG_FIS,
140 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
141 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
142 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
143 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
144 PORT_CMD_CLO = (1 << 3), /* Command list override */
145 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
146 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
147 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
149 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
150 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
151 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
153 /* hpriv->flags bits */
154 AHCI_FLAG_MSI = (1 << 0),
157 struct ahci_cmd_hdr {
172 struct ahci_host_priv {
174 u32 cap; /* cache of HOST_CAP register */
175 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
178 struct ahci_port_priv {
179 struct ahci_cmd_hdr *cmd_slot;
180 dma_addr_t cmd_slot_dma;
182 dma_addr_t cmd_tbl_dma;
183 struct ahci_sg *cmd_tbl_sg;
185 dma_addr_t rx_fis_dma;
188 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
189 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
190 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
191 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
192 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
193 static void ahci_phy_reset(struct ata_port *ap);
194 static void ahci_irq_clear(struct ata_port *ap);
195 static void ahci_eng_timeout(struct ata_port *ap);
196 static int ahci_port_start(struct ata_port *ap);
197 static void ahci_port_stop(struct ata_port *ap);
198 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
199 static void ahci_qc_prep(struct ata_queued_cmd *qc);
200 static u8 ahci_check_status(struct ata_port *ap);
201 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
202 static void ahci_remove_one (struct pci_dev *pdev);
204 static struct scsi_host_template ahci_sht = {
205 .module = THIS_MODULE,
207 .ioctl = ata_scsi_ioctl,
208 .queuecommand = ata_scsi_queuecmd,
209 .eh_strategy_handler = ata_scsi_error,
210 .can_queue = ATA_DEF_QUEUE,
211 .this_id = ATA_SHT_THIS_ID,
212 .sg_tablesize = AHCI_MAX_SG,
213 .max_sectors = ATA_MAX_SECTORS,
214 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
215 .emulated = ATA_SHT_EMULATED,
216 .use_clustering = AHCI_USE_CLUSTERING,
217 .proc_name = DRV_NAME,
218 .dma_boundary = AHCI_DMA_BOUNDARY,
219 .slave_configure = ata_scsi_slave_config,
220 .bios_param = ata_std_bios_param,
223 static const struct ata_port_operations ahci_ops = {
224 .port_disable = ata_port_disable,
226 .check_status = ahci_check_status,
227 .check_altstatus = ahci_check_status,
228 .dev_select = ata_noop_dev_select,
230 .tf_read = ahci_tf_read,
232 .phy_reset = ahci_phy_reset,
234 .qc_prep = ahci_qc_prep,
235 .qc_issue = ahci_qc_issue,
237 .eng_timeout = ahci_eng_timeout,
239 .irq_handler = ahci_interrupt,
240 .irq_clear = ahci_irq_clear,
242 .scr_read = ahci_scr_read,
243 .scr_write = ahci_scr_write,
245 .port_start = ahci_port_start,
246 .port_stop = ahci_port_stop,
249 static const struct ata_port_info ahci_port_info[] = {
253 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
254 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
256 .pio_mask = 0x1f, /* pio0-4 */
257 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
258 .port_ops = &ahci_ops,
262 static const struct pci_device_id ahci_pci_tbl[] = {
263 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
264 board_ahci }, /* ICH6 */
265 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
266 board_ahci }, /* ICH6M */
267 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
268 board_ahci }, /* ICH7 */
269 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
270 board_ahci }, /* ICH7M */
271 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
272 board_ahci }, /* ICH7R */
273 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
274 board_ahci }, /* ULi M5288 */
275 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
276 board_ahci }, /* ESB2 */
277 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
278 board_ahci }, /* ESB2 */
279 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
280 board_ahci }, /* ESB2 */
281 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
282 board_ahci }, /* ICH7-M DH */
283 { PCI_VENDOR_ID_INTEL, 0x2821, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
284 board_ahci }, /* ICH8 */
285 { PCI_VENDOR_ID_INTEL, 0x2822, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
286 board_ahci }, /* ICH8 */
287 { PCI_VENDOR_ID_INTEL, 0x2824, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
288 board_ahci }, /* ICH8 */
289 { PCI_VENDOR_ID_INTEL, 0x2829, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
290 board_ahci }, /* ICH8M */
291 { PCI_VENDOR_ID_INTEL, 0x282a, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
292 board_ahci }, /* ICH8M */
293 { 0x197b, 0x2360, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
294 board_ahci }, /* JMicron JMB360 */
295 { } /* terminate list */
299 static struct pci_driver ahci_pci_driver = {
301 .id_table = ahci_pci_tbl,
302 .probe = ahci_init_one,
303 .remove = ahci_remove_one,
307 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
309 return base + 0x100 + (port * 0x80);
312 static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
314 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
317 static int ahci_port_start(struct ata_port *ap)
319 struct device *dev = ap->host_set->dev;
320 struct ahci_host_priv *hpriv = ap->host_set->private_data;
321 struct ahci_port_priv *pp;
322 void __iomem *mmio = ap->host_set->mmio_base;
323 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
328 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
331 memset(pp, 0, sizeof(*pp));
333 rc = ata_pad_alloc(ap, dev);
339 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
341 ata_pad_free(ap, dev);
345 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
348 * First item in chunk of DMA memory: 32-slot command table,
349 * 32 bytes each in size
352 pp->cmd_slot_dma = mem_dma;
354 mem += AHCI_CMD_SLOT_SZ;
355 mem_dma += AHCI_CMD_SLOT_SZ;
358 * Second item: Received-FIS area
361 pp->rx_fis_dma = mem_dma;
363 mem += AHCI_RX_FIS_SZ;
364 mem_dma += AHCI_RX_FIS_SZ;
367 * Third item: data area for storing a single command
368 * and its scatter-gather table
371 pp->cmd_tbl_dma = mem_dma;
373 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
375 ap->private_data = pp;
377 if (hpriv->cap & HOST_CAP_64)
378 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
379 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
380 readl(port_mmio + PORT_LST_ADDR); /* flush */
382 if (hpriv->cap & HOST_CAP_64)
383 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
384 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
385 readl(port_mmio + PORT_FIS_ADDR); /* flush */
387 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
388 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
389 PORT_CMD_START, port_mmio + PORT_CMD);
390 readl(port_mmio + PORT_CMD); /* flush */
396 static void ahci_port_stop(struct ata_port *ap)
398 struct device *dev = ap->host_set->dev;
399 struct ahci_port_priv *pp = ap->private_data;
400 void __iomem *mmio = ap->host_set->mmio_base;
401 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
404 tmp = readl(port_mmio + PORT_CMD);
405 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
406 writel(tmp, port_mmio + PORT_CMD);
407 readl(port_mmio + PORT_CMD); /* flush */
409 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
410 * this is slightly incorrect.
414 ap->private_data = NULL;
415 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
416 pp->cmd_slot, pp->cmd_slot_dma);
417 ata_pad_free(ap, dev);
421 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
426 case SCR_STATUS: sc_reg = 0; break;
427 case SCR_CONTROL: sc_reg = 1; break;
428 case SCR_ERROR: sc_reg = 2; break;
429 case SCR_ACTIVE: sc_reg = 3; break;
434 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
438 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
444 case SCR_STATUS: sc_reg = 0; break;
445 case SCR_CONTROL: sc_reg = 1; break;
446 case SCR_ERROR: sc_reg = 2; break;
447 case SCR_ACTIVE: sc_reg = 3; break;
452 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
455 static int ahci_stop_engine(struct ata_port *ap)
457 void __iomem *mmio = ap->host_set->mmio_base;
458 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
462 tmp = readl(port_mmio + PORT_CMD);
463 tmp &= ~PORT_CMD_START;
464 writel(tmp, port_mmio + PORT_CMD);
466 /* wait for engine to stop. TODO: this could be
467 * as long as 500 msec
471 tmp = readl(port_mmio + PORT_CMD);
472 if ((tmp & PORT_CMD_LIST_ON) == 0)
480 static void ahci_start_engine(struct ata_port *ap)
482 void __iomem *mmio = ap->host_set->mmio_base;
483 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
486 tmp = readl(port_mmio + PORT_CMD);
487 tmp |= PORT_CMD_START;
488 writel(tmp, port_mmio + PORT_CMD);
489 readl(port_mmio + PORT_CMD); /* flush */
492 static unsigned int ahci_dev_classify(struct ata_port *ap)
494 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
495 struct ata_taskfile tf;
498 tmp = readl(port_mmio + PORT_SIG);
499 tf.lbah = (tmp >> 24) & 0xff;
500 tf.lbam = (tmp >> 16) & 0xff;
501 tf.lbal = (tmp >> 8) & 0xff;
502 tf.nsect = (tmp) & 0xff;
504 return ata_dev_classify(&tf);
507 static void ahci_phy_reset(struct ata_port *ap)
509 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
510 struct ata_device *dev = &ap->device[0];
513 ahci_stop_engine(ap);
514 __sata_phy_reset(ap);
515 ahci_start_engine(ap);
517 if (ap->flags & ATA_FLAG_PORT_DISABLED)
520 dev->class = ahci_dev_classify(ap);
521 if (!ata_dev_present(dev)) {
522 ata_port_disable(ap);
526 /* Make sure port's ATAPI bit is set appropriately */
527 new_tmp = tmp = readl(port_mmio + PORT_CMD);
528 if (dev->class == ATA_DEV_ATAPI)
529 new_tmp |= PORT_CMD_ATAPI;
531 new_tmp &= ~PORT_CMD_ATAPI;
532 if (new_tmp != tmp) {
533 writel(new_tmp, port_mmio + PORT_CMD);
534 readl(port_mmio + PORT_CMD); /* flush */
538 static u8 ahci_check_status(struct ata_port *ap)
540 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
542 return readl(mmio + PORT_TFDATA) & 0xFF;
545 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
547 struct ahci_port_priv *pp = ap->private_data;
548 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
550 ata_tf_from_fis(d2h_fis, tf);
553 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc)
555 struct ahci_port_priv *pp = qc->ap->private_data;
556 struct scatterlist *sg;
557 struct ahci_sg *ahci_sg;
558 unsigned int n_sg = 0;
563 * Next, the S/G list.
565 ahci_sg = pp->cmd_tbl_sg;
566 ata_for_each_sg(sg, qc) {
567 dma_addr_t addr = sg_dma_address(sg);
568 u32 sg_len = sg_dma_len(sg);
570 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
571 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
572 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
581 static void ahci_qc_prep(struct ata_queued_cmd *qc)
583 struct ata_port *ap = qc->ap;
584 struct ahci_port_priv *pp = ap->private_data;
586 const u32 cmd_fis_len = 5; /* five dwords */
590 * Fill in command slot information (currently only one slot,
591 * slot 0, is currently since we don't do queueing)
595 if (qc->tf.flags & ATA_TFLAG_WRITE)
596 opts |= AHCI_CMD_WRITE;
597 if (is_atapi_taskfile(&qc->tf))
598 opts |= AHCI_CMD_ATAPI;
600 pp->cmd_slot[0].opts = cpu_to_le32(opts);
601 pp->cmd_slot[0].status = 0;
602 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
603 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
606 * Fill in command table information. First, the header,
607 * a SATA Register - Host to Device command FIS.
609 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
610 if (opts & AHCI_CMD_ATAPI) {
611 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
612 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, ap->cdb_len);
615 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
618 n_elem = ahci_fill_sg(qc);
620 pp->cmd_slot[0].opts |= cpu_to_le32(n_elem << 16);
623 static void ahci_restart_port(struct ata_port *ap, u32 irq_stat)
625 void __iomem *mmio = ap->host_set->mmio_base;
626 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
629 if ((ap->device[0].class != ATA_DEV_ATAPI) ||
630 ((irq_stat & PORT_IRQ_TF_ERR) == 0))
631 printk(KERN_WARNING "ata%u: port reset, "
632 "p_is %x is %x pis %x cmd %x tf %x ss %x se %x\n",
635 readl(mmio + HOST_IRQ_STAT),
636 readl(port_mmio + PORT_IRQ_STAT),
637 readl(port_mmio + PORT_CMD),
638 readl(port_mmio + PORT_TFDATA),
639 readl(port_mmio + PORT_SCR_STAT),
640 readl(port_mmio + PORT_SCR_ERR));
643 ahci_stop_engine(ap);
645 /* clear SATA phy error, if any */
646 tmp = readl(port_mmio + PORT_SCR_ERR);
647 writel(tmp, port_mmio + PORT_SCR_ERR);
649 /* if DRQ/BSY is set, device needs to be reset.
650 * if so, issue COMRESET
652 tmp = readl(port_mmio + PORT_TFDATA);
653 if (tmp & (ATA_BUSY | ATA_DRQ)) {
654 writel(0x301, port_mmio + PORT_SCR_CTL);
655 readl(port_mmio + PORT_SCR_CTL); /* flush */
657 writel(0x300, port_mmio + PORT_SCR_CTL);
658 readl(port_mmio + PORT_SCR_CTL); /* flush */
662 ahci_start_engine(ap);
665 static void ahci_eng_timeout(struct ata_port *ap)
667 struct ata_host_set *host_set = ap->host_set;
668 void __iomem *mmio = host_set->mmio_base;
669 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
670 struct ata_queued_cmd *qc;
673 printk(KERN_WARNING "ata%u: handling error/timeout\n", ap->id);
675 spin_lock_irqsave(&host_set->lock, flags);
677 qc = ata_qc_from_tag(ap, ap->active_tag);
679 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
682 ahci_restart_port(ap, readl(port_mmio + PORT_IRQ_STAT));
683 qc->err_mask |= AC_ERR_TIMEOUT;
686 spin_unlock_irqrestore(&host_set->lock, flags);
689 ata_eh_qc_complete(qc);
692 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
694 void __iomem *mmio = ap->host_set->mmio_base;
695 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
696 u32 status, serr, ci;
698 serr = readl(port_mmio + PORT_SCR_ERR);
699 writel(serr, port_mmio + PORT_SCR_ERR);
701 status = readl(port_mmio + PORT_IRQ_STAT);
702 writel(status, port_mmio + PORT_IRQ_STAT);
704 ci = readl(port_mmio + PORT_CMD_ISSUE);
705 if (likely((ci & 0x1) == 0)) {
707 assert(qc->err_mask == 0);
713 if (status & PORT_IRQ_FATAL) {
714 unsigned int err_mask;
715 if (status & PORT_IRQ_TF_ERR)
716 err_mask = AC_ERR_DEV;
717 else if (status & PORT_IRQ_IF_ERR)
718 err_mask = AC_ERR_ATA_BUS;
720 err_mask = AC_ERR_HOST_BUS;
722 /* command processing has stopped due to error; restart */
723 ahci_restart_port(ap, status);
726 qc->err_mask |= err_mask;
734 static void ahci_irq_clear(struct ata_port *ap)
739 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
741 struct ata_host_set *host_set = dev_instance;
742 struct ahci_host_priv *hpriv;
743 unsigned int i, handled = 0;
745 u32 irq_stat, irq_ack = 0;
749 hpriv = host_set->private_data;
750 mmio = host_set->mmio_base;
752 /* sigh. 0xffffffff is a valid return from h/w */
753 irq_stat = readl(mmio + HOST_IRQ_STAT);
754 irq_stat &= hpriv->port_map;
758 spin_lock(&host_set->lock);
760 for (i = 0; i < host_set->n_ports; i++) {
763 if (!(irq_stat & (1 << i)))
766 ap = host_set->ports[i];
768 struct ata_queued_cmd *qc;
769 qc = ata_qc_from_tag(ap, ap->active_tag);
770 if (!ahci_host_intr(ap, qc))
771 if (ata_ratelimit()) {
772 struct pci_dev *pdev =
773 to_pci_dev(ap->host_set->dev);
774 dev_printk(KERN_WARNING, &pdev->dev,
775 "unhandled interrupt on port %u\n",
779 VPRINTK("port %u\n", i);
781 VPRINTK("port %u (no irq)\n", i);
782 if (ata_ratelimit()) {
783 struct pci_dev *pdev =
784 to_pci_dev(ap->host_set->dev);
785 dev_printk(KERN_WARNING, &pdev->dev,
786 "interrupt on disabled port %u\n", i);
794 writel(irq_ack, mmio + HOST_IRQ_STAT);
798 spin_unlock(&host_set->lock);
802 return IRQ_RETVAL(handled);
805 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
807 struct ata_port *ap = qc->ap;
808 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
810 writel(1, port_mmio + PORT_CMD_ISSUE);
811 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
816 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
817 unsigned int port_idx)
819 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
820 base = ahci_port_base_ul(base, port_idx);
821 VPRINTK("base now==0x%lx\n", base);
823 port->cmd_addr = base;
824 port->scr_addr = base + PORT_SCR;
829 static int ahci_host_init(struct ata_probe_ent *probe_ent)
831 struct ahci_host_priv *hpriv = probe_ent->private_data;
832 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
833 void __iomem *mmio = probe_ent->mmio_base;
835 unsigned int i, j, using_dac;
837 void __iomem *port_mmio;
839 cap_save = readl(mmio + HOST_CAP);
840 cap_save &= ( (1<<28) | (1<<17) );
841 cap_save |= (1 << 27);
843 /* global controller reset */
844 tmp = readl(mmio + HOST_CTL);
845 if ((tmp & HOST_RESET) == 0) {
846 writel(tmp | HOST_RESET, mmio + HOST_CTL);
847 readl(mmio + HOST_CTL); /* flush */
850 /* reset must complete within 1 second, or
851 * the hardware should be considered fried.
855 tmp = readl(mmio + HOST_CTL);
856 if (tmp & HOST_RESET) {
857 dev_printk(KERN_ERR, &pdev->dev,
858 "controller reset failed (0x%x)\n", tmp);
862 writel(HOST_AHCI_EN, mmio + HOST_CTL);
863 (void) readl(mmio + HOST_CTL); /* flush */
864 writel(cap_save, mmio + HOST_CAP);
865 writel(0xf, mmio + HOST_PORTS_IMPL);
866 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
868 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
871 pci_read_config_word(pdev, 0x92, &tmp16);
873 pci_write_config_word(pdev, 0x92, tmp16);
876 hpriv->cap = readl(mmio + HOST_CAP);
877 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
878 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
880 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
881 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
883 using_dac = hpriv->cap & HOST_CAP_64;
885 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
886 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
888 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
890 dev_printk(KERN_ERR, &pdev->dev,
891 "64-bit DMA enable failed\n");
896 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
898 dev_printk(KERN_ERR, &pdev->dev,
899 "32-bit DMA enable failed\n");
902 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
904 dev_printk(KERN_ERR, &pdev->dev,
905 "32-bit consistent DMA enable failed\n");
910 for (i = 0; i < probe_ent->n_ports; i++) {
911 #if 0 /* BIOSen initialize this incorrectly */
912 if (!(hpriv->port_map & (1 << i)))
916 port_mmio = ahci_port_base(mmio, i);
917 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
919 ahci_setup_port(&probe_ent->port[i],
920 (unsigned long) mmio, i);
922 /* make sure port is not active */
923 tmp = readl(port_mmio + PORT_CMD);
924 VPRINTK("PORT_CMD 0x%x\n", tmp);
925 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
926 PORT_CMD_FIS_RX | PORT_CMD_START)) {
927 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
928 PORT_CMD_FIS_RX | PORT_CMD_START);
929 writel(tmp, port_mmio + PORT_CMD);
930 readl(port_mmio + PORT_CMD); /* flush */
932 /* spec says 500 msecs for each bit, so
933 * this is slightly incorrect.
938 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
943 tmp = readl(port_mmio + PORT_SCR_STAT);
944 if ((tmp & 0xf) == 0x3)
949 tmp = readl(port_mmio + PORT_SCR_ERR);
950 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
951 writel(tmp, port_mmio + PORT_SCR_ERR);
953 /* ack any pending irq events for this port */
954 tmp = readl(port_mmio + PORT_IRQ_STAT);
955 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
957 writel(tmp, port_mmio + PORT_IRQ_STAT);
959 writel(1 << i, mmio + HOST_IRQ_STAT);
961 /* set irq mask (enables interrupts) */
962 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
965 tmp = readl(mmio + HOST_CTL);
966 VPRINTK("HOST_CTL 0x%x\n", tmp);
967 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
968 tmp = readl(mmio + HOST_CTL);
969 VPRINTK("HOST_CTL 0x%x\n", tmp);
971 pci_set_master(pdev);
976 static void ahci_print_info(struct ata_probe_ent *probe_ent)
978 struct ahci_host_priv *hpriv = probe_ent->private_data;
979 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
980 void __iomem *mmio = probe_ent->mmio_base;
981 u32 vers, cap, impl, speed;
986 vers = readl(mmio + HOST_VERSION);
988 impl = hpriv->port_map;
990 speed = (cap >> 20) & 0xf;
998 pci_read_config_word(pdev, 0x0a, &cc);
1001 else if (cc == 0x0106)
1003 else if (cc == 0x0104)
1008 dev_printk(KERN_INFO, &pdev->dev,
1009 "AHCI %02x%02x.%02x%02x "
1010 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1013 (vers >> 24) & 0xff,
1014 (vers >> 16) & 0xff,
1018 ((cap >> 8) & 0x1f) + 1,
1024 dev_printk(KERN_INFO, &pdev->dev,
1030 cap & (1 << 31) ? "64bit " : "",
1031 cap & (1 << 30) ? "ncq " : "",
1032 cap & (1 << 28) ? "ilck " : "",
1033 cap & (1 << 27) ? "stag " : "",
1034 cap & (1 << 26) ? "pm " : "",
1035 cap & (1 << 25) ? "led " : "",
1037 cap & (1 << 24) ? "clo " : "",
1038 cap & (1 << 19) ? "nz " : "",
1039 cap & (1 << 18) ? "only " : "",
1040 cap & (1 << 17) ? "pmp " : "",
1041 cap & (1 << 15) ? "pio " : "",
1042 cap & (1 << 14) ? "slum " : "",
1043 cap & (1 << 13) ? "part " : ""
1047 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1049 static int printed_version;
1050 struct ata_probe_ent *probe_ent = NULL;
1051 struct ahci_host_priv *hpriv;
1053 void __iomem *mmio_base;
1054 unsigned int board_idx = (unsigned int) ent->driver_data;
1055 int have_msi, pci_dev_busy = 0;
1060 if (!printed_version++)
1061 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1063 rc = pci_enable_device(pdev);
1067 rc = pci_request_regions(pdev, DRV_NAME);
1073 if (pci_enable_msi(pdev) == 0)
1080 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1081 if (probe_ent == NULL) {
1086 memset(probe_ent, 0, sizeof(*probe_ent));
1087 probe_ent->dev = pci_dev_to_dev(pdev);
1088 INIT_LIST_HEAD(&probe_ent->node);
1090 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1091 if (mmio_base == NULL) {
1093 goto err_out_free_ent;
1095 base = (unsigned long) mmio_base;
1097 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1100 goto err_out_iounmap;
1102 memset(hpriv, 0, sizeof(*hpriv));
1104 probe_ent->sht = ahci_port_info[board_idx].sht;
1105 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1106 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1107 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1108 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1110 probe_ent->irq = pdev->irq;
1111 probe_ent->irq_flags = SA_SHIRQ;
1112 probe_ent->mmio_base = mmio_base;
1113 probe_ent->private_data = hpriv;
1116 hpriv->flags |= AHCI_FLAG_MSI;
1118 /* JMicron-specific fixup: make sure we're in AHCI mode */
1119 if (pdev->vendor == 0x197b)
1120 pci_write_config_byte(pdev, 0x41, 0xa1);
1122 /* initialize adapter */
1123 rc = ahci_host_init(probe_ent);
1127 ahci_print_info(probe_ent);
1129 /* FIXME: check ata_device_add return value */
1130 ata_device_add(probe_ent);
1138 pci_iounmap(pdev, mmio_base);
1143 pci_disable_msi(pdev);
1146 pci_release_regions(pdev);
1149 pci_disable_device(pdev);
1153 static void ahci_remove_one (struct pci_dev *pdev)
1155 struct device *dev = pci_dev_to_dev(pdev);
1156 struct ata_host_set *host_set = dev_get_drvdata(dev);
1157 struct ahci_host_priv *hpriv = host_set->private_data;
1158 struct ata_port *ap;
1162 for (i = 0; i < host_set->n_ports; i++) {
1163 ap = host_set->ports[i];
1165 scsi_remove_host(ap->host);
1168 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1169 free_irq(host_set->irq, host_set);
1171 for (i = 0; i < host_set->n_ports; i++) {
1172 ap = host_set->ports[i];
1174 ata_scsi_release(ap->host);
1175 scsi_host_put(ap->host);
1179 pci_iounmap(pdev, host_set->mmio_base);
1183 pci_disable_msi(pdev);
1186 pci_release_regions(pdev);
1187 pci_disable_device(pdev);
1188 dev_set_drvdata(dev, NULL);
1191 static int __init ahci_init(void)
1193 return pci_module_init(&ahci_pci_driver);
1196 static void __exit ahci_exit(void)
1198 pci_unregister_driver(&ahci_pci_driver);
1202 MODULE_AUTHOR("Jeff Garzik");
1203 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1204 MODULE_LICENSE("GPL");
1205 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1206 MODULE_VERSION(DRV_VERSION);
1208 module_init(ahci_init);
1209 module_exit(ahci_exit);