1 #define ASC_VERSION "3.4" /* AdvanSys Driver Version */
4 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
6 * Copyright (c) 1995-2000 Advanced System Products, Inc.
7 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
8 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
18 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
19 * changed its name to ConnectCom Solutions, Inc.
20 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
23 #include <linux/module.h>
24 #include <linux/string.h>
25 #include <linux/kernel.h>
26 #include <linux/types.h>
27 #include <linux/ioport.h>
28 #include <linux/interrupt.h>
29 #include <linux/delay.h>
30 #include <linux/slab.h>
32 #include <linux/proc_fs.h>
33 #include <linux/init.h>
34 #include <linux/blkdev.h>
35 #include <linux/isa.h>
36 #include <linux/eisa.h>
37 #include <linux/pci.h>
38 #include <linux/spinlock.h>
39 #include <linux/dma-mapping.h>
42 #include <asm/system.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <scsi/scsi_device.h>
47 #include <scsi/scsi_tcq.h>
48 #include <scsi/scsi.h>
49 #include <scsi/scsi_host.h>
53 * 1. Although all of the necessary command mapping places have the
54 * appropriate dma_map.. APIs, the driver still processes its internal
55 * queue using bus_to_virt() and virt_to_bus() which are illegal under
56 * the API. The entire queue processing structure will need to be
57 * altered to fix this.
58 * 2. Need to add memory mapping workaround. Test the memory mapping.
59 * If it doesn't work revert to I/O port access. Can a test be done
61 * 3. Handle an interrupt not working. Keep an interrupt counter in
62 * the interrupt handler. In the timeout function if the interrupt
63 * has not occurred then print a message and run in polled mode.
64 * 4. Need to add support for target mode commands, cf. CAM XPT.
65 * 5. check DMA mapping functions for failure
66 * 6. Use scsi_transport_spi
67 * 7. advansys_info is not safe against multiple simultaneous callers
69 * 9. Add module_param to override ISA/VLB ioport array
71 #warning this driver is still not properly converted to the DMA API
73 /* Enable driver /proc statistics. */
74 #define ADVANSYS_STATS
76 /* Enable driver tracing. */
77 /* #define ADVANSYS_DEBUG */
80 * --- Asc Library Constants and Macros
83 #define ASC_LIB_VERSION_MAJOR 1
84 #define ASC_LIB_VERSION_MINOR 24
85 #define ASC_LIB_SERIAL_NUMBER 123
90 * Any instance where a 32-bit long or pointer type is assumed
91 * for precision or HW defined structures, the following define
92 * types must be used. In Linux the char, short, and int types
93 * are all consistent at 8, 16, and 32 bits respectively. Pointers
94 * and long types are 64 bits on Alpha and UltraSPARC.
96 #define ASC_PADDR __u32 /* Physical/Bus address data type. */
97 #define ASC_VADDR __u32 /* Virtual address data type. */
98 #define ASC_DCNT __u32 /* Unsigned Data count type. */
99 #define ASC_SDCNT __s32 /* Signed Data count type. */
102 * These macros are used to convert a virtual address to a
103 * 32-bit value. This currently can be used on Linux Alpha
104 * which uses 64-bit virtual address but a 32-bit bus address.
105 * This is likely to break in the future, but doing this now
106 * will give us time to change the HW and FW to handle 64-bit
109 #define ASC_VADDR_TO_U32 virt_to_bus
110 #define ASC_U32_TO_VADDR bus_to_virt
112 typedef unsigned char uchar;
123 #define UW_ERR (uint)(0xFFFF)
124 #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
126 #define ASC_DVCLIB_CALL_DONE (1)
127 #define ASC_DVCLIB_CALL_FAILED (0)
128 #define ASC_DVCLIB_CALL_ERROR (-1)
130 #define PCI_VENDOR_ID_ASP 0x10cd
131 #define PCI_DEVICE_ID_ASP_1200A 0x1100
132 #define PCI_DEVICE_ID_ASP_ABP940 0x1200
133 #define PCI_DEVICE_ID_ASP_ABP940U 0x1300
134 #define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
135 #define PCI_DEVICE_ID_38C0800_REV1 0x2500
136 #define PCI_DEVICE_ID_38C1600_REV1 0x2700
139 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
140 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
141 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
144 #define CC_VERY_LONG_SG_LIST 0
145 #define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
147 #define PortAddr unsigned short /* port address size */
148 #define inp(port) inb(port)
149 #define outp(port, byte) outb((byte), (port))
151 #define inpw(port) inw(port)
152 #define outpw(port, word) outw((word), (port))
154 #define ASC_MAX_SG_QUEUE 7
155 #define ASC_MAX_SG_LIST 255
157 #define ASC_CS_TYPE unsigned short
159 #define ASC_IS_ISA (0x0001)
160 #define ASC_IS_ISAPNP (0x0081)
161 #define ASC_IS_EISA (0x0002)
162 #define ASC_IS_PCI (0x0004)
163 #define ASC_IS_PCI_ULTRA (0x0104)
164 #define ASC_IS_PCMCIA (0x0008)
165 #define ASC_IS_MCA (0x0020)
166 #define ASC_IS_VL (0x0040)
167 #define ASC_ISA_PNP_PORT_ADDR (0x279)
168 #define ASC_ISA_PNP_PORT_WRITE (ASC_ISA_PNP_PORT_ADDR+0x800)
169 #define ASC_IS_WIDESCSI_16 (0x0100)
170 #define ASC_IS_WIDESCSI_32 (0x0200)
171 #define ASC_IS_BIG_ENDIAN (0x8000)
172 #define ASC_CHIP_MIN_VER_VL (0x01)
173 #define ASC_CHIP_MAX_VER_VL (0x07)
174 #define ASC_CHIP_MIN_VER_PCI (0x09)
175 #define ASC_CHIP_MAX_VER_PCI (0x0F)
176 #define ASC_CHIP_VER_PCI_BIT (0x08)
177 #define ASC_CHIP_MIN_VER_ISA (0x11)
178 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
179 #define ASC_CHIP_MAX_VER_ISA (0x27)
180 #define ASC_CHIP_VER_ISA_BIT (0x30)
181 #define ASC_CHIP_VER_ISAPNP_BIT (0x20)
182 #define ASC_CHIP_VER_ASYN_BUG (0x21)
183 #define ASC_CHIP_VER_PCI 0x08
184 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
185 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
186 #define ASC_CHIP_MIN_VER_EISA (0x41)
187 #define ASC_CHIP_MAX_VER_EISA (0x47)
188 #define ASC_CHIP_VER_EISA_BIT (0x40)
189 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
190 #define ASC_MAX_LIB_SUPPORTED_ISA_CHIP_VER 0x21
191 #define ASC_MAX_LIB_SUPPORTED_PCI_CHIP_VER 0x0A
192 #define ASC_MAX_VL_DMA_ADDR (0x07FFFFFFL)
193 #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
194 #define ASC_MAX_PCI_DMA_ADDR (0xFFFFFFFFL)
195 #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
196 #define ASC_MAX_ISA_DMA_ADDR (0x00FFFFFFL)
197 #define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
198 #define ASC_MAX_EISA_DMA_ADDR (0x07FFFFFFL)
199 #define ASC_MAX_EISA_DMA_COUNT (0x07FFFFFFL)
201 #define ASC_SCSI_ID_BITS 3
202 #define ASC_SCSI_TIX_TYPE uchar
203 #define ASC_ALL_DEVICE_BIT_SET 0xFF
204 #define ASC_SCSI_BIT_ID_TYPE uchar
205 #define ASC_MAX_TID 7
206 #define ASC_MAX_LUN 7
207 #define ASC_SCSI_WIDTH_BIT_SET 0xFF
208 #define ASC_MAX_SENSE_LEN 32
209 #define ASC_MIN_SENSE_LEN 14
210 #define ASC_SCSI_RESET_HOLD_TIME_US 60
213 * Narrow boards only support 12-byte commands, while wide boards
214 * extend to 16-byte commands.
216 #define ASC_MAX_CDB_LEN 12
217 #define ADV_MAX_CDB_LEN 16
220 * Inquiry SPC-2 SPI Byte 1 EVPD (Enable Vital Product Data)
221 * and CmdDt (Command Support Data) field bit definitions.
223 #define ADV_INQ_RTN_VPD_AND_CMDDT 0x3
224 #define ADV_INQ_RTN_CMDDT_FOR_OP_CODE 0x2
225 #define ADV_INQ_RTN_VPD_FOR_PG_CODE 0x1
226 #define ADV_INQ_RTN_STD_INQUIRY_DATA 0x0
228 #define ASC_SCSIDIR_NOCHK 0x00
229 #define ASC_SCSIDIR_T2H 0x08
230 #define ASC_SCSIDIR_H2T 0x10
231 #define ASC_SCSIDIR_NODATA 0x18
232 #define SCSI_ASC_NOMEDIA 0x3A
233 #define ASC_SRB_HOST(x) ((uchar)((uchar)(x) >> 4))
234 #define ASC_SRB_TID(x) ((uchar)((uchar)(x) & (uchar)0x0F))
235 #define ASC_SRB_LUN(x) ((uchar)((uint)(x) >> 13))
236 #define PUT_CDB1(x) ((uchar)((uint)(x) >> 8))
237 #define MS_SDTR_LEN 0x03
238 #define MS_WDTR_LEN 0x02
240 #define ASC_SG_LIST_PER_Q 7
242 #define QS_READY 0x01
243 #define QS_DISC1 0x02
244 #define QS_DISC2 0x04
246 #define QS_ABORTED 0x40
248 #define QC_NO_CALLBACK 0x01
249 #define QC_SG_SWAP_QUEUE 0x02
250 #define QC_SG_HEAD 0x04
251 #define QC_DATA_IN 0x08
252 #define QC_DATA_OUT 0x10
253 #define QC_URGENT 0x20
254 #define QC_MSG_OUT 0x40
255 #define QC_REQ_SENSE 0x80
256 #define QCSG_SG_XFER_LIST 0x02
257 #define QCSG_SG_XFER_MORE 0x04
258 #define QCSG_SG_XFER_END 0x08
259 #define QD_IN_PROGRESS 0x00
260 #define QD_NO_ERROR 0x01
261 #define QD_ABORTED_BY_HOST 0x02
262 #define QD_WITH_ERROR 0x04
263 #define QD_INVALID_REQUEST 0x80
264 #define QD_INVALID_HOST_NUM 0x81
265 #define QD_INVALID_DEVICE 0x82
266 #define QD_ERR_INTERNAL 0xFF
267 #define QHSTA_NO_ERROR 0x00
268 #define QHSTA_M_SEL_TIMEOUT 0x11
269 #define QHSTA_M_DATA_OVER_RUN 0x12
270 #define QHSTA_M_DATA_UNDER_RUN 0x12
271 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
272 #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
273 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
274 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
275 #define QHSTA_D_HOST_ABORT_FAILED 0x23
276 #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
277 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
278 #define QHSTA_D_ASPI_NO_BUF_POOL 0x26
279 #define QHSTA_M_WTM_TIMEOUT 0x41
280 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
281 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
282 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
283 #define QHSTA_M_TARGET_STATUS_BUSY 0x45
284 #define QHSTA_M_BAD_TAG_CODE 0x46
285 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
286 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
287 #define QHSTA_D_LRAM_CMP_ERROR 0x81
288 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
289 #define ASC_FLAG_SCSIQ_REQ 0x01
290 #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
291 #define ASC_FLAG_BIOS_ASYNC_IO 0x04
292 #define ASC_FLAG_SRB_LINEAR_ADDR 0x08
293 #define ASC_FLAG_WIN16 0x10
294 #define ASC_FLAG_WIN32 0x20
295 #define ASC_FLAG_ISA_OVER_16MB 0x40
296 #define ASC_FLAG_DOS_VM_CALLBACK 0x80
297 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10
298 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
299 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
300 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
301 #define ASC_SCSIQ_CPY_BEG 4
302 #define ASC_SCSIQ_SGHD_CPY_BEG 2
303 #define ASC_SCSIQ_B_FWD 0
304 #define ASC_SCSIQ_B_BWD 1
305 #define ASC_SCSIQ_B_STATUS 2
306 #define ASC_SCSIQ_B_QNO 3
307 #define ASC_SCSIQ_B_CNTL 4
308 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5
309 #define ASC_SCSIQ_D_DATA_ADDR 8
310 #define ASC_SCSIQ_D_DATA_CNT 12
311 #define ASC_SCSIQ_B_SENSE_LEN 20
312 #define ASC_SCSIQ_DONE_INFO_BEG 22
313 #define ASC_SCSIQ_D_SRBPTR 22
314 #define ASC_SCSIQ_B_TARGET_IX 26
315 #define ASC_SCSIQ_B_CDB_LEN 28
316 #define ASC_SCSIQ_B_TAG_CODE 29
317 #define ASC_SCSIQ_W_VM_ID 30
318 #define ASC_SCSIQ_DONE_STATUS 32
319 #define ASC_SCSIQ_HOST_STATUS 33
320 #define ASC_SCSIQ_SCSI_STATUS 34
321 #define ASC_SCSIQ_CDB_BEG 36
322 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
323 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
324 #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
325 #define ASC_SCSIQ_B_SG_WK_QP 49
326 #define ASC_SCSIQ_B_SG_WK_IX 50
327 #define ASC_SCSIQ_W_ALT_DC1 52
328 #define ASC_SCSIQ_B_LIST_CNT 6
329 #define ASC_SCSIQ_B_CUR_LIST_CNT 7
330 #define ASC_SGQ_B_SG_CNTL 4
331 #define ASC_SGQ_B_SG_HEAD_QP 5
332 #define ASC_SGQ_B_SG_LIST_CNT 6
333 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7
334 #define ASC_SGQ_LIST_BEG 8
335 #define ASC_DEF_SCSI1_QNG 4
336 #define ASC_MAX_SCSI1_QNG 4
337 #define ASC_DEF_SCSI2_QNG 16
338 #define ASC_MAX_SCSI2_QNG 32
339 #define ASC_TAG_CODE_MASK 0x23
340 #define ASC_STOP_REQ_RISC_STOP 0x01
341 #define ASC_STOP_ACK_RISC_STOP 0x03
342 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
343 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20
344 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
345 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
346 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
347 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
348 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
349 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
350 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
351 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
353 typedef struct asc_scsiq_1 {
362 ASC_PADDR sense_addr;
367 typedef struct asc_scsiq_2 {
376 typedef struct asc_scsiq_3 {
383 typedef struct asc_scsiq_4 {
384 uchar cdb[ASC_MAX_CDB_LEN];
385 uchar y_first_sg_list_qp;
386 uchar y_working_sg_qp;
387 uchar y_working_sg_ix;
390 ushort x_reconnect_rtn;
391 ASC_PADDR x_saved_data_addr;
392 ASC_DCNT x_saved_data_cnt;
395 typedef struct asc_q_done_info {
404 ASC_DCNT remain_bytes;
407 typedef struct asc_sg_list {
412 typedef struct asc_sg_head {
415 ushort entry_to_copy;
417 ASC_SG_LIST sg_list[ASC_MAX_SG_LIST];
420 #define ASC_MIN_SG_LIST 2
422 typedef struct asc_min_sg_head {
425 ushort entry_to_copy;
427 ASC_SG_LIST sg_list[ASC_MIN_SG_LIST];
430 #define QCX_SORT (0x0001)
431 #define QCX_COALEASE (0x0002)
433 typedef struct asc_scsi_q {
437 ASC_SG_HEAD *sg_head;
438 ushort remain_sg_entry_cnt;
439 ushort next_sg_index;
442 typedef struct asc_scsi_req_q {
446 ASC_SG_HEAD *sg_head;
449 uchar cdb[ASC_MAX_CDB_LEN];
450 uchar sense[ASC_MIN_SENSE_LEN];
453 typedef struct asc_scsi_bios_req_q {
457 ASC_SG_HEAD *sg_head;
460 uchar cdb[ASC_MAX_CDB_LEN];
461 uchar sense[ASC_MIN_SENSE_LEN];
462 } ASC_SCSI_BIOS_REQ_Q;
464 typedef struct asc_risc_q {
473 typedef struct asc_sg_list_q {
479 uchar sg_cur_list_cnt;
482 typedef struct asc_risc_sg_list_q {
486 ASC_SG_LIST sg_list[7];
487 } ASC_RISC_SG_LIST_Q;
489 #define ASC_EXE_SCSI_IO_MAX_IDLE_LOOP 0x1000000UL
490 #define ASC_EXE_SCSI_IO_MAX_WAIT_LOOP 1024
491 #define ASCQ_ERR_NO_ERROR 0
492 #define ASCQ_ERR_IO_NOT_FOUND 1
493 #define ASCQ_ERR_LOCAL_MEM 2
494 #define ASCQ_ERR_CHKSUM 3
495 #define ASCQ_ERR_START_CHIP 4
496 #define ASCQ_ERR_INT_TARGET_ID 5
497 #define ASCQ_ERR_INT_LOCAL_MEM 6
498 #define ASCQ_ERR_HALT_RISC 7
499 #define ASCQ_ERR_GET_ASPI_ENTRY 8
500 #define ASCQ_ERR_CLOSE_ASPI 9
501 #define ASCQ_ERR_HOST_INQUIRY 0x0A
502 #define ASCQ_ERR_SAVED_SRB_BAD 0x0B
503 #define ASCQ_ERR_QCNTL_SG_LIST 0x0C
504 #define ASCQ_ERR_Q_STATUS 0x0D
505 #define ASCQ_ERR_WR_SCSIQ 0x0E
506 #define ASCQ_ERR_PC_ADDR 0x0F
507 #define ASCQ_ERR_SYN_OFFSET 0x10
508 #define ASCQ_ERR_SYN_XFER_TIME 0x11
509 #define ASCQ_ERR_LOCK_DMA 0x12
510 #define ASCQ_ERR_UNLOCK_DMA 0x13
511 #define ASCQ_ERR_VDS_CHK_INSTALL 0x14
512 #define ASCQ_ERR_MICRO_CODE_HALT 0x15
513 #define ASCQ_ERR_SET_LRAM_ADDR 0x16
514 #define ASCQ_ERR_CUR_QNG 0x17
515 #define ASCQ_ERR_SG_Q_LINKS 0x18
516 #define ASCQ_ERR_SCSIQ_PTR 0x19
517 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A
518 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
519 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
522 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
524 #define ASC_WARN_NO_ERROR 0x0000
525 #define ASC_WARN_IO_PORT_ROTATE 0x0001
526 #define ASC_WARN_EEPROM_CHKSUM 0x0002
527 #define ASC_WARN_IRQ_MODIFIED 0x0004
528 #define ASC_WARN_AUTO_CONFIG 0x0008
529 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010
530 #define ASC_WARN_EEPROM_RECOVER 0x0020
531 #define ASC_WARN_CFG_MSW_RECOVER 0x0040
532 #define ASC_WARN_SET_PCI_CONFIG_SPACE 0x0080
535 * Error code values are set in ASC_DVC_VAR 'err_code'.
537 #define ASC_IERR_WRITE_EEPROM 0x0001
538 #define ASC_IERR_MCODE_CHKSUM 0x0002
539 #define ASC_IERR_SET_PC_ADDR 0x0004
540 #define ASC_IERR_START_STOP_CHIP 0x0008
541 #define ASC_IERR_IRQ_NO 0x0010
542 #define ASC_IERR_SET_IRQ_NO 0x0020
543 #define ASC_IERR_CHIP_VERSION 0x0040
544 #define ASC_IERR_SET_SCSI_ID 0x0080
545 #define ASC_IERR_GET_PHY_ADDR 0x0100
546 #define ASC_IERR_BAD_SIGNATURE 0x0200
547 #define ASC_IERR_NO_BUS_TYPE 0x0400
548 #define ASC_IERR_SCAM 0x0800
549 #define ASC_IERR_SET_SDTR 0x1000
550 #define ASC_IERR_RW_LRAM 0x8000
552 #define ASC_DEF_IRQ_NO 10
553 #define ASC_MAX_IRQ_NO 15
554 #define ASC_MIN_IRQ_NO 10
555 #define ASC_MIN_REMAIN_Q (0x02)
556 #define ASC_DEF_MAX_TOTAL_QNG (0xF0)
557 #define ASC_MIN_TAG_Q_PER_DVC (0x04)
558 #define ASC_DEF_TAG_Q_PER_DVC (0x04)
559 #define ASC_MIN_FREE_Q ASC_MIN_REMAIN_Q
560 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
561 #define ASC_MAX_TOTAL_QNG 240
562 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
563 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
564 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
565 #define ASC_MAX_INRAM_TAG_QNG 16
566 #define ASC_IOADR_TABLE_MAX_IX 11
567 #define ASC_IOADR_GAP 0x10
568 #define ASC_LIB_SCSIQ_WK_SP 256
569 #define ASC_MAX_SYN_XFER_NO 16
570 #define ASC_SYN_MAX_OFFSET 0x0F
571 #define ASC_DEF_SDTR_OFFSET 0x0F
572 #define ASC_DEF_SDTR_INDEX 0x00
573 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
574 #define SYN_XFER_NS_0 25
575 #define SYN_XFER_NS_1 30
576 #define SYN_XFER_NS_2 35
577 #define SYN_XFER_NS_3 40
578 #define SYN_XFER_NS_4 50
579 #define SYN_XFER_NS_5 60
580 #define SYN_XFER_NS_6 70
581 #define SYN_XFER_NS_7 85
582 #define SYN_ULTRA_XFER_NS_0 12
583 #define SYN_ULTRA_XFER_NS_1 19
584 #define SYN_ULTRA_XFER_NS_2 25
585 #define SYN_ULTRA_XFER_NS_3 32
586 #define SYN_ULTRA_XFER_NS_4 38
587 #define SYN_ULTRA_XFER_NS_5 44
588 #define SYN_ULTRA_XFER_NS_6 50
589 #define SYN_ULTRA_XFER_NS_7 57
590 #define SYN_ULTRA_XFER_NS_8 63
591 #define SYN_ULTRA_XFER_NS_9 69
592 #define SYN_ULTRA_XFER_NS_10 75
593 #define SYN_ULTRA_XFER_NS_11 82
594 #define SYN_ULTRA_XFER_NS_12 88
595 #define SYN_ULTRA_XFER_NS_13 94
596 #define SYN_ULTRA_XFER_NS_14 100
597 #define SYN_ULTRA_XFER_NS_15 107
599 typedef struct ext_msg {
605 uchar sdtr_xfer_period;
606 uchar sdtr_req_ack_offset;
621 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
622 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
623 #define wdtr_width u_ext_msg.wdtr.wdtr_width
624 #define mdp_b3 u_ext_msg.mdp_b3
625 #define mdp_b2 u_ext_msg.mdp_b2
626 #define mdp_b1 u_ext_msg.mdp_b1
627 #define mdp_b0 u_ext_msg.mdp_b0
629 typedef struct asc_dvc_cfg {
630 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
631 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
632 ASC_SCSI_BIT_ID_TYPE disc_enable;
633 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
636 uchar isa_dma_channel;
638 ushort lib_serial_no;
641 ushort mcode_version;
642 uchar max_tag_qng[ASC_MAX_TID + 1];
644 uchar sdtr_period_offset[ASC_MAX_TID + 1];
645 uchar adapter_info[6];
648 #define ASC_DEF_DVC_CNTL 0xFFFF
649 #define ASC_DEF_CHIP_SCSI_ID 7
650 #define ASC_DEF_ISA_DMA_SPEED 4
651 #define ASC_INIT_STATE_NULL 0x0000
652 #define ASC_INIT_STATE_BEG_GET_CFG 0x0001
653 #define ASC_INIT_STATE_END_GET_CFG 0x0002
654 #define ASC_INIT_STATE_BEG_SET_CFG 0x0004
655 #define ASC_INIT_STATE_END_SET_CFG 0x0008
656 #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
657 #define ASC_INIT_STATE_END_LOAD_MC 0x0020
658 #define ASC_INIT_STATE_BEG_INQUIRY 0x0040
659 #define ASC_INIT_STATE_END_INQUIRY 0x0080
660 #define ASC_INIT_RESET_SCSI_DONE 0x0100
661 #define ASC_INIT_STATE_WITHOUT_EEP 0x8000
662 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001
663 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
664 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
665 #define ASC_MIN_TAGGED_CMD 7
666 #define ASC_MAX_SCSI_RESET_WAIT 30
668 struct asc_dvc_var; /* Forward Declaration. */
670 typedef struct asc_dvc_var {
676 ASC_SCSI_BIT_ID_TYPE init_sdtr;
677 ASC_SCSI_BIT_ID_TYPE sdtr_done;
678 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
679 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
680 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
681 ASC_SCSI_BIT_ID_TYPE start_motor;
682 uchar scsi_reset_wait;
687 uchar in_critical_cnt;
689 uchar last_q_shortage;
691 uchar cur_dvc_qng[ASC_MAX_TID + 1];
692 uchar max_dvc_qng[ASC_MAX_TID + 1];
693 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
694 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
695 uchar sdtr_period_tbl[ASC_MAX_SYN_XFER_NO];
697 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
700 uchar dos_int13_table[ASC_MAX_TID + 1];
701 ASC_DCNT max_dma_count;
702 ASC_SCSI_BIT_ID_TYPE no_scam;
703 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
704 uchar max_sdtr_index;
705 uchar host_init_sdtr_index;
706 struct asc_board *drv_ptr;
710 typedef struct asc_dvc_inq_info {
711 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
714 typedef struct asc_cap_info {
719 typedef struct asc_cap_info_array {
720 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
721 } ASC_CAP_INFO_ARRAY;
723 #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
724 #define ASC_MCNTL_NULL_TARGET (ushort)0x0002
725 #define ASC_CNTL_INITIATOR (ushort)0x0001
726 #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
727 #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
728 #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
729 #define ASC_CNTL_NO_SCAM (ushort)0x0010
730 #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
731 #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
732 #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
733 #define ASC_CNTL_RESET_SCSI (ushort)0x0200
734 #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
735 #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
736 #define ASC_CNTL_SCSI_PARITY (ushort)0x1000
737 #define ASC_CNTL_BURST_MODE (ushort)0x2000
738 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
739 #define ASC_EEP_DVC_CFG_BEG_VL 2
740 #define ASC_EEP_MAX_DVC_ADDR_VL 15
741 #define ASC_EEP_DVC_CFG_BEG 32
742 #define ASC_EEP_MAX_DVC_ADDR 45
743 #define ASC_EEP_DEFINED_WORDS 10
744 #define ASC_EEP_MAX_ADDR 63
745 #define ASC_EEP_RES_WORDS 0
746 #define ASC_EEP_MAX_RETRY 20
747 #define ASC_MAX_INIT_BUSY_RETRY 8
748 #define ASC_EEP_ISA_PNP_WSIZE 16
751 * These macros keep the chip SCSI id and ISA DMA speed
752 * bitfields in board order. C bitfields aren't portable
753 * between big and little-endian platforms so they are
757 #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
758 #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
759 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
760 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
761 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
762 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
764 typedef struct asceep_config {
776 uchar id_speed; /* low order 4 bits is chip scsi id */
777 /* high order 4 bits is isa dma speed */
778 uchar dos_int13_table[ASC_MAX_TID + 1];
779 uchar adapter_info[6];
784 #define ASC_PCI_CFG_LSW_SCSI_PARITY 0x0800
785 #define ASC_PCI_CFG_LSW_BURST_MODE 0x0080
786 #define ASC_PCI_CFG_LSW_INTR_ABLE 0x0020
788 #define ASC_EEP_CMD_READ 0x80
789 #define ASC_EEP_CMD_WRITE 0x40
790 #define ASC_EEP_CMD_WRITE_ABLE 0x30
791 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
792 #define ASC_OVERRUN_BSIZE 0x00000048UL
793 #define ASC_CTRL_BREAK_ONCE 0x0001
794 #define ASC_CTRL_BREAK_STAY_IDLE 0x0002
795 #define ASCV_MSGOUT_BEG 0x0000
796 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
797 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
798 #define ASCV_BREAK_SAVED_CODE (ushort)0x0006
799 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
800 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
801 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
802 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
803 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
804 #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
805 #define ASCV_BREAK_ADDR (ushort)0x0028
806 #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
807 #define ASCV_BREAK_CONTROL (ushort)0x002C
808 #define ASCV_BREAK_HIT_COUNT (ushort)0x002E
810 #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
811 #define ASCV_MCODE_CHKSUM_W (ushort)0x0032
812 #define ASCV_MCODE_SIZE_W (ushort)0x0034
813 #define ASCV_STOP_CODE_B (ushort)0x0036
814 #define ASCV_DVC_ERR_CODE_B (ushort)0x0037
815 #define ASCV_OVERRUN_PADDR_D (ushort)0x0038
816 #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
817 #define ASCV_HALTCODE_W (ushort)0x0040
818 #define ASCV_CHKSUM_W (ushort)0x0042
819 #define ASCV_MC_DATE_W (ushort)0x0044
820 #define ASCV_MC_VER_W (ushort)0x0046
821 #define ASCV_NEXTRDY_B (ushort)0x0048
822 #define ASCV_DONENEXT_B (ushort)0x0049
823 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
824 #define ASCV_SCSIBUSY_B (ushort)0x004B
825 #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
826 #define ASCV_CURCDB_B (ushort)0x004D
827 #define ASCV_RCLUN_B (ushort)0x004E
828 #define ASCV_BUSY_QHEAD_B (ushort)0x004F
829 #define ASCV_DISC1_QHEAD_B (ushort)0x0050
830 #define ASCV_DISC_ENABLE_B (ushort)0x0052
831 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
832 #define ASCV_HOSTSCSI_ID_B (ushort)0x0055
833 #define ASCV_MCODE_CNTL_B (ushort)0x0056
834 #define ASCV_NULL_TARGET_B (ushort)0x0057
835 #define ASCV_FREE_Q_HEAD_W (ushort)0x0058
836 #define ASCV_DONE_Q_TAIL_W (ushort)0x005A
837 #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
838 #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
839 #define ASCV_HOST_FLAG_B (ushort)0x005D
840 #define ASCV_TOTAL_READY_Q_B (ushort)0x0064
841 #define ASCV_VER_SERIAL_B (ushort)0x0065
842 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
843 #define ASCV_WTM_FLAG_B (ushort)0x0068
844 #define ASCV_RISC_FLAG_B (ushort)0x006A
845 #define ASCV_REQ_SG_LIST_QP (ushort)0x006B
846 #define ASC_HOST_FLAG_IN_ISR 0x01
847 #define ASC_HOST_FLAG_ACK_INT 0x02
848 #define ASC_RISC_FLAG_GEN_INT 0x01
849 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02
850 #define IOP_CTRL (0x0F)
851 #define IOP_STATUS (0x0E)
852 #define IOP_INT_ACK IOP_STATUS
853 #define IOP_REG_IFC (0x0D)
854 #define IOP_SYN_OFFSET (0x0B)
855 #define IOP_EXTRA_CONTROL (0x0D)
856 #define IOP_REG_PC (0x0C)
857 #define IOP_RAM_ADDR (0x0A)
858 #define IOP_RAM_DATA (0x08)
859 #define IOP_EEP_DATA (0x06)
860 #define IOP_EEP_CMD (0x07)
861 #define IOP_VERSION (0x03)
862 #define IOP_CONFIG_HIGH (0x04)
863 #define IOP_CONFIG_LOW (0x02)
864 #define IOP_SIG_BYTE (0x01)
865 #define IOP_SIG_WORD (0x00)
866 #define IOP_REG_DC1 (0x0E)
867 #define IOP_REG_DC0 (0x0C)
868 #define IOP_REG_SB (0x0B)
869 #define IOP_REG_DA1 (0x0A)
870 #define IOP_REG_DA0 (0x08)
871 #define IOP_REG_SC (0x09)
872 #define IOP_DMA_SPEED (0x07)
873 #define IOP_REG_FLAG (0x07)
874 #define IOP_FIFO_H (0x06)
875 #define IOP_FIFO_L (0x04)
876 #define IOP_REG_ID (0x05)
877 #define IOP_REG_QP (0x03)
878 #define IOP_REG_IH (0x02)
879 #define IOP_REG_IX (0x01)
880 #define IOP_REG_AX (0x00)
881 #define IFC_REG_LOCK (0x00)
882 #define IFC_REG_UNLOCK (0x09)
883 #define IFC_WR_EN_FILTER (0x10)
884 #define IFC_RD_NO_EEPROM (0x10)
885 #define IFC_SLEW_RATE (0x20)
886 #define IFC_ACT_NEG (0x40)
887 #define IFC_INP_FILTER (0x80)
888 #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
889 #define SC_SEL (uchar)(0x80)
890 #define SC_BSY (uchar)(0x40)
891 #define SC_ACK (uchar)(0x20)
892 #define SC_REQ (uchar)(0x10)
893 #define SC_ATN (uchar)(0x08)
894 #define SC_IO (uchar)(0x04)
895 #define SC_CD (uchar)(0x02)
896 #define SC_MSG (uchar)(0x01)
897 #define SEC_SCSI_CTL (uchar)(0x80)
898 #define SEC_ACTIVE_NEGATE (uchar)(0x40)
899 #define SEC_SLEW_RATE (uchar)(0x20)
900 #define SEC_ENABLE_FILTER (uchar)(0x10)
901 #define ASC_HALT_EXTMSG_IN (ushort)0x8000
902 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
903 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
904 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
905 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
906 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
907 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
908 #define ASC_MAX_QNO 0xF8
909 #define ASC_DATA_SEC_BEG (ushort)0x0080
910 #define ASC_DATA_SEC_END (ushort)0x0080
911 #define ASC_CODE_SEC_BEG (ushort)0x0080
912 #define ASC_CODE_SEC_END (ushort)0x0080
913 #define ASC_QADR_BEG (0x4000)
914 #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
915 #define ASC_QADR_END (ushort)0x7FFF
916 #define ASC_QLAST_ADR (ushort)0x7FC0
917 #define ASC_QBLK_SIZE 0x40
918 #define ASC_BIOS_DATA_QBEG 0xF8
919 #define ASC_MIN_ACTIVE_QNO 0x01
920 #define ASC_QLINK_END 0xFF
921 #define ASC_EEPROM_WORDS 0x10
922 #define ASC_MAX_MGS_LEN 0x10
923 #define ASC_BIOS_ADDR_DEF 0xDC00
924 #define ASC_BIOS_SIZE 0x3800
925 #define ASC_BIOS_RAM_OFF 0x3800
926 #define ASC_BIOS_RAM_SIZE 0x800
927 #define ASC_BIOS_MIN_ADDR 0xC000
928 #define ASC_BIOS_MAX_ADDR 0xEC00
929 #define ASC_BIOS_BANK_SIZE 0x0400
930 #define ASC_MCODE_START_ADDR 0x0080
931 #define ASC_CFG0_HOST_INT_ON 0x0020
932 #define ASC_CFG0_BIOS_ON 0x0040
933 #define ASC_CFG0_VERA_BURST_ON 0x0080
934 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
935 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
936 #define ASC_CFG1_LRAM_8BITS_ON 0x0800
937 #define ASC_CFG_MSW_CLR_MASK 0x3080
938 #define CSW_TEST1 (ASC_CS_TYPE)0x8000
939 #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
940 #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
941 #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
942 #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
943 #define CSW_TEST2 (ASC_CS_TYPE)0x0400
944 #define CSW_TEST3 (ASC_CS_TYPE)0x0200
945 #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
946 #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
947 #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
948 #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
949 #define CSW_HALTED (ASC_CS_TYPE)0x0010
950 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
951 #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
952 #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
953 #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
954 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
955 #define CIW_INT_ACK (ASC_CS_TYPE)0x0100
956 #define CIW_TEST1 (ASC_CS_TYPE)0x0200
957 #define CIW_TEST2 (ASC_CS_TYPE)0x0400
958 #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
959 #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
960 #define CC_CHIP_RESET (uchar)0x80
961 #define CC_SCSI_RESET (uchar)0x40
962 #define CC_HALT (uchar)0x20
963 #define CC_SINGLE_STEP (uchar)0x10
964 #define CC_DMA_ABLE (uchar)0x08
965 #define CC_TEST (uchar)0x04
966 #define CC_BANK_ONE (uchar)0x02
967 #define CC_DIAG (uchar)0x01
968 #define ASC_1000_ID0W 0x04C1
969 #define ASC_1000_ID0W_FIX 0x00C1
970 #define ASC_1000_ID1B 0x25
971 #define ASC_EISA_REV_IOP_MASK (0x0C83)
972 #define ASC_EISA_PID_IOP_MASK (0x0C80)
973 #define ASC_EISA_CFG_IOP_MASK (0x0C86)
974 #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
975 #define INS_HALTINT (ushort)0x6281
976 #define INS_HALT (ushort)0x6280
977 #define INS_SINT (ushort)0x6200
978 #define INS_RFLAG_WTM (ushort)0x7380
979 #define ASC_MC_SAVE_CODE_WSIZE 0x500
980 #define ASC_MC_SAVE_DATA_WSIZE 0x40
982 typedef struct asc_mc_saved {
983 ushort data[ASC_MC_SAVE_DATA_WSIZE];
984 ushort code[ASC_MC_SAVE_CODE_WSIZE];
987 #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
988 #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
989 #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
990 #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
991 #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
992 #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
993 #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
994 #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
995 #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
996 #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
997 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data));
998 #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id));
999 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data);
1000 #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id));
1001 #define AscSynIndexToPeriod(index) (uchar)(asc_dvc->sdtr_period_tbl[ (index) ])
1002 #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
1003 #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
1004 #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
1005 #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
1006 #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
1007 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
1008 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
1009 #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
1010 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
1011 #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
1012 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
1013 #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
1014 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
1015 #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
1016 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
1017 #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
1018 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
1019 #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
1020 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
1021 #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
1022 #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
1023 #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
1024 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
1025 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
1026 #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
1027 #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
1028 #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
1029 #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
1030 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
1031 #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
1032 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
1033 #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
1034 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
1035 #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
1036 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
1037 #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
1038 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
1039 #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
1040 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
1041 #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
1042 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
1043 #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
1044 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
1045 #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
1046 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
1047 #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
1048 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
1049 #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
1050 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
1051 #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
1052 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
1053 #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
1054 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
1056 static int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg);
1057 static int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg);
1058 static void AscWaitEEPRead(void);
1059 static void AscWaitEEPWrite(void);
1060 static ushort AscReadEEPWord(PortAddr, uchar);
1061 static ushort AscWriteEEPWord(PortAddr, uchar, ushort);
1062 static ushort AscGetEEPConfig(PortAddr, ASCEEP_CONFIG *, ushort);
1063 static int AscSetEEPConfigOnce(PortAddr, ASCEEP_CONFIG *, ushort);
1064 static int AscSetEEPConfig(PortAddr, ASCEEP_CONFIG *, ushort);
1065 static int AscStartChip(PortAddr);
1066 static int AscStopChip(PortAddr);
1067 static void AscSetChipIH(PortAddr, ushort);
1068 static int AscIsChipHalted(PortAddr);
1069 static void AscAckInterrupt(PortAddr);
1070 static void AscDisableInterrupt(PortAddr);
1071 static void AscEnableInterrupt(PortAddr);
1072 static void AscSetBank(PortAddr, uchar);
1073 static int AscResetChipAndScsiBus(ASC_DVC_VAR *);
1075 static uchar AscGetIsaDmaSpeed(PortAddr);
1076 #endif /* CONFIG_ISA */
1077 static uchar AscReadLramByte(PortAddr, ushort);
1078 static ushort AscReadLramWord(PortAddr, ushort);
1079 #if CC_VERY_LONG_SG_LIST
1080 static ASC_DCNT AscReadLramDWord(PortAddr, ushort);
1081 #endif /* CC_VERY_LONG_SG_LIST */
1082 static void AscWriteLramWord(PortAddr, ushort, ushort);
1083 static void AscWriteLramByte(PortAddr, ushort, uchar);
1084 static ASC_DCNT AscMemSumLramWord(PortAddr, ushort, int);
1085 static void AscMemWordSetLram(PortAddr, ushort, ushort, int);
1086 static void AscMemWordCopyPtrToLram(PortAddr, ushort, uchar *, int);
1087 static void AscMemDWordCopyPtrToLram(PortAddr, ushort, uchar *, int);
1088 static void AscMemWordCopyPtrFromLram(PortAddr, ushort, uchar *, int);
1089 static ushort AscInitAscDvcVar(ASC_DVC_VAR *);
1090 static ushort AscInitFromEEP(ASC_DVC_VAR *);
1091 static ushort AscInitMicroCodeVar(ASC_DVC_VAR *);
1092 static int AscTestExternalLram(ASC_DVC_VAR *);
1093 static uchar AscMsgOutSDTR(ASC_DVC_VAR *, uchar, uchar);
1094 static uchar AscCalSDTRData(ASC_DVC_VAR *, uchar, uchar);
1095 static void AscSetChipSDTR(PortAddr, uchar, uchar);
1096 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *, uchar);
1097 static uchar AscAllocFreeQueue(PortAddr, uchar);
1098 static uchar AscAllocMultipleFreeQueue(PortAddr, uchar, uchar);
1099 static int AscHostReqRiscHalt(PortAddr);
1100 static int AscStopQueueExe(PortAddr);
1101 static int AscSendScsiQueue(ASC_DVC_VAR *,
1102 ASC_SCSI_Q *scsiq, uchar n_q_required);
1103 static int AscPutReadyQueue(ASC_DVC_VAR *, ASC_SCSI_Q *, uchar);
1104 static int AscPutReadySgListQueue(ASC_DVC_VAR *, ASC_SCSI_Q *, uchar);
1105 static int AscSetChipSynRegAtID(PortAddr, uchar, uchar);
1106 static int AscSetRunChipSynRegAtID(PortAddr, uchar, uchar);
1107 static ushort AscInitLram(ASC_DVC_VAR *);
1108 static ushort AscInitQLinkVar(ASC_DVC_VAR *);
1109 static int AscSetLibErrorCode(ASC_DVC_VAR *, ushort);
1110 static int AscIsrChipHalted(ASC_DVC_VAR *);
1111 static uchar _AscCopyLramScsiDoneQ(PortAddr, ushort,
1112 ASC_QDONE_INFO *, ASC_DCNT);
1113 static int AscIsrQDone(ASC_DVC_VAR *);
1115 static ushort AscGetEisaChipCfg(PortAddr);
1116 #endif /* CONFIG_ISA */
1117 static uchar AscGetChipScsiCtrl(PortAddr);
1118 static uchar AscGetChipVersion(PortAddr, ushort);
1119 static ASC_DCNT AscLoadMicroCode(PortAddr, ushort, uchar *, ushort);
1120 static void AscToggleIRQAct(PortAddr);
1121 static void DvcPutScsiQ(PortAddr, ushort, uchar *, int);
1122 static void DvcGetQinfo(PortAddr, ushort, uchar *, int);
1123 static ushort AscInitAsc1000Driver(ASC_DVC_VAR *);
1124 static void AscAsyncFix(ASC_DVC_VAR *, struct scsi_device *);
1125 static int AscExeScsiQueue(ASC_DVC_VAR *, ASC_SCSI_Q *);
1126 static int AscISR(ASC_DVC_VAR *);
1127 static uint AscGetNumOfFreeQueue(ASC_DVC_VAR *, uchar, uchar);
1128 static int AscSgListToQueue(int);
1130 static void AscEnableIsaDma(uchar);
1131 #endif /* CONFIG_ISA */
1132 static const char *advansys_info(struct Scsi_Host *shost);
1135 * --- Adv Library Constants and Macros
1138 #define ADV_LIB_VERSION_MAJOR 5
1139 #define ADV_LIB_VERSION_MINOR 14
1142 * Define Adv Library required special types.
1146 * Portable Data Types
1148 * Any instance where a 32-bit long or pointer type is assumed
1149 * for precision or HW defined structures, the following define
1150 * types must be used. In Linux the char, short, and int types
1151 * are all consistent at 8, 16, and 32 bits respectively. Pointers
1152 * and long types are 64 bits on Alpha and UltraSPARC.
1154 #define ADV_PADDR __u32 /* Physical address data type. */
1155 #define ADV_VADDR __u32 /* Virtual address data type. */
1156 #define ADV_DCNT __u32 /* Unsigned Data count type. */
1157 #define ADV_SDCNT __s32 /* Signed Data count type. */
1160 * These macros are used to convert a virtual address to a
1161 * 32-bit value. This currently can be used on Linux Alpha
1162 * which uses 64-bit virtual address but a 32-bit bus address.
1163 * This is likely to break in the future, but doing this now
1164 * will give us time to change the HW and FW to handle 64-bit
1167 #define ADV_VADDR_TO_U32 virt_to_bus
1168 #define ADV_U32_TO_VADDR bus_to_virt
1170 #define AdvPortAddr void __iomem * /* Virtual memory address size */
1173 * Define Adv Library required memory access macros.
1175 #define ADV_MEM_READB(addr) readb(addr)
1176 #define ADV_MEM_READW(addr) readw(addr)
1177 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
1178 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
1179 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
1181 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
1184 * Define total number of simultaneous maximum element scatter-gather
1185 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
1186 * maximum number of outstanding commands per wide host adapter. Each
1187 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
1188 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
1189 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
1190 * structures or 255 scatter-gather elements.
1193 #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
1196 * Define Adv Library required maximum number of scatter-gather
1197 * elements per request.
1199 #define ADV_MAX_SG_LIST 255
1201 /* Number of SG blocks needed. */
1202 #define ADV_NUM_SG_BLOCK \
1203 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK)
1205 /* Total contiguous memory needed for SG blocks. */
1206 #define ADV_SG_TOTAL_MEM_SIZE \
1207 (sizeof(ADV_SG_BLOCK) * ADV_NUM_SG_BLOCK)
1209 #define ADV_PAGE_SIZE PAGE_SIZE
1211 #define ADV_NUM_PAGE_CROSSING \
1212 ((ADV_SG_TOTAL_MEM_SIZE + (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
1214 #define ADV_EEP_DVC_CFG_BEGIN (0x00)
1215 #define ADV_EEP_DVC_CFG_END (0x15)
1216 #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
1217 #define ADV_EEP_MAX_WORD_ADDR (0x1E)
1219 #define ADV_EEP_DELAY_MS 100
1221 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
1222 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
1224 * For the ASC3550 Bit 13 is Termination Polarity control bit.
1225 * For later ICs Bit 13 controls whether the CIS (Card Information
1226 * Service Section) is loaded from EEPROM.
1228 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
1229 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
1233 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
1234 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
1235 * Function 0 will specify INT B.
1237 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
1238 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
1239 * Function 1 will specify INT A.
1241 #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
1243 typedef struct adveep_3550_config {
1244 /* Word Offset, Description */
1246 ushort cfg_lsw; /* 00 power up initialization */
1247 /* bit 13 set - Term Polarity Control */
1248 /* bit 14 set - BIOS Enable */
1249 /* bit 15 set - Big Endian Mode */
1250 ushort cfg_msw; /* 01 unused */
1251 ushort disc_enable; /* 02 disconnect enable */
1252 ushort wdtr_able; /* 03 Wide DTR able */
1253 ushort sdtr_able; /* 04 Synchronous DTR able */
1254 ushort start_motor; /* 05 send start up motor */
1255 ushort tagqng_able; /* 06 tag queuing able */
1256 ushort bios_scan; /* 07 BIOS device control */
1257 ushort scam_tolerant; /* 08 no scam */
1259 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1260 uchar bios_boot_delay; /* power up wait */
1262 uchar scsi_reset_delay; /* 10 reset delay */
1263 uchar bios_id_lun; /* first boot device scsi id & lun */
1264 /* high nibble is lun */
1265 /* low nibble is scsi id */
1267 uchar termination; /* 11 0 - automatic */
1268 /* 1 - low off / high off */
1269 /* 2 - low off / high on */
1270 /* 3 - low on / high on */
1271 /* There is no low on / high off */
1273 uchar reserved1; /* reserved byte (not used) */
1275 ushort bios_ctrl; /* 12 BIOS control bits */
1276 /* bit 0 BIOS don't act as initiator. */
1277 /* bit 1 BIOS > 1 GB support */
1278 /* bit 2 BIOS > 2 Disk Support */
1279 /* bit 3 BIOS don't support removables */
1280 /* bit 4 BIOS support bootable CD */
1281 /* bit 5 BIOS scan enabled */
1282 /* bit 6 BIOS support multiple LUNs */
1283 /* bit 7 BIOS display of message */
1284 /* bit 8 SCAM disabled */
1285 /* bit 9 Reset SCSI bus during init. */
1287 /* bit 11 No verbose initialization. */
1288 /* bit 12 SCSI parity enabled */
1292 ushort ultra_able; /* 13 ULTRA speed able */
1293 ushort reserved2; /* 14 reserved */
1294 uchar max_host_qng; /* 15 maximum host queuing */
1295 uchar max_dvc_qng; /* maximum per device queuing */
1296 ushort dvc_cntl; /* 16 control bit for driver */
1297 ushort bug_fix; /* 17 control bit for bug fix */
1298 ushort serial_number_word1; /* 18 Board serial number word 1 */
1299 ushort serial_number_word2; /* 19 Board serial number word 2 */
1300 ushort serial_number_word3; /* 20 Board serial number word 3 */
1301 ushort check_sum; /* 21 EEP check sum */
1302 uchar oem_name[16]; /* 22 OEM name */
1303 ushort dvc_err_code; /* 30 last device driver error code */
1304 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1305 ushort adv_err_addr; /* 32 last uc error address */
1306 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1307 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1308 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1309 ushort num_of_err; /* 36 number of error */
1310 } ADVEEP_3550_CONFIG;
1312 typedef struct adveep_38C0800_config {
1313 /* Word Offset, Description */
1315 ushort cfg_lsw; /* 00 power up initialization */
1316 /* bit 13 set - Load CIS */
1317 /* bit 14 set - BIOS Enable */
1318 /* bit 15 set - Big Endian Mode */
1319 ushort cfg_msw; /* 01 unused */
1320 ushort disc_enable; /* 02 disconnect enable */
1321 ushort wdtr_able; /* 03 Wide DTR able */
1322 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1323 ushort start_motor; /* 05 send start up motor */
1324 ushort tagqng_able; /* 06 tag queuing able */
1325 ushort bios_scan; /* 07 BIOS device control */
1326 ushort scam_tolerant; /* 08 no scam */
1328 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1329 uchar bios_boot_delay; /* power up wait */
1331 uchar scsi_reset_delay; /* 10 reset delay */
1332 uchar bios_id_lun; /* first boot device scsi id & lun */
1333 /* high nibble is lun */
1334 /* low nibble is scsi id */
1336 uchar termination_se; /* 11 0 - automatic */
1337 /* 1 - low off / high off */
1338 /* 2 - low off / high on */
1339 /* 3 - low on / high on */
1340 /* There is no low on / high off */
1342 uchar termination_lvd; /* 11 0 - automatic */
1343 /* 1 - low off / high off */
1344 /* 2 - low off / high on */
1345 /* 3 - low on / high on */
1346 /* There is no low on / high off */
1348 ushort bios_ctrl; /* 12 BIOS control bits */
1349 /* bit 0 BIOS don't act as initiator. */
1350 /* bit 1 BIOS > 1 GB support */
1351 /* bit 2 BIOS > 2 Disk Support */
1352 /* bit 3 BIOS don't support removables */
1353 /* bit 4 BIOS support bootable CD */
1354 /* bit 5 BIOS scan enabled */
1355 /* bit 6 BIOS support multiple LUNs */
1356 /* bit 7 BIOS display of message */
1357 /* bit 8 SCAM disabled */
1358 /* bit 9 Reset SCSI bus during init. */
1360 /* bit 11 No verbose initialization. */
1361 /* bit 12 SCSI parity enabled */
1365 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1366 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1367 uchar max_host_qng; /* 15 maximum host queueing */
1368 uchar max_dvc_qng; /* maximum per device queuing */
1369 ushort dvc_cntl; /* 16 control bit for driver */
1370 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1371 ushort serial_number_word1; /* 18 Board serial number word 1 */
1372 ushort serial_number_word2; /* 19 Board serial number word 2 */
1373 ushort serial_number_word3; /* 20 Board serial number word 3 */
1374 ushort check_sum; /* 21 EEP check sum */
1375 uchar oem_name[16]; /* 22 OEM name */
1376 ushort dvc_err_code; /* 30 last device driver error code */
1377 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1378 ushort adv_err_addr; /* 32 last uc error address */
1379 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1380 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1381 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1382 ushort reserved36; /* 36 reserved */
1383 ushort reserved37; /* 37 reserved */
1384 ushort reserved38; /* 38 reserved */
1385 ushort reserved39; /* 39 reserved */
1386 ushort reserved40; /* 40 reserved */
1387 ushort reserved41; /* 41 reserved */
1388 ushort reserved42; /* 42 reserved */
1389 ushort reserved43; /* 43 reserved */
1390 ushort reserved44; /* 44 reserved */
1391 ushort reserved45; /* 45 reserved */
1392 ushort reserved46; /* 46 reserved */
1393 ushort reserved47; /* 47 reserved */
1394 ushort reserved48; /* 48 reserved */
1395 ushort reserved49; /* 49 reserved */
1396 ushort reserved50; /* 50 reserved */
1397 ushort reserved51; /* 51 reserved */
1398 ushort reserved52; /* 52 reserved */
1399 ushort reserved53; /* 53 reserved */
1400 ushort reserved54; /* 54 reserved */
1401 ushort reserved55; /* 55 reserved */
1402 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1403 ushort cisprt_msw; /* 57 CIS PTR MSW */
1404 ushort subsysvid; /* 58 SubSystem Vendor ID */
1405 ushort subsysid; /* 59 SubSystem ID */
1406 ushort reserved60; /* 60 reserved */
1407 ushort reserved61; /* 61 reserved */
1408 ushort reserved62; /* 62 reserved */
1409 ushort reserved63; /* 63 reserved */
1410 } ADVEEP_38C0800_CONFIG;
1412 typedef struct adveep_38C1600_config {
1413 /* Word Offset, Description */
1415 ushort cfg_lsw; /* 00 power up initialization */
1416 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
1417 /* clear - Func. 0 INTA, Func. 1 INTB */
1418 /* bit 13 set - Load CIS */
1419 /* bit 14 set - BIOS Enable */
1420 /* bit 15 set - Big Endian Mode */
1421 ushort cfg_msw; /* 01 unused */
1422 ushort disc_enable; /* 02 disconnect enable */
1423 ushort wdtr_able; /* 03 Wide DTR able */
1424 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1425 ushort start_motor; /* 05 send start up motor */
1426 ushort tagqng_able; /* 06 tag queuing able */
1427 ushort bios_scan; /* 07 BIOS device control */
1428 ushort scam_tolerant; /* 08 no scam */
1430 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1431 uchar bios_boot_delay; /* power up wait */
1433 uchar scsi_reset_delay; /* 10 reset delay */
1434 uchar bios_id_lun; /* first boot device scsi id & lun */
1435 /* high nibble is lun */
1436 /* low nibble is scsi id */
1438 uchar termination_se; /* 11 0 - automatic */
1439 /* 1 - low off / high off */
1440 /* 2 - low off / high on */
1441 /* 3 - low on / high on */
1442 /* There is no low on / high off */
1444 uchar termination_lvd; /* 11 0 - automatic */
1445 /* 1 - low off / high off */
1446 /* 2 - low off / high on */
1447 /* 3 - low on / high on */
1448 /* There is no low on / high off */
1450 ushort bios_ctrl; /* 12 BIOS control bits */
1451 /* bit 0 BIOS don't act as initiator. */
1452 /* bit 1 BIOS > 1 GB support */
1453 /* bit 2 BIOS > 2 Disk Support */
1454 /* bit 3 BIOS don't support removables */
1455 /* bit 4 BIOS support bootable CD */
1456 /* bit 5 BIOS scan enabled */
1457 /* bit 6 BIOS support multiple LUNs */
1458 /* bit 7 BIOS display of message */
1459 /* bit 8 SCAM disabled */
1460 /* bit 9 Reset SCSI bus during init. */
1461 /* bit 10 Basic Integrity Checking disabled */
1462 /* bit 11 No verbose initialization. */
1463 /* bit 12 SCSI parity enabled */
1464 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1467 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1468 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1469 uchar max_host_qng; /* 15 maximum host queueing */
1470 uchar max_dvc_qng; /* maximum per device queuing */
1471 ushort dvc_cntl; /* 16 control bit for driver */
1472 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1473 ushort serial_number_word1; /* 18 Board serial number word 1 */
1474 ushort serial_number_word2; /* 19 Board serial number word 2 */
1475 ushort serial_number_word3; /* 20 Board serial number word 3 */
1476 ushort check_sum; /* 21 EEP check sum */
1477 uchar oem_name[16]; /* 22 OEM name */
1478 ushort dvc_err_code; /* 30 last device driver error code */
1479 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1480 ushort adv_err_addr; /* 32 last uc error address */
1481 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1482 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1483 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1484 ushort reserved36; /* 36 reserved */
1485 ushort reserved37; /* 37 reserved */
1486 ushort reserved38; /* 38 reserved */
1487 ushort reserved39; /* 39 reserved */
1488 ushort reserved40; /* 40 reserved */
1489 ushort reserved41; /* 41 reserved */
1490 ushort reserved42; /* 42 reserved */
1491 ushort reserved43; /* 43 reserved */
1492 ushort reserved44; /* 44 reserved */
1493 ushort reserved45; /* 45 reserved */
1494 ushort reserved46; /* 46 reserved */
1495 ushort reserved47; /* 47 reserved */
1496 ushort reserved48; /* 48 reserved */
1497 ushort reserved49; /* 49 reserved */
1498 ushort reserved50; /* 50 reserved */
1499 ushort reserved51; /* 51 reserved */
1500 ushort reserved52; /* 52 reserved */
1501 ushort reserved53; /* 53 reserved */
1502 ushort reserved54; /* 54 reserved */
1503 ushort reserved55; /* 55 reserved */
1504 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1505 ushort cisprt_msw; /* 57 CIS PTR MSW */
1506 ushort subsysvid; /* 58 SubSystem Vendor ID */
1507 ushort subsysid; /* 59 SubSystem ID */
1508 ushort reserved60; /* 60 reserved */
1509 ushort reserved61; /* 61 reserved */
1510 ushort reserved62; /* 62 reserved */
1511 ushort reserved63; /* 63 reserved */
1512 } ADVEEP_38C1600_CONFIG;
1517 #define ASC_EEP_CMD_DONE 0x0200
1518 #define ASC_EEP_CMD_DONE_ERR 0x0001
1521 #define EEP_CFG_WORD_BIG_ENDIAN 0x8000
1524 #define BIOS_CTRL_BIOS 0x0001
1525 #define BIOS_CTRL_EXTENDED_XLAT 0x0002
1526 #define BIOS_CTRL_GT_2_DISK 0x0004
1527 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008
1528 #define BIOS_CTRL_BOOTABLE_CD 0x0010
1529 #define BIOS_CTRL_MULTIPLE_LUN 0x0040
1530 #define BIOS_CTRL_DISPLAY_MSG 0x0080
1531 #define BIOS_CTRL_NO_SCAM 0x0100
1532 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200
1533 #define BIOS_CTRL_INIT_VERBOSE 0x0800
1534 #define BIOS_CTRL_SCSI_PARITY 0x1000
1535 #define BIOS_CTRL_AIPP_DIS 0x2000
1537 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
1539 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1542 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1543 * a special 16K Adv Library and Microcode version. After the issue is
1544 * resolved, should restore 32K support.
1546 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
1548 #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1551 * Byte I/O register address from base of 'iop_base'.
1553 #define IOPB_INTR_STATUS_REG 0x00
1554 #define IOPB_CHIP_ID_1 0x01
1555 #define IOPB_INTR_ENABLES 0x02
1556 #define IOPB_CHIP_TYPE_REV 0x03
1557 #define IOPB_RES_ADDR_4 0x04
1558 #define IOPB_RES_ADDR_5 0x05
1559 #define IOPB_RAM_DATA 0x06
1560 #define IOPB_RES_ADDR_7 0x07
1561 #define IOPB_FLAG_REG 0x08
1562 #define IOPB_RES_ADDR_9 0x09
1563 #define IOPB_RISC_CSR 0x0A
1564 #define IOPB_RES_ADDR_B 0x0B
1565 #define IOPB_RES_ADDR_C 0x0C
1566 #define IOPB_RES_ADDR_D 0x0D
1567 #define IOPB_SOFT_OVER_WR 0x0E
1568 #define IOPB_RES_ADDR_F 0x0F
1569 #define IOPB_MEM_CFG 0x10
1570 #define IOPB_RES_ADDR_11 0x11
1571 #define IOPB_GPIO_DATA 0x12
1572 #define IOPB_RES_ADDR_13 0x13
1573 #define IOPB_FLASH_PAGE 0x14
1574 #define IOPB_RES_ADDR_15 0x15
1575 #define IOPB_GPIO_CNTL 0x16
1576 #define IOPB_RES_ADDR_17 0x17
1577 #define IOPB_FLASH_DATA 0x18
1578 #define IOPB_RES_ADDR_19 0x19
1579 #define IOPB_RES_ADDR_1A 0x1A
1580 #define IOPB_RES_ADDR_1B 0x1B
1581 #define IOPB_RES_ADDR_1C 0x1C
1582 #define IOPB_RES_ADDR_1D 0x1D
1583 #define IOPB_RES_ADDR_1E 0x1E
1584 #define IOPB_RES_ADDR_1F 0x1F
1585 #define IOPB_DMA_CFG0 0x20
1586 #define IOPB_DMA_CFG1 0x21
1587 #define IOPB_TICKLE 0x22
1588 #define IOPB_DMA_REG_WR 0x23
1589 #define IOPB_SDMA_STATUS 0x24
1590 #define IOPB_SCSI_BYTE_CNT 0x25
1591 #define IOPB_HOST_BYTE_CNT 0x26
1592 #define IOPB_BYTE_LEFT_TO_XFER 0x27
1593 #define IOPB_BYTE_TO_XFER_0 0x28
1594 #define IOPB_BYTE_TO_XFER_1 0x29
1595 #define IOPB_BYTE_TO_XFER_2 0x2A
1596 #define IOPB_BYTE_TO_XFER_3 0x2B
1597 #define IOPB_ACC_GRP 0x2C
1598 #define IOPB_RES_ADDR_2D 0x2D
1599 #define IOPB_DEV_ID 0x2E
1600 #define IOPB_RES_ADDR_2F 0x2F
1601 #define IOPB_SCSI_DATA 0x30
1602 #define IOPB_RES_ADDR_31 0x31
1603 #define IOPB_RES_ADDR_32 0x32
1604 #define IOPB_SCSI_DATA_HSHK 0x33
1605 #define IOPB_SCSI_CTRL 0x34
1606 #define IOPB_RES_ADDR_35 0x35
1607 #define IOPB_RES_ADDR_36 0x36
1608 #define IOPB_RES_ADDR_37 0x37
1609 #define IOPB_RAM_BIST 0x38
1610 #define IOPB_PLL_TEST 0x39
1611 #define IOPB_PCI_INT_CFG 0x3A
1612 #define IOPB_RES_ADDR_3B 0x3B
1613 #define IOPB_RFIFO_CNT 0x3C
1614 #define IOPB_RES_ADDR_3D 0x3D
1615 #define IOPB_RES_ADDR_3E 0x3E
1616 #define IOPB_RES_ADDR_3F 0x3F
1619 * Word I/O register address from base of 'iop_base'.
1621 #define IOPW_CHIP_ID_0 0x00 /* CID0 */
1622 #define IOPW_CTRL_REG 0x02 /* CC */
1623 #define IOPW_RAM_ADDR 0x04 /* LA */
1624 #define IOPW_RAM_DATA 0x06 /* LD */
1625 #define IOPW_RES_ADDR_08 0x08
1626 #define IOPW_RISC_CSR 0x0A /* CSR */
1627 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */
1628 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */
1629 #define IOPW_RES_ADDR_10 0x10
1630 #define IOPW_SEL_MASK 0x12 /* SM */
1631 #define IOPW_RES_ADDR_14 0x14
1632 #define IOPW_FLASH_ADDR 0x16 /* FA */
1633 #define IOPW_RES_ADDR_18 0x18
1634 #define IOPW_EE_CMD 0x1A /* EC */
1635 #define IOPW_EE_DATA 0x1C /* ED */
1636 #define IOPW_SFIFO_CNT 0x1E /* SFC */
1637 #define IOPW_RES_ADDR_20 0x20
1638 #define IOPW_Q_BASE 0x22 /* QB */
1639 #define IOPW_QP 0x24 /* QP */
1640 #define IOPW_IX 0x26 /* IX */
1641 #define IOPW_SP 0x28 /* SP */
1642 #define IOPW_PC 0x2A /* PC */
1643 #define IOPW_RES_ADDR_2C 0x2C
1644 #define IOPW_RES_ADDR_2E 0x2E
1645 #define IOPW_SCSI_DATA 0x30 /* SD */
1646 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
1647 #define IOPW_SCSI_CTRL 0x34 /* SC */
1648 #define IOPW_HSHK_CFG 0x36 /* HCFG */
1649 #define IOPW_SXFR_STATUS 0x36 /* SXS */
1650 #define IOPW_SXFR_CNTL 0x38 /* SXL */
1651 #define IOPW_SXFR_CNTH 0x3A /* SXH */
1652 #define IOPW_RES_ADDR_3C 0x3C
1653 #define IOPW_RFIFO_DATA 0x3E /* RFD */
1656 * Doubleword I/O register address from base of 'iop_base'.
1658 #define IOPDW_RES_ADDR_0 0x00
1659 #define IOPDW_RAM_DATA 0x04
1660 #define IOPDW_RES_ADDR_8 0x08
1661 #define IOPDW_RES_ADDR_C 0x0C
1662 #define IOPDW_RES_ADDR_10 0x10
1663 #define IOPDW_COMMA 0x14
1664 #define IOPDW_COMMB 0x18
1665 #define IOPDW_RES_ADDR_1C 0x1C
1666 #define IOPDW_SDMA_ADDR0 0x20
1667 #define IOPDW_SDMA_ADDR1 0x24
1668 #define IOPDW_SDMA_COUNT 0x28
1669 #define IOPDW_SDMA_ERROR 0x2C
1670 #define IOPDW_RDMA_ADDR0 0x30
1671 #define IOPDW_RDMA_ADDR1 0x34
1672 #define IOPDW_RDMA_COUNT 0x38
1673 #define IOPDW_RDMA_ERROR 0x3C
1675 #define ADV_CHIP_ID_BYTE 0x25
1676 #define ADV_CHIP_ID_WORD 0x04C1
1678 #define ADV_SC_SCSI_BUS_RESET 0x2000
1680 #define ADV_INTR_ENABLE_HOST_INTR 0x01
1681 #define ADV_INTR_ENABLE_SEL_INTR 0x02
1682 #define ADV_INTR_ENABLE_DPR_INTR 0x04
1683 #define ADV_INTR_ENABLE_RTA_INTR 0x08
1684 #define ADV_INTR_ENABLE_RMA_INTR 0x10
1685 #define ADV_INTR_ENABLE_RST_INTR 0x20
1686 #define ADV_INTR_ENABLE_DPE_INTR 0x40
1687 #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
1689 #define ADV_INTR_STATUS_INTRA 0x01
1690 #define ADV_INTR_STATUS_INTRB 0x02
1691 #define ADV_INTR_STATUS_INTRC 0x04
1693 #define ADV_RISC_CSR_STOP (0x0000)
1694 #define ADV_RISC_TEST_COND (0x2000)
1695 #define ADV_RISC_CSR_RUN (0x4000)
1696 #define ADV_RISC_CSR_SINGLE_STEP (0x8000)
1698 #define ADV_CTRL_REG_HOST_INTR 0x0100
1699 #define ADV_CTRL_REG_SEL_INTR 0x0200
1700 #define ADV_CTRL_REG_DPR_INTR 0x0400
1701 #define ADV_CTRL_REG_RTA_INTR 0x0800
1702 #define ADV_CTRL_REG_RMA_INTR 0x1000
1703 #define ADV_CTRL_REG_RES_BIT14 0x2000
1704 #define ADV_CTRL_REG_DPE_INTR 0x4000
1705 #define ADV_CTRL_REG_POWER_DONE 0x8000
1706 #define ADV_CTRL_REG_ANY_INTR 0xFF00
1708 #define ADV_CTRL_REG_CMD_RESET 0x00C6
1709 #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
1710 #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
1711 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
1712 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
1714 #define ADV_TICKLE_NOP 0x00
1715 #define ADV_TICKLE_A 0x01
1716 #define ADV_TICKLE_B 0x02
1717 #define ADV_TICKLE_C 0x03
1719 #define ADV_SCSI_CTRL_RSTOUT 0x2000
1721 #define AdvIsIntPending(port) \
1722 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1725 * SCSI_CFG0 Register bit definitions
1727 #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
1728 #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
1729 #define EVEN_PARITY 0x1000 /* Select Even Parity */
1730 #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1731 #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
1732 #define PRIM_MODE 0x0100 /* Primitive SCSI mode */
1733 #define SCAM_EN 0x0080 /* Enable SCAM selection */
1734 #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1735 #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1736 #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
1737 #define OUR_ID 0x000F /* SCSI ID */
1740 * SCSI_CFG1 Register bit definitions
1742 #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
1743 #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1744 #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
1745 #define FILTER_SEL 0x0C00 /* Filter Period Selection */
1746 #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
1747 #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1748 #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1749 #define ACTIVE_DBL 0x0200 /* Disable Active Negation */
1750 #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
1751 #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
1752 #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
1753 #define TERM_CTL 0x0030 /* External SCSI Termination Bits */
1754 #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
1755 #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
1756 #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
1759 * Addendum for ASC-38C0800 Chip
1761 * The ASC-38C1600 Chip uses the same definitions except that the
1762 * bus mode override bits [12:10] have been moved to byte register
1763 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1764 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1765 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1766 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1767 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1769 #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
1770 #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
1771 #define HVD 0x1000 /* HVD Device Detect */
1772 #define LVD 0x0800 /* LVD Device Detect */
1773 #define SE 0x0400 /* SE Device Detect */
1774 #define TERM_LVD 0x00C0 /* LVD Termination Bits */
1775 #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
1776 #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
1777 #define TERM_SE 0x0030 /* SE Termination Bits */
1778 #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
1779 #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
1780 #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
1781 #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
1782 #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
1783 #define C_DET_SE 0x0003 /* SE Cable Detect Bits */
1784 #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
1785 #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
1787 #define CABLE_ILLEGAL_A 0x7
1788 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
1790 #define CABLE_ILLEGAL_B 0xB
1791 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
1794 * MEM_CFG Register bit definitions
1796 #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
1797 #define FAST_EE_CLK 0x20 /* Diagnostic Bit */
1798 #define RAM_SZ 0x1C /* Specify size of RAM to RISC */
1799 #define RAM_SZ_2KB 0x00 /* 2 KB */
1800 #define RAM_SZ_4KB 0x04 /* 4 KB */
1801 #define RAM_SZ_8KB 0x08 /* 8 KB */
1802 #define RAM_SZ_16KB 0x0C /* 16 KB */
1803 #define RAM_SZ_32KB 0x10 /* 32 KB */
1804 #define RAM_SZ_64KB 0x14 /* 64 KB */
1807 * DMA_CFG0 Register bit definitions
1809 * This register is only accessible to the host.
1811 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
1812 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
1813 #define FIFO_THRESH_16B 0x00 /* 16 bytes */
1814 #define FIFO_THRESH_32B 0x20 /* 32 bytes */
1815 #define FIFO_THRESH_48B 0x30 /* 48 bytes */
1816 #define FIFO_THRESH_64B 0x40 /* 64 bytes */
1817 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
1818 #define FIFO_THRESH_96B 0x60 /* 96 bytes */
1819 #define FIFO_THRESH_112B 0x70 /* 112 bytes */
1820 #define START_CTL 0x0C /* DMA start conditions */
1821 #define START_CTL_TH 0x00 /* Wait threshold level (default) */
1822 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
1823 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
1824 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
1825 #define READ_CMD 0x03 /* Memory Read Method */
1826 #define READ_CMD_MR 0x00 /* Memory Read */
1827 #define READ_CMD_MRL 0x02 /* Memory Read Long */
1828 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
1831 * ASC-38C0800 RAM BIST Register bit definitions
1833 #define RAM_TEST_MODE 0x80
1834 #define PRE_TEST_MODE 0x40
1835 #define NORMAL_MODE 0x00
1836 #define RAM_TEST_DONE 0x10
1837 #define RAM_TEST_STATUS 0x0F
1838 #define RAM_TEST_HOST_ERROR 0x08
1839 #define RAM_TEST_INTRAM_ERROR 0x04
1840 #define RAM_TEST_RISC_ERROR 0x02
1841 #define RAM_TEST_SCSI_ERROR 0x01
1842 #define RAM_TEST_SUCCESS 0x00
1843 #define PRE_TEST_VALUE 0x05
1844 #define NORMAL_VALUE 0x00
1847 * ASC38C1600 Definitions
1849 * IOPB_PCI_INT_CFG Bit Field Definitions
1852 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
1855 * Bit 1 can be set to change the interrupt for the Function to operate in
1856 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1857 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1858 * mode, otherwise the operating mode is undefined.
1860 #define TOTEMPOLE 0x02
1863 * Bit 0 can be used to change the Int Pin for the Function. The value is
1864 * 0 by default for both Functions with Function 0 using INT A and Function
1865 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1868 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1869 * value specified in the PCI Configuration Space.
1876 * Adv Library Status Definitions
1880 #define ADV_NOERROR 1
1881 #define ADV_SUCCESS 1
1883 #define ADV_ERROR (-1)
1886 * ADV_DVC_VAR 'warn_code' values
1888 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
1889 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
1890 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
1891 #define ASC_WARN_SET_PCI_CONFIG_SPACE 0x0080 /* PCI config space set error */
1892 #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
1894 #define ADV_MAX_TID 15 /* max. target identifier */
1895 #define ADV_MAX_LUN 7 /* max. logical unit number */
1898 * Error code values are set in ADV_DVC_VAR 'err_code'.
1900 #define ASC_IERR_WRITE_EEPROM 0x0001 /* write EEPROM error */
1901 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
1902 #define ASC_IERR_NO_CARRIER 0x0004 /* No more carrier memory. */
1903 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
1904 #define ASC_IERR_CHIP_VERSION 0x0040 /* wrong chip version */
1905 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
1906 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD attached to LVD connector. */
1907 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
1908 #define ASC_IERR_ILLEGAL_CONNECTION 0x0400 /* Illegal cable connection */
1909 #define ASC_IERR_SINGLE_END_DEVICE 0x0800 /* Single-end used w/differential */
1910 #define ASC_IERR_REVERSED_CABLE 0x1000 /* Narrow flat cable reversed */
1911 #define ASC_IERR_BIST_PRE_TEST 0x2000 /* BIST pre-test error */
1912 #define ASC_IERR_BIST_RAM_TEST 0x4000 /* BIST RAM test error */
1913 #define ASC_IERR_BAD_CHIPTYPE 0x8000 /* Invalid 'chip_type' setting. */
1916 * Fixed locations of microcode operating variables.
1918 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
1919 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
1920 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
1921 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
1922 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */
1923 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
1924 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
1925 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
1926 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
1927 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
1928 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
1929 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
1930 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
1931 #define ASC_MC_CHIP_TYPE 0x009A
1932 #define ASC_MC_INTRB_CODE 0x009B
1933 #define ASC_MC_WDTR_ABLE 0x009C
1934 #define ASC_MC_SDTR_ABLE 0x009E
1935 #define ASC_MC_TAGQNG_ABLE 0x00A0
1936 #define ASC_MC_DISC_ENABLE 0x00A2
1937 #define ASC_MC_IDLE_CMD_STATUS 0x00A4
1938 #define ASC_MC_IDLE_CMD 0x00A6
1939 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
1940 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
1941 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
1942 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0
1943 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2
1944 #define ASC_MC_SDTR_DONE 0x00B6
1945 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
1946 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
1947 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
1948 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
1949 #define ASC_MC_WDTR_DONE 0x0124
1950 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
1951 #define ASC_MC_ICQ 0x0160
1952 #define ASC_MC_IRQ 0x0164
1953 #define ASC_MC_PPR_ABLE 0x017A
1956 * BIOS LRAM variable absolute offsets.
1958 #define BIOS_CODESEG 0x54
1959 #define BIOS_CODELEN 0x56
1960 #define BIOS_SIGNATURE 0x58
1961 #define BIOS_VERSION 0x5A
1964 * Microcode Control Flags
1966 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1967 * and handled by the microcode.
1969 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
1970 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
1973 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1975 #define HSHK_CFG_WIDE_XFR 0x8000
1976 #define HSHK_CFG_RATE 0x0F00
1977 #define HSHK_CFG_OFFSET 0x001F
1979 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
1980 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
1981 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
1982 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
1984 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1985 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
1986 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1987 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
1988 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1990 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
1991 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
1992 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
1993 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
1994 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
1996 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1997 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1999 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
2000 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
2003 * All fields here are accessed by the board microcode and need to be
2006 typedef struct adv_carr_t {
2007 ADV_VADDR carr_va; /* Carrier Virtual Address */
2008 ADV_PADDR carr_pa; /* Carrier Physical Address */
2009 ADV_VADDR areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
2011 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
2013 * next_vpa [3:1] Reserved Bits
2014 * next_vpa [0] Done Flag set in Response Queue.
2020 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
2022 #define ASC_NEXT_VPA_MASK 0xFFFFFFF0
2024 #define ASC_RQ_DONE 0x00000001
2025 #define ASC_RQ_GOOD 0x00000002
2026 #define ASC_CQ_STOPPER 0x00000000
2028 #define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
2030 #define ADV_CARRIER_NUM_PAGE_CROSSING \
2031 (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + \
2032 (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
2034 #define ADV_CARRIER_BUFSIZE \
2035 ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
2038 * ASC_SCSI_REQ_Q 'a_flag' definitions
2040 * The Adv Library should limit use to the lower nibble (4 bits) of
2041 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
2043 #define ADV_POLL_REQUEST 0x01 /* poll for request completion */
2044 #define ADV_SCSIQ_DONE 0x02 /* request done */
2045 #define ADV_DONT_RETRY 0x08 /* don't do retry */
2047 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
2048 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
2049 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
2052 * Adapter temporary configuration structure
2054 * This structure can be discarded after initialization. Don't add
2055 * fields here needed after initialization.
2057 * Field naming convention:
2059 * *_enable indicates the field enables or disables a feature. The
2060 * value of the field is never reset.
2062 typedef struct adv_dvc_cfg {
2063 ushort disc_enable; /* enable disconnection */
2064 uchar chip_version; /* chip version */
2065 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
2066 ushort lib_version; /* Adv Library version number */
2067 ushort control_flag; /* Microcode Control Flag */
2068 ushort mcode_date; /* Microcode date */
2069 ushort mcode_version; /* Microcode version */
2070 ushort serial1; /* EEPROM serial number word 1 */
2071 ushort serial2; /* EEPROM serial number word 2 */
2072 ushort serial3; /* EEPROM serial number word 3 */
2076 struct adv_scsi_req_q;
2079 * Adapter operation variable structure.
2081 * One structure is required per host adapter.
2083 * Field naming convention:
2085 * *_able indicates both whether a feature should be enabled or disabled
2086 * and whether a device isi capable of the feature. At initialization
2087 * this field may be set, but later if a device is found to be incapable
2088 * of the feature, the field is cleared.
2090 typedef struct adv_dvc_var {
2091 AdvPortAddr iop_base; /* I/O port address */
2092 ushort err_code; /* fatal error code */
2093 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
2094 ushort wdtr_able; /* try WDTR for a device */
2095 ushort sdtr_able; /* try SDTR for a device */
2096 ushort ultra_able; /* try SDTR Ultra speed for a device */
2097 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
2098 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
2099 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
2100 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
2101 ushort tagqng_able; /* try tagged queuing with a device */
2102 ushort ppr_able; /* PPR message capable per TID bitmask. */
2103 uchar max_dvc_qng; /* maximum number of tagged commands per device */
2104 ushort start_motor; /* start motor command allowed */
2105 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
2106 uchar chip_no; /* should be assigned by caller */
2107 uchar max_host_qng; /* maximum number of Q'ed command allowed */
2108 uchar irq_no; /* IRQ number */
2109 ushort no_scam; /* scam_tolerant of EEPROM */
2110 struct asc_board *drv_ptr; /* driver pointer to private structure */
2111 uchar chip_scsi_id; /* chip SCSI target ID */
2113 uchar bist_err_code;
2114 ADV_CARR_T *carrier_buf;
2115 ADV_CARR_T *carr_freelist; /* Carrier free list. */
2116 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
2117 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
2118 ushort carr_pending_cnt; /* Count of pending carriers. */
2120 * Note: The following fields will not be used after initialization. The
2121 * driver may discard the buffer after initialization is done.
2123 ADV_DVC_CFG *cfg; /* temporary configuration structure */
2126 #define NO_OF_SG_PER_BLOCK 15
2128 typedef struct asc_sg_block {
2132 uchar sg_cnt; /* Valid entries in block. */
2133 ADV_PADDR sg_ptr; /* Pointer to next sg block. */
2135 ADV_PADDR sg_addr; /* SG element address. */
2136 ADV_DCNT sg_count; /* SG element count. */
2137 } sg_list[NO_OF_SG_PER_BLOCK];
2141 * ADV_SCSI_REQ_Q - microcode request structure
2143 * All fields in this structure up to byte 60 are used by the microcode.
2144 * The microcode makes assumptions about the size and ordering of fields
2145 * in this structure. Do not change the structure definition here without
2146 * coordinating the change with the microcode.
2148 * All fields accessed by microcode must be maintained in little_endian
2151 typedef struct adv_scsi_req_q {
2152 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
2154 uchar target_id; /* Device target identifier. */
2155 uchar target_lun; /* Device target logical unit number. */
2156 ADV_PADDR data_addr; /* Data buffer physical address. */
2157 ADV_DCNT data_cnt; /* Data count. Ucode sets to residual. */
2158 ADV_PADDR sense_addr;
2162 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
2164 uchar done_status; /* Completion status. */
2165 uchar scsi_status; /* SCSI status byte. */
2166 uchar host_status; /* Ucode host status. */
2167 uchar sg_working_ix;
2168 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
2169 ADV_PADDR sg_real_addr; /* SG list physical address. */
2170 ADV_PADDR scsiq_rptr;
2171 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
2172 ADV_VADDR scsiq_ptr;
2175 * End of microcode structure - 60 bytes. The rest of the structure
2176 * is used by the Adv Library and ignored by the microcode.
2179 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
2180 char *vdata_addr; /* Data buffer virtual address. */
2182 uchar pad[2]; /* Pad out to a word boundary. */
2186 * Microcode idle loop commands
2188 #define IDLE_CMD_COMPLETED 0
2189 #define IDLE_CMD_STOP_CHIP 0x0001
2190 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
2191 #define IDLE_CMD_SEND_INT 0x0004
2192 #define IDLE_CMD_ABORT 0x0008
2193 #define IDLE_CMD_DEVICE_RESET 0x0010
2194 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
2195 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
2196 #define IDLE_CMD_SCSIREQ 0x0080
2198 #define IDLE_CMD_STATUS_SUCCESS 0x0001
2199 #define IDLE_CMD_STATUS_FAILURE 0x0002
2202 * AdvSendIdleCmd() flag definitions.
2204 #define ADV_NOWAIT 0x01
2207 * Wait loop time out values.
2209 #define SCSI_WAIT_10_SEC 10UL /* 10 seconds */
2210 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
2211 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
2212 #define SCSI_MS_PER_SEC 1000UL /* milliseconds per second */
2213 #define SCSI_MAX_RETRY 10 /* retry count */
2215 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
2216 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
2217 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
2218 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
2220 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
2222 static ADV_PADDR DvcGetPhyAddr(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *,
2223 uchar *, ASC_SDCNT *, int);
2226 * Adv Library functions available to drivers.
2228 static int AdvExeScsiQueue(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *);
2229 static int AdvISR(ADV_DVC_VAR *);
2230 static int AdvInitAsc3550Driver(ADV_DVC_VAR *);
2231 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *);
2232 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *);
2233 static int AdvResetChipAndSB(ADV_DVC_VAR *);
2234 static int AdvResetSB(ADV_DVC_VAR *asc_dvc);
2237 * Internal Adv Library functions.
2239 static int AdvSendIdleCmd(ADV_DVC_VAR *, ushort, ADV_DCNT);
2240 static int AdvInitFrom3550EEP(ADV_DVC_VAR *);
2241 static int AdvInitFrom38C0800EEP(ADV_DVC_VAR *);
2242 static int AdvInitFrom38C1600EEP(ADV_DVC_VAR *);
2243 static ushort AdvGet3550EEPConfig(AdvPortAddr, ADVEEP_3550_CONFIG *);
2244 static void AdvSet3550EEPConfig(AdvPortAddr, ADVEEP_3550_CONFIG *);
2245 static ushort AdvGet38C0800EEPConfig(AdvPortAddr, ADVEEP_38C0800_CONFIG *);
2246 static void AdvSet38C0800EEPConfig(AdvPortAddr, ADVEEP_38C0800_CONFIG *);
2247 static ushort AdvGet38C1600EEPConfig(AdvPortAddr, ADVEEP_38C1600_CONFIG *);
2248 static void AdvSet38C1600EEPConfig(AdvPortAddr, ADVEEP_38C1600_CONFIG *);
2249 static void AdvWaitEEPCmd(AdvPortAddr);
2250 static ushort AdvReadEEPWord(AdvPortAddr, int);
2252 /* Read byte from a register. */
2253 #define AdvReadByteRegister(iop_base, reg_off) \
2254 (ADV_MEM_READB((iop_base) + (reg_off)))
2256 /* Write byte to a register. */
2257 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
2258 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
2260 /* Read word (2 bytes) from a register. */
2261 #define AdvReadWordRegister(iop_base, reg_off) \
2262 (ADV_MEM_READW((iop_base) + (reg_off)))
2264 /* Write word (2 bytes) to a register. */
2265 #define AdvWriteWordRegister(iop_base, reg_off, word) \
2266 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
2268 /* Write dword (4 bytes) to a register. */
2269 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
2270 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
2272 /* Read byte from LRAM. */
2273 #define AdvReadByteLram(iop_base, addr, byte) \
2275 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2276 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
2279 /* Write byte to LRAM. */
2280 #define AdvWriteByteLram(iop_base, addr, byte) \
2281 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2282 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
2284 /* Read word (2 bytes) from LRAM. */
2285 #define AdvReadWordLram(iop_base, addr, word) \
2287 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2288 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
2291 /* Write word (2 bytes) to LRAM. */
2292 #define AdvWriteWordLram(iop_base, addr, word) \
2293 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2294 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2296 /* Write little-endian double word (4 bytes) to LRAM */
2297 /* Because of unspecified C language ordering don't use auto-increment. */
2298 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
2299 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2300 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2301 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
2302 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
2303 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2304 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
2306 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
2307 #define AdvReadWordAutoIncLram(iop_base) \
2308 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
2310 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
2311 #define AdvWriteWordAutoIncLram(iop_base, word) \
2312 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2315 * Define macro to check for Condor signature.
2317 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
2318 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
2320 #define AdvFindSignature(iop_base) \
2321 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
2322 ADV_CHIP_ID_BYTE) && \
2323 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
2324 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
2327 * Define macro to Return the version number of the chip at 'iop_base'.
2329 * The second parameter 'bus_type' is currently unused.
2331 #define AdvGetChipVersion(iop_base, bus_type) \
2332 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
2335 * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
2336 * match the ASC_SCSI_REQ_Q 'srb_ptr' field.
2338 * If the request has not yet been sent to the device it will simply be
2339 * aborted from RISC memory. If the request is disconnected it will be
2340 * aborted on reselection by sending an Abort Message to the target ID.
2343 * ADV_TRUE(1) - Queue was successfully aborted.
2344 * ADV_FALSE(0) - Queue was not found on the active queue list.
2346 #define AdvAbortQueue(asc_dvc, scsiq) \
2347 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2351 * Send a Bus Device Reset Message to the specified target ID.
2353 * All outstanding commands will be purged if sending the
2354 * Bus Device Reset Message is successful.
2357 * ADV_TRUE(1) - All requests on the target are purged.
2358 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2361 #define AdvResetDevice(asc_dvc, target_id) \
2362 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2363 (ADV_DCNT) (target_id))
2366 * SCSI Wide Type definition.
2368 #define ADV_SCSI_BIT_ID_TYPE ushort
2371 * AdvInitScsiTarget() 'cntl_flag' options.
2373 #define ADV_SCAN_LUN 0x01
2374 #define ADV_CAPINFO_NOLUN 0x02
2377 * Convert target id to target id bit mask.
2379 #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
2382 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2385 #define QD_NO_STATUS 0x00 /* Request not completed yet. */
2386 #define QD_NO_ERROR 0x01
2387 #define QD_ABORTED_BY_HOST 0x02
2388 #define QD_WITH_ERROR 0x04
2390 #define QHSTA_NO_ERROR 0x00
2391 #define QHSTA_M_SEL_TIMEOUT 0x11
2392 #define QHSTA_M_DATA_OVER_RUN 0x12
2393 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2394 #define QHSTA_M_QUEUE_ABORTED 0x15
2395 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
2396 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
2397 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
2398 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
2399 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
2400 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
2401 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
2402 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
2403 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
2404 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
2405 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
2406 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
2407 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
2408 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
2409 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
2410 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
2411 #define QHSTA_M_WTM_TIMEOUT 0x41
2412 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
2413 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
2414 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
2415 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
2416 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
2417 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
2420 * DvcGetPhyAddr() flag arguments
2422 #define ADV_IS_SCSIQ_FLAG 0x01 /* 'addr' is ASC_SCSI_REQ_Q pointer */
2423 #define ADV_ASCGETSGLIST_VADDR 0x02 /* 'addr' is AscGetSGList() virtual addr */
2424 #define ADV_IS_SENSE_FLAG 0x04 /* 'addr' is sense virtual pointer */
2425 #define ADV_IS_DATA_FLAG 0x08 /* 'addr' is data virtual pointer */
2426 #define ADV_IS_SGLIST_FLAG 0x10 /* 'addr' is sglist virtual pointer */
2427 #define ADV_IS_CARRIER_FLAG 0x20 /* 'addr' is ADV_CARR_T pointer */
2429 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
2430 #define ADV_8BALIGN(addr) (((ulong) (addr) + 0x7) & ~0x7)
2431 #define ADV_16BALIGN(addr) (((ulong) (addr) + 0xF) & ~0xF)
2432 #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
2435 * Total contiguous memory needed for driver SG blocks.
2437 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2438 * number of scatter-gather elements the driver supports in a
2442 #define ADV_SG_LIST_MAX_BYTE_SIZE \
2443 (sizeof(ADV_SG_BLOCK) * \
2444 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2447 * --- Driver Constants and Macros
2450 /* Reference Scsi_Host hostdata */
2451 #define ASC_BOARDP(host) ((asc_board_t *) &((host)->hostdata))
2453 /* asc_board_t flags */
2454 #define ASC_HOST_IN_RESET 0x01
2455 #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
2456 #define ASC_SELECT_QUEUE_DEPTHS 0x08
2458 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
2459 #define ASC_WIDE_BOARD(boardp) ((boardp)->flags & ASC_IS_WIDE_BOARD)
2461 #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
2463 #define ASC_INFO_SIZE 128 /* advansys_info() line size */
2465 #ifdef CONFIG_PROC_FS
2466 /* /proc/scsi/advansys/[0...] related definitions */
2467 #define ASC_PRTBUF_SIZE 2048
2468 #define ASC_PRTLINE_SIZE 160
2470 #define ASC_PRT_NEXT() \
2474 if (leftlen == 0) { \
2479 #endif /* CONFIG_PROC_FS */
2481 /* Asc Library return codes */
2484 #define ASC_NOERROR 1
2486 #define ASC_ERROR (-1)
2488 /* struct scsi_cmnd function return codes */
2489 #define STATUS_BYTE(byte) (byte)
2490 #define MSG_BYTE(byte) ((byte) << 8)
2491 #define HOST_BYTE(byte) ((byte) << 16)
2492 #define DRIVER_BYTE(byte) ((byte) << 24)
2494 #ifndef ADVANSYS_STATS
2495 #define ASC_STATS(shost, counter)
2496 #define ASC_STATS_ADD(shost, counter, count)
2497 #else /* ADVANSYS_STATS */
2498 #define ASC_STATS(shost, counter) \
2499 (ASC_BOARDP(shost)->asc_stats.counter++)
2501 #define ASC_STATS_ADD(shost, counter, count) \
2502 (ASC_BOARDP(shost)->asc_stats.counter += (count))
2503 #endif /* ADVANSYS_STATS */
2505 #define ASC_CEILING(val, unit) (((val) + ((unit) - 1))/(unit))
2507 /* If the result wraps when calculating tenths, return 0. */
2508 #define ASC_TENTHS(num, den) \
2509 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2510 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2513 * Display a message to the console.
2515 #define ASC_PRINT(s) \
2517 printk("advansys: "); \
2521 #define ASC_PRINT1(s, a1) \
2523 printk("advansys: "); \
2524 printk((s), (a1)); \
2527 #define ASC_PRINT2(s, a1, a2) \
2529 printk("advansys: "); \
2530 printk((s), (a1), (a2)); \
2533 #define ASC_PRINT3(s, a1, a2, a3) \
2535 printk("advansys: "); \
2536 printk((s), (a1), (a2), (a3)); \
2539 #define ASC_PRINT4(s, a1, a2, a3, a4) \
2541 printk("advansys: "); \
2542 printk((s), (a1), (a2), (a3), (a4)); \
2545 #ifndef ADVANSYS_DEBUG
2547 #define ASC_DBG(lvl, s)
2548 #define ASC_DBG1(lvl, s, a1)
2549 #define ASC_DBG2(lvl, s, a1, a2)
2550 #define ASC_DBG3(lvl, s, a1, a2, a3)
2551 #define ASC_DBG4(lvl, s, a1, a2, a3, a4)
2552 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
2553 #define ASC_DBG_PRT_SCSI_CMND(lvl, s)
2554 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2555 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2556 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2557 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2558 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
2559 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
2560 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
2561 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2563 #else /* ADVANSYS_DEBUG */
2566 * Debugging Message Levels:
2568 * 1: High-Level Tracing
2569 * 2-N: Verbose Tracing
2572 #define ASC_DBG(lvl, s) \
2574 if (asc_dbglvl >= (lvl)) { \
2579 #define ASC_DBG1(lvl, s, a1) \
2581 if (asc_dbglvl >= (lvl)) { \
2582 printk((s), (a1)); \
2586 #define ASC_DBG2(lvl, s, a1, a2) \
2588 if (asc_dbglvl >= (lvl)) { \
2589 printk((s), (a1), (a2)); \
2593 #define ASC_DBG3(lvl, s, a1, a2, a3) \
2595 if (asc_dbglvl >= (lvl)) { \
2596 printk((s), (a1), (a2), (a3)); \
2600 #define ASC_DBG4(lvl, s, a1, a2, a3, a4) \
2602 if (asc_dbglvl >= (lvl)) { \
2603 printk((s), (a1), (a2), (a3), (a4)); \
2607 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2609 if (asc_dbglvl >= (lvl)) { \
2610 asc_prt_scsi_host(s); \
2614 #define ASC_DBG_PRT_SCSI_CMND(lvl, s) \
2616 if (asc_dbglvl >= (lvl)) { \
2617 asc_prt_scsi_cmnd(s); \
2621 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2623 if (asc_dbglvl >= (lvl)) { \
2624 asc_prt_asc_scsi_q(scsiqp); \
2628 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2630 if (asc_dbglvl >= (lvl)) { \
2631 asc_prt_asc_qdone_info(qdone); \
2635 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2637 if (asc_dbglvl >= (lvl)) { \
2638 asc_prt_adv_scsi_req_q(scsiqp); \
2642 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2644 if (asc_dbglvl >= (lvl)) { \
2645 asc_prt_hex((name), (start), (length)); \
2649 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2650 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2652 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2653 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2655 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2656 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2657 #endif /* ADVANSYS_DEBUG */
2659 #ifdef ADVANSYS_STATS
2661 /* Per board statistics structure */
2663 /* Driver Entrypoint Statistics */
2664 ADV_DCNT queuecommand; /* # calls to advansys_queuecommand() */
2665 ADV_DCNT reset; /* # calls to advansys_eh_bus_reset() */
2666 ADV_DCNT biosparam; /* # calls to advansys_biosparam() */
2667 ADV_DCNT interrupt; /* # advansys_interrupt() calls */
2668 ADV_DCNT callback; /* # calls to asc/adv_isr_callback() */
2669 ADV_DCNT done; /* # calls to request's scsi_done function */
2670 ADV_DCNT build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
2671 ADV_DCNT adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
2672 ADV_DCNT adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
2673 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2674 ADV_DCNT exe_noerror; /* # ASC_NOERROR returns. */
2675 ADV_DCNT exe_busy; /* # ASC_BUSY returns. */
2676 ADV_DCNT exe_error; /* # ASC_ERROR returns. */
2677 ADV_DCNT exe_unknown; /* # unknown returns. */
2678 /* Data Transfer Statistics */
2679 ADV_DCNT cont_cnt; /* # non-scatter-gather I/O requests received */
2680 ADV_DCNT cont_xfer; /* # contiguous transfer 512-bytes */
2681 ADV_DCNT sg_cnt; /* # scatter-gather I/O requests received */
2682 ADV_DCNT sg_elem; /* # scatter-gather elements */
2683 ADV_DCNT sg_xfer; /* # scatter-gather transfer 512-bytes */
2685 #endif /* ADVANSYS_STATS */
2688 * Adv Library Request Structures
2690 * The following two structures are used to process Wide Board requests.
2692 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
2693 * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the
2694 * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the
2695 * Mid-Level SCSI request structure.
2697 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
2698 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
2699 * up to 255 scatter-gather elements may be used per request or
2702 * Both structures must be 32 byte aligned.
2704 typedef struct adv_sgblk {
2705 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
2706 uchar align[32]; /* Sgblock structure padding. */
2707 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
2710 typedef struct adv_req {
2711 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
2712 uchar align[32]; /* Request structure padding. */
2713 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
2714 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
2715 struct adv_req *next_reqp; /* Next Request Structure. */
2719 * Structure allocated for each board.
2721 * This structure is allocated by scsi_host_alloc() at the end
2722 * of the 'Scsi_Host' structure starting at the 'hostdata'
2723 * field. It is guaranteed to be allocated from DMA-able memory.
2725 typedef struct asc_board {
2727 int id; /* Board Id */
2728 uint flags; /* Board flags */
2730 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
2731 ADV_DVC_VAR adv_dvc_var; /* Wide board */
2734 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
2735 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
2737 ushort asc_n_io_port; /* Number I/O ports. */
2738 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
2739 struct scsi_device *device[ADV_MAX_TID + 1]; /* Mid-Level Scsi Device */
2740 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2741 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
2742 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2744 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
2745 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
2746 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
2747 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
2749 ulong last_reset; /* Saved last reset time */
2750 spinlock_t lock; /* Board spinlock */
2751 /* /proc/scsi/advansys/[0...] */
2752 char *prtbuf; /* /proc print buffer */
2753 #ifdef ADVANSYS_STATS
2754 struct asc_stats asc_stats; /* Board statistics */
2755 #endif /* ADVANSYS_STATS */
2757 * The following fields are used only for Narrow Boards.
2759 uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */
2761 * The following fields are used only for Wide Boards.
2763 void __iomem *ioremap_addr; /* I/O Memory remap address. */
2764 ushort ioport; /* I/O Port address. */
2765 ADV_CARR_T *carrp; /* ADV_CARR_T memory block. */
2766 adv_req_t *orig_reqp; /* adv_req_t memory block. */
2767 adv_req_t *adv_reqp; /* Request structures. */
2768 adv_sgblk_t *adv_sgblkp; /* Scatter-gather structures. */
2769 ushort bios_signature; /* BIOS Signature. */
2770 ushort bios_version; /* BIOS Version. */
2771 ushort bios_codeseg; /* BIOS Code Segment. */
2772 ushort bios_codelen; /* BIOS Code Segment Length. */
2775 #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2776 dvc_var.adv_dvc_var)
2777 #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2779 /* Number of boards detected in system. */
2780 static int asc_board_count;
2782 /* Overrun buffer used by all narrow boards. */
2783 static uchar overrun_buf[ASC_OVERRUN_BSIZE] = { 0 };
2786 * Global structures required to issue a command.
2788 static ASC_SCSI_Q asc_scsi_q = { {0} };
2789 static ASC_SG_HEAD asc_sg_head = { 0 };
2791 #ifdef ADVANSYS_DEBUG
2792 static int asc_dbglvl = 3;
2793 #endif /* ADVANSYS_DEBUG */
2796 * --- Driver Function Prototypes
2799 static int advansys_slave_configure(struct scsi_device *);
2800 static int asc_execute_scsi_cmnd(struct scsi_cmnd *);
2801 static int asc_build_req(asc_board_t *, struct scsi_cmnd *);
2802 static int adv_build_req(asc_board_t *, struct scsi_cmnd *, ADV_SCSI_REQ_Q **);
2803 static int adv_get_sglist(asc_board_t *, adv_req_t *, struct scsi_cmnd *, int);
2804 #ifdef CONFIG_PROC_FS
2805 static int asc_proc_copy(off_t, off_t, char *, int, char *, int);
2806 static int asc_prt_board_devices(struct Scsi_Host *, char *, int);
2807 static int asc_prt_adv_bios(struct Scsi_Host *, char *, int);
2808 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp);
2809 static int asc_prt_asc_board_eeprom(struct Scsi_Host *, char *, int);
2810 static int asc_prt_adv_board_eeprom(struct Scsi_Host *, char *, int);
2811 static int asc_prt_driver_conf(struct Scsi_Host *, char *, int);
2812 static int asc_prt_asc_board_info(struct Scsi_Host *, char *, int);
2813 static int asc_prt_adv_board_info(struct Scsi_Host *, char *, int);
2814 static int asc_prt_line(char *, int, char *fmt, ...);
2815 #endif /* CONFIG_PROC_FS */
2817 /* Statistics function prototypes. */
2818 #ifdef ADVANSYS_STATS
2819 #ifdef CONFIG_PROC_FS
2820 static int asc_prt_board_stats(struct Scsi_Host *, char *, int);
2821 #endif /* CONFIG_PROC_FS */
2822 #endif /* ADVANSYS_STATS */
2824 /* Debug function prototypes. */
2825 #ifdef ADVANSYS_DEBUG
2826 static void asc_prt_scsi_host(struct Scsi_Host *);
2827 static void asc_prt_scsi_cmnd(struct scsi_cmnd *);
2828 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *);
2829 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *);
2830 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *);
2831 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *);
2832 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *);
2833 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *);
2834 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *);
2835 static void asc_prt_adv_sgblock(int, ADV_SG_BLOCK *);
2836 static void asc_prt_hex(char *f, uchar *, int);
2837 #endif /* ADVANSYS_DEBUG */
2839 #ifdef CONFIG_PROC_FS
2841 * advansys_proc_info() - /proc/scsi/advansys/{0,1,2,3,...}
2843 * *buffer: I/O buffer
2844 * **start: if inout == FALSE pointer into buffer where user read should start
2845 * offset: current offset into a /proc/scsi/advansys/[0...] file
2846 * length: length of buffer
2847 * hostno: Scsi_Host host_no
2848 * inout: TRUE - user is writing; FALSE - user is reading
2850 * Return the number of bytes read from or written to a
2851 * /proc/scsi/advansys/[0...] file.
2853 * Note: This function uses the per board buffer 'prtbuf' which is
2854 * allocated when the board is initialized in advansys_detect(). The
2855 * buffer is ASC_PRTBUF_SIZE bytes. The function asc_proc_copy() is
2856 * used to write to the buffer. The way asc_proc_copy() is written
2857 * if 'prtbuf' is too small it will not be overwritten. Instead the
2858 * user just won't get all the available statistics.
2861 advansys_proc_info(struct Scsi_Host *shost, char *buffer, char **start,
2862 off_t offset, int length, int inout)
2864 asc_board_t *boardp;
2873 ASC_DBG(1, "advansys_proc_info: begin\n");
2876 * User write not supported.
2878 if (inout == TRUE) {
2883 * User read of /proc/scsi/advansys/[0...] file.
2886 boardp = ASC_BOARDP(shost);
2888 /* Copy read data starting at the beginning of the buffer. */
2896 * Get board configuration information.
2898 * advansys_info() returns the board string from its own static buffer.
2900 cp = (char *)advansys_info(shost);
2903 /* Copy board information. */
2904 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
2908 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
2915 * Display Wide Board BIOS Information.
2917 if (ASC_WIDE_BOARD(boardp)) {
2918 cp = boardp->prtbuf;
2919 cplen = asc_prt_adv_bios(shost, cp, ASC_PRTBUF_SIZE);
2920 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
2921 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp,
2926 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
2934 * Display driver information for each device attached to the board.
2936 cp = boardp->prtbuf;
2937 cplen = asc_prt_board_devices(shost, cp, ASC_PRTBUF_SIZE);
2938 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
2939 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
2943 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
2950 * Display EEPROM configuration for the board.
2952 cp = boardp->prtbuf;
2953 if (ASC_NARROW_BOARD(boardp)) {
2954 cplen = asc_prt_asc_board_eeprom(shost, cp, ASC_PRTBUF_SIZE);
2956 cplen = asc_prt_adv_board_eeprom(shost, cp, ASC_PRTBUF_SIZE);
2958 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
2959 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
2963 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
2970 * Display driver configuration and information for the board.
2972 cp = boardp->prtbuf;
2973 cplen = asc_prt_driver_conf(shost, cp, ASC_PRTBUF_SIZE);
2974 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
2975 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
2979 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
2985 #ifdef ADVANSYS_STATS
2987 * Display driver statistics for the board.
2989 cp = boardp->prtbuf;
2990 cplen = asc_prt_board_stats(shost, cp, ASC_PRTBUF_SIZE);
2991 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
2992 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
2996 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
3001 #endif /* ADVANSYS_STATS */
3004 * Display Asc Library dynamic configuration information
3007 cp = boardp->prtbuf;
3008 if (ASC_NARROW_BOARD(boardp)) {
3009 cplen = asc_prt_asc_board_info(shost, cp, ASC_PRTBUF_SIZE);
3011 cplen = asc_prt_adv_board_info(shost, cp, ASC_PRTBUF_SIZE);
3013 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
3014 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
3018 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
3024 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
3028 #endif /* CONFIG_PROC_FS */
3033 * Return suitable for printing on the console with the argument
3034 * adapter's configuration information.
3036 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
3037 * otherwise the static 'info' array will be overrun.
3039 static const char *advansys_info(struct Scsi_Host *shost)
3041 static char info[ASC_INFO_SIZE];
3042 asc_board_t *boardp;
3043 ASC_DVC_VAR *asc_dvc_varp;
3044 ADV_DVC_VAR *adv_dvc_varp;
3046 char *widename = NULL;
3048 boardp = ASC_BOARDP(shost);
3049 if (ASC_NARROW_BOARD(boardp)) {
3050 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
3051 ASC_DBG(1, "advansys_info: begin\n");
3052 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
3053 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
3055 busname = "ISA PnP";
3060 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
3061 ASC_VERSION, busname,
3062 (ulong)shost->io_port,
3063 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
3064 shost->irq, shost->dma_channel);
3066 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
3068 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
3070 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
3071 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
3072 == ASC_IS_PCI_ULTRA) {
3073 busname = "PCI Ultra";
3079 ASC_PRINT2("advansys_info: board %d: unknown "
3080 "bus type %d\n", boardp->id,
3081 asc_dvc_varp->bus_type);
3084 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
3085 ASC_VERSION, busname, (ulong)shost->io_port,
3086 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
3091 * Wide Adapter Information
3093 * Memory-mapped I/O is used instead of I/O space to access
3094 * the adapter, but display the I/O Port range. The Memory
3095 * I/O address is displayed through the driver /proc file.
3097 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3098 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3099 widename = "Ultra-Wide";
3100 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3101 widename = "Ultra2-Wide";
3103 widename = "Ultra3-Wide";
3106 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
3107 ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
3108 (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, shost->irq);
3110 BUG_ON(strlen(info) >= ASC_INFO_SIZE);
3111 ASC_DBG(1, "advansys_info: end\n");
3115 static void asc_scsi_done(struct scsi_cmnd *scp)
3117 struct asc_board *boardp = ASC_BOARDP(scp->device->host);
3120 dma_unmap_sg(boardp->dev,
3121 (struct scatterlist *)scp->request_buffer,
3122 scp->use_sg, scp->sc_data_direction);
3123 else if (scp->request_bufflen)
3124 dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
3125 scp->request_bufflen, scp->sc_data_direction);
3127 ASC_STATS(scp->device->host, done);
3129 scp->scsi_done(scp);
3133 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
3135 * This function always returns 0. Command return status is saved
3136 * in the 'scp' result field.
3139 advansys_queuecommand(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
3141 struct Scsi_Host *shost = scp->device->host;
3142 asc_board_t *boardp = ASC_BOARDP(shost);
3143 unsigned long flags;
3144 int asc_res, result = 0;
3146 ASC_STATS(shost, queuecommand);
3147 scp->scsi_done = done;
3150 * host_lock taken by mid-level prior to call, but need
3151 * to protect against own ISR
3153 spin_lock_irqsave(&boardp->lock, flags);
3154 asc_res = asc_execute_scsi_cmnd(scp);
3155 spin_unlock_irqrestore(&boardp->lock, flags);
3161 result = SCSI_MLQUEUE_HOST_BUSY;
3175 * Reset the bus associated with the command 'scp'.
3177 * This function runs its own thread. Interrupts must be blocked but
3178 * sleeping is allowed and no locking other than for host structures is
3179 * required. Returns SUCCESS or FAILED.
3181 static int advansys_reset(struct scsi_cmnd *scp)
3183 struct Scsi_Host *shost;
3184 asc_board_t *boardp;
3185 ASC_DVC_VAR *asc_dvc_varp;
3186 ADV_DVC_VAR *adv_dvc_varp;
3191 ASC_DBG1(1, "advansys_reset: 0x%lx\n", (ulong)scp);
3193 #ifdef ADVANSYS_STATS
3194 if (scp->device->host != NULL) {
3195 ASC_STATS(scp->device->host, reset);
3197 #endif /* ADVANSYS_STATS */
3199 if ((shost = scp->device->host) == NULL) {
3200 scp->result = HOST_BYTE(DID_ERROR);
3204 boardp = ASC_BOARDP(shost);
3206 ASC_PRINT1("advansys_reset: board %d: SCSI bus reset started...\n",
3209 * Check for re-entrancy.
3211 spin_lock_irqsave(&boardp->lock, flags);
3212 if (boardp->flags & ASC_HOST_IN_RESET) {
3213 spin_unlock_irqrestore(&boardp->lock, flags);
3216 boardp->flags |= ASC_HOST_IN_RESET;
3217 spin_unlock_irqrestore(&boardp->lock, flags);
3219 if (ASC_NARROW_BOARD(boardp)) {
3223 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
3226 * Reset the chip and SCSI bus.
3228 ASC_DBG(1, "advansys_reset: before AscInitAsc1000Driver()\n");
3229 status = AscInitAsc1000Driver(asc_dvc_varp);
3231 /* Refer to ASC_IERR_* defintions for meaning of 'err_code'. */
3232 if (asc_dvc_varp->err_code) {
3233 ASC_PRINT2("advansys_reset: board %d: SCSI bus reset "
3234 "error: 0x%x\n", boardp->id,
3235 asc_dvc_varp->err_code);
3237 } else if (status) {
3238 ASC_PRINT2("advansys_reset: board %d: SCSI bus reset "
3239 "warning: 0x%x\n", boardp->id, status);
3241 ASC_PRINT1("advansys_reset: board %d: SCSI bus reset "
3242 "successful.\n", boardp->id);
3245 ASC_DBG(1, "advansys_reset: after AscInitAsc1000Driver()\n");
3246 spin_lock_irqsave(&boardp->lock, flags);
3252 * If the suggest reset bus flags are set, then reset the bus.
3253 * Otherwise only reset the device.
3255 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3258 * Reset the target's SCSI bus.
3260 ASC_DBG(1, "advansys_reset: before AdvResetChipAndSB()\n");
3261 switch (AdvResetChipAndSB(adv_dvc_varp)) {
3263 ASC_PRINT1("advansys_reset: board %d: SCSI bus reset "
3264 "successful.\n", boardp->id);
3268 ASC_PRINT1("advansys_reset: board %d: SCSI bus reset "
3269 "error.\n", boardp->id);
3273 spin_lock_irqsave(&boardp->lock, flags);
3274 (void)AdvISR(adv_dvc_varp);
3276 /* Board lock is held. */
3278 /* Save the time of the most recently completed reset. */
3279 boardp->last_reset = jiffies;
3281 /* Clear reset flag. */
3282 boardp->flags &= ~ASC_HOST_IN_RESET;
3283 spin_unlock_irqrestore(&boardp->lock, flags);
3285 ASC_DBG1(1, "advansys_reset: ret %d\n", ret);
3291 * advansys_biosparam()
3293 * Translate disk drive geometry if the "BIOS greater than 1 GB"
3294 * support is enabled for a drive.
3296 * ip (information pointer) is an int array with the following definition:
3302 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
3303 sector_t capacity, int ip[])
3305 asc_board_t *boardp;
3307 ASC_DBG(1, "advansys_biosparam: begin\n");
3308 ASC_STATS(sdev->host, biosparam);
3309 boardp = ASC_BOARDP(sdev->host);
3310 if (ASC_NARROW_BOARD(boardp)) {
3311 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
3312 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
3320 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
3321 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
3329 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
3330 ASC_DBG(1, "advansys_biosparam: end\n");
3334 static struct scsi_host_template advansys_template = {
3335 .proc_name = "advansys",
3336 #ifdef CONFIG_PROC_FS
3337 .proc_info = advansys_proc_info,
3340 .info = advansys_info,
3341 .queuecommand = advansys_queuecommand,
3342 .eh_bus_reset_handler = advansys_reset,
3343 .bios_param = advansys_biosparam,
3344 .slave_configure = advansys_slave_configure,
3346 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
3347 * must be set. The flag will be cleared in advansys_board_found
3348 * for non-ISA adapters.
3350 .unchecked_isa_dma = 1,
3352 * All adapters controlled by this driver are capable of large
3353 * scatter-gather lists. According to the mid-level SCSI documentation
3354 * this obviates any performance gain provided by setting
3355 * 'use_clustering'. But empirically while CPU utilization is increased
3356 * by enabling clustering, I/O throughput increases as well.
3358 .use_clustering = ENABLE_CLUSTERING,
3362 * --- Miscellaneous Driver Functions
3366 * First-level interrupt handler.
3368 * 'dev_id' is a pointer to the interrupting adapter's asc_board_t. Because
3369 * all boards are currently checked for interrupts on each interrupt, 'dev_id'
3370 * is not referenced. 'dev_id' could be used to identify an interrupt passed
3371 * to the AdvanSys driver which is for a device sharing an interrupt with
3372 * an AdvanSys adapter.
3374 static irqreturn_t advansys_interrupt(int irq, void *dev_id)
3376 unsigned long flags;
3377 struct Scsi_Host *shost = dev_id;
3378 asc_board_t *boardp = ASC_BOARDP(shost);
3379 irqreturn_t result = IRQ_NONE;
3381 ASC_DBG1(2, "advansys_interrupt: boardp 0x%p\n", boardp);
3382 spin_lock_irqsave(&boardp->lock, flags);
3383 if (ASC_NARROW_BOARD(boardp)) {
3387 if (AscIsIntPending(shost->io_port)) {
3388 result = IRQ_HANDLED;
3389 ASC_STATS(shost, interrupt);
3390 ASC_DBG(1, "advansys_interrupt: before AscISR()\n");
3391 AscISR(&boardp->dvc_var.asc_dvc_var);
3397 ASC_DBG(1, "advansys_interrupt: before AdvISR()\n");
3398 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
3399 result = IRQ_HANDLED;
3400 ASC_STATS(shost, interrupt);
3404 spin_unlock_irqrestore(&boardp->lock, flags);
3407 * If interrupts were enabled on entry, then they
3408 * are now enabled here.
3411 ASC_DBG(1, "advansys_interrupt: end\n");
3416 advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
3418 ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
3419 ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
3421 if (sdev->lun == 0) {
3422 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
3423 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
3424 asc_dvc->init_sdtr |= tid_bit;
3426 asc_dvc->init_sdtr &= ~tid_bit;
3429 if (orig_init_sdtr != asc_dvc->init_sdtr)
3430 AscAsyncFix(asc_dvc, sdev);
3433 if (sdev->tagged_supported) {
3434 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
3435 if (sdev->lun == 0) {
3436 asc_dvc->cfg->can_tagged_qng |= tid_bit;
3437 asc_dvc->use_tagged_qng |= tid_bit;
3439 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG,
3440 asc_dvc->max_dvc_qng[sdev->id]);
3443 if (sdev->lun == 0) {
3444 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
3445 asc_dvc->use_tagged_qng &= ~tid_bit;
3447 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
3450 if ((sdev->lun == 0) &&
3451 (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
3452 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
3453 asc_dvc->cfg->disc_enable);
3454 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
3455 asc_dvc->use_tagged_qng);
3456 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
3457 asc_dvc->cfg->can_tagged_qng);
3459 asc_dvc->max_dvc_qng[sdev->id] =
3460 asc_dvc->cfg->max_tag_qng[sdev->id];
3461 AscWriteLramByte(asc_dvc->iop_base,
3462 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
3463 asc_dvc->max_dvc_qng[sdev->id]);
3470 * If the EEPROM enabled WDTR for the device and the device supports wide
3471 * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
3472 * write the new value to the microcode.
3475 advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
3477 unsigned short cfg_word;
3478 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
3479 if ((cfg_word & tidmask) != 0)
3482 cfg_word |= tidmask;
3483 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
3486 * Clear the microcode SDTR and WDTR negotiation done indicators for
3487 * the target to cause it to negotiate with the new setting set above.
3488 * WDTR when accepted causes the target to enter asynchronous mode, so
3489 * SDTR must be negotiated.
3491 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
3492 cfg_word &= ~tidmask;
3493 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
3494 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
3495 cfg_word &= ~tidmask;
3496 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
3500 * Synchronous Transfers
3502 * If the EEPROM enabled SDTR for the device and the device
3503 * supports synchronous transfers, then turn on the device's
3504 * 'sdtr_able' bit. Write the new value to the microcode.
3507 advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
3509 unsigned short cfg_word;
3510 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
3511 if ((cfg_word & tidmask) != 0)
3514 cfg_word |= tidmask;
3515 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
3518 * Clear the microcode "SDTR negotiation" done indicator for the
3519 * target to cause it to negotiate with the new setting set above.
3521 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
3522 cfg_word &= ~tidmask;
3523 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
3527 * PPR (Parallel Protocol Request) Capable
3529 * If the device supports DT mode, then it must be PPR capable.
3530 * The PPR message will be used in place of the SDTR and WDTR
3531 * messages to negotiate synchronous speed and offset, transfer
3532 * width, and protocol options.
3534 static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
3535 AdvPortAddr iop_base, unsigned short tidmask)
3537 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
3538 adv_dvc->ppr_able |= tidmask;
3539 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
3543 advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
3545 AdvPortAddr iop_base = adv_dvc->iop_base;
3546 unsigned short tidmask = 1 << sdev->id;
3548 if (sdev->lun == 0) {
3550 * Handle WDTR, SDTR, and Tag Queuing. If the feature
3551 * is enabled in the EEPROM and the device supports the
3552 * feature, then enable it in the microcode.
3555 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
3556 advansys_wide_enable_wdtr(iop_base, tidmask);
3557 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
3558 advansys_wide_enable_sdtr(iop_base, tidmask);
3559 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
3560 advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
3563 * Tag Queuing is disabled for the BIOS which runs in polled
3564 * mode and would see no benefit from Tag Queuing. Also by
3565 * disabling Tag Queuing in the BIOS devices with Tag Queuing
3566 * bugs will at least work with the BIOS.
3568 if ((adv_dvc->tagqng_able & tidmask) &&
3569 sdev->tagged_supported) {
3570 unsigned short cfg_word;
3571 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
3572 cfg_word |= tidmask;
3573 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
3575 AdvWriteByteLram(iop_base,
3576 ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
3577 adv_dvc->max_dvc_qng);
3581 if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported) {
3582 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG,
3583 adv_dvc->max_dvc_qng);
3585 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
3590 * Set the number of commands to queue per device for the
3591 * specified host adapter.
3593 static int advansys_slave_configure(struct scsi_device *sdev)
3595 asc_board_t *boardp = ASC_BOARDP(sdev->host);
3596 boardp->flags |= ASC_SELECT_QUEUE_DEPTHS;
3599 * Save a pointer to the sdev and set its initial/maximum
3600 * queue depth. Only save the pointer for a lun0 dev though.
3603 boardp->device[sdev->id] = sdev;
3605 if (ASC_NARROW_BOARD(boardp))
3606 advansys_narrow_slave_configure(sdev,
3607 &boardp->dvc_var.asc_dvc_var);
3609 advansys_wide_slave_configure(sdev,
3610 &boardp->dvc_var.adv_dvc_var);
3616 * Execute a single 'Scsi_Cmnd'.
3618 * The function 'done' is called when the request has been completed.
3622 * host - board controlling device
3623 * device - device to send command
3624 * target - target of device
3625 * lun - lun of device
3626 * cmd_len - length of SCSI CDB
3627 * cmnd - buffer for SCSI 8, 10, or 12 byte CDB
3628 * use_sg - if non-zero indicates scatter-gather request with use_sg elements
3630 * if (use_sg == 0) {
3631 * request_buffer - buffer address for request
3632 * request_bufflen - length of request buffer
3634 * request_buffer - pointer to scatterlist structure
3637 * sense_buffer - sense command buffer
3639 * result (4 bytes of an int):
3641 * 0 SCSI Status Byte Code
3642 * 1 SCSI One Byte Message Code
3644 * 3 Mid-Level Error Code
3646 * host driver fields:
3647 * SCp - Scsi_Pointer used for command processing status
3648 * scsi_done - used to save caller's done function
3649 * host_scribble - used for pointer to another struct scsi_cmnd
3651 * If this function returns ASC_NOERROR the request will be completed
3652 * from the interrupt handler.
3654 * If this function returns ASC_ERROR the host error code has been set,
3655 * and the called must call asc_scsi_done.
3657 * If ASC_BUSY is returned the request will be returned to the midlayer
3658 * and re-tried later.
3660 static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
3662 asc_board_t *boardp;
3663 ASC_DVC_VAR *asc_dvc_varp;
3664 ADV_DVC_VAR *adv_dvc_varp;
3665 ADV_SCSI_REQ_Q *adv_scsiqp;
3666 struct scsi_device *device;
3669 ASC_DBG2(1, "asc_execute_scsi_cmnd: scp 0x%lx, done 0x%lx\n",
3670 (ulong)scp, (ulong)scp->scsi_done);
3672 boardp = ASC_BOARDP(scp->device->host);
3673 device = boardp->device[scp->device->id];
3675 if (ASC_NARROW_BOARD(boardp)) {
3677 * Build and execute Narrow Board request.
3680 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
3683 * Build Asc Library request structure using the
3684 * global structures 'asc_scsi_req' and 'asc_sg_head'.
3686 * If an error is returned, then the request has been
3687 * queued on the board done queue. It will be completed
3690 * asc_build_req() can not return ASC_BUSY.
3692 if (asc_build_req(boardp, scp) == ASC_ERROR) {
3693 ASC_STATS(scp->device->host, build_error);
3697 switch (ret = AscExeScsiQueue(asc_dvc_varp, &asc_scsi_q)) {
3699 ASC_STATS(scp->device->host, exe_noerror);
3701 * Increment monotonically increasing per device
3702 * successful request counter. Wrapping doesn't matter.
3704 boardp->reqcnt[scp->device->id]++;
3705 ASC_DBG(1, "asc_execute_scsi_cmnd: AscExeScsiQueue(), "
3709 ASC_STATS(scp->device->host, exe_busy);
3712 ASC_PRINT2("asc_execute_scsi_cmnd: board %d: "
3713 "AscExeScsiQueue() ASC_ERROR, err_code 0x%x\n",
3714 boardp->id, asc_dvc_varp->err_code);
3715 ASC_STATS(scp->device->host, exe_error);
3716 scp->result = HOST_BYTE(DID_ERROR);
3719 ASC_PRINT2("asc_execute_scsi_cmnd: board %d: "
3720 "AscExeScsiQueue() unknown, err_code 0x%x\n",
3721 boardp->id, asc_dvc_varp->err_code);
3722 ASC_STATS(scp->device->host, exe_unknown);
3723 scp->result = HOST_BYTE(DID_ERROR);
3728 * Build and execute Wide Board request.
3730 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3733 * Build and get a pointer to an Adv Library request structure.
3735 * If the request is successfully built then send it below,
3736 * otherwise return with an error.
3738 switch (adv_build_req(boardp, scp, &adv_scsiqp)) {
3740 ASC_DBG(3, "asc_execute_scsi_cmnd: adv_build_req "
3744 ASC_DBG(1, "asc_execute_scsi_cmnd: adv_build_req "
3747 * The asc_stats fields 'adv_build_noreq' and
3748 * 'adv_build_nosg' count wide board busy conditions.
3749 * They are updated in adv_build_req and
3750 * adv_get_sglist, respectively.
3755 ASC_DBG(1, "asc_execute_scsi_cmnd: adv_build_req "
3757 ASC_STATS(scp->device->host, build_error);
3761 switch (ret = AdvExeScsiQueue(adv_dvc_varp, adv_scsiqp)) {
3763 ASC_STATS(scp->device->host, exe_noerror);
3765 * Increment monotonically increasing per device
3766 * successful request counter. Wrapping doesn't matter.
3768 boardp->reqcnt[scp->device->id]++;
3769 ASC_DBG(1, "asc_execute_scsi_cmnd: AdvExeScsiQueue(), "
3773 ASC_STATS(scp->device->host, exe_busy);
3776 ASC_PRINT2("asc_execute_scsi_cmnd: board %d: "
3777 "AdvExeScsiQueue() ASC_ERROR, err_code 0x%x\n",
3778 boardp->id, adv_dvc_varp->err_code);
3779 ASC_STATS(scp->device->host, exe_error);
3780 scp->result = HOST_BYTE(DID_ERROR);
3783 ASC_PRINT2("asc_execute_scsi_cmnd: board %d: "
3784 "AdvExeScsiQueue() unknown, err_code 0x%x\n",
3785 boardp->id, adv_dvc_varp->err_code);
3786 ASC_STATS(scp->device->host, exe_unknown);
3787 scp->result = HOST_BYTE(DID_ERROR);
3792 ASC_DBG(1, "asc_execute_scsi_cmnd: end\n");
3797 * Build a request structure for the Asc Library (Narrow Board).
3799 * The global structures 'asc_scsi_q' and 'asc_sg_head' are
3800 * used to build the request.
3802 * If an error occurs, then return ASC_ERROR.
3804 static int asc_build_req(asc_board_t *boardp, struct scsi_cmnd *scp)
3807 * Mutually exclusive access is required to 'asc_scsi_q' and
3808 * 'asc_sg_head' until after the request is started.
3810 memset(&asc_scsi_q, 0, sizeof(ASC_SCSI_Q));
3813 * Point the ASC_SCSI_Q to the 'struct scsi_cmnd'.
3815 asc_scsi_q.q2.srb_ptr = ASC_VADDR_TO_U32(scp);
3818 * Build the ASC_SCSI_Q request.
3820 asc_scsi_q.cdbptr = &scp->cmnd[0];
3821 asc_scsi_q.q2.cdb_len = scp->cmd_len;
3822 asc_scsi_q.q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
3823 asc_scsi_q.q1.target_lun = scp->device->lun;
3824 asc_scsi_q.q2.target_ix =
3825 ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
3826 asc_scsi_q.q1.sense_addr =
3827 cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
3828 asc_scsi_q.q1.sense_len = sizeof(scp->sense_buffer);
3831 * If there are any outstanding requests for the current target,
3832 * then every 255th request send an ORDERED request. This heuristic
3833 * tries to retain the benefit of request sorting while preventing
3834 * request starvation. 255 is the max number of tags or pending commands
3835 * a device may have outstanding.
3837 * The request count is incremented below for every successfully
3841 if ((boardp->dvc_var.asc_dvc_var.cur_dvc_qng[scp->device->id] > 0) &&
3842 (boardp->reqcnt[scp->device->id] % 255) == 0) {
3843 asc_scsi_q.q2.tag_code = MSG_ORDERED_TAG;
3845 asc_scsi_q.q2.tag_code = MSG_SIMPLE_TAG;
3849 * Build ASC_SCSI_Q for a contiguous buffer or a scatter-gather
3852 if (scp->use_sg == 0) {
3854 * CDB request of single contiguous buffer.
3856 ASC_STATS(scp->device->host, cont_cnt);
3857 scp->SCp.dma_handle = scp->request_bufflen ?
3858 dma_map_single(boardp->dev, scp->request_buffer,
3859 scp->request_bufflen,
3860 scp->sc_data_direction) : 0;
3861 asc_scsi_q.q1.data_addr = cpu_to_le32(scp->SCp.dma_handle);
3862 asc_scsi_q.q1.data_cnt = cpu_to_le32(scp->request_bufflen);
3863 ASC_STATS_ADD(scp->device->host, cont_xfer,
3864 ASC_CEILING(scp->request_bufflen, 512));
3865 asc_scsi_q.q1.sg_queue_cnt = 0;
3866 asc_scsi_q.sg_head = NULL;
3869 * CDB scatter-gather request list.
3873 struct scatterlist *slp;
3875 slp = (struct scatterlist *)scp->request_buffer;
3876 use_sg = dma_map_sg(boardp->dev, slp, scp->use_sg,
3877 scp->sc_data_direction);
3879 if (use_sg > scp->device->host->sg_tablesize) {
3880 ASC_PRINT3("asc_build_req: board %d: use_sg %d > "
3881 "sg_tablesize %d\n", boardp->id, use_sg,
3882 scp->device->host->sg_tablesize);
3883 dma_unmap_sg(boardp->dev, slp, scp->use_sg,
3884 scp->sc_data_direction);
3885 scp->result = HOST_BYTE(DID_ERROR);
3889 ASC_STATS(scp->device->host, sg_cnt);
3892 * Use global ASC_SG_HEAD structure and set the ASC_SCSI_Q
3893 * structure to point to it.
3895 memset(&asc_sg_head, 0, sizeof(ASC_SG_HEAD));
3897 asc_scsi_q.q1.cntl |= QC_SG_HEAD;
3898 asc_scsi_q.sg_head = &asc_sg_head;
3899 asc_scsi_q.q1.data_cnt = 0;
3900 asc_scsi_q.q1.data_addr = 0;
3901 /* This is a byte value, otherwise it would need to be swapped. */
3902 asc_sg_head.entry_cnt = asc_scsi_q.q1.sg_queue_cnt = use_sg;
3903 ASC_STATS_ADD(scp->device->host, sg_elem,
3904 asc_sg_head.entry_cnt);
3907 * Convert scatter-gather list into ASC_SG_HEAD list.
3909 for (sgcnt = 0; sgcnt < use_sg; sgcnt++, slp++) {
3910 asc_sg_head.sg_list[sgcnt].addr =
3911 cpu_to_le32(sg_dma_address(slp));
3912 asc_sg_head.sg_list[sgcnt].bytes =
3913 cpu_to_le32(sg_dma_len(slp));
3914 ASC_STATS_ADD(scp->device->host, sg_xfer,
3915 ASC_CEILING(sg_dma_len(slp), 512));
3919 ASC_DBG_PRT_ASC_SCSI_Q(2, &asc_scsi_q);
3920 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
3926 * Build a request structure for the Adv Library (Wide Board).
3928 * If an adv_req_t can not be allocated to issue the request,
3929 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
3931 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
3932 * microcode for DMA addresses or math operations are byte swapped
3933 * to little-endian order.
3936 adv_build_req(asc_board_t *boardp, struct scsi_cmnd *scp,
3937 ADV_SCSI_REQ_Q **adv_scsiqpp)
3940 ADV_SCSI_REQ_Q *scsiqp;
3945 * Allocate an adv_req_t structure from the board to execute
3948 if (boardp->adv_reqp == NULL) {
3949 ASC_DBG(1, "adv_build_req: no free adv_req_t\n");
3950 ASC_STATS(scp->device->host, adv_build_noreq);
3953 reqp = boardp->adv_reqp;
3954 boardp->adv_reqp = reqp->next_reqp;
3955 reqp->next_reqp = NULL;
3959 * Get 32-byte aligned ADV_SCSI_REQ_Q and ADV_SG_BLOCK pointers.
3961 scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
3964 * Initialize the structure.
3966 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
3969 * Set the ADV_SCSI_REQ_Q 'srb_ptr' to point to the adv_req_t structure.
3971 scsiqp->srb_ptr = ASC_VADDR_TO_U32(reqp);
3974 * Set the adv_req_t 'cmndp' to point to the struct scsi_cmnd structure.
3979 * Build the ADV_SCSI_REQ_Q request.
3982 /* Set CDB length and copy it to the request structure. */
3983 scsiqp->cdb_len = scp->cmd_len;
3984 /* Copy first 12 CDB bytes to cdb[]. */
3985 for (i = 0; i < scp->cmd_len && i < 12; i++) {
3986 scsiqp->cdb[i] = scp->cmnd[i];
3988 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
3989 for (; i < scp->cmd_len; i++) {
3990 scsiqp->cdb16[i - 12] = scp->cmnd[i];
3993 scsiqp->target_id = scp->device->id;
3994 scsiqp->target_lun = scp->device->lun;
3996 scsiqp->sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
3997 scsiqp->sense_len = sizeof(scp->sense_buffer);
4000 * Build ADV_SCSI_REQ_Q for a contiguous buffer or a scatter-gather
4004 scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
4005 scsiqp->vdata_addr = scp->request_buffer;
4006 scsiqp->data_addr = cpu_to_le32(virt_to_bus(scp->request_buffer));
4008 if (scp->use_sg == 0) {
4010 * CDB request of single contiguous buffer.
4012 reqp->sgblkp = NULL;
4013 scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
4014 if (scp->request_bufflen) {
4015 scsiqp->vdata_addr = scp->request_buffer;
4016 scp->SCp.dma_handle =
4017 dma_map_single(boardp->dev, scp->request_buffer,
4018 scp->request_bufflen,
4019 scp->sc_data_direction);
4021 scsiqp->vdata_addr = NULL;
4022 scp->SCp.dma_handle = 0;
4024 scsiqp->data_addr = cpu_to_le32(scp->SCp.dma_handle);
4025 scsiqp->sg_list_ptr = NULL;
4026 scsiqp->sg_real_addr = 0;
4027 ASC_STATS(scp->device->host, cont_cnt);
4028 ASC_STATS_ADD(scp->device->host, cont_xfer,
4029 ASC_CEILING(scp->request_bufflen, 512));
4032 * CDB scatter-gather request list.
4034 struct scatterlist *slp;
4037 slp = (struct scatterlist *)scp->request_buffer;
4038 use_sg = dma_map_sg(boardp->dev, slp, scp->use_sg,
4039 scp->sc_data_direction);
4041 if (use_sg > ADV_MAX_SG_LIST) {
4042 ASC_PRINT3("adv_build_req: board %d: use_sg %d > "
4043 "ADV_MAX_SG_LIST %d\n", boardp->id, use_sg,
4044 scp->device->host->sg_tablesize);
4045 dma_unmap_sg(boardp->dev, slp, scp->use_sg,
4046 scp->sc_data_direction);
4047 scp->result = HOST_BYTE(DID_ERROR);
4050 * Free the 'adv_req_t' structure by adding it back
4051 * to the board free list.
4053 reqp->next_reqp = boardp->adv_reqp;
4054 boardp->adv_reqp = reqp;
4059 ret = adv_get_sglist(boardp, reqp, scp, use_sg);
4060 if (ret != ADV_SUCCESS) {
4062 * Free the adv_req_t structure by adding it back to
4063 * the board free list.
4065 reqp->next_reqp = boardp->adv_reqp;
4066 boardp->adv_reqp = reqp;
4071 ASC_STATS(scp->device->host, sg_cnt);
4072 ASC_STATS_ADD(scp->device->host, sg_elem, use_sg);
4075 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
4076 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
4078 *adv_scsiqpp = scsiqp;
4084 * Build scatter-gather list for Adv Library (Wide Board).
4086 * Additional ADV_SG_BLOCK structures will need to be allocated
4087 * if the total number of scatter-gather elements exceeds
4088 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
4089 * assumed to be physically contiguous.
4092 * ADV_SUCCESS(1) - SG List successfully created
4093 * ADV_ERROR(-1) - SG List creation failed
4096 adv_get_sglist(asc_board_t *boardp, adv_req_t *reqp, struct scsi_cmnd *scp,
4099 adv_sgblk_t *sgblkp;
4100 ADV_SCSI_REQ_Q *scsiqp;
4101 struct scatterlist *slp;
4103 ADV_SG_BLOCK *sg_block, *prev_sg_block;
4104 ADV_PADDR sg_block_paddr;
4107 scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
4108 slp = (struct scatterlist *)scp->request_buffer;
4109 sg_elem_cnt = use_sg;
4110 prev_sg_block = NULL;
4111 reqp->sgblkp = NULL;
4115 * Allocate a 'adv_sgblk_t' structure from the board free
4116 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
4117 * (15) scatter-gather elements.
4119 if ((sgblkp = boardp->adv_sgblkp) == NULL) {
4120 ASC_DBG(1, "adv_get_sglist: no free adv_sgblk_t\n");
4121 ASC_STATS(scp->device->host, adv_build_nosg);
4124 * Allocation failed. Free 'adv_sgblk_t' structures already
4125 * allocated for the request.
4127 while ((sgblkp = reqp->sgblkp) != NULL) {
4128 /* Remove 'sgblkp' from the request list. */
4129 reqp->sgblkp = sgblkp->next_sgblkp;
4131 /* Add 'sgblkp' to the board free list. */
4132 sgblkp->next_sgblkp = boardp->adv_sgblkp;
4133 boardp->adv_sgblkp = sgblkp;
4137 /* Complete 'adv_sgblk_t' board allocation. */
4138 boardp->adv_sgblkp = sgblkp->next_sgblkp;
4139 sgblkp->next_sgblkp = NULL;
4142 * Get 8 byte aligned virtual and physical addresses for
4143 * the allocated ADV_SG_BLOCK structure.
4146 (ADV_SG_BLOCK *)ADV_8BALIGN(&sgblkp->sg_block);
4147 sg_block_paddr = virt_to_bus(sg_block);
4150 * Check if this is the first 'adv_sgblk_t' for the request.
4152 if (reqp->sgblkp == NULL) {
4153 /* Request's first scatter-gather block. */
4154 reqp->sgblkp = sgblkp;
4157 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
4160 scsiqp->sg_list_ptr = sg_block;
4161 scsiqp->sg_real_addr =
4162 cpu_to_le32(sg_block_paddr);
4164 /* Request's second or later scatter-gather block. */
4165 sgblkp->next_sgblkp = reqp->sgblkp;
4166 reqp->sgblkp = sgblkp;
4169 * Point the previous ADV_SG_BLOCK structure to
4170 * the newly allocated ADV_SG_BLOCK structure.
4172 prev_sg_block->sg_ptr =
4173 cpu_to_le32(sg_block_paddr);
4177 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
4178 sg_block->sg_list[i].sg_addr =
4179 cpu_to_le32(sg_dma_address(slp));
4180 sg_block->sg_list[i].sg_count =
4181 cpu_to_le32(sg_dma_len(slp));
4182 ASC_STATS_ADD(scp->device->host, sg_xfer,
4183 ASC_CEILING(sg_dma_len(slp), 512));
4185 if (--sg_elem_cnt == 0) { /* Last ADV_SG_BLOCK and scatter-gather entry. */
4186 sg_block->sg_cnt = i + 1;
4187 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
4192 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
4193 prev_sg_block = sg_block;
4200 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
4202 * Interrupt callback function for the Narrow SCSI Asc Library.
4204 static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
4206 asc_board_t *boardp;
4207 struct scsi_cmnd *scp;
4208 struct Scsi_Host *shost;
4210 ASC_DBG2(1, "asc_isr_callback: asc_dvc_varp 0x%lx, qdonep 0x%lx\n",
4211 (ulong)asc_dvc_varp, (ulong)qdonep);
4212 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
4215 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
4216 * command that has been completed.
4218 scp = (struct scsi_cmnd *)ASC_U32_TO_VADDR(qdonep->d2.srb_ptr);
4219 ASC_DBG1(1, "asc_isr_callback: scp 0x%lx\n", (ulong)scp);
4222 ASC_PRINT("asc_isr_callback: scp is NULL\n");
4225 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
4227 shost = scp->device->host;
4228 ASC_STATS(shost, callback);
4229 ASC_DBG1(1, "asc_isr_callback: shost 0x%lx\n", (ulong)shost);
4231 boardp = ASC_BOARDP(shost);
4232 BUG_ON(asc_dvc_varp != &boardp->dvc_var.asc_dvc_var);
4235 * 'qdonep' contains the command's ending status.
4237 switch (qdonep->d3.done_stat) {
4239 ASC_DBG(2, "asc_isr_callback: QD_NO_ERROR\n");
4243 * Check for an underrun condition.
4245 * If there was no error and an underrun condition, then
4246 * return the number of underrun bytes.
4248 if (scp->request_bufflen != 0 && qdonep->remain_bytes != 0 &&
4249 qdonep->remain_bytes <= scp->request_bufflen) {
4251 "asc_isr_callback: underrun condition %u bytes\n",
4252 (unsigned)qdonep->remain_bytes);
4253 scp->resid = qdonep->remain_bytes;
4258 ASC_DBG(2, "asc_isr_callback: QD_WITH_ERROR\n");
4259 switch (qdonep->d3.host_stat) {
4260 case QHSTA_NO_ERROR:
4261 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
4263 "asc_isr_callback: SAM_STAT_CHECK_CONDITION\n");
4264 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
4265 sizeof(scp->sense_buffer));
4267 * Note: The 'status_byte()' macro used by target drivers
4268 * defined in scsi.h shifts the status byte returned by
4269 * host drivers right by 1 bit. This is why target drivers
4270 * also use right shifted status byte definitions. For
4271 * instance target drivers use CHECK_CONDITION, defined to
4272 * 0x1, instead of the SCSI defined check condition value
4273 * of 0x2. Host drivers are supposed to return the status
4274 * byte as it is defined by SCSI.
4276 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
4277 STATUS_BYTE(qdonep->d3.scsi_stat);
4279 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
4284 /* QHSTA error occurred */
4285 ASC_DBG1(1, "asc_isr_callback: host_stat 0x%x\n",
4286 qdonep->d3.host_stat);
4287 scp->result = HOST_BYTE(DID_BAD_TARGET);
4292 case QD_ABORTED_BY_HOST:
4293 ASC_DBG(1, "asc_isr_callback: QD_ABORTED_BY_HOST\n");
4295 HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
4297 STATUS_BYTE(qdonep->d3.scsi_stat);
4301 ASC_DBG1(1, "asc_isr_callback: done_stat 0x%x\n",
4302 qdonep->d3.done_stat);
4304 HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
4306 STATUS_BYTE(qdonep->d3.scsi_stat);
4311 * If the 'init_tidmask' bit isn't already set for the target and the
4312 * current request finished normally, then set the bit for the target
4313 * to indicate that a device is present.
4315 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
4316 qdonep->d3.done_stat == QD_NO_ERROR &&
4317 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
4318 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
4327 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
4329 * Callback function for the Wide SCSI Adv Library.
4331 static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
4333 asc_board_t *boardp;
4335 adv_sgblk_t *sgblkp;
4336 struct scsi_cmnd *scp;
4337 struct Scsi_Host *shost;
4340 ASC_DBG2(1, "adv_isr_callback: adv_dvc_varp 0x%lx, scsiqp 0x%lx\n",
4341 (ulong)adv_dvc_varp, (ulong)scsiqp);
4342 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
4345 * Get the adv_req_t structure for the command that has been
4346 * completed. The adv_req_t structure actually contains the
4347 * completed ADV_SCSI_REQ_Q structure.
4349 reqp = (adv_req_t *)ADV_U32_TO_VADDR(scsiqp->srb_ptr);
4350 ASC_DBG1(1, "adv_isr_callback: reqp 0x%lx\n", (ulong)reqp);
4352 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
4357 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
4358 * command that has been completed.
4360 * Note: The adv_req_t request structure and adv_sgblk_t structure,
4361 * if any, are dropped, because a board structure pointer can not be
4365 ASC_DBG1(1, "adv_isr_callback: scp 0x%lx\n", (ulong)scp);
4368 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
4371 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
4373 shost = scp->device->host;
4374 ASC_STATS(shost, callback);
4375 ASC_DBG1(1, "adv_isr_callback: shost 0x%lx\n", (ulong)shost);
4377 boardp = ASC_BOARDP(shost);
4378 BUG_ON(adv_dvc_varp != &boardp->dvc_var.adv_dvc_var);
4381 * 'done_status' contains the command's ending status.
4383 switch (scsiqp->done_status) {
4385 ASC_DBG(2, "adv_isr_callback: QD_NO_ERROR\n");
4389 * Check for an underrun condition.
4391 * If there was no error and an underrun condition, then
4392 * then return the number of underrun bytes.
4394 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
4395 if (scp->request_bufflen != 0 && resid_cnt != 0 &&
4396 resid_cnt <= scp->request_bufflen) {
4398 "adv_isr_callback: underrun condition %lu bytes\n",
4400 scp->resid = resid_cnt;
4405 ASC_DBG(2, "adv_isr_callback: QD_WITH_ERROR\n");
4406 switch (scsiqp->host_status) {
4407 case QHSTA_NO_ERROR:
4408 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
4410 "adv_isr_callback: SAM_STAT_CHECK_CONDITION\n");
4411 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
4412 sizeof(scp->sense_buffer));
4414 * Note: The 'status_byte()' macro used by target drivers
4415 * defined in scsi.h shifts the status byte returned by
4416 * host drivers right by 1 bit. This is why target drivers
4417 * also use right shifted status byte definitions. For
4418 * instance target drivers use CHECK_CONDITION, defined to
4419 * 0x1, instead of the SCSI defined check condition value
4420 * of 0x2. Host drivers are supposed to return the status
4421 * byte as it is defined by SCSI.
4423 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
4424 STATUS_BYTE(scsiqp->scsi_status);
4426 scp->result = STATUS_BYTE(scsiqp->scsi_status);
4431 /* Some other QHSTA error occurred. */
4432 ASC_DBG1(1, "adv_isr_callback: host_status 0x%x\n",
4433 scsiqp->host_status);
4434 scp->result = HOST_BYTE(DID_BAD_TARGET);
4439 case QD_ABORTED_BY_HOST:
4440 ASC_DBG(1, "adv_isr_callback: QD_ABORTED_BY_HOST\n");
4442 HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
4446 ASC_DBG1(1, "adv_isr_callback: done_status 0x%x\n",
4447 scsiqp->done_status);
4449 HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
4454 * If the 'init_tidmask' bit isn't already set for the target and the
4455 * current request finished normally, then set the bit for the target
4456 * to indicate that a device is present.
4458 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
4459 scsiqp->done_status == QD_NO_ERROR &&
4460 scsiqp->host_status == QHSTA_NO_ERROR) {
4461 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
4467 * Free all 'adv_sgblk_t' structures allocated for the request.
4469 while ((sgblkp = reqp->sgblkp) != NULL) {
4470 /* Remove 'sgblkp' from the request list. */
4471 reqp->sgblkp = sgblkp->next_sgblkp;
4473 /* Add 'sgblkp' to the board free list. */
4474 sgblkp->next_sgblkp = boardp->adv_sgblkp;
4475 boardp->adv_sgblkp = sgblkp;
4479 * Free the adv_req_t structure used with the command by adding
4480 * it back to the board free list.
4482 reqp->next_reqp = boardp->adv_reqp;
4483 boardp->adv_reqp = reqp;
4485 ASC_DBG(1, "adv_isr_callback: done\n");
4491 * adv_async_callback() - Adv Library asynchronous event callback function.
4493 static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
4496 case ADV_ASYNC_SCSI_BUS_RESET_DET:
4498 * The firmware detected a SCSI Bus reset.
4501 "adv_async_callback: ADV_ASYNC_SCSI_BUS_RESET_DET\n");
4504 case ADV_ASYNC_RDMA_FAILURE:
4506 * Handle RDMA failure by resetting the SCSI Bus and
4507 * possibly the chip if it is unresponsive. Log the error
4508 * with a unique code.
4510 ASC_DBG(0, "adv_async_callback: ADV_ASYNC_RDMA_FAILURE\n");
4511 AdvResetChipAndSB(adv_dvc_varp);
4514 case ADV_HOST_SCSI_BUS_RESET:
4516 * Host generated SCSI bus reset occurred.
4518 ASC_DBG(0, "adv_async_callback: ADV_HOST_SCSI_BUS_RESET\n");
4522 ASC_DBG1(0, "DvcAsyncCallBack: unknown code 0x%x\n", code);
4527 #ifdef CONFIG_PROC_FS
4529 * asc_prt_board_devices()
4531 * Print driver information for devices attached to the board.
4533 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
4534 * cf. asc_prt_line().
4536 * Return the number of characters copied into 'cp'. No more than
4537 * 'cplen' characters will be copied to 'cp'.
4539 static int asc_prt_board_devices(struct Scsi_Host *shost, char *cp, int cplen)
4541 asc_board_t *boardp;
4548 boardp = ASC_BOARDP(shost);
4552 len = asc_prt_line(cp, leftlen,
4553 "\nDevice Information for AdvanSys SCSI Host %d:\n",
4557 if (ASC_NARROW_BOARD(boardp)) {
4558 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
4560 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
4563 len = asc_prt_line(cp, leftlen, "Target IDs Detected:");
4565 for (i = 0; i <= ADV_MAX_TID; i++) {
4566 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) {
4567 len = asc_prt_line(cp, leftlen, " %X,", i);
4571 len = asc_prt_line(cp, leftlen, " (%X=Host Adapter)\n", chip_scsi_id);
4578 * Display Wide Board BIOS Information.
4580 static int asc_prt_adv_bios(struct Scsi_Host *shost, char *cp, int cplen)
4582 asc_board_t *boardp;
4586 ushort major, minor, letter;
4588 boardp = ASC_BOARDP(shost);
4592 len = asc_prt_line(cp, leftlen, "\nROM BIOS Version: ");
4596 * If the BIOS saved a valid signature, then fill in
4597 * the BIOS code segment base address.
4599 if (boardp->bios_signature != 0x55AA) {
4600 len = asc_prt_line(cp, leftlen, "Disabled or Pre-3.1\n");
4602 len = asc_prt_line(cp, leftlen,
4603 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n");
4605 len = asc_prt_line(cp, leftlen,
4606 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
4609 major = (boardp->bios_version >> 12) & 0xF;
4610 minor = (boardp->bios_version >> 8) & 0xF;
4611 letter = (boardp->bios_version & 0xFF);
4613 len = asc_prt_line(cp, leftlen, "%d.%d%c\n",
4615 letter >= 26 ? '?' : letter + 'A');
4619 * Current available ROM BIOS release is 3.1I for UW
4620 * and 3.2I for U2W. This code doesn't differentiate
4621 * UW and U2W boards.
4623 if (major < 3 || (major <= 3 && minor < 1) ||
4624 (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
4625 len = asc_prt_line(cp, leftlen,
4626 "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n");
4628 len = asc_prt_line(cp, leftlen,
4629 "ftp://ftp.connectcom.net/pub\n");
4638 * Add serial number to information bar if signature AAh
4639 * is found in at bit 15-9 (7 bits) of word 1.
4641 * Serial Number consists fo 12 alpha-numeric digits.
4643 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
4644 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
4645 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
4646 * 5 - Product revision (A-J) Word0: " "
4648 * Signature Word1: 15-9 (7 bits)
4649 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
4650 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
4652 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
4654 * Note 1: Only production cards will have a serial number.
4656 * Note 2: Signature is most significant 7 bits (0xFE).
4658 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
4660 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
4664 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
4668 * First word - 6 digits.
4672 /* Product type - 1st digit. */
4673 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
4674 /* Product type is P=Prototype */
4679 /* Manufacturing location - 2nd digit. */
4680 *cp++ = 'A' + ((w & 0x1C00) >> 10);
4682 /* Product ID - 3rd, 4th digits. */
4684 *cp++ = '0' + (num / 100);
4686 *cp++ = '0' + (num / 10);
4688 /* Product revision - 5th digit. */
4689 *cp++ = 'A' + (num % 10);
4699 * If bit 15 of third word is set, then the
4700 * last digit of the year is greater than 7.
4702 if (serialnum[2] & 0x8000) {
4703 *cp++ = '8' + ((w & 0x1C0) >> 6);
4705 *cp++ = '0' + ((w & 0x1C0) >> 6);
4708 /* Week of year - 7th, 8th digits. */
4710 *cp++ = '0' + num / 10;
4717 w = serialnum[2] & 0x7FFF;
4719 /* Serial number - 9th digit. */
4720 *cp++ = 'A' + (w / 1000);
4722 /* 10th, 11th, 12th digits. */
4724 *cp++ = '0' + num / 100;
4726 *cp++ = '0' + num / 10;
4730 *cp = '\0'; /* Null Terminate the string. */
4736 * asc_prt_asc_board_eeprom()
4738 * Print board EEPROM configuration.
4740 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
4741 * cf. asc_prt_line().
4743 * Return the number of characters copied into 'cp'. No more than
4744 * 'cplen' characters will be copied to 'cp'.
4746 static int asc_prt_asc_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen)
4748 asc_board_t *boardp;
4749 ASC_DVC_VAR *asc_dvc_varp;
4756 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
4757 #endif /* CONFIG_ISA */
4758 uchar serialstr[13];
4760 boardp = ASC_BOARDP(shost);
4761 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
4762 ep = &boardp->eep_config.asc_eep;
4767 len = asc_prt_line(cp, leftlen,
4768 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
4772 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
4775 asc_prt_line(cp, leftlen, " Serial Number: %s\n",
4779 if (ep->adapter_info[5] == 0xBB) {
4780 len = asc_prt_line(cp, leftlen,
4781 " Default Settings Used for EEPROM-less Adapter.\n");
4784 len = asc_prt_line(cp, leftlen,
4785 " Serial Number Signature Not Present.\n");
4790 len = asc_prt_line(cp, leftlen,
4791 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
4792 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
4796 len = asc_prt_line(cp, leftlen,
4797 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
4800 len = asc_prt_line(cp, leftlen, " Target ID: ");
4802 for (i = 0; i <= ASC_MAX_TID; i++) {
4803 len = asc_prt_line(cp, leftlen, " %d", i);
4806 len = asc_prt_line(cp, leftlen, "\n");
4809 len = asc_prt_line(cp, leftlen, " Disconnects: ");
4811 for (i = 0; i <= ASC_MAX_TID; i++) {
4812 len = asc_prt_line(cp, leftlen, " %c",
4814 disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
4818 len = asc_prt_line(cp, leftlen, "\n");
4821 len = asc_prt_line(cp, leftlen, " Command Queuing: ");
4823 for (i = 0; i <= ASC_MAX_TID; i++) {
4824 len = asc_prt_line(cp, leftlen, " %c",
4826 use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
4830 len = asc_prt_line(cp, leftlen, "\n");
4833 len = asc_prt_line(cp, leftlen, " Start Motor: ");
4835 for (i = 0; i <= ASC_MAX_TID; i++) {
4836 len = asc_prt_line(cp, leftlen, " %c",
4838 start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
4842 len = asc_prt_line(cp, leftlen, "\n");
4845 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
4847 for (i = 0; i <= ASC_MAX_TID; i++) {
4848 len = asc_prt_line(cp, leftlen, " %c",
4850 init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
4854 len = asc_prt_line(cp, leftlen, "\n");
4858 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
4859 len = asc_prt_line(cp, leftlen,
4860 " Host ISA DMA speed: %d MB/S\n",
4861 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
4864 #endif /* CONFIG_ISA */
4870 * asc_prt_adv_board_eeprom()
4872 * Print board EEPROM configuration.
4874 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
4875 * cf. asc_prt_line().
4877 * Return the number of characters copied into 'cp'. No more than
4878 * 'cplen' characters will be copied to 'cp'.
4880 static int asc_prt_adv_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen)
4882 asc_board_t *boardp;
4883 ADV_DVC_VAR *adv_dvc_varp;
4889 uchar serialstr[13];
4890 ADVEEP_3550_CONFIG *ep_3550 = NULL;
4891 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
4892 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
4895 ushort sdtr_speed = 0;
4897 boardp = ASC_BOARDP(shost);
4898 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
4899 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
4900 ep_3550 = &boardp->eep_config.adv_3550_eep;
4901 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
4902 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
4904 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
4910 len = asc_prt_line(cp, leftlen,
4911 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
4915 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
4916 wordp = &ep_3550->serial_number_word1;
4917 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
4918 wordp = &ep_38C0800->serial_number_word1;
4920 wordp = &ep_38C1600->serial_number_word1;
4923 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE) {
4925 asc_prt_line(cp, leftlen, " Serial Number: %s\n",
4929 len = asc_prt_line(cp, leftlen,
4930 " Serial Number Signature Not Present.\n");
4934 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
4935 len = asc_prt_line(cp, leftlen,
4936 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
4937 ep_3550->adapter_scsi_id,
4938 ep_3550->max_host_qng, ep_3550->max_dvc_qng);
4940 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
4941 len = asc_prt_line(cp, leftlen,
4942 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
4943 ep_38C0800->adapter_scsi_id,
4944 ep_38C0800->max_host_qng,
4945 ep_38C0800->max_dvc_qng);
4948 len = asc_prt_line(cp, leftlen,
4949 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
4950 ep_38C1600->adapter_scsi_id,
4951 ep_38C1600->max_host_qng,
4952 ep_38C1600->max_dvc_qng);
4955 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
4956 word = ep_3550->termination;
4957 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
4958 word = ep_38C0800->termination_lvd;
4960 word = ep_38C1600->termination_lvd;
4964 termstr = "Low Off/High Off";
4967 termstr = "Low Off/High On";
4970 termstr = "Low On/High On";
4974 termstr = "Automatic";
4978 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
4979 len = asc_prt_line(cp, leftlen,
4980 " termination: %u (%s), bios_ctrl: 0x%x\n",
4981 ep_3550->termination, termstr,
4982 ep_3550->bios_ctrl);
4984 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
4985 len = asc_prt_line(cp, leftlen,
4986 " termination: %u (%s), bios_ctrl: 0x%x\n",
4987 ep_38C0800->termination_lvd, termstr,
4988 ep_38C0800->bios_ctrl);
4991 len = asc_prt_line(cp, leftlen,
4992 " termination: %u (%s), bios_ctrl: 0x%x\n",
4993 ep_38C1600->termination_lvd, termstr,
4994 ep_38C1600->bios_ctrl);
4998 len = asc_prt_line(cp, leftlen, " Target ID: ");
5000 for (i = 0; i <= ADV_MAX_TID; i++) {
5001 len = asc_prt_line(cp, leftlen, " %X", i);
5004 len = asc_prt_line(cp, leftlen, "\n");
5007 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
5008 word = ep_3550->disc_enable;
5009 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
5010 word = ep_38C0800->disc_enable;
5012 word = ep_38C1600->disc_enable;
5014 len = asc_prt_line(cp, leftlen, " Disconnects: ");
5016 for (i = 0; i <= ADV_MAX_TID; i++) {
5017 len = asc_prt_line(cp, leftlen, " %c",
5018 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
5021 len = asc_prt_line(cp, leftlen, "\n");
5024 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
5025 word = ep_3550->tagqng_able;
5026 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
5027 word = ep_38C0800->tagqng_able;
5029 word = ep_38C1600->tagqng_able;
5031 len = asc_prt_line(cp, leftlen, " Command Queuing: ");
5033 for (i = 0; i <= ADV_MAX_TID; i++) {
5034 len = asc_prt_line(cp, leftlen, " %c",
5035 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
5038 len = asc_prt_line(cp, leftlen, "\n");
5041 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
5042 word = ep_3550->start_motor;
5043 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
5044 word = ep_38C0800->start_motor;
5046 word = ep_38C1600->start_motor;
5048 len = asc_prt_line(cp, leftlen, " Start Motor: ");
5050 for (i = 0; i <= ADV_MAX_TID; i++) {
5051 len = asc_prt_line(cp, leftlen, " %c",
5052 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
5055 len = asc_prt_line(cp, leftlen, "\n");
5058 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
5059 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
5061 for (i = 0; i <= ADV_MAX_TID; i++) {
5062 len = asc_prt_line(cp, leftlen, " %c",
5064 sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
5068 len = asc_prt_line(cp, leftlen, "\n");
5072 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
5073 len = asc_prt_line(cp, leftlen, " Ultra Transfer: ");
5075 for (i = 0; i <= ADV_MAX_TID; i++) {
5076 len = asc_prt_line(cp, leftlen, " %c",
5078 ultra_able & ADV_TID_TO_TIDMASK(i))
5082 len = asc_prt_line(cp, leftlen, "\n");
5086 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
5087 word = ep_3550->wdtr_able;
5088 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
5089 word = ep_38C0800->wdtr_able;
5091 word = ep_38C1600->wdtr_able;
5093 len = asc_prt_line(cp, leftlen, " Wide Transfer: ");
5095 for (i = 0; i <= ADV_MAX_TID; i++) {
5096 len = asc_prt_line(cp, leftlen, " %c",
5097 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
5100 len = asc_prt_line(cp, leftlen, "\n");
5103 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
5104 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
5105 len = asc_prt_line(cp, leftlen,
5106 " Synchronous Transfer Speed (Mhz):\n ");
5108 for (i = 0; i <= ADV_MAX_TID; i++) {
5112 sdtr_speed = adv_dvc_varp->sdtr_speed1;
5113 } else if (i == 4) {
5114 sdtr_speed = adv_dvc_varp->sdtr_speed2;
5115 } else if (i == 8) {
5116 sdtr_speed = adv_dvc_varp->sdtr_speed3;
5117 } else if (i == 12) {
5118 sdtr_speed = adv_dvc_varp->sdtr_speed4;
5120 switch (sdtr_speed & ADV_MAX_TID) {
5143 len = asc_prt_line(cp, leftlen, "%X:%s ", i, speed_str);
5146 len = asc_prt_line(cp, leftlen, "\n ");
5151 len = asc_prt_line(cp, leftlen, "\n");
5159 * asc_prt_driver_conf()
5161 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
5162 * cf. asc_prt_line().
5164 * Return the number of characters copied into 'cp'. No more than
5165 * 'cplen' characters will be copied to 'cp'.
5167 static int asc_prt_driver_conf(struct Scsi_Host *shost, char *cp, int cplen)
5169 asc_board_t *boardp;
5175 boardp = ASC_BOARDP(shost);
5180 len = asc_prt_line(cp, leftlen,
5181 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
5185 len = asc_prt_line(cp, leftlen,
5186 " host_busy %u, last_reset %u, max_id %u, max_lun %u, max_channel %u\n",
5187 shost->host_busy, shost->last_reset, shost->max_id,
5188 shost->max_lun, shost->max_channel);
5191 len = asc_prt_line(cp, leftlen,
5192 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
5193 shost->unique_id, shost->can_queue, shost->this_id,
5194 shost->sg_tablesize, shost->cmd_per_lun);
5197 len = asc_prt_line(cp, leftlen,
5198 " unchecked_isa_dma %d, use_clustering %d\n",
5199 shost->unchecked_isa_dma, shost->use_clustering);
5202 len = asc_prt_line(cp, leftlen,
5203 " flags 0x%x, last_reset 0x%x, jiffies 0x%x, asc_n_io_port 0x%x\n",
5204 boardp->flags, boardp->last_reset, jiffies,
5205 boardp->asc_n_io_port);
5208 len = asc_prt_line(cp, leftlen, " io_port 0x%x\n", shost->io_port);
5211 if (ASC_NARROW_BOARD(boardp)) {
5212 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
5214 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
5221 * asc_prt_asc_board_info()
5223 * Print dynamic board configuration information.
5225 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
5226 * cf. asc_prt_line().
5228 * Return the number of characters copied into 'cp'. No more than
5229 * 'cplen' characters will be copied to 'cp'.
5231 static int asc_prt_asc_board_info(struct Scsi_Host *shost, char *cp, int cplen)
5233 asc_board_t *boardp;
5241 int renegotiate = 0;
5243 boardp = ASC_BOARDP(shost);
5244 v = &boardp->dvc_var.asc_dvc_var;
5245 c = &boardp->dvc_cfg.asc_dvc_cfg;
5246 chip_scsi_id = c->chip_scsi_id;
5251 len = asc_prt_line(cp, leftlen,
5252 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
5256 len = asc_prt_line(cp, leftlen,
5257 " chip_version %u, lib_version 0x%x, lib_serial_no %u, mcode_date 0x%x\n",
5258 c->chip_version, c->lib_version, c->lib_serial_no,
5262 len = asc_prt_line(cp, leftlen,
5263 " mcode_version 0x%x, err_code %u\n",
5264 c->mcode_version, v->err_code);
5267 /* Current number of commands waiting for the host. */
5268 len = asc_prt_line(cp, leftlen,
5269 " Total Command Pending: %d\n", v->cur_total_qng);
5272 len = asc_prt_line(cp, leftlen, " Command Queuing:");
5274 for (i = 0; i <= ASC_MAX_TID; i++) {
5275 if ((chip_scsi_id == i) ||
5276 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
5279 len = asc_prt_line(cp, leftlen, " %X:%c",
5282 use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ?
5286 len = asc_prt_line(cp, leftlen, "\n");
5289 /* Current number of commands waiting for a device. */
5290 len = asc_prt_line(cp, leftlen, " Command Queue Pending:");
5292 for (i = 0; i <= ASC_MAX_TID; i++) {
5293 if ((chip_scsi_id == i) ||
5294 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
5297 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->cur_dvc_qng[i]);
5300 len = asc_prt_line(cp, leftlen, "\n");
5303 /* Current limit on number of commands that can be sent to a device. */
5304 len = asc_prt_line(cp, leftlen, " Command Queue Limit:");
5306 for (i = 0; i <= ASC_MAX_TID; i++) {
5307 if ((chip_scsi_id == i) ||
5308 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
5311 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->max_dvc_qng[i]);
5314 len = asc_prt_line(cp, leftlen, "\n");
5317 /* Indicate whether the device has returned queue full status. */
5318 len = asc_prt_line(cp, leftlen, " Command Queue Full:");
5320 for (i = 0; i <= ASC_MAX_TID; i++) {
5321 if ((chip_scsi_id == i) ||
5322 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
5325 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i)) {
5326 len = asc_prt_line(cp, leftlen, " %X:Y-%d",
5327 i, boardp->queue_full_cnt[i]);
5329 len = asc_prt_line(cp, leftlen, " %X:N", i);
5333 len = asc_prt_line(cp, leftlen, "\n");
5336 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
5338 for (i = 0; i <= ASC_MAX_TID; i++) {
5339 if ((chip_scsi_id == i) ||
5340 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
5343 len = asc_prt_line(cp, leftlen, " %X:%c",
5346 sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
5350 len = asc_prt_line(cp, leftlen, "\n");
5353 for (i = 0; i <= ASC_MAX_TID; i++) {
5354 uchar syn_period_ix;
5356 if ((chip_scsi_id == i) ||
5357 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
5358 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
5362 len = asc_prt_line(cp, leftlen, " %X:", i);
5365 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
5366 len = asc_prt_line(cp, leftlen, " Asynchronous");
5370 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
5373 len = asc_prt_line(cp, leftlen,
5374 " Transfer Period Factor: %d (%d.%d Mhz),",
5375 v->sdtr_period_tbl[syn_period_ix],
5377 v->sdtr_period_tbl[syn_period_ix],
5384 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
5386 sdtr_data[i] & ASC_SYN_MAX_OFFSET);
5390 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
5391 len = asc_prt_line(cp, leftlen, "*\n");
5394 len = asc_prt_line(cp, leftlen, "\n");
5400 len = asc_prt_line(cp, leftlen,
5401 " * = Re-negotiation pending before next command.\n");
5409 * asc_prt_adv_board_info()
5411 * Print dynamic board configuration information.
5413 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
5414 * cf. asc_prt_line().
5416 * Return the number of characters copied into 'cp'. No more than
5417 * 'cplen' characters will be copied to 'cp'.
5419 static int asc_prt_adv_board_info(struct Scsi_Host *shost, char *cp, int cplen)
5421 asc_board_t *boardp;
5428 AdvPortAddr iop_base;
5429 ushort chip_scsi_id;
5433 ushort sdtr_able, wdtr_able;
5434 ushort wdtr_done, sdtr_done;
5436 int renegotiate = 0;
5438 boardp = ASC_BOARDP(shost);
5439 v = &boardp->dvc_var.adv_dvc_var;
5440 c = &boardp->dvc_cfg.adv_dvc_cfg;
5441 iop_base = v->iop_base;
5442 chip_scsi_id = v->chip_scsi_id;
5447 len = asc_prt_line(cp, leftlen,
5448 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
5452 len = asc_prt_line(cp, leftlen,
5453 " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
5455 AdvReadWordRegister(iop_base,
5456 IOPW_SCSI_CFG1) & CABLE_DETECT,
5460 len = asc_prt_line(cp, leftlen,
5461 " chip_version %u, lib_version 0x%x, mcode_date 0x%x, mcode_version 0x%x\n",
5462 c->chip_version, c->lib_version, c->mcode_date,
5466 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5467 len = asc_prt_line(cp, leftlen, " Queuing Enabled:");
5469 for (i = 0; i <= ADV_MAX_TID; i++) {
5470 if ((chip_scsi_id == i) ||
5471 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
5475 len = asc_prt_line(cp, leftlen, " %X:%c",
5477 (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
5481 len = asc_prt_line(cp, leftlen, "\n");
5484 len = asc_prt_line(cp, leftlen, " Queue Limit:");
5486 for (i = 0; i <= ADV_MAX_TID; i++) {
5487 if ((chip_scsi_id == i) ||
5488 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
5492 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
5495 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
5498 len = asc_prt_line(cp, leftlen, "\n");
5501 len = asc_prt_line(cp, leftlen, " Command Pending:");
5503 for (i = 0; i <= ADV_MAX_TID; i++) {
5504 if ((chip_scsi_id == i) ||
5505 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
5509 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
5512 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
5515 len = asc_prt_line(cp, leftlen, "\n");
5518 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5519 len = asc_prt_line(cp, leftlen, " Wide Enabled:");
5521 for (i = 0; i <= ADV_MAX_TID; i++) {
5522 if ((chip_scsi_id == i) ||
5523 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
5527 len = asc_prt_line(cp, leftlen, " %X:%c",
5529 (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
5533 len = asc_prt_line(cp, leftlen, "\n");
5536 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
5537 len = asc_prt_line(cp, leftlen, " Transfer Bit Width:");
5539 for (i = 0; i <= ADV_MAX_TID; i++) {
5540 if ((chip_scsi_id == i) ||
5541 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
5545 AdvReadWordLram(iop_base,
5546 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
5549 len = asc_prt_line(cp, leftlen, " %X:%d",
5550 i, (lramword & 0x8000) ? 16 : 8);
5553 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
5554 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
5555 len = asc_prt_line(cp, leftlen, "*");
5560 len = asc_prt_line(cp, leftlen, "\n");
5563 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5564 len = asc_prt_line(cp, leftlen, " Synchronous Enabled:");
5566 for (i = 0; i <= ADV_MAX_TID; i++) {
5567 if ((chip_scsi_id == i) ||
5568 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
5572 len = asc_prt_line(cp, leftlen, " %X:%c",
5574 (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
5578 len = asc_prt_line(cp, leftlen, "\n");
5581 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
5582 for (i = 0; i <= ADV_MAX_TID; i++) {
5584 AdvReadWordLram(iop_base,
5585 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
5587 lramword &= ~0x8000;
5589 if ((chip_scsi_id == i) ||
5590 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
5591 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
5595 len = asc_prt_line(cp, leftlen, " %X:", i);
5598 if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */
5599 len = asc_prt_line(cp, leftlen, " Asynchronous");
5603 asc_prt_line(cp, leftlen,
5604 " Transfer Period Factor: ");
5607 if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */
5609 asc_prt_line(cp, leftlen, "9 (80.0 Mhz),");
5611 } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */
5613 asc_prt_line(cp, leftlen, "10 (40.0 Mhz),");
5615 } else { /* 20 Mhz or below. */
5617 period = (((lramword >> 8) * 25) + 50) / 4;
5619 if (period == 0) { /* Should never happen. */
5621 asc_prt_line(cp, leftlen,
5625 len = asc_prt_line(cp, leftlen,
5627 period, 250 / period,
5634 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
5639 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
5640 len = asc_prt_line(cp, leftlen, "*\n");
5643 len = asc_prt_line(cp, leftlen, "\n");
5649 len = asc_prt_line(cp, leftlen,
5650 " * = Re-negotiation pending before next command.\n");
5660 * Copy proc information to a read buffer taking into account the current
5661 * read offset in the file and the remaining space in the read buffer.
5664 asc_proc_copy(off_t advoffset, off_t offset, char *curbuf, int leftlen,
5665 char *cp, int cplen)
5669 ASC_DBG3(2, "asc_proc_copy: offset %d, advoffset %d, cplen %d\n",
5670 (unsigned)offset, (unsigned)advoffset, cplen);
5671 if (offset <= advoffset) {
5672 /* Read offset below current offset, copy everything. */
5673 cnt = min(cplen, leftlen);
5674 ASC_DBG3(2, "asc_proc_copy: curbuf 0x%lx, cp 0x%lx, cnt %d\n",
5675 (ulong)curbuf, (ulong)cp, cnt);
5676 memcpy(curbuf, cp, cnt);
5677 } else if (offset < advoffset + cplen) {
5678 /* Read offset within current range, partial copy. */
5679 cnt = (advoffset + cplen) - offset;
5680 cp = (cp + cplen) - cnt;
5681 cnt = min(cnt, leftlen);
5682 ASC_DBG3(2, "asc_proc_copy: curbuf 0x%lx, cp 0x%lx, cnt %d\n",
5683 (ulong)curbuf, (ulong)cp, cnt);
5684 memcpy(curbuf, cp, cnt);
5692 * If 'cp' is NULL print to the console, otherwise print to a buffer.
5694 * Return 0 if printing to the console, otherwise return the number of
5695 * bytes written to the buffer.
5697 * Note: If any single line is greater than ASC_PRTLINE_SIZE bytes the stack
5698 * will be corrupted. 's[]' is defined to be ASC_PRTLINE_SIZE bytes.
5700 static int asc_prt_line(char *buf, int buflen, char *fmt, ...)
5704 char s[ASC_PRTLINE_SIZE];
5706 va_start(args, fmt);
5707 ret = vsprintf(s, fmt, args);
5708 BUG_ON(ret >= ASC_PRTLINE_SIZE);
5713 ret = min(buflen, ret);
5714 memcpy(buf, s, ret);
5719 #endif /* CONFIG_PROC_FS */
5722 * --- Functions Required by the Asc Library
5727 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
5729 * Calling/Exit State:
5733 * Output an ASC_SCSI_Q structure to the chip
5736 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
5740 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
5741 AscSetChipLramAddr(iop_base, s_addr);
5742 for (i = 0; i < 2 * words; i += 2) {
5743 if (i == 4 || i == 20) {
5746 outpw(iop_base + IOP_RAM_DATA,
5747 ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
5753 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
5755 * Calling/Exit State:
5759 * Input an ASC_QDONE_INFO structure from the chip
5762 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
5767 AscSetChipLramAddr(iop_base, s_addr);
5768 for (i = 0; i < 2 * words; i += 2) {
5772 word = inpw(iop_base + IOP_RAM_DATA);
5773 inbuf[i] = word & 0xff;
5774 inbuf[i + 1] = (word >> 8) & 0xff;
5776 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
5780 * Return the BIOS address of the adapter at the specified
5781 * I/O port and with the specified bus type.
5783 static unsigned short __devinit
5784 AscGetChipBiosAddress(PortAddr iop_base, unsigned short bus_type)
5786 unsigned short cfg_lsw;
5787 unsigned short bios_addr;
5790 * The PCI BIOS is re-located by the motherboard BIOS. Because
5791 * of this the driver can not determine where a PCI BIOS is
5792 * loaded and executes.
5794 if (bus_type & ASC_IS_PCI)
5798 if ((bus_type & ASC_IS_EISA) != 0) {
5799 cfg_lsw = AscGetEisaChipCfg(iop_base);
5801 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
5804 #endif /* CONFIG_ISA */
5806 cfg_lsw = AscGetChipCfgLsw(iop_base);
5809 * ISA PnP uses the top bit as the 32K BIOS flag
5811 if (bus_type == ASC_IS_ISAPNP)
5813 bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
5818 * --- Functions Required by the Adv Library
5824 * Return the physical address of 'vaddr' and set '*lenp' to the
5825 * number of physically contiguous bytes that follow 'vaddr'.
5826 * 'flag' indicates the type of structure whose physical address
5827 * is being translated.
5829 * Note: Because Linux currently doesn't page the kernel and all
5830 * kernel buffers are physically contiguous, leave '*lenp' unchanged.
5833 DvcGetPhyAddr(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq,
5834 uchar *vaddr, ADV_SDCNT *lenp, int flag)
5838 paddr = virt_to_bus(vaddr);
5841 "DvcGetPhyAddr: vaddr 0x%lx, lenp 0x%lx *lenp %lu, paddr 0x%lx\n",
5842 (ulong)vaddr, (ulong)lenp, (ulong)*((ulong *)lenp),
5849 * --- Tracing and Debugging Functions
5852 #ifdef ADVANSYS_STATS
5853 #ifdef CONFIG_PROC_FS
5855 * asc_prt_board_stats()
5857 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
5858 * cf. asc_prt_line().
5860 * Return the number of characters copied into 'cp'. No more than
5861 * 'cplen' characters will be copied to 'cp'.
5863 static int asc_prt_board_stats(struct Scsi_Host *shost, char *cp, int cplen)
5868 struct asc_stats *s;
5869 asc_board_t *boardp;
5874 boardp = ASC_BOARDP(shost);
5875 s = &boardp->asc_stats;
5877 len = asc_prt_line(cp, leftlen,
5878 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
5882 len = asc_prt_line(cp, leftlen,
5883 " queuecommand %lu, reset %lu, biosparam %lu, interrupt %lu\n",
5884 s->queuecommand, s->reset, s->biosparam,
5888 len = asc_prt_line(cp, leftlen,
5889 " callback %lu, done %lu, build_error %lu, build_noreq %lu, build_nosg %lu\n",
5890 s->callback, s->done, s->build_error,
5891 s->adv_build_noreq, s->adv_build_nosg);
5894 len = asc_prt_line(cp, leftlen,
5895 " exe_noerror %lu, exe_busy %lu, exe_error %lu, exe_unknown %lu\n",
5896 s->exe_noerror, s->exe_busy, s->exe_error,
5901 * Display data transfer statistics.
5903 if (s->cont_cnt > 0) {
5904 len = asc_prt_line(cp, leftlen, " cont_cnt %lu, ", s->cont_cnt);
5907 len = asc_prt_line(cp, leftlen, "cont_xfer %lu.%01lu kb ",
5909 ASC_TENTHS(s->cont_xfer, 2));
5912 /* Contiguous transfer average size */
5913 len = asc_prt_line(cp, leftlen, "avg_xfer %lu.%01lu kb\n",
5914 (s->cont_xfer / 2) / s->cont_cnt,
5915 ASC_TENTHS((s->cont_xfer / 2), s->cont_cnt));
5919 if (s->sg_cnt > 0) {
5921 len = asc_prt_line(cp, leftlen, " sg_cnt %lu, sg_elem %lu, ",
5922 s->sg_cnt, s->sg_elem);
5925 len = asc_prt_line(cp, leftlen, "sg_xfer %lu.%01lu kb\n",
5926 s->sg_xfer / 2, ASC_TENTHS(s->sg_xfer, 2));
5929 /* Scatter gather transfer statistics */
5930 len = asc_prt_line(cp, leftlen, " avg_num_elem %lu.%01lu, ",
5931 s->sg_elem / s->sg_cnt,
5932 ASC_TENTHS(s->sg_elem, s->sg_cnt));
5935 len = asc_prt_line(cp, leftlen, "avg_elem_size %lu.%01lu kb, ",
5936 (s->sg_xfer / 2) / s->sg_elem,
5937 ASC_TENTHS((s->sg_xfer / 2), s->sg_elem));
5940 len = asc_prt_line(cp, leftlen, "avg_xfer_size %lu.%01lu kb\n",
5941 (s->sg_xfer / 2) / s->sg_cnt,
5942 ASC_TENTHS((s->sg_xfer / 2), s->sg_cnt));
5947 * Display request queuing statistics.
5949 len = asc_prt_line(cp, leftlen,
5950 " Active and Waiting Request Queues (Time Unit: %d HZ):\n",
5956 #endif /* CONFIG_PROC_FS */
5957 #endif /* ADVANSYS_STATS */
5959 #ifdef ADVANSYS_DEBUG
5961 * asc_prt_scsi_host()
5963 static void asc_prt_scsi_host(struct Scsi_Host *s)
5965 asc_board_t *boardp;
5967 boardp = ASC_BOARDP(s);
5969 printk("Scsi_Host at addr 0x%lx\n", (ulong)s);
5970 printk(" host_busy %u, host_no %d, last_reset %d,\n",
5971 s->host_busy, s->host_no, (unsigned)s->last_reset);
5973 printk(" base 0x%lx, io_port 0x%lx, irq 0x%x,\n",
5974 (ulong)s->base, (ulong)s->io_port, s->irq);
5976 printk(" dma_channel %d, this_id %d, can_queue %d,\n",
5977 s->dma_channel, s->this_id, s->can_queue);
5979 printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
5980 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
5982 if (ASC_NARROW_BOARD(boardp)) {
5983 asc_prt_asc_dvc_var(&ASC_BOARDP(s)->dvc_var.asc_dvc_var);
5984 asc_prt_asc_dvc_cfg(&ASC_BOARDP(s)->dvc_cfg.asc_dvc_cfg);
5986 asc_prt_adv_dvc_var(&ASC_BOARDP(s)->dvc_var.adv_dvc_var);
5987 asc_prt_adv_dvc_cfg(&ASC_BOARDP(s)->dvc_cfg.adv_dvc_cfg);
5992 * asc_prt_scsi_cmnd()
5994 static void asc_prt_scsi_cmnd(struct scsi_cmnd *s)
5996 printk("struct scsi_cmnd at addr 0x%lx\n", (ulong)s);
5998 printk(" host 0x%lx, device 0x%lx, target %u, lun %u, channel %u,\n",
5999 (ulong)s->device->host, (ulong)s->device, s->device->id,
6000 s->device->lun, s->device->channel);
6002 asc_prt_hex(" CDB", s->cmnd, s->cmd_len);
6004 printk("sc_data_direction %u, resid %d\n",
6005 s->sc_data_direction, s->resid);
6007 printk(" use_sg %u, sglist_len %u\n", s->use_sg, s->sglist_len);
6009 printk(" serial_number 0x%x, retries %d, allowed %d\n",
6010 (unsigned)s->serial_number, s->retries, s->allowed);
6012 printk(" timeout_per_command %d\n", s->timeout_per_command);
6014 printk(" scsi_done 0x%p, done 0x%p, host_scribble 0x%p, result 0x%x\n",
6015 s->scsi_done, s->done, s->host_scribble, s->result);
6017 printk(" tag %u, pid %u\n", (unsigned)s->tag, (unsigned)s->pid);
6021 * asc_prt_asc_dvc_var()
6023 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
6025 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
6027 printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
6028 "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
6030 printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
6031 (unsigned)h->init_sdtr);
6033 printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
6034 "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
6035 (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
6036 (unsigned)h->chip_no);
6038 printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
6039 "%u,\n", (unsigned)h->queue_full_or_busy,
6040 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
6042 printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
6043 "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
6044 (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
6045 (unsigned)h->in_critical_cnt);
6047 printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
6048 "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
6049 (unsigned)h->init_state, (unsigned)h->no_scam,
6050 (unsigned)h->pci_fix_asyn_xfer);
6052 printk(" cfg 0x%lx, irq_no 0x%x\n", (ulong)h->cfg, (unsigned)h->irq_no);
6056 * asc_prt_asc_dvc_cfg()
6058 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
6060 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
6062 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
6063 h->can_tagged_qng, h->cmd_qng_enabled);
6064 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
6065 h->disc_enable, h->sdtr_enable);
6068 (" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, chip_version %d,\n",
6069 h->chip_scsi_id, h->isa_dma_speed, h->isa_dma_channel,
6073 (" pci_device_id %d, lib_serial_no %u, lib_version %u, mcode_date 0x%x,\n",
6074 to_pci_dev(h->dev)->device, h->lib_serial_no, h->lib_version,
6077 printk(" mcode_version %d, overrun_buf 0x%lx\n",
6078 h->mcode_version, (ulong)h->overrun_buf);
6082 * asc_prt_asc_scsi_q()
6084 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
6089 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
6092 (" target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n",
6093 q->q2.target_ix, q->q1.target_lun, (ulong)q->q2.srb_ptr,
6097 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
6098 (ulong)le32_to_cpu(q->q1.data_addr),
6099 (ulong)le32_to_cpu(q->q1.data_cnt),
6100 (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
6102 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
6103 (ulong)q->cdbptr, q->q2.cdb_len,
6104 (ulong)q->sg_head, q->q1.sg_queue_cnt);
6108 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
6109 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
6111 for (i = 0; i < sgp->entry_cnt; i++) {
6112 printk(" [%u]: addr 0x%lx, bytes %lu\n",
6113 i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
6114 (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
6121 * asc_prt_asc_qdone_info()
6123 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
6125 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
6126 printk(" srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n",
6127 (ulong)q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len,
6130 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
6131 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
6135 * asc_prt_adv_dvc_var()
6137 * Display an ADV_DVC_VAR structure.
6139 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
6141 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
6143 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
6144 (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
6146 printk(" isr_callback 0x%lx, sdtr_able 0x%x, wdtr_able 0x%x\n",
6147 (ulong)h->isr_callback, (unsigned)h->sdtr_able,
6148 (unsigned)h->wdtr_able);
6150 printk(" start_motor 0x%x, scsi_reset_wait 0x%x, irq_no 0x%x,\n",
6151 (unsigned)h->start_motor,
6152 (unsigned)h->scsi_reset_wait, (unsigned)h->irq_no);
6154 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n",
6155 (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
6156 (ulong)h->carr_freelist);
6158 printk(" icq_sp 0x%lx, irq_sp 0x%lx\n",
6159 (ulong)h->icq_sp, (ulong)h->irq_sp);
6161 printk(" no_scam 0x%x, tagqng_able 0x%x\n",
6162 (unsigned)h->no_scam, (unsigned)h->tagqng_able);
6164 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n",
6165 (unsigned)h->chip_scsi_id, (ulong)h->cfg);
6169 * asc_prt_adv_dvc_cfg()
6171 * Display an ADV_DVC_CFG structure.
6173 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
6175 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
6177 printk(" disc_enable 0x%x, termination 0x%x\n",
6178 h->disc_enable, h->termination);
6180 printk(" chip_version 0x%x, mcode_date 0x%x\n",
6181 h->chip_version, h->mcode_date);
6183 printk(" mcode_version 0x%x, pci_device_id 0x%x, lib_version %u\n",
6184 h->mcode_version, to_pci_dev(h->dev)->device, h->lib_version);
6186 printk(" control_flag 0x%x\n", h->control_flag);
6190 * asc_prt_adv_scsi_req_q()
6192 * Display an ADV_SCSI_REQ_Q structure.
6194 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
6197 struct asc_sg_block *sg_ptr;
6199 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
6201 printk(" target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n",
6202 q->target_id, q->target_lun, (ulong)q->srb_ptr, q->a_flag);
6204 printk(" cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
6205 q->cntl, (ulong)le32_to_cpu(q->data_addr), (ulong)q->vdata_addr);
6207 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
6208 (ulong)le32_to_cpu(q->data_cnt),
6209 (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
6212 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
6213 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
6215 printk(" sg_working_ix 0x%x, target_cmd %u\n",
6216 q->sg_working_ix, q->target_cmd);
6218 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
6219 (ulong)le32_to_cpu(q->scsiq_rptr),
6220 (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
6222 /* Display the request's ADV_SG_BLOCK structures. */
6223 if (q->sg_list_ptr != NULL) {
6227 * 'sg_ptr' is a physical address. Convert it to a virtual
6228 * address by indexing 'sg_blk_cnt' into the virtual address
6229 * array 'sg_list_ptr'.
6231 * XXX - Assumes all SG physical blocks are virtually contiguous.
6234 &(((ADV_SG_BLOCK *)(q->sg_list_ptr))[sg_blk_cnt]);
6235 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
6236 if (sg_ptr->sg_ptr == 0) {
6245 * asc_prt_adv_sgblock()
6247 * Display an ADV_SG_BLOCK structure.
6249 static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
6253 printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
6254 (ulong)b, sgblockno);
6255 printk(" sg_cnt %u, sg_ptr 0x%lx\n",
6256 b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
6257 BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
6259 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
6260 for (i = 0; i < b->sg_cnt; i++) {
6261 printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
6262 i, (ulong)b->sg_list[i].sg_addr,
6263 (ulong)b->sg_list[i].sg_count);
6270 * Print hexadecimal output in 4 byte groupings 32 bytes
6271 * or 8 double-words per line.
6273 static void asc_prt_hex(char *f, uchar *s, int l)
6280 printk("%s: (%d bytes)\n", f, l);
6282 for (i = 0; i < l; i += 32) {
6284 /* Display a maximum of 8 double-words per line. */
6285 if ((k = (l - i) / 4) >= 8) {
6292 for (j = 0; j < k; j++) {
6293 printk(" %2.2X%2.2X%2.2X%2.2X",
6294 (unsigned)s[i + (j * 4)],
6295 (unsigned)s[i + (j * 4) + 1],
6296 (unsigned)s[i + (j * 4) + 2],
6297 (unsigned)s[i + (j * 4) + 3]);
6305 printk(" %2.2X", (unsigned)s[i + (j * 4)]);
6308 printk(" %2.2X%2.2X",
6309 (unsigned)s[i + (j * 4)],
6310 (unsigned)s[i + (j * 4) + 1]);
6313 printk(" %2.2X%2.2X%2.2X",
6314 (unsigned)s[i + (j * 4) + 1],
6315 (unsigned)s[i + (j * 4) + 2],
6316 (unsigned)s[i + (j * 4) + 3]);
6323 #endif /* ADVANSYS_DEBUG */
6326 * --- Asc Library Functions
6329 static ushort __devinit AscGetEisaChipCfg(PortAddr iop_base)
6331 PortAddr eisa_cfg_iop;
6333 eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
6334 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
6335 return (inpw(eisa_cfg_iop));
6338 static uchar __devinit AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
6342 if (AscGetChipScsiID(iop_base) == new_host_id) {
6343 return (new_host_id);
6345 cfg_lsw = AscGetChipCfgLsw(iop_base);
6347 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
6348 AscSetChipCfgLsw(iop_base, cfg_lsw);
6349 return (AscGetChipScsiID(iop_base));
6352 static unsigned char __devinit AscGetChipScsiCtrl(PortAddr iop_base)
6356 AscSetBank(iop_base, 1);
6357 sc = inp(iop_base + IOP_REG_SC);
6358 AscSetBank(iop_base, 0);
6362 static unsigned char __devinit
6363 AscGetChipVersion(PortAddr iop_base, unsigned short bus_type)
6365 if (bus_type & ASC_IS_EISA) {
6367 unsigned char revision;
6368 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
6369 (PortAddr) ASC_EISA_REV_IOP_MASK;
6370 revision = inp(eisa_iop);
6371 return ASC_CHIP_MIN_VER_EISA - 1 + revision;
6373 return AscGetChipVerNo(iop_base);
6377 AscLoadMicroCode(PortAddr iop_base,
6378 ushort s_addr, uchar *mcode_buf, ushort mcode_size)
6381 ushort mcode_word_size;
6382 ushort mcode_chksum;
6384 /* Write the microcode buffer starting at LRAM address 0. */
6385 mcode_word_size = (ushort)(mcode_size >> 1);
6386 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
6387 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
6389 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
6390 ASC_DBG1(1, "AscLoadMicroCode: chksum 0x%lx\n", (ulong)chksum);
6391 mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
6392 (ushort)ASC_CODE_SEC_BEG,
6393 (ushort)((mcode_size -
6397 ASC_DBG1(1, "AscLoadMicroCode: mcode_chksum 0x%lx\n",
6398 (ulong)mcode_chksum);
6399 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
6400 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
6404 static int AscFindSignature(PortAddr iop_base)
6408 ASC_DBG2(1, "AscFindSignature: AscGetChipSignatureByte(0x%x) 0x%x\n",
6409 iop_base, AscGetChipSignatureByte(iop_base));
6410 if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
6412 "AscFindSignature: AscGetChipSignatureWord(0x%x) 0x%x\n",
6413 iop_base, AscGetChipSignatureWord(iop_base));
6414 sig_word = AscGetChipSignatureWord(iop_base);
6415 if ((sig_word == (ushort)ASC_1000_ID0W) ||
6416 (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
6423 static void __devinit AscToggleIRQAct(PortAddr iop_base)
6425 AscSetChipStatus(iop_base, CIW_IRQ_ACT);
6426 AscSetChipStatus(iop_base, 0);
6430 static uchar __devinit AscGetChipIRQ(PortAddr iop_base, ushort bus_type)
6435 if ((bus_type & ASC_IS_EISA) != 0) {
6436 cfg_lsw = AscGetEisaChipCfg(iop_base);
6437 chip_irq = (uchar)(((cfg_lsw >> 8) & 0x07) + 10);
6438 if ((chip_irq == 13) || (chip_irq > 15)) {
6443 if ((bus_type & ASC_IS_VL) != 0) {
6444 cfg_lsw = AscGetChipCfgLsw(iop_base);
6445 chip_irq = (uchar)(((cfg_lsw >> 2) & 0x07));
6446 if ((chip_irq == 0) || (chip_irq == 4) || (chip_irq == 7)) {
6449 return ((uchar)(chip_irq + (ASC_MIN_IRQ_NO - 1)));
6451 cfg_lsw = AscGetChipCfgLsw(iop_base);
6452 chip_irq = (uchar)(((cfg_lsw >> 2) & 0x03));
6454 chip_irq += (uchar)2;
6455 return ((uchar)(chip_irq + ASC_MIN_IRQ_NO));
6458 static uchar __devinit
6459 AscSetChipIRQ(PortAddr iop_base, uchar irq_no, ushort bus_type)
6463 if ((bus_type & ASC_IS_VL) != 0) {
6465 if ((irq_no < ASC_MIN_IRQ_NO)
6466 || (irq_no > ASC_MAX_IRQ_NO)) {
6469 irq_no -= (uchar)((ASC_MIN_IRQ_NO - 1));
6472 cfg_lsw = (ushort)(AscGetChipCfgLsw(iop_base) & 0xFFE3);
6473 cfg_lsw |= (ushort)0x0010;
6474 AscSetChipCfgLsw(iop_base, cfg_lsw);
6475 AscToggleIRQAct(iop_base);
6476 cfg_lsw = (ushort)(AscGetChipCfgLsw(iop_base) & 0xFFE0);
6477 cfg_lsw |= (ushort)((irq_no & 0x07) << 2);
6478 AscSetChipCfgLsw(iop_base, cfg_lsw);
6479 AscToggleIRQAct(iop_base);
6480 return (AscGetChipIRQ(iop_base, bus_type));
6482 if ((bus_type & (ASC_IS_ISA)) != 0) {
6485 irq_no -= (uchar)ASC_MIN_IRQ_NO;
6486 cfg_lsw = (ushort)(AscGetChipCfgLsw(iop_base) & 0xFFF3);
6487 cfg_lsw |= (ushort)((irq_no & 0x03) << 2);
6488 AscSetChipCfgLsw(iop_base, cfg_lsw);
6489 return (AscGetChipIRQ(iop_base, bus_type));
6495 static void __devinit AscEnableIsaDma(uchar dma_channel)
6497 if (dma_channel < 4) {
6498 outp(0x000B, (ushort)(0xC0 | dma_channel));
6499 outp(0x000A, dma_channel);
6500 } else if (dma_channel < 8) {
6501 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
6502 outp(0x00D4, (ushort)(dma_channel - 4));
6506 #endif /* CONFIG_ISA */
6508 static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
6514 ushort int_halt_code;
6515 ASC_SCSI_BIT_ID_TYPE scsi_busy;
6516 ASC_SCSI_BIT_ID_TYPE target_id;
6523 uchar q_cntl, tid_no;
6527 asc_board_t *boardp;
6529 BUG_ON(!asc_dvc->drv_ptr);
6530 boardp = asc_dvc->drv_ptr;
6532 iop_base = asc_dvc->iop_base;
6533 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
6535 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
6536 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
6537 target_ix = AscReadLramByte(iop_base,
6538 (ushort)(halt_q_addr +
6539 (ushort)ASC_SCSIQ_B_TARGET_IX));
6541 AscReadLramByte(iop_base,
6542 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6543 tid_no = ASC_TIX_TO_TID(target_ix);
6544 target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
6545 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6546 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
6550 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
6551 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6552 AscSetChipSDTR(iop_base, 0, tid_no);
6553 boardp->sdtr_data[tid_no] = 0;
6555 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6557 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
6558 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6559 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6560 boardp->sdtr_data[tid_no] = asyn_sdtr;
6562 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6564 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
6566 AscMemWordCopyPtrFromLram(iop_base,
6569 sizeof(EXT_MSG) >> 1);
6571 if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6572 ext_msg.msg_req == EXTENDED_SDTR &&
6573 ext_msg.msg_len == MS_SDTR_LEN) {
6575 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
6577 sdtr_accept = FALSE;
6578 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
6580 if ((ext_msg.xfer_period <
6581 asc_dvc->sdtr_period_tbl[asc_dvc->
6582 host_init_sdtr_index])
6583 || (ext_msg.xfer_period >
6584 asc_dvc->sdtr_period_tbl[asc_dvc->
6586 sdtr_accept = FALSE;
6587 ext_msg.xfer_period =
6588 asc_dvc->sdtr_period_tbl[asc_dvc->
6589 host_init_sdtr_index];
6593 AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
6594 ext_msg.req_ack_offset);
6595 if ((sdtr_data == 0xFF)) {
6597 q_cntl |= QC_MSG_OUT;
6598 asc_dvc->init_sdtr &= ~target_id;
6599 asc_dvc->sdtr_done &= ~target_id;
6600 AscSetChipSDTR(iop_base, asyn_sdtr,
6602 boardp->sdtr_data[tid_no] = asyn_sdtr;
6605 if (ext_msg.req_ack_offset == 0) {
6607 q_cntl &= ~QC_MSG_OUT;
6608 asc_dvc->init_sdtr &= ~target_id;
6609 asc_dvc->sdtr_done &= ~target_id;
6610 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6612 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
6614 q_cntl &= ~QC_MSG_OUT;
6615 asc_dvc->sdtr_done |= target_id;
6616 asc_dvc->init_sdtr |= target_id;
6617 asc_dvc->pci_fix_asyn_xfer &=
6620 AscCalSDTRData(asc_dvc,
6621 ext_msg.xfer_period,
6624 AscSetChipSDTR(iop_base, sdtr_data,
6626 boardp->sdtr_data[tid_no] = sdtr_data;
6629 q_cntl |= QC_MSG_OUT;
6630 AscMsgOutSDTR(asc_dvc,
6631 ext_msg.xfer_period,
6632 ext_msg.req_ack_offset);
6633 asc_dvc->pci_fix_asyn_xfer &=
6636 AscCalSDTRData(asc_dvc,
6637 ext_msg.xfer_period,
6640 AscSetChipSDTR(iop_base, sdtr_data,
6642 boardp->sdtr_data[tid_no] = sdtr_data;
6643 asc_dvc->sdtr_done |= target_id;
6644 asc_dvc->init_sdtr |= target_id;
6648 AscWriteLramByte(iop_base,
6649 (ushort)(halt_q_addr +
6650 (ushort)ASC_SCSIQ_B_CNTL),
6652 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6654 } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6655 ext_msg.msg_req == EXTENDED_WDTR &&
6656 ext_msg.msg_len == MS_WDTR_LEN) {
6658 ext_msg.wdtr_width = 0;
6659 AscMemWordCopyPtrToLram(iop_base,
6662 sizeof(EXT_MSG) >> 1);
6663 q_cntl |= QC_MSG_OUT;
6664 AscWriteLramByte(iop_base,
6665 (ushort)(halt_q_addr +
6666 (ushort)ASC_SCSIQ_B_CNTL),
6668 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6672 ext_msg.msg_type = MESSAGE_REJECT;
6673 AscMemWordCopyPtrToLram(iop_base,
6676 sizeof(EXT_MSG) >> 1);
6677 q_cntl |= QC_MSG_OUT;
6678 AscWriteLramByte(iop_base,
6679 (ushort)(halt_q_addr +
6680 (ushort)ASC_SCSIQ_B_CNTL),
6682 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6685 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
6687 q_cntl |= QC_REQ_SENSE;
6689 if ((asc_dvc->init_sdtr & target_id) != 0) {
6691 asc_dvc->sdtr_done &= ~target_id;
6693 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
6694 q_cntl |= QC_MSG_OUT;
6695 AscMsgOutSDTR(asc_dvc,
6697 sdtr_period_tbl[(sdtr_data >> 4) &
6701 (uchar)(sdtr_data & (uchar)
6702 ASC_SYN_MAX_OFFSET));
6705 AscWriteLramByte(iop_base,
6706 (ushort)(halt_q_addr +
6707 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6709 tag_code = AscReadLramByte(iop_base,
6710 (ushort)(halt_q_addr + (ushort)
6711 ASC_SCSIQ_B_TAG_CODE));
6713 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
6714 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
6717 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
6718 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
6721 AscWriteLramByte(iop_base,
6722 (ushort)(halt_q_addr +
6723 (ushort)ASC_SCSIQ_B_TAG_CODE),
6726 q_status = AscReadLramByte(iop_base,
6727 (ushort)(halt_q_addr + (ushort)
6728 ASC_SCSIQ_B_STATUS));
6729 q_status |= (QS_READY | QS_BUSY);
6730 AscWriteLramByte(iop_base,
6731 (ushort)(halt_q_addr +
6732 (ushort)ASC_SCSIQ_B_STATUS),
6735 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
6736 scsi_busy &= ~target_id;
6737 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6739 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6741 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
6743 AscMemWordCopyPtrFromLram(iop_base,
6746 sizeof(EXT_MSG) >> 1);
6748 if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
6749 (out_msg.msg_len == MS_SDTR_LEN) &&
6750 (out_msg.msg_req == EXTENDED_SDTR)) {
6752 asc_dvc->init_sdtr &= ~target_id;
6753 asc_dvc->sdtr_done &= ~target_id;
6754 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6755 boardp->sdtr_data[tid_no] = asyn_sdtr;
6757 q_cntl &= ~QC_MSG_OUT;
6758 AscWriteLramByte(iop_base,
6759 (ushort)(halt_q_addr +
6760 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6761 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6763 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
6765 scsi_status = AscReadLramByte(iop_base,
6766 (ushort)((ushort)halt_q_addr +
6768 ASC_SCSIQ_SCSI_STATUS));
6770 AscReadLramByte(iop_base,
6771 (ushort)((ushort)ASC_QADR_BEG +
6772 (ushort)target_ix));
6773 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
6775 scsi_busy = AscReadLramByte(iop_base,
6776 (ushort)ASCV_SCSIBUSY_B);
6777 scsi_busy |= target_id;
6778 AscWriteLramByte(iop_base,
6779 (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6780 asc_dvc->queue_full_or_busy |= target_id;
6782 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
6783 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
6785 asc_dvc->max_dvc_qng[tid_no] =
6788 AscWriteLramByte(iop_base,
6790 ASCV_MAX_DVC_QNG_BEG
6796 * Set the device queue depth to the number of
6797 * active requests when the QUEUE FULL condition
6800 boardp->queue_full |= target_id;
6801 boardp->queue_full_cnt[tid_no] =
6806 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6809 #if CC_VERY_LONG_SG_LIST
6810 else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC) {
6814 uchar first_sg_wk_q_no;
6815 ASC_SCSI_Q *scsiq; /* Ptr to driver request. */
6816 ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */
6817 ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */
6818 ushort sg_list_dwords;
6819 ushort sg_entry_cnt;
6823 q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP);
6824 if (q_no == ASC_QLINK_END) {
6828 q_addr = ASC_QNO_TO_QADDR(q_no);
6831 * Convert the request's SRB pointer to a host ASC_SCSI_REQ
6832 * structure pointer using a macro provided by the driver.
6833 * The ASC_SCSI_REQ pointer provides a pointer to the
6834 * host ASC_SG_HEAD structure.
6836 /* Read request's SRB pointer. */
6837 scsiq = (ASC_SCSI_Q *)
6838 ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
6841 ASC_SCSIQ_D_SRBPTR))));
6844 * Get request's first and working SG queue.
6846 sg_wk_q_no = AscReadLramByte(iop_base,
6848 ASC_SCSIQ_B_SG_WK_QP));
6850 first_sg_wk_q_no = AscReadLramByte(iop_base,
6852 ASC_SCSIQ_B_FIRST_SG_WK_QP));
6855 * Reset request's working SG queue back to the
6858 AscWriteLramByte(iop_base,
6860 (ushort)ASC_SCSIQ_B_SG_WK_QP),
6863 sg_head = scsiq->sg_head;
6866 * Set sg_entry_cnt to the number of SG elements
6867 * that will be completed on this interrupt.
6869 * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
6870 * SG elements. The data_cnt and data_addr fields which
6871 * add 1 to the SG element capacity are not used when
6872 * restarting SG handling after a halt.
6874 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1)) {
6875 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
6878 * Keep track of remaining number of SG elements that will
6879 * need to be handled on the next interrupt.
6881 scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
6883 sg_entry_cnt = scsiq->remain_sg_entry_cnt;
6884 scsiq->remain_sg_entry_cnt = 0;
6888 * Copy SG elements into the list of allocated SG queues.
6890 * Last index completed is saved in scsiq->next_sg_index.
6892 next_qp = first_sg_wk_q_no;
6893 q_addr = ASC_QNO_TO_QADDR(next_qp);
6894 scsi_sg_q.sg_head_qp = q_no;
6895 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
6896 for (i = 0; i < sg_head->queue_cnt; i++) {
6897 scsi_sg_q.seq_no = i + 1;
6898 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
6899 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
6900 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
6902 * After very first SG queue RISC FW uses next
6903 * SG queue first element then checks sg_list_cnt
6904 * against zero and then decrements, so set
6905 * sg_list_cnt 1 less than number of SG elements
6908 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
6909 scsi_sg_q.sg_cur_list_cnt =
6910 ASC_SG_LIST_PER_Q - 1;
6913 * This is the last SG queue in the list of
6914 * allocated SG queues. If there are more
6915 * SG elements than will fit in the allocated
6916 * queues, then set the QCSG_SG_XFER_MORE flag.
6918 if (scsiq->remain_sg_entry_cnt != 0) {
6919 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
6921 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
6923 /* equals sg_entry_cnt * 2 */
6924 sg_list_dwords = sg_entry_cnt << 1;
6925 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
6926 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
6930 scsi_sg_q.q_no = next_qp;
6931 AscMemWordCopyPtrToLram(iop_base,
6932 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
6933 (uchar *)&scsi_sg_q,
6934 sizeof(ASC_SG_LIST_Q) >> 1);
6936 AscMemDWordCopyPtrToLram(iop_base,
6937 q_addr + ASC_SGQ_LIST_BEG,
6939 sg_list[scsiq->next_sg_index],
6942 scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
6945 * If the just completed SG queue contained the
6946 * last SG element, then no more SG queues need
6949 if (scsi_sg_q.cntl & QCSG_SG_XFER_END) {
6953 next_qp = AscReadLramByte(iop_base,
6956 q_addr = ASC_QNO_TO_QADDR(next_qp);
6960 * Clear the halt condition so the RISC will be restarted
6963 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6966 #endif /* CC_VERY_LONG_SG_LIST */
6971 _AscCopyLramScsiDoneQ(PortAddr iop_base,
6973 ASC_QDONE_INFO *scsiq, ASC_DCNT max_dma_count)
6978 DvcGetQinfo(iop_base,
6979 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
6981 (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
6983 _val = AscReadLramWord(iop_base,
6984 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
6985 scsiq->q_status = (uchar)_val;
6986 scsiq->q_no = (uchar)(_val >> 8);
6987 _val = AscReadLramWord(iop_base,
6988 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6989 scsiq->cntl = (uchar)_val;
6990 sg_queue_cnt = (uchar)(_val >> 8);
6991 _val = AscReadLramWord(iop_base,
6993 (ushort)ASC_SCSIQ_B_SENSE_LEN));
6994 scsiq->sense_len = (uchar)_val;
6995 scsiq->extra_bytes = (uchar)(_val >> 8);
6998 * Read high word of remain bytes from alternate location.
7000 scsiq->remain_bytes = (((ADV_DCNT)AscReadLramWord(iop_base,
7003 ASC_SCSIQ_W_ALT_DC1)))
7006 * Read low word of remain bytes from original location.
7008 scsiq->remain_bytes += AscReadLramWord(iop_base,
7009 (ushort)(q_addr + (ushort)
7010 ASC_SCSIQ_DW_REMAIN_XFER_CNT));
7012 scsiq->remain_bytes &= max_dma_count;
7013 return (sg_queue_cnt);
7016 static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
7025 ASC_SCSI_BIT_ID_TYPE scsi_busy;
7026 ASC_SCSI_BIT_ID_TYPE target_id;
7030 uchar cur_target_qng;
7031 ASC_QDONE_INFO scsiq_buf;
7032 ASC_QDONE_INFO *scsiq;
7035 iop_base = asc_dvc->iop_base;
7037 scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
7038 done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
7039 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
7040 next_qp = AscReadLramByte(iop_base,
7041 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
7042 if (next_qp != ASC_QLINK_END) {
7043 AscPutVarDoneQTail(iop_base, next_qp);
7044 q_addr = ASC_QNO_TO_QADDR(next_qp);
7045 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
7046 asc_dvc->max_dma_count);
7047 AscWriteLramByte(iop_base,
7049 (ushort)ASC_SCSIQ_B_STATUS),
7051 q_status & (uchar)~(QS_READY |
7053 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
7054 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
7055 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
7057 sg_list_qp = next_qp;
7058 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
7059 sg_list_qp = AscReadLramByte(iop_base,
7063 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
7064 if (sg_list_qp == ASC_QLINK_END) {
7065 AscSetLibErrorCode(asc_dvc,
7066 ASCQ_ERR_SG_Q_LINKS);
7067 scsiq->d3.done_stat = QD_WITH_ERROR;
7068 scsiq->d3.host_stat =
7069 QHSTA_D_QDONE_SG_LIST_CORRUPTED;
7070 goto FATAL_ERR_QDONE;
7072 AscWriteLramByte(iop_base,
7073 (ushort)(sg_q_addr + (ushort)
7074 ASC_SCSIQ_B_STATUS),
7077 n_q_used = sg_queue_cnt + 1;
7078 AscPutVarDoneQTail(iop_base, sg_list_qp);
7080 if (asc_dvc->queue_full_or_busy & target_id) {
7081 cur_target_qng = AscReadLramByte(iop_base,
7087 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
7088 scsi_busy = AscReadLramByte(iop_base, (ushort)
7090 scsi_busy &= ~target_id;
7091 AscWriteLramByte(iop_base,
7092 (ushort)ASCV_SCSIBUSY_B,
7094 asc_dvc->queue_full_or_busy &= ~target_id;
7097 if (asc_dvc->cur_total_qng >= n_q_used) {
7098 asc_dvc->cur_total_qng -= n_q_used;
7099 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
7100 asc_dvc->cur_dvc_qng[tid_no]--;
7103 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
7104 scsiq->d3.done_stat = QD_WITH_ERROR;
7105 goto FATAL_ERR_QDONE;
7107 if ((scsiq->d2.srb_ptr == 0UL) ||
7108 ((scsiq->q_status & QS_ABORTED) != 0)) {
7110 } else if (scsiq->q_status == QS_DONE) {
7111 false_overrun = FALSE;
7112 if (scsiq->extra_bytes != 0) {
7113 scsiq->remain_bytes +=
7114 (ADV_DCNT)scsiq->extra_bytes;
7116 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
7117 if (scsiq->d3.host_stat ==
7118 QHSTA_M_DATA_OVER_RUN) {
7120 cntl & (QC_DATA_IN | QC_DATA_OUT))
7122 scsiq->d3.done_stat =
7124 scsiq->d3.host_stat =
7126 } else if (false_overrun) {
7127 scsiq->d3.done_stat =
7129 scsiq->d3.host_stat =
7132 } else if (scsiq->d3.host_stat ==
7133 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
7134 AscStopChip(iop_base);
7135 AscSetChipControl(iop_base,
7136 (uchar)(CC_SCSI_RESET
7139 AscSetChipControl(iop_base, CC_HALT);
7140 AscSetChipStatus(iop_base,
7141 CIW_CLR_SCSI_RESET_INT);
7142 AscSetChipStatus(iop_base, 0);
7143 AscSetChipControl(iop_base, 0);
7146 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7147 asc_isr_callback(asc_dvc, scsiq);
7149 if ((AscReadLramByte(iop_base,
7150 (ushort)(q_addr + (ushort)
7153 asc_dvc->unit_not_ready &= ~target_id;
7154 if (scsiq->d3.done_stat != QD_NO_ERROR) {
7155 asc_dvc->start_motor &=
7162 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
7164 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7165 asc_isr_callback(asc_dvc, scsiq);
7173 static int AscISR(ASC_DVC_VAR *asc_dvc)
7175 ASC_CS_TYPE chipstat;
7177 ushort saved_ram_addr;
7179 uchar saved_ctrl_reg;
7184 iop_base = asc_dvc->iop_base;
7185 int_pending = FALSE;
7187 if (AscIsIntPending(iop_base) == 0) {
7191 if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
7194 if (asc_dvc->in_critical_cnt != 0) {
7195 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
7198 if (asc_dvc->is_in_int) {
7199 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
7202 asc_dvc->is_in_int = TRUE;
7203 ctrl_reg = AscGetChipControl(iop_base);
7204 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
7205 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
7206 chipstat = AscGetChipStatus(iop_base);
7207 if (chipstat & CSW_SCSI_RESET_LATCH) {
7208 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
7211 asc_dvc->sdtr_done = 0;
7212 saved_ctrl_reg &= (uchar)(~CC_HALT);
7213 while ((AscGetChipStatus(iop_base) &
7214 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
7217 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
7218 AscSetChipControl(iop_base, CC_HALT);
7219 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
7220 AscSetChipStatus(iop_base, 0);
7221 chipstat = AscGetChipStatus(iop_base);
7224 saved_ram_addr = AscGetChipLramAddr(iop_base);
7225 host_flag = AscReadLramByte(iop_base,
7227 (uchar)(~ASC_HOST_FLAG_IN_ISR);
7228 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
7229 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
7230 if ((chipstat & CSW_INT_PENDING)
7233 AscAckInterrupt(iop_base);
7235 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
7236 if (AscIsrChipHalted(asc_dvc) == ERR) {
7237 goto ISR_REPORT_QDONE_FATAL_ERROR;
7239 saved_ctrl_reg &= (uchar)(~CC_HALT);
7242 ISR_REPORT_QDONE_FATAL_ERROR:
7243 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
7245 AscIsrQDone(asc_dvc)) & 0x01) != 0) {
7250 AscIsrQDone(asc_dvc)) == 1) {
7253 } while (status == 0x11);
7255 if ((status & 0x80) != 0)
7259 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
7260 AscSetChipLramAddr(iop_base, saved_ram_addr);
7261 AscSetChipControl(iop_base, saved_ctrl_reg);
7262 asc_dvc->is_in_int = FALSE;
7263 return (int_pending);
7266 /* Microcode buffer is kept after initialization for error recovery. */
7267 static uchar _asc_mcode_buf[] = {
7268 0x01, 0x03, 0x01, 0x19, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7269 0x00, 0x00, 0x00, 0x00, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,
7270 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7271 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7272 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7273 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC3, 0x12, 0x0D, 0x05,
7274 0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7275 0xFF, 0x80, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7276 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xFF,
7277 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
7278 0x00, 0x00, 0xE4, 0x88, 0x00, 0x00, 0x00, 0x00, 0x80, 0x73, 0x48, 0x04,
7279 0x36, 0x00, 0x00, 0xA2, 0xC2, 0x00, 0x80, 0x73, 0x03, 0x23, 0x36, 0x40,
7280 0xB6, 0x00, 0x36, 0x00, 0x05, 0xD6, 0x0C, 0xD2, 0x12, 0xDA, 0x00, 0xA2,
7281 0xC2, 0x00, 0x92, 0x80, 0x1E, 0x98, 0x50, 0x00, 0xF5, 0x00, 0x48, 0x98,
7282 0xDF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x4F, 0x00, 0xF5, 0x00,
7283 0x48, 0x98, 0xEF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x80, 0x62,
7284 0x92, 0x80, 0x00, 0x46, 0x15, 0xEE, 0x13, 0xEA, 0x02, 0x01, 0x09, 0xD8,
7285 0xCD, 0x04, 0x4D, 0x00, 0x00, 0xA3, 0xD6, 0x00, 0xA6, 0x97, 0x7F, 0x23,
7286 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84, 0xD2, 0xC1, 0x80, 0x73, 0xCD, 0x04,
7287 0x4D, 0x00, 0x00, 0xA3, 0xDA, 0x01, 0xA6, 0x97, 0xC6, 0x81, 0xC2, 0x88,
7288 0x80, 0x73, 0x80, 0x77, 0x00, 0x01, 0x01, 0xA1, 0xFE, 0x00, 0x4F, 0x00,
7289 0x84, 0x97, 0x07, 0xA6, 0x08, 0x01, 0x00, 0x33, 0x03, 0x00, 0xC2, 0x88,
7290 0x03, 0x03, 0x01, 0xDE, 0xC2, 0x88, 0xCE, 0x00, 0x69, 0x60, 0xCE, 0x00,
7291 0x02, 0x03, 0x4A, 0x60, 0x00, 0xA2, 0x78, 0x01, 0x80, 0x63, 0x07, 0xA6,
7292 0x24, 0x01, 0x78, 0x81, 0x03, 0x03, 0x80, 0x63, 0xE2, 0x00, 0x07, 0xA6,
7293 0x34, 0x01, 0x00, 0x33, 0x04, 0x00, 0xC2, 0x88, 0x03, 0x07, 0x02, 0x01,
7294 0x04, 0xCA, 0x0D, 0x23, 0x68, 0x98, 0x4D, 0x04, 0x04, 0x85, 0x05, 0xD8,
7295 0x0D, 0x23, 0x68, 0x98, 0xCD, 0x04, 0x15, 0x23, 0xF8, 0x88, 0xFB, 0x23,
7296 0x02, 0x61, 0x82, 0x01, 0x80, 0x63, 0x02, 0x03, 0x06, 0xA3, 0x62, 0x01,
7297 0x00, 0x33, 0x0A, 0x00, 0xC2, 0x88, 0x4E, 0x00, 0x07, 0xA3, 0x6E, 0x01,
7298 0x00, 0x33, 0x0B, 0x00, 0xC2, 0x88, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33,
7299 0x1A, 0x00, 0xC2, 0x88, 0x50, 0x04, 0x88, 0x81, 0x06, 0xAB, 0x82, 0x01,
7300 0x88, 0x81, 0x4E, 0x00, 0x07, 0xA3, 0x92, 0x01, 0x50, 0x00, 0x00, 0xA3,
7301 0x3C, 0x01, 0x00, 0x05, 0x7C, 0x81, 0x46, 0x97, 0x02, 0x01, 0x05, 0xC6,
7302 0x04, 0x23, 0xA0, 0x01, 0x15, 0x23, 0xA1, 0x01, 0xBE, 0x81, 0xFD, 0x23,
7303 0x02, 0x61, 0x82, 0x01, 0x0A, 0xDA, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA0,
7304 0xB4, 0x01, 0x80, 0x63, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33, 0x1B, 0x00,
7305 0xC2, 0x88, 0x06, 0x23, 0x68, 0x98, 0xCD, 0x04, 0xE6, 0x84, 0x06, 0x01,
7306 0x00, 0xA2, 0xD4, 0x01, 0x57, 0x60, 0x00, 0xA0, 0xDA, 0x01, 0xE6, 0x84,
7307 0x80, 0x23, 0xA0, 0x01, 0xE6, 0x84, 0x80, 0x73, 0x4B, 0x00, 0x06, 0x61,
7308 0x00, 0xA2, 0x00, 0x02, 0x04, 0x01, 0x0C, 0xDE, 0x02, 0x01, 0x03, 0xCC,
7309 0x4F, 0x00, 0x84, 0x97, 0xFC, 0x81, 0x08, 0x23, 0x02, 0x41, 0x82, 0x01,
7310 0x4F, 0x00, 0x62, 0x97, 0x48, 0x04, 0x84, 0x80, 0xF0, 0x97, 0x00, 0x46,
7311 0x56, 0x00, 0x03, 0xC0, 0x01, 0x23, 0xE8, 0x00, 0x81, 0x73, 0x06, 0x29,
7312 0x03, 0x42, 0x06, 0xE2, 0x03, 0xEE, 0x6B, 0xEB, 0x11, 0x23, 0xF8, 0x88,
7313 0x04, 0x98, 0xF0, 0x80, 0x80, 0x73, 0x80, 0x77, 0x07, 0xA4, 0x2A, 0x02,
7314 0x7C, 0x95, 0x06, 0xA6, 0x34, 0x02, 0x03, 0xA6, 0x4C, 0x04, 0x46, 0x82,
7315 0x04, 0x01, 0x03, 0xD8, 0xB4, 0x98, 0x6A, 0x96, 0x46, 0x82, 0xFE, 0x95,
7316 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0xB6, 0x2D, 0x02, 0xA6, 0x6C, 0x02,
7317 0x07, 0xA6, 0x5A, 0x02, 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x62, 0x02,
7318 0xC2, 0x88, 0x7C, 0x95, 0x48, 0x82, 0x60, 0x96, 0x48, 0x82, 0x04, 0x23,
7319 0xA0, 0x01, 0x14, 0x23, 0xA1, 0x01, 0x3C, 0x84, 0x04, 0x01, 0x0C, 0xDC,
7320 0xE0, 0x23, 0x25, 0x61, 0xEF, 0x00, 0x14, 0x01, 0x4F, 0x04, 0xA8, 0x01,
7321 0x6F, 0x00, 0xA5, 0x01, 0x03, 0x23, 0xA4, 0x01, 0x06, 0x23, 0x9C, 0x01,
7322 0x24, 0x2B, 0x1C, 0x01, 0x02, 0xA6, 0xAA, 0x02, 0x07, 0xA6, 0x5A, 0x02,
7323 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x20, 0x04, 0x01, 0xA6, 0xB4, 0x02,
7324 0x00, 0xA6, 0xB4, 0x02, 0x00, 0x33, 0x12, 0x00, 0xC2, 0x88, 0x00, 0x0E,
7325 0x80, 0x63, 0x00, 0x43, 0x00, 0xA0, 0x8C, 0x02, 0x4D, 0x04, 0x04, 0x01,
7326 0x0B, 0xDC, 0xE7, 0x23, 0x04, 0x61, 0x84, 0x01, 0x10, 0x31, 0x12, 0x35,
7327 0x14, 0x01, 0xEC, 0x00, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0xEA, 0x82,
7328 0x18, 0x23, 0x04, 0x61, 0x18, 0xA0, 0xE2, 0x02, 0x04, 0x01, 0xA2, 0xC8,
7329 0x00, 0x33, 0x1F, 0x00, 0xC2, 0x88, 0x08, 0x31, 0x0A, 0x35, 0x0C, 0x39,
7330 0x0E, 0x3D, 0x7E, 0x98, 0xB6, 0x2D, 0x01, 0xA6, 0x14, 0x03, 0x00, 0xA6,
7331 0x14, 0x03, 0x07, 0xA6, 0x0C, 0x03, 0x06, 0xA6, 0x10, 0x03, 0x03, 0xA6,
7332 0x20, 0x04, 0x02, 0xA6, 0x6C, 0x02, 0x00, 0x33, 0x33, 0x00, 0xC2, 0x88,
7333 0x7C, 0x95, 0xEE, 0x82, 0x60, 0x96, 0xEE, 0x82, 0x82, 0x98, 0x80, 0x42,
7334 0x7E, 0x98, 0x64, 0xE4, 0x04, 0x01, 0x2D, 0xC8, 0x31, 0x05, 0x07, 0x01,
7335 0x00, 0xA2, 0x54, 0x03, 0x00, 0x43, 0x87, 0x01, 0x05, 0x05, 0x86, 0x98,
7336 0x7E, 0x98, 0x00, 0xA6, 0x16, 0x03, 0x07, 0xA6, 0x4C, 0x03, 0x03, 0xA6,
7337 0x3C, 0x04, 0x06, 0xA6, 0x50, 0x03, 0x01, 0xA6, 0x16, 0x03, 0x00, 0x33,
7338 0x25, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x32, 0x83, 0x60, 0x96, 0x32, 0x83,
7339 0x04, 0x01, 0x10, 0xCE, 0x07, 0xC8, 0x05, 0x05, 0xEB, 0x04, 0x00, 0x33,
7340 0x00, 0x20, 0xC0, 0x20, 0x81, 0x62, 0x72, 0x83, 0x00, 0x01, 0x05, 0x05,
7341 0xFF, 0xA2, 0x7A, 0x03, 0xB1, 0x01, 0x08, 0x23, 0xB2, 0x01, 0x2E, 0x83,
7342 0x05, 0x05, 0x15, 0x01, 0x00, 0xA2, 0x9A, 0x03, 0xEC, 0x00, 0x6E, 0x00,
7343 0x95, 0x01, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0x01, 0xA6, 0x96, 0x03,
7344 0x00, 0xA6, 0x96, 0x03, 0x10, 0x84, 0x80, 0x42, 0x7E, 0x98, 0x01, 0xA6,
7345 0xA4, 0x03, 0x00, 0xA6, 0xBC, 0x03, 0x10, 0x84, 0xA8, 0x98, 0x80, 0x42,
7346 0x01, 0xA6, 0xA4, 0x03, 0x07, 0xA6, 0xB2, 0x03, 0xD4, 0x83, 0x7C, 0x95,
7347 0xA8, 0x83, 0x00, 0x33, 0x2F, 0x00, 0xC2, 0x88, 0xA8, 0x98, 0x80, 0x42,
7348 0x00, 0xA6, 0xBC, 0x03, 0x07, 0xA6, 0xCA, 0x03, 0xD4, 0x83, 0x7C, 0x95,
7349 0xC0, 0x83, 0x00, 0x33, 0x26, 0x00, 0xC2, 0x88, 0x38, 0x2B, 0x80, 0x32,
7350 0x80, 0x36, 0x04, 0x23, 0xA0, 0x01, 0x12, 0x23, 0xA1, 0x01, 0x10, 0x84,
7351 0x07, 0xF0, 0x06, 0xA4, 0xF4, 0x03, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23,
7352 0x83, 0x03, 0x80, 0x63, 0x03, 0xA6, 0x0E, 0x04, 0x07, 0xA6, 0x06, 0x04,
7353 0x06, 0xA6, 0x0A, 0x04, 0x00, 0x33, 0x17, 0x00, 0xC2, 0x88, 0x7C, 0x95,
7354 0xF4, 0x83, 0x60, 0x96, 0xF4, 0x83, 0x20, 0x84, 0x07, 0xF0, 0x06, 0xA4,
7355 0x20, 0x04, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23, 0x83, 0x03, 0x80, 0x63,
7356 0xB6, 0x2D, 0x03, 0xA6, 0x3C, 0x04, 0x07, 0xA6, 0x34, 0x04, 0x06, 0xA6,
7357 0x38, 0x04, 0x00, 0x33, 0x30, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x20, 0x84,
7358 0x60, 0x96, 0x20, 0x84, 0x1D, 0x01, 0x06, 0xCC, 0x00, 0x33, 0x00, 0x84,
7359 0xC0, 0x20, 0x00, 0x23, 0xEA, 0x00, 0x81, 0x62, 0xA2, 0x0D, 0x80, 0x63,
7360 0x07, 0xA6, 0x5A, 0x04, 0x00, 0x33, 0x18, 0x00, 0xC2, 0x88, 0x03, 0x03,
7361 0x80, 0x63, 0xA3, 0x01, 0x07, 0xA4, 0x64, 0x04, 0x23, 0x01, 0x00, 0xA2,
7362 0x86, 0x04, 0x0A, 0xA0, 0x76, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1D, 0x00,
7363 0xC2, 0x88, 0x0B, 0xA0, 0x82, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1E, 0x00,
7364 0xC2, 0x88, 0x42, 0x23, 0xF8, 0x88, 0x00, 0x23, 0x22, 0xA3, 0xE6, 0x04,
7365 0x08, 0x23, 0x22, 0xA3, 0xA2, 0x04, 0x28, 0x23, 0x22, 0xA3, 0xAE, 0x04,
7366 0x02, 0x23, 0x22, 0xA3, 0xC4, 0x04, 0x42, 0x23, 0xF8, 0x88, 0x4A, 0x00,
7367 0x06, 0x61, 0x00, 0xA0, 0xAE, 0x04, 0x45, 0x23, 0xF8, 0x88, 0x04, 0x98,
7368 0x00, 0xA2, 0xC0, 0x04, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x82, 0xC0, 0x20,
7369 0x81, 0x62, 0xE8, 0x81, 0x47, 0x23, 0xF8, 0x88, 0x04, 0x01, 0x0B, 0xDE,
7370 0x04, 0x98, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x81, 0xC0, 0x20, 0x81, 0x62,
7371 0x14, 0x01, 0x00, 0xA0, 0x00, 0x02, 0x43, 0x23, 0xF8, 0x88, 0x04, 0x23,
7372 0xA0, 0x01, 0x44, 0x23, 0xA1, 0x01, 0x80, 0x73, 0x4D, 0x00, 0x03, 0xA3,
7373 0xF4, 0x04, 0x00, 0x33, 0x27, 0x00, 0xC2, 0x88, 0x04, 0x01, 0x04, 0xDC,
7374 0x02, 0x23, 0xA2, 0x01, 0x04, 0x23, 0xA0, 0x01, 0x04, 0x98, 0x26, 0x95,
7375 0x4B, 0x00, 0xF6, 0x00, 0x4F, 0x04, 0x4F, 0x00, 0x00, 0xA3, 0x22, 0x05,
7376 0x00, 0x05, 0x76, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x1C, 0x05, 0x0A, 0x85,
7377 0x46, 0x97, 0xCD, 0x04, 0x24, 0x85, 0x48, 0x04, 0x84, 0x80, 0x02, 0x01,
7378 0x03, 0xDA, 0x80, 0x23, 0x82, 0x01, 0x34, 0x85, 0x02, 0x23, 0xA0, 0x01,
7379 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x40, 0x05, 0x1D, 0x01, 0x04, 0xD6,
7380 0xFF, 0x23, 0x86, 0x41, 0x4B, 0x60, 0xCB, 0x00, 0xFF, 0x23, 0x80, 0x01,
7381 0x49, 0x00, 0x81, 0x01, 0x04, 0x01, 0x02, 0xC8, 0x30, 0x01, 0x80, 0x01,
7382 0xF7, 0x04, 0x03, 0x01, 0x49, 0x04, 0x80, 0x01, 0xC9, 0x00, 0x00, 0x05,
7383 0x00, 0x01, 0xFF, 0xA0, 0x60, 0x05, 0x77, 0x04, 0x01, 0x23, 0xEA, 0x00,
7384 0x5D, 0x00, 0xFE, 0xC7, 0x00, 0x62, 0x00, 0x23, 0xEA, 0x00, 0x00, 0x63,
7385 0x07, 0xA4, 0xF8, 0x05, 0x03, 0x03, 0x02, 0xA0, 0x8E, 0x05, 0xF4, 0x85,
7386 0x00, 0x33, 0x2D, 0x00, 0xC2, 0x88, 0x04, 0xA0, 0xB8, 0x05, 0x80, 0x63,
7387 0x00, 0x23, 0xDF, 0x00, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0xA4, 0x05,
7388 0x1D, 0x01, 0x06, 0xD6, 0x02, 0x23, 0x02, 0x41, 0x82, 0x01, 0x50, 0x00,
7389 0x62, 0x97, 0x04, 0x85, 0x04, 0x23, 0x02, 0x41, 0x82, 0x01, 0x04, 0x85,
7390 0x08, 0xA0, 0xBE, 0x05, 0xF4, 0x85, 0x03, 0xA0, 0xC4, 0x05, 0xF4, 0x85,
7391 0x01, 0xA0, 0xCE, 0x05, 0x88, 0x00, 0x80, 0x63, 0xCC, 0x86, 0x07, 0xA0,
7392 0xEE, 0x05, 0x5F, 0x00, 0x00, 0x2B, 0xDF, 0x08, 0x00, 0xA2, 0xE6, 0x05,
7393 0x80, 0x67, 0x80, 0x63, 0x01, 0xA2, 0x7A, 0x06, 0x7C, 0x85, 0x06, 0x23,
7394 0x68, 0x98, 0x48, 0x23, 0xF8, 0x88, 0x07, 0x23, 0x80, 0x00, 0x06, 0x87,
7395 0x80, 0x63, 0x7C, 0x85, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63, 0x4A, 0x00,
7396 0x06, 0x61, 0x00, 0xA2, 0x36, 0x06, 0x1D, 0x01, 0x16, 0xD4, 0xC0, 0x23,
7397 0x07, 0x41, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x1C, 0x06, 0x00, 0x33,
7398 0x37, 0x00, 0xC2, 0x88, 0x1D, 0x01, 0x01, 0xD6, 0x20, 0x23, 0x63, 0x60,
7399 0x83, 0x03, 0x80, 0x63, 0x02, 0x23, 0xDF, 0x00, 0x07, 0xA6, 0x7C, 0x05,
7400 0xEF, 0x04, 0x6F, 0x00, 0x00, 0x63, 0x4B, 0x00, 0x06, 0x41, 0xCB, 0x00,
7401 0x52, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x4E, 0x06, 0x1D, 0x01, 0x03, 0xCA,
7402 0xC0, 0x23, 0x07, 0x41, 0x00, 0x63, 0x1D, 0x01, 0x04, 0xCC, 0x00, 0x33,
7403 0x00, 0x83, 0xC0, 0x20, 0x81, 0x62, 0x80, 0x23, 0x07, 0x41, 0x00, 0x63,
7404 0x80, 0x67, 0x08, 0x23, 0x83, 0x03, 0x80, 0x63, 0x00, 0x63, 0x01, 0x23,
7405 0xDF, 0x00, 0x06, 0xA6, 0x84, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67,
7406 0x80, 0x63, 0x00, 0x33, 0x00, 0x40, 0xC0, 0x20, 0x81, 0x62, 0x00, 0x63,
7407 0x00, 0x00, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x94, 0x06,
7408 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x00, 0x01, 0xA0, 0x14, 0x07, 0x00, 0x2B,
7409 0x40, 0x0E, 0x80, 0x63, 0x01, 0x00, 0x06, 0xA6, 0xAA, 0x06, 0x07, 0xA6,
7410 0x7C, 0x05, 0x40, 0x0E, 0x80, 0x63, 0x00, 0x43, 0x00, 0xA0, 0xA2, 0x06,
7411 0x06, 0xA6, 0xBC, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67, 0x40, 0x0E,
7412 0x80, 0x63, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63,
7413 0x07, 0xA6, 0xD6, 0x06, 0x00, 0x33, 0x2A, 0x00, 0xC2, 0x88, 0x03, 0x03,
7414 0x80, 0x63, 0x89, 0x00, 0x0A, 0x2B, 0x07, 0xA6, 0xE8, 0x06, 0x00, 0x33,
7415 0x29, 0x00, 0xC2, 0x88, 0x00, 0x43, 0x00, 0xA2, 0xF4, 0x06, 0xC0, 0x0E,
7416 0x80, 0x63, 0xDE, 0x86, 0xC0, 0x0E, 0x00, 0x33, 0x00, 0x80, 0xC0, 0x20,
7417 0x81, 0x62, 0x04, 0x01, 0x02, 0xDA, 0x80, 0x63, 0x7C, 0x85, 0x80, 0x7B,
7418 0x80, 0x63, 0x06, 0xA6, 0x8C, 0x06, 0x00, 0x33, 0x2C, 0x00, 0xC2, 0x88,
7419 0x0C, 0xA2, 0x2E, 0x07, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6,
7420 0x2C, 0x07, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x33, 0x3D, 0x00, 0xC2, 0x88,
7421 0x00, 0x00, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0x0C, 0xA0, 0x44, 0x07,
7422 0x07, 0xA6, 0x7C, 0x05, 0xBF, 0x23, 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84,
7423 0x00, 0x63, 0xF0, 0x04, 0x01, 0x01, 0xF1, 0x00, 0x00, 0x01, 0xF2, 0x00,
7424 0x01, 0x05, 0x80, 0x01, 0x72, 0x04, 0x71, 0x00, 0x81, 0x01, 0x70, 0x04,
7425 0x80, 0x05, 0x81, 0x05, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04,
7426 0x01, 0x01, 0xF1, 0x00, 0x70, 0x00, 0x81, 0x01, 0x70, 0x04, 0x71, 0x00,
7427 0x81, 0x01, 0x72, 0x00, 0x80, 0x01, 0x71, 0x04, 0x70, 0x00, 0x80, 0x01,
7428 0x70, 0x04, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04, 0x00, 0x01,
7429 0xF1, 0x00, 0x70, 0x00, 0x80, 0x01, 0x70, 0x04, 0x71, 0x00, 0x80, 0x01,
7430 0x72, 0x00, 0x81, 0x01, 0x71, 0x04, 0x70, 0x00, 0x81, 0x01, 0x70, 0x04,
7431 0x00, 0x63, 0x00, 0x23, 0xB3, 0x01, 0x83, 0x05, 0xA3, 0x01, 0xA2, 0x01,
7432 0xA1, 0x01, 0x01, 0x23, 0xA0, 0x01, 0x00, 0x01, 0xC8, 0x00, 0x03, 0xA1,
7433 0xC4, 0x07, 0x00, 0x33, 0x07, 0x00, 0xC2, 0x88, 0x80, 0x05, 0x81, 0x05,
7434 0x04, 0x01, 0x11, 0xC8, 0x48, 0x00, 0xB0, 0x01, 0xB1, 0x01, 0x08, 0x23,
7435 0xB2, 0x01, 0x05, 0x01, 0x48, 0x04, 0x00, 0x43, 0x00, 0xA2, 0xE4, 0x07,
7436 0x00, 0x05, 0xDA, 0x87, 0x00, 0x01, 0xC8, 0x00, 0xFF, 0x23, 0x80, 0x01,
7437 0x05, 0x05, 0x00, 0x63, 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04,
7438 0x00, 0x02, 0x80, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04, 0x00, 0x63,
7439 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04, 0x00, 0x02, 0x00, 0xA0,
7440 0x14, 0x08, 0x16, 0x88, 0x00, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04,
7441 0x00, 0x63, 0xF3, 0x04, 0x00, 0x23, 0xF4, 0x00, 0x74, 0x00, 0x80, 0x43,
7442 0xF4, 0x00, 0xCF, 0x40, 0x00, 0xA2, 0x44, 0x08, 0x74, 0x04, 0x02, 0x01,
7443 0xF7, 0xC9, 0xF6, 0xD9, 0x00, 0x01, 0x01, 0xA1, 0x24, 0x08, 0x04, 0x98,
7444 0x26, 0x95, 0x24, 0x88, 0x73, 0x04, 0x00, 0x63, 0xF3, 0x04, 0x75, 0x04,
7445 0x5A, 0x88, 0x02, 0x01, 0x04, 0xD8, 0x46, 0x97, 0x04, 0x98, 0x26, 0x95,
7446 0x4A, 0x88, 0x75, 0x00, 0x00, 0xA3, 0x64, 0x08, 0x00, 0x05, 0x4E, 0x88,
7447 0x73, 0x04, 0x00, 0x63, 0x80, 0x7B, 0x80, 0x63, 0x06, 0xA6, 0x76, 0x08,
7448 0x00, 0x33, 0x3E, 0x00, 0xC2, 0x88, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63,
7449 0x00, 0x63, 0x38, 0x2B, 0x9C, 0x88, 0x38, 0x2B, 0x92, 0x88, 0x32, 0x09,
7450 0x31, 0x05, 0x92, 0x98, 0x05, 0x05, 0xB2, 0x09, 0x00, 0x63, 0x00, 0x32,
7451 0x00, 0x36, 0x00, 0x3A, 0x00, 0x3E, 0x00, 0x63, 0x80, 0x32, 0x80, 0x36,
7452 0x80, 0x3A, 0x80, 0x3E, 0xB4, 0x3D, 0x00, 0x63, 0x38, 0x2B, 0x40, 0x32,
7453 0x40, 0x36, 0x40, 0x3A, 0x40, 0x3E, 0x00, 0x63, 0x5A, 0x20, 0xC9, 0x40,
7454 0x00, 0xA0, 0xB4, 0x08, 0x5D, 0x00, 0xFE, 0xC3, 0x00, 0x63, 0x80, 0x73,
7455 0xE6, 0x20, 0x02, 0x23, 0xE8, 0x00, 0x82, 0x73, 0xFF, 0xFD, 0x80, 0x73,
7456 0x13, 0x23, 0xF8, 0x88, 0x66, 0x20, 0xC0, 0x20, 0x04, 0x23, 0xA0, 0x01,
7457 0xA1, 0x23, 0xA1, 0x01, 0x81, 0x62, 0xE2, 0x88, 0x80, 0x73, 0x80, 0x77,
7458 0x68, 0x00, 0x00, 0xA2, 0x80, 0x00, 0x03, 0xC2, 0xF1, 0xC7, 0x41, 0x23,
7459 0xF8, 0x88, 0x11, 0x23, 0xA1, 0x01, 0x04, 0x23, 0xA0, 0x01, 0xE6, 0x84,
7462 static ushort _asc_mcode_size = sizeof(_asc_mcode_buf);
7463 static ADV_DCNT _asc_mcode_chksum = 0x012C453FUL;
7465 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
7466 static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
7485 static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
7490 int disable_syn_offset_one_fix;
7493 ushort sg_entry_cnt = 0;
7494 ushort sg_entry_cnt_minus_one = 0;
7501 ASC_SG_HEAD *sg_head;
7504 iop_base = asc_dvc->iop_base;
7505 sg_head = scsiq->sg_head;
7506 if (asc_dvc->err_code != 0)
7509 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
7510 scsiq->q1.extra_bytes = 0;
7513 target_ix = scsiq->q2.target_ix;
7514 tid_no = ASC_TIX_TO_TID(target_ix);
7516 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
7517 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
7518 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
7519 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
7520 AscMsgOutSDTR(asc_dvc,
7522 sdtr_period_tbl[(sdtr_data >> 4) &
7526 (uchar)(sdtr_data & (uchar)
7527 ASC_SYN_MAX_OFFSET));
7528 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
7531 if (asc_dvc->in_critical_cnt != 0) {
7532 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
7535 asc_dvc->in_critical_cnt++;
7536 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
7537 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
7538 asc_dvc->in_critical_cnt--;
7541 #if !CC_VERY_LONG_SG_LIST
7542 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
7543 asc_dvc->in_critical_cnt--;
7546 #endif /* !CC_VERY_LONG_SG_LIST */
7547 if (sg_entry_cnt == 1) {
7548 scsiq->q1.data_addr =
7549 (ADV_PADDR)sg_head->sg_list[0].addr;
7550 scsiq->q1.data_cnt =
7551 (ADV_DCNT)sg_head->sg_list[0].bytes;
7552 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
7554 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
7556 scsi_cmd = scsiq->cdbptr[0];
7557 disable_syn_offset_one_fix = FALSE;
7558 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
7559 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
7560 if (scsiq->q1.cntl & QC_SG_HEAD) {
7562 for (i = 0; i < sg_entry_cnt; i++) {
7564 (ADV_DCNT)le32_to_cpu(sg_head->sg_list[i].
7568 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
7570 if (data_cnt != 0UL) {
7571 if (data_cnt < 512UL) {
7572 disable_syn_offset_one_fix = TRUE;
7574 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
7577 _syn_offset_one_disable_cmd[i];
7578 if (disable_cmd == 0xFF) {
7581 if (scsi_cmd == disable_cmd) {
7582 disable_syn_offset_one_fix =
7590 if (disable_syn_offset_one_fix) {
7591 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
7592 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
7593 ASC_TAG_FLAG_DISABLE_DISCONNECT);
7595 scsiq->q2.tag_code &= 0x27;
7597 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
7598 if (asc_dvc->bug_fix_cntl) {
7599 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
7600 if ((scsi_cmd == READ_6) ||
7601 (scsi_cmd == READ_10)) {
7603 (ADV_PADDR)le32_to_cpu(sg_head->
7605 [sg_entry_cnt_minus_one].
7607 (ADV_DCNT)le32_to_cpu(sg_head->
7609 [sg_entry_cnt_minus_one].
7612 (uchar)((ushort)addr & 0x0003);
7613 if ((extra_bytes != 0)
7617 ASC_TAG_FLAG_EXTRA_BYTES)
7619 scsiq->q2.tag_code |=
7620 ASC_TAG_FLAG_EXTRA_BYTES;
7621 scsiq->q1.extra_bytes =
7624 le32_to_cpu(sg_head->
7626 [sg_entry_cnt_minus_one].
7629 (ASC_DCNT) extra_bytes;
7632 [sg_entry_cnt_minus_one].
7634 cpu_to_le32(data_cnt);
7639 sg_head->entry_to_copy = sg_head->entry_cnt;
7640 #if CC_VERY_LONG_SG_LIST
7642 * Set the sg_entry_cnt to the maximum possible. The rest of
7643 * the SG elements will be copied when the RISC completes the
7644 * SG elements that fit and halts.
7646 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
7647 sg_entry_cnt = ASC_MAX_SG_LIST;
7649 #endif /* CC_VERY_LONG_SG_LIST */
7650 n_q_required = AscSgListToQueue(sg_entry_cnt);
7651 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
7652 (uint) n_q_required)
7653 || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
7655 AscSendScsiQueue(asc_dvc, scsiq,
7656 n_q_required)) == 1) {
7657 asc_dvc->in_critical_cnt--;
7662 if (asc_dvc->bug_fix_cntl) {
7663 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
7664 if ((scsi_cmd == READ_6) ||
7665 (scsi_cmd == READ_10)) {
7667 le32_to_cpu(scsiq->q1.data_addr) +
7668 le32_to_cpu(scsiq->q1.data_cnt);
7670 (uchar)((ushort)addr & 0x0003);
7671 if ((extra_bytes != 0)
7675 ASC_TAG_FLAG_EXTRA_BYTES)
7678 le32_to_cpu(scsiq->q1.
7680 if (((ushort)data_cnt & 0x01FF)
7682 scsiq->q2.tag_code |=
7683 ASC_TAG_FLAG_EXTRA_BYTES;
7684 data_cnt -= (ASC_DCNT)
7686 scsiq->q1.data_cnt =
7689 scsiq->q1.extra_bytes =
7697 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
7698 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
7699 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
7700 n_q_required)) == 1) {
7701 asc_dvc->in_critical_cnt--;
7706 asc_dvc->in_critical_cnt--;
7711 AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
7720 iop_base = asc_dvc->iop_base;
7721 target_ix = scsiq->q2.target_ix;
7722 tid_no = ASC_TIX_TO_TID(target_ix);
7724 free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
7725 if (n_q_required > 1) {
7726 if ((next_qp = AscAllocMultipleFreeQueue(iop_base,
7727 free_q_head, (uchar)
7729 != (uchar)ASC_QLINK_END) {
7730 asc_dvc->last_q_shortage = 0;
7731 scsiq->sg_head->queue_cnt = n_q_required - 1;
7732 scsiq->q1.q_no = free_q_head;
7733 if ((sta = AscPutReadySgListQueue(asc_dvc, scsiq,
7734 free_q_head)) == 1) {
7735 AscPutVarFreeQHead(iop_base, next_qp);
7736 asc_dvc->cur_total_qng += (uchar)(n_q_required);
7737 asc_dvc->cur_dvc_qng[tid_no]++;
7741 } else if (n_q_required == 1) {
7742 if ((next_qp = AscAllocFreeQueue(iop_base,
7745 scsiq->q1.q_no = free_q_head;
7746 if ((sta = AscPutReadyQueue(asc_dvc, scsiq,
7747 free_q_head)) == 1) {
7748 AscPutVarFreeQHead(iop_base, next_qp);
7749 asc_dvc->cur_total_qng++;
7750 asc_dvc->cur_dvc_qng[tid_no]++;
7758 static int AscSgListToQueue(int sg_list)
7762 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
7763 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
7765 return (n_sg_list_qs + 1);
7769 AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
7773 ASC_SCSI_BIT_ID_TYPE target_id;
7776 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
7777 tid_no = ASC_TIX_TO_TID(target_ix);
7778 if ((asc_dvc->unit_not_ready & target_id) ||
7779 (asc_dvc->queue_full_or_busy & target_id)) {
7783 cur_used_qs = (uint) asc_dvc->cur_total_qng +
7784 (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
7786 cur_used_qs = (uint) asc_dvc->cur_total_qng +
7787 (uint) ASC_MIN_FREE_Q;
7789 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
7790 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
7791 if (asc_dvc->cur_dvc_qng[tid_no] >=
7792 asc_dvc->max_dvc_qng[tid_no]) {
7795 return (cur_free_qs);
7798 if ((n_qs > asc_dvc->last_q_shortage)
7799 && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
7800 asc_dvc->last_q_shortage = n_qs;
7806 static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
7811 uchar syn_period_ix;
7815 iop_base = asc_dvc->iop_base;
7816 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
7817 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
7818 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
7819 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
7821 (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
7822 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
7823 AscMsgOutSDTR(asc_dvc,
7824 asc_dvc->sdtr_period_tbl[syn_period_ix],
7826 scsiq->q1.cntl |= QC_MSG_OUT;
7828 q_addr = ASC_QNO_TO_QADDR(q_no);
7829 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
7830 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
7832 scsiq->q1.status = QS_FREE;
7833 AscMemWordCopyPtrToLram(iop_base,
7834 q_addr + ASC_SCSIQ_CDB_BEG,
7835 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
7837 DvcPutScsiQ(iop_base,
7838 q_addr + ASC_SCSIQ_CPY_BEG,
7839 (uchar *)&scsiq->q1.cntl,
7840 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
7841 AscWriteLramWord(iop_base,
7842 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
7843 (ushort)(((ushort)scsiq->q1.
7844 q_no << 8) | (ushort)QS_READY));
7849 AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
7853 ASC_SG_HEAD *sg_head;
7854 ASC_SG_LIST_Q scsi_sg_q;
7855 ASC_DCNT saved_data_addr;
7856 ASC_DCNT saved_data_cnt;
7858 ushort sg_list_dwords;
7860 ushort sg_entry_cnt;
7864 iop_base = asc_dvc->iop_base;
7865 sg_head = scsiq->sg_head;
7866 saved_data_addr = scsiq->q1.data_addr;
7867 saved_data_cnt = scsiq->q1.data_cnt;
7868 scsiq->q1.data_addr = (ASC_PADDR) sg_head->sg_list[0].addr;
7869 scsiq->q1.data_cnt = (ASC_DCNT) sg_head->sg_list[0].bytes;
7870 #if CC_VERY_LONG_SG_LIST
7872 * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
7873 * then not all SG elements will fit in the allocated queues.
7874 * The rest of the SG elements will be copied when the RISC
7875 * completes the SG elements that fit and halts.
7877 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
7879 * Set sg_entry_cnt to be the number of SG elements that
7880 * will fit in the allocated SG queues. It is minus 1, because
7881 * the first SG element is handled above. ASC_MAX_SG_LIST is
7882 * already inflated by 1 to account for this. For example it
7883 * may be 50 which is 1 + 7 queues * 7 SG elements.
7885 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
7888 * Keep track of remaining number of SG elements that will
7889 * need to be handled from a_isr.c.
7891 scsiq->remain_sg_entry_cnt =
7892 sg_head->entry_cnt - ASC_MAX_SG_LIST;
7894 #endif /* CC_VERY_LONG_SG_LIST */
7896 * Set sg_entry_cnt to be the number of SG elements that
7897 * will fit in the allocated SG queues. It is minus 1, because
7898 * the first SG element is handled above.
7900 sg_entry_cnt = sg_head->entry_cnt - 1;
7901 #if CC_VERY_LONG_SG_LIST
7903 #endif /* CC_VERY_LONG_SG_LIST */
7904 if (sg_entry_cnt != 0) {
7905 scsiq->q1.cntl |= QC_SG_HEAD;
7906 q_addr = ASC_QNO_TO_QADDR(q_no);
7908 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
7909 scsi_sg_q.sg_head_qp = q_no;
7910 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
7911 for (i = 0; i < sg_head->queue_cnt; i++) {
7912 scsi_sg_q.seq_no = i + 1;
7913 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
7914 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
7915 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
7917 scsi_sg_q.sg_list_cnt =
7919 scsi_sg_q.sg_cur_list_cnt =
7922 scsi_sg_q.sg_list_cnt =
7923 ASC_SG_LIST_PER_Q - 1;
7924 scsi_sg_q.sg_cur_list_cnt =
7925 ASC_SG_LIST_PER_Q - 1;
7928 #if CC_VERY_LONG_SG_LIST
7930 * This is the last SG queue in the list of
7931 * allocated SG queues. If there are more
7932 * SG elements than will fit in the allocated
7933 * queues, then set the QCSG_SG_XFER_MORE flag.
7935 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
7936 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
7938 #endif /* CC_VERY_LONG_SG_LIST */
7939 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
7940 #if CC_VERY_LONG_SG_LIST
7942 #endif /* CC_VERY_LONG_SG_LIST */
7943 sg_list_dwords = sg_entry_cnt << 1;
7945 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
7946 scsi_sg_q.sg_cur_list_cnt =
7949 scsi_sg_q.sg_list_cnt =
7951 scsi_sg_q.sg_cur_list_cnt =
7956 next_qp = AscReadLramByte(iop_base,
7959 scsi_sg_q.q_no = next_qp;
7960 q_addr = ASC_QNO_TO_QADDR(next_qp);
7961 AscMemWordCopyPtrToLram(iop_base,
7962 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
7963 (uchar *)&scsi_sg_q,
7964 sizeof(ASC_SG_LIST_Q) >> 1);
7965 AscMemDWordCopyPtrToLram(iop_base,
7966 q_addr + ASC_SGQ_LIST_BEG,
7970 sg_index += ASC_SG_LIST_PER_Q;
7971 scsiq->next_sg_index = sg_index;
7974 scsiq->q1.cntl &= ~QC_SG_HEAD;
7976 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
7977 scsiq->q1.data_addr = saved_data_addr;
7978 scsiq->q1.data_cnt = saved_data_cnt;
7983 AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
7987 if (AscHostReqRiscHalt(iop_base)) {
7988 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
7989 AscStartChip(iop_base);
7995 static int AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
7997 ASC_SCSI_BIT_ID_TYPE org_id;
8001 AscSetBank(iop_base, 1);
8002 org_id = AscReadChipDvcID(iop_base);
8003 for (i = 0; i <= ASC_MAX_TID; i++) {
8004 if (org_id == (0x01 << i))
8007 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
8008 AscWriteChipDvcID(iop_base, id);
8009 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
8010 AscSetBank(iop_base, 0);
8011 AscSetChipSyn(iop_base, sdtr_data);
8012 if (AscGetChipSyn(iop_base) != sdtr_data) {
8018 AscSetBank(iop_base, 1);
8019 AscWriteChipDvcID(iop_base, org_id);
8020 AscSetBank(iop_base, 0);
8024 static ushort AscInitLram(ASC_DVC_VAR *asc_dvc)
8031 iop_base = asc_dvc->iop_base;
8033 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
8034 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
8037 i = ASC_MIN_ACTIVE_QNO;
8038 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
8039 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
8041 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
8042 (uchar)(asc_dvc->max_total_qng));
8043 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
8046 s_addr += ASC_QBLK_SIZE;
8047 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
8048 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
8050 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
8052 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
8055 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
8056 (uchar)ASC_QLINK_END);
8057 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
8058 (uchar)(asc_dvc->max_total_qng - 1));
8059 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
8060 (uchar)asc_dvc->max_total_qng);
8062 s_addr += ASC_QBLK_SIZE;
8063 for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
8064 i++, s_addr += ASC_QBLK_SIZE) {
8065 AscWriteLramByte(iop_base,
8066 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
8067 AscWriteLramByte(iop_base,
8068 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
8069 AscWriteLramByte(iop_base,
8070 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
8075 static ushort AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
8081 iop_base = asc_dvc->iop_base;
8082 AscPutRiscVarFreeQHead(iop_base, 1);
8083 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
8084 AscPutVarFreeQHead(iop_base, 1);
8085 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
8086 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
8087 (uchar)((int)asc_dvc->max_total_qng + 1));
8088 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
8089 (uchar)((int)asc_dvc->max_total_qng + 2));
8090 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
8091 asc_dvc->max_total_qng);
8092 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
8093 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8094 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
8095 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
8096 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
8097 AscPutQDoneInProgress(iop_base, 0);
8098 lram_addr = ASC_QADR_BEG;
8099 for (i = 0; i < 32; i++, lram_addr += 2) {
8100 AscWriteLramWord(iop_base, lram_addr, 0);
8105 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
8107 if (asc_dvc->err_code == 0) {
8108 asc_dvc->err_code = err_code;
8109 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
8116 AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
8119 uchar sdtr_period_index;
8122 iop_base = asc_dvc->iop_base;
8123 sdtr_buf.msg_type = EXTENDED_MESSAGE;
8124 sdtr_buf.msg_len = MS_SDTR_LEN;
8125 sdtr_buf.msg_req = EXTENDED_SDTR;
8126 sdtr_buf.xfer_period = sdtr_period;
8127 sdtr_offset &= ASC_SYN_MAX_OFFSET;
8128 sdtr_buf.req_ack_offset = sdtr_offset;
8129 if ((sdtr_period_index =
8130 AscGetSynPeriodIndex(asc_dvc, sdtr_period)) <=
8131 asc_dvc->max_sdtr_index) {
8132 AscMemWordCopyPtrToLram(iop_base,
8135 sizeof(EXT_MSG) >> 1);
8136 return ((sdtr_period_index << 4) | sdtr_offset);
8139 sdtr_buf.req_ack_offset = 0;
8140 AscMemWordCopyPtrToLram(iop_base,
8143 sizeof(EXT_MSG) >> 1);
8149 AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
8152 uchar sdtr_period_ix;
8154 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
8155 if ((sdtr_period_ix > asc_dvc->max_sdtr_index)
8159 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
8163 static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
8165 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
8166 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
8170 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
8172 uchar *period_table;
8177 period_table = asc_dvc->sdtr_period_tbl;
8178 max_index = (int)asc_dvc->max_sdtr_index;
8179 min_index = (int)asc_dvc->host_init_sdtr_index;
8180 if ((syn_time <= period_table[max_index])) {
8181 for (i = min_index; i < (max_index - 1); i++) {
8182 if (syn_time <= period_table[i]) {
8186 return ((uchar)max_index);
8188 return ((uchar)(max_index + 1));
8192 static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
8198 q_addr = ASC_QNO_TO_QADDR(free_q_head);
8199 q_status = (uchar)AscReadLramByte(iop_base,
8201 ASC_SCSIQ_B_STATUS));
8202 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
8203 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END)) {
8206 return (ASC_QLINK_END);
8210 AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
8214 for (i = 0; i < n_free_q; i++) {
8215 if ((free_q_head = AscAllocFreeQueue(iop_base, free_q_head))
8217 return (ASC_QLINK_END);
8220 return (free_q_head);
8223 static int AscHostReqRiscHalt(PortAddr iop_base)
8227 uchar saved_stop_code;
8229 if (AscIsChipHalted(iop_base))
8231 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
8232 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
8233 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
8235 if (AscIsChipHalted(iop_base)) {
8240 } while (count++ < 20);
8241 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
8245 static int AscStopQueueExe(PortAddr iop_base)
8249 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
8250 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
8251 ASC_STOP_REQ_RISC_STOP);
8253 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
8254 ASC_STOP_ACK_RISC_STOP) {
8258 } while (count++ < 20);
8263 static int AscStartChip(PortAddr iop_base)
8265 AscSetChipControl(iop_base, 0);
8266 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
8272 static int AscStopChip(PortAddr iop_base)
8277 AscGetChipControl(iop_base) &
8278 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
8279 AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
8280 AscSetChipIH(iop_base, INS_HALT);
8281 AscSetChipIH(iop_base, INS_RFLAG_WTM);
8282 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
8288 static int AscIsChipHalted(PortAddr iop_base)
8290 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
8291 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
8298 static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
8300 AscSetBank(iop_base, 1);
8301 AscWriteChipIH(iop_base, ins_code);
8302 AscSetBank(iop_base, 0);
8306 static void AscAckInterrupt(PortAddr iop_base)
8314 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
8315 if (loop++ > 0x7FFF) {
8318 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
8320 AscReadLramByte(iop_base,
8321 ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
8322 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
8323 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
8324 AscSetChipStatus(iop_base, CIW_INT_ACK);
8326 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
8327 AscSetChipStatus(iop_base, CIW_INT_ACK);
8332 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
8336 static void AscDisableInterrupt(PortAddr iop_base)
8340 cfg = AscGetChipCfgLsw(iop_base);
8341 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
8345 static void AscEnableInterrupt(PortAddr iop_base)
8349 cfg = AscGetChipCfgLsw(iop_base);
8350 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
8354 static void AscSetBank(PortAddr iop_base, uchar bank)
8358 val = AscGetChipControl(iop_base) &
8360 (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
8364 } else if (bank == 2) {
8365 val |= CC_DIAG | CC_BANK_ONE;
8367 val &= ~CC_BANK_ONE;
8369 AscSetChipControl(iop_base, val);
8373 static int AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
8378 iop_base = asc_dvc->iop_base;
8379 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
8383 AscStopChip(iop_base);
8384 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
8386 AscSetChipIH(iop_base, INS_RFLAG_WTM);
8387 AscSetChipIH(iop_base, INS_HALT);
8388 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
8389 AscSetChipControl(iop_base, CC_HALT);
8391 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
8392 AscSetChipStatus(iop_base, 0);
8393 return (AscIsChipHalted(iop_base));
8396 static ASC_DCNT __devinit AscGetMaxDmaCount(ushort bus_type)
8398 if (bus_type & ASC_IS_ISA)
8399 return (ASC_MAX_ISA_DMA_COUNT);
8400 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
8401 return (ASC_MAX_VL_DMA_COUNT);
8402 return (ASC_MAX_PCI_DMA_COUNT);
8406 static ushort __devinit AscGetIsaDmaChannel(PortAddr iop_base)
8410 channel = AscGetChipCfgLsw(iop_base) & 0x0003;
8411 if (channel == 0x03)
8413 else if (channel == 0x00)
8415 return (channel + 4);
8418 static ushort __devinit AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
8423 if ((dma_channel >= 5) && (dma_channel <= 7)) {
8424 if (dma_channel == 7)
8427 value = dma_channel - 4;
8428 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
8430 AscSetChipCfgLsw(iop_base, cfg_lsw);
8431 return (AscGetIsaDmaChannel(iop_base));
8436 static uchar __devinit AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
8438 speed_value &= 0x07;
8439 AscSetBank(iop_base, 1);
8440 AscWriteChipDmaSpeed(iop_base, speed_value);
8441 AscSetBank(iop_base, 0);
8442 return (AscGetIsaDmaSpeed(iop_base));
8445 static uchar __devinit AscGetIsaDmaSpeed(PortAddr iop_base)
8449 AscSetBank(iop_base, 1);
8450 speed_value = AscReadChipDmaSpeed(iop_base);
8451 speed_value &= 0x07;
8452 AscSetBank(iop_base, 0);
8453 return (speed_value);
8455 #endif /* CONFIG_ISA */
8457 static int __devinit AscInitGetConfig(asc_board_t *boardp)
8459 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
8460 unsigned short warn_code = 0;
8462 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
8463 if (asc_dvc->err_code != 0)
8464 return asc_dvc->err_code;
8466 if (AscFindSignature(asc_dvc->iop_base)) {
8467 warn_code |= AscInitAscDvcVar(asc_dvc);
8468 warn_code |= AscInitFromEEP(asc_dvc);
8469 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
8470 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
8471 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
8473 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
8476 switch (warn_code) {
8477 case 0: /* No error */
8479 case ASC_WARN_IO_PORT_ROTATE:
8480 ASC_PRINT1("AscInitGetConfig: board %d: I/O port address "
8481 "modified\n", boardp->id);
8483 case ASC_WARN_AUTO_CONFIG:
8484 ASC_PRINT1("AscInitGetConfig: board %d: I/O port increment "
8485 "switch enabled\n", boardp->id);
8487 case ASC_WARN_EEPROM_CHKSUM:
8488 ASC_PRINT1("AscInitGetConfig: board %d: EEPROM checksum "
8489 "error\n", boardp->id);
8491 case ASC_WARN_IRQ_MODIFIED:
8492 ASC_PRINT1("AscInitGetConfig: board %d: IRQ modified\n",
8495 case ASC_WARN_CMD_QNG_CONFLICT:
8496 ASC_PRINT1("AscInitGetConfig: board %d: tag queuing enabled "
8497 "w/o disconnects\n", boardp->id);
8500 ASC_PRINT2("AscInitGetConfig: board %d: unknown warning: "
8501 "0x%x\n", boardp->id, warn_code);
8505 if (asc_dvc->err_code != 0) {
8506 ASC_PRINT3("AscInitGetConfig: board %d error: init_state 0x%x, "
8507 "err_code 0x%x\n", boardp->id, asc_dvc->init_state,
8511 return asc_dvc->err_code;
8514 static int __devinit AscInitSetConfig(struct pci_dev *pdev, asc_board_t *boardp)
8516 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
8517 PortAddr iop_base = asc_dvc->iop_base;
8518 unsigned short cfg_msw;
8519 unsigned short warn_code = 0;
8521 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
8522 if (asc_dvc->err_code != 0)
8523 return asc_dvc->err_code;
8524 if (!AscFindSignature(asc_dvc->iop_base)) {
8525 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
8526 return asc_dvc->err_code;
8529 cfg_msw = AscGetChipCfgMsw(iop_base);
8530 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
8531 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
8532 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
8533 AscSetChipCfgMsw(iop_base, cfg_msw);
8535 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
8536 asc_dvc->cfg->cmd_qng_enabled) {
8537 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
8538 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
8540 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
8541 warn_code |= ASC_WARN_AUTO_CONFIG;
8543 if ((asc_dvc->bus_type & (ASC_IS_ISA | ASC_IS_VL)) != 0) {
8544 if (AscSetChipIRQ(iop_base, asc_dvc->irq_no, asc_dvc->bus_type)
8545 != asc_dvc->irq_no) {
8546 asc_dvc->err_code |= ASC_IERR_SET_IRQ_NO;
8550 if (asc_dvc->bus_type & ASC_IS_PCI) {
8552 AscSetChipCfgMsw(iop_base, cfg_msw);
8553 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
8555 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
8556 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
8557 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
8558 asc_dvc->bug_fix_cntl |=
8559 ASC_BUG_FIX_ASYN_USE_SYN;
8563 #endif /* CONFIG_PCI */
8564 if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
8565 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
8566 == ASC_CHIP_VER_ASYN_BUG) {
8567 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
8570 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
8571 asc_dvc->cfg->chip_scsi_id) {
8572 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
8575 if (asc_dvc->bus_type & ASC_IS_ISA) {
8576 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
8577 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
8579 #endif /* CONFIG_ISA */
8581 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
8583 switch (warn_code) {
8584 case 0: /* No error. */
8586 case ASC_WARN_IO_PORT_ROTATE:
8587 ASC_PRINT1("AscInitSetConfig: board %d: I/O port address "
8588 "modified\n", boardp->id);
8590 case ASC_WARN_AUTO_CONFIG:
8591 ASC_PRINT1("AscInitSetConfig: board %d: I/O port increment "
8592 "switch enabled\n", boardp->id);
8594 case ASC_WARN_EEPROM_CHKSUM:
8595 ASC_PRINT1("AscInitSetConfig: board %d: EEPROM checksum "
8596 "error\n", boardp->id);
8598 case ASC_WARN_IRQ_MODIFIED:
8599 ASC_PRINT1("AscInitSetConfig: board %d: IRQ modified\n",
8602 case ASC_WARN_CMD_QNG_CONFLICT:
8603 ASC_PRINT1("AscInitSetConfig: board %d: tag queuing w/o "
8608 ASC_PRINT2("AscInitSetConfig: board %d: unknown warning: "
8609 "0x%x\n", boardp->id, warn_code);
8613 if (asc_dvc->err_code != 0) {
8614 ASC_PRINT3("AscInitSetConfig: board %d error: init_state 0x%x, "
8615 "err_code 0x%x\n", boardp->id, asc_dvc->init_state,
8619 return asc_dvc->err_code;
8622 static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
8627 iop_base = asc_dvc->iop_base;
8629 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
8630 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
8631 AscResetChipAndScsiBus(asc_dvc);
8632 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
8634 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
8635 if (asc_dvc->err_code != 0)
8637 if (!AscFindSignature(asc_dvc->iop_base)) {
8638 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
8641 AscDisableInterrupt(iop_base);
8642 warn_code |= AscInitLram(asc_dvc);
8643 if (asc_dvc->err_code != 0)
8645 ASC_DBG1(1, "AscInitAsc1000Driver: _asc_mcode_chksum 0x%lx\n",
8646 (ulong)_asc_mcode_chksum);
8647 if (AscLoadMicroCode(iop_base, 0, _asc_mcode_buf,
8648 _asc_mcode_size) != _asc_mcode_chksum) {
8649 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
8652 warn_code |= AscInitMicroCodeVar(asc_dvc);
8653 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
8654 AscEnableInterrupt(iop_base);
8658 static ushort __devinit AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
8665 iop_base = asc_dvc->iop_base;
8667 asc_dvc->err_code = 0;
8668 if ((asc_dvc->bus_type &
8669 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
8670 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
8672 AscSetChipControl(iop_base, CC_HALT);
8673 AscSetChipStatus(iop_base, 0);
8674 asc_dvc->bug_fix_cntl = 0;
8675 asc_dvc->pci_fix_asyn_xfer = 0;
8676 asc_dvc->pci_fix_asyn_xfer_always = 0;
8677 /* asc_dvc->init_state initalized in AscInitGetConfig(). */
8678 asc_dvc->sdtr_done = 0;
8679 asc_dvc->cur_total_qng = 0;
8680 asc_dvc->is_in_int = 0;
8681 asc_dvc->in_critical_cnt = 0;
8682 asc_dvc->last_q_shortage = 0;
8683 asc_dvc->use_tagged_qng = 0;
8684 asc_dvc->no_scam = 0;
8685 asc_dvc->unit_not_ready = 0;
8686 asc_dvc->queue_full_or_busy = 0;
8687 asc_dvc->redo_scam = 0;
8689 asc_dvc->host_init_sdtr_index = 0;
8690 asc_dvc->cfg->can_tagged_qng = 0;
8691 asc_dvc->cfg->cmd_qng_enabled = 0;
8692 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
8693 asc_dvc->init_sdtr = 0;
8694 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
8695 asc_dvc->scsi_reset_wait = 3;
8696 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
8697 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
8698 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
8699 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
8700 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
8701 asc_dvc->cfg->lib_serial_no = ASC_LIB_SERIAL_NUMBER;
8702 asc_dvc->cfg->lib_version = (ASC_LIB_VERSION_MAJOR << 8) |
8703 ASC_LIB_VERSION_MINOR;
8704 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
8705 asc_dvc->cfg->chip_version = chip_version;
8706 asc_dvc->sdtr_period_tbl[0] = SYN_XFER_NS_0;
8707 asc_dvc->sdtr_period_tbl[1] = SYN_XFER_NS_1;
8708 asc_dvc->sdtr_period_tbl[2] = SYN_XFER_NS_2;
8709 asc_dvc->sdtr_period_tbl[3] = SYN_XFER_NS_3;
8710 asc_dvc->sdtr_period_tbl[4] = SYN_XFER_NS_4;
8711 asc_dvc->sdtr_period_tbl[5] = SYN_XFER_NS_5;
8712 asc_dvc->sdtr_period_tbl[6] = SYN_XFER_NS_6;
8713 asc_dvc->sdtr_period_tbl[7] = SYN_XFER_NS_7;
8714 asc_dvc->max_sdtr_index = 7;
8715 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
8716 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
8717 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
8718 asc_dvc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0;
8719 asc_dvc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1;
8720 asc_dvc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2;
8721 asc_dvc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3;
8722 asc_dvc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4;
8723 asc_dvc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5;
8724 asc_dvc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6;
8725 asc_dvc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7;
8726 asc_dvc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8;
8727 asc_dvc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9;
8728 asc_dvc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10;
8729 asc_dvc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11;
8730 asc_dvc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12;
8731 asc_dvc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13;
8732 asc_dvc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14;
8733 asc_dvc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15;
8734 asc_dvc->max_sdtr_index = 15;
8735 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
8736 AscSetExtraControl(iop_base,
8737 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
8738 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
8739 AscSetExtraControl(iop_base,
8740 (SEC_ACTIVE_NEGATE |
8741 SEC_ENABLE_FILTER));
8744 if (asc_dvc->bus_type == ASC_IS_PCI) {
8745 AscSetExtraControl(iop_base,
8746 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
8749 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
8751 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
8752 if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) {
8753 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
8754 asc_dvc->bus_type = ASC_IS_ISAPNP;
8756 asc_dvc->cfg->isa_dma_channel =
8757 (uchar)AscGetIsaDmaChannel(iop_base);
8759 #endif /* CONFIG_ISA */
8760 for (i = 0; i <= ASC_MAX_TID; i++) {
8761 asc_dvc->cur_dvc_qng[i] = 0;
8762 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
8763 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
8764 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
8765 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
8770 static ushort __devinit AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
8772 ASCEEP_CONFIG eep_config_buf;
8773 ASCEEP_CONFIG *eep_config;
8777 ushort cfg_msw, cfg_lsw;
8781 iop_base = asc_dvc->iop_base;
8783 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
8784 AscStopQueueExe(iop_base);
8785 if ((AscStopChip(iop_base) == FALSE) ||
8786 (AscGetChipScsiCtrl(iop_base) != 0)) {
8787 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
8788 AscResetChipAndScsiBus(asc_dvc);
8789 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
8791 if (AscIsChipHalted(iop_base) == FALSE) {
8792 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
8795 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
8796 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
8797 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
8800 eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
8801 cfg_msw = AscGetChipCfgMsw(iop_base);
8802 cfg_lsw = AscGetChipCfgLsw(iop_base);
8803 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
8804 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
8805 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
8806 AscSetChipCfgMsw(iop_base, cfg_msw);
8808 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
8809 ASC_DBG1(1, "AscInitFromEEP: chksum 0x%x\n", chksum);
8813 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
8814 warn_code |= ASC_WARN_AUTO_CONFIG;
8815 if (asc_dvc->cfg->chip_version == 3) {
8816 if (eep_config->cfg_lsw != cfg_lsw) {
8817 warn_code |= ASC_WARN_EEPROM_RECOVER;
8818 eep_config->cfg_lsw =
8819 AscGetChipCfgLsw(iop_base);
8821 if (eep_config->cfg_msw != cfg_msw) {
8822 warn_code |= ASC_WARN_EEPROM_RECOVER;
8823 eep_config->cfg_msw =
8824 AscGetChipCfgMsw(iop_base);
8828 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
8829 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
8830 ASC_DBG1(1, "AscInitFromEEP: eep_config->chksum 0x%x\n",
8831 eep_config->chksum);
8832 if (chksum != eep_config->chksum) {
8833 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
8834 ASC_CHIP_VER_PCI_ULTRA_3050) {
8836 "AscInitFromEEP: chksum error ignored; EEPROM-less board\n");
8837 eep_config->init_sdtr = 0xFF;
8838 eep_config->disc_enable = 0xFF;
8839 eep_config->start_motor = 0xFF;
8840 eep_config->use_cmd_qng = 0;
8841 eep_config->max_total_qng = 0xF0;
8842 eep_config->max_tag_qng = 0x20;
8843 eep_config->cntl = 0xBFFF;
8844 ASC_EEP_SET_CHIP_ID(eep_config, 7);
8845 eep_config->no_scam = 0;
8846 eep_config->adapter_info[0] = 0;
8847 eep_config->adapter_info[1] = 0;
8848 eep_config->adapter_info[2] = 0;
8849 eep_config->adapter_info[3] = 0;
8850 eep_config->adapter_info[4] = 0;
8851 /* Indicate EEPROM-less board. */
8852 eep_config->adapter_info[5] = 0xBB;
8855 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
8857 warn_code |= ASC_WARN_EEPROM_CHKSUM;
8860 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
8861 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
8862 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
8863 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
8864 asc_dvc->start_motor = eep_config->start_motor;
8865 asc_dvc->dvc_cntl = eep_config->cntl;
8866 asc_dvc->no_scam = eep_config->no_scam;
8867 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
8868 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
8869 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
8870 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
8871 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
8872 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
8873 if (!AscTestExternalLram(asc_dvc)) {
8874 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
8875 ASC_IS_PCI_ULTRA)) {
8876 eep_config->max_total_qng =
8877 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
8878 eep_config->max_tag_qng =
8879 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
8881 eep_config->cfg_msw |= 0x0800;
8883 AscSetChipCfgMsw(iop_base, cfg_msw);
8884 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
8885 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
8889 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
8890 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
8892 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
8893 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
8895 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
8896 eep_config->max_tag_qng = eep_config->max_total_qng;
8898 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
8899 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
8901 asc_dvc->max_total_qng = eep_config->max_total_qng;
8902 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
8903 eep_config->use_cmd_qng) {
8904 eep_config->disc_enable = eep_config->use_cmd_qng;
8905 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
8907 if (asc_dvc->bus_type & (ASC_IS_ISA | ASC_IS_VL | ASC_IS_EISA)) {
8908 asc_dvc->irq_no = AscGetChipIRQ(iop_base, asc_dvc->bus_type);
8910 ASC_EEP_SET_CHIP_ID(eep_config,
8911 ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
8912 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
8913 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
8914 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
8915 asc_dvc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
8918 for (i = 0; i <= ASC_MAX_TID; i++) {
8919 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
8920 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
8921 asc_dvc->cfg->sdtr_period_offset[i] =
8922 (uchar)(ASC_DEF_SDTR_OFFSET |
8923 (asc_dvc->host_init_sdtr_index << 4));
8925 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
8928 AscSetEEPConfig(iop_base, eep_config,
8929 asc_dvc->bus_type)) != 0) {
8931 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
8935 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
8941 static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
8949 iop_base = asc_dvc->iop_base;
8951 for (i = 0; i <= ASC_MAX_TID; i++) {
8952 AscPutMCodeInitSDTRAtID(iop_base, i,
8953 asc_dvc->cfg->sdtr_period_offset[i]
8957 AscInitQLinkVar(asc_dvc);
8958 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
8959 asc_dvc->cfg->disc_enable);
8960 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
8961 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
8963 /* Align overrun buffer on an 8 byte boundary. */
8964 phy_addr = virt_to_bus(asc_dvc->cfg->overrun_buf);
8965 phy_addr = cpu_to_le32((phy_addr + 7) & ~0x7);
8966 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
8967 (uchar *)&phy_addr, 1);
8968 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE - 8);
8969 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
8970 (uchar *)&phy_size, 1);
8972 asc_dvc->cfg->mcode_date =
8973 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
8974 asc_dvc->cfg->mcode_version =
8975 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
8977 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
8978 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
8979 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
8982 if (AscStartChip(iop_base) != 1) {
8983 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
8990 static int __devinit AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
8997 iop_base = asc_dvc->iop_base;
8999 q_addr = ASC_QNO_TO_QADDR(241);
9000 saved_word = AscReadLramWord(iop_base, q_addr);
9001 AscSetChipLramAddr(iop_base, q_addr);
9002 AscSetChipLramData(iop_base, 0x55AA);
9004 AscSetChipLramAddr(iop_base, q_addr);
9005 if (AscGetChipLramData(iop_base) == 0x55AA) {
9007 AscWriteLramWord(iop_base, q_addr, saved_word);
9012 static int __devinit AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
9019 AscSetChipEEPCmd(iop_base, cmd_reg);
9021 read_back = AscGetChipEEPCmd(iop_base);
9022 if (read_back == cmd_reg) {
9025 if (retry++ > ASC_EEP_MAX_RETRY) {
9031 static int __devinit AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
9038 AscSetChipEEPData(iop_base, data_reg);
9040 read_back = AscGetChipEEPData(iop_base);
9041 if (read_back == data_reg) {
9044 if (retry++ > ASC_EEP_MAX_RETRY) {
9050 static void __devinit AscWaitEEPRead(void)
9056 static void __devinit AscWaitEEPWrite(void)
9062 static ushort __devinit AscReadEEPWord(PortAddr iop_base, uchar addr)
9067 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9069 cmd_reg = addr | ASC_EEP_CMD_READ;
9070 AscWriteEEPCmdReg(iop_base, cmd_reg);
9072 read_wval = AscGetChipEEPData(iop_base);
9077 static ushort __devinit
9078 AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
9082 read_wval = AscReadEEPWord(iop_base, addr);
9083 if (read_wval != word_val) {
9084 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
9086 AscWriteEEPDataReg(iop_base, word_val);
9088 AscWriteEEPCmdReg(iop_base,
9089 (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
9091 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9093 return (AscReadEEPWord(iop_base, addr));
9098 static ushort __devinit
9099 AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
9106 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9109 wbuf = (ushort *)cfg_buf;
9111 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
9112 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9113 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
9116 if (bus_type & ASC_IS_VL) {
9117 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9118 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9120 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9121 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9123 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9124 wval = AscReadEEPWord(iop_base, (uchar)s_addr);
9125 if (s_addr <= uchar_end_in_config) {
9127 * Swap all char fields - must unswap bytes already swapped
9128 * by AscReadEEPWord().
9130 *wbuf = le16_to_cpu(wval);
9132 /* Don't swap word field at the end - cntl field. */
9135 sum += wval; /* Checksum treats all EEPROM data as words. */
9138 * Read the checksum word which will be compared against 'sum'
9139 * by the caller. Word field already swapped.
9141 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
9145 static int __devinit
9146 AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
9155 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9157 wbuf = (ushort *)cfg_buf;
9160 /* Write two config words; AscWriteEEPWord() will swap bytes. */
9161 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9163 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9167 if (bus_type & ASC_IS_VL) {
9168 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9169 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9171 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9172 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9174 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9175 if (s_addr <= uchar_end_in_config) {
9177 * This is a char field. Swap char fields before they are
9178 * swapped again by AscWriteEEPWord().
9180 word = cpu_to_le16(*wbuf);
9182 AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
9186 /* Don't swap word field at the end - cntl field. */
9188 AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9192 sum += *wbuf; /* Checksum calculated from word values. */
9194 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
9196 if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
9200 /* Read EEPROM back again. */
9201 wbuf = (ushort *)cfg_buf;
9203 * Read two config words; Byte-swapping done by AscReadEEPWord().
9205 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9206 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
9210 if (bus_type & ASC_IS_VL) {
9211 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9212 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9214 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9215 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9217 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9218 if (s_addr <= uchar_end_in_config) {
9220 * Swap all char fields. Must unswap bytes already swapped
9221 * by AscReadEEPWord().
9224 le16_to_cpu(AscReadEEPWord
9225 (iop_base, (uchar)s_addr));
9227 /* Don't swap word field at the end - cntl field. */
9228 word = AscReadEEPWord(iop_base, (uchar)s_addr);
9230 if (*wbuf != word) {
9234 /* Read checksum; Byte swapping not needed. */
9235 if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
9241 static int __devinit
9242 AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
9249 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
9253 if (++retry > ASC_EEP_MAX_RETRY) {
9260 static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
9262 char type = sdev->type;
9263 ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
9265 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN) {
9266 if (!(asc_dvc->init_sdtr & tid_bits)) {
9267 if ((type == TYPE_ROM) &&
9268 (strncmp(sdev->vendor, "HP ", 3) == 0)) {
9269 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
9271 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
9272 if ((type == TYPE_PROCESSOR) ||
9273 (type == TYPE_SCANNER) || (type == TYPE_ROM) ||
9274 (type == TYPE_TAPE)) {
9275 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
9278 if (asc_dvc->pci_fix_asyn_xfer & tid_bits) {
9279 AscSetRunChipSynRegAtID(asc_dvc->iop_base,
9281 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
9287 static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
9292 if (isodd_word(addr)) {
9293 AscSetChipLramAddr(iop_base, addr - 1);
9294 word_data = AscGetChipLramData(iop_base);
9295 byte_data = (uchar)((word_data >> 8) & 0xFF);
9297 AscSetChipLramAddr(iop_base, addr);
9298 word_data = AscGetChipLramData(iop_base);
9299 byte_data = (uchar)(word_data & 0xFF);
9304 static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
9308 AscSetChipLramAddr(iop_base, addr);
9309 word_data = AscGetChipLramData(iop_base);
9313 #if CC_VERY_LONG_SG_LIST
9314 static ASC_DCNT AscReadLramDWord(PortAddr iop_base, ushort addr)
9316 ushort val_low, val_high;
9317 ASC_DCNT dword_data;
9319 AscSetChipLramAddr(iop_base, addr);
9320 val_low = AscGetChipLramData(iop_base);
9321 val_high = AscGetChipLramData(iop_base);
9322 dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
9323 return (dword_data);
9325 #endif /* CC_VERY_LONG_SG_LIST */
9327 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
9329 AscSetChipLramAddr(iop_base, addr);
9330 AscSetChipLramData(iop_base, word_val);
9334 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
9338 if (isodd_word(addr)) {
9340 word_data = AscReadLramWord(iop_base, addr);
9341 word_data &= 0x00FF;
9342 word_data |= (((ushort)byte_val << 8) & 0xFF00);
9344 word_data = AscReadLramWord(iop_base, addr);
9345 word_data &= 0xFF00;
9346 word_data |= ((ushort)byte_val & 0x00FF);
9348 AscWriteLramWord(iop_base, addr, word_data);
9353 * Copy 2 bytes to LRAM.
9355 * The source data is assumed to be in little-endian order in memory
9356 * and is maintained in little-endian order when written to LRAM.
9359 AscMemWordCopyPtrToLram(PortAddr iop_base,
9360 ushort s_addr, uchar *s_buffer, int words)
9364 AscSetChipLramAddr(iop_base, s_addr);
9365 for (i = 0; i < 2 * words; i += 2) {
9367 * On a little-endian system the second argument below
9368 * produces a little-endian ushort which is written to
9369 * LRAM in little-endian order. On a big-endian system
9370 * the second argument produces a big-endian ushort which
9371 * is "transparently" byte-swapped by outpw() and written
9372 * in little-endian order to LRAM.
9374 outpw(iop_base + IOP_RAM_DATA,
9375 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
9381 * Copy 4 bytes to LRAM.
9383 * The source data is assumed to be in little-endian order in memory
9384 * and is maintained in little-endian order when writen to LRAM.
9387 AscMemDWordCopyPtrToLram(PortAddr iop_base,
9388 ushort s_addr, uchar *s_buffer, int dwords)
9392 AscSetChipLramAddr(iop_base, s_addr);
9393 for (i = 0; i < 4 * dwords; i += 4) {
9394 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
9395 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
9401 * Copy 2 bytes from LRAM.
9403 * The source data is assumed to be in little-endian order in LRAM
9404 * and is maintained in little-endian order when written to memory.
9407 AscMemWordCopyPtrFromLram(PortAddr iop_base,
9408 ushort s_addr, uchar *d_buffer, int words)
9413 AscSetChipLramAddr(iop_base, s_addr);
9414 for (i = 0; i < 2 * words; i += 2) {
9415 word = inpw(iop_base + IOP_RAM_DATA);
9416 d_buffer[i] = word & 0xff;
9417 d_buffer[i + 1] = (word >> 8) & 0xff;
9422 static ASC_DCNT AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
9428 for (i = 0; i < words; i++, s_addr += 2) {
9429 sum += AscReadLramWord(iop_base, s_addr);
9435 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
9439 AscSetChipLramAddr(iop_base, s_addr);
9440 for (i = 0; i < words; i++) {
9441 AscSetChipLramData(iop_base, set_wval);
9447 * --- Adv Library Functions
9452 /* Microcode buffer is kept after initialization for error recovery. */
9453 static unsigned char _adv_asc3550_buf[] = {
9454 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0x16, 0x18, 0xe4, 0x00, 0xfc,
9455 0x01, 0x00, 0x48, 0xe4, 0xbe, 0x18, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00,
9456 0x00, 0xfa, 0xff, 0xff, 0x28, 0x0e, 0x9e, 0xe7, 0xff, 0x00, 0x82, 0xe7,
9457 0x00, 0xea, 0x00, 0xf6, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0, 0x01, 0xf6,
9458 0x01, 0xfa, 0x08, 0x00, 0x03, 0x00, 0x04, 0x00, 0x18, 0xf4, 0x10, 0x00,
9459 0x00, 0xec, 0x85, 0xf0, 0xbc, 0x00, 0xd5, 0xf0, 0x8e, 0x0c, 0x38, 0x54,
9460 0x00, 0xe6, 0x1e, 0xf0, 0x86, 0xf0, 0xb4, 0x00, 0x98, 0x57, 0xd0, 0x01,
9461 0x0c, 0x1c, 0x3e, 0x1c, 0x0c, 0x00, 0xbb, 0x00, 0xaa, 0x18, 0x02, 0x80,
9462 0x32, 0xf0, 0x01, 0xfc, 0x88, 0x0c, 0xc6, 0x12, 0x02, 0x13, 0x18, 0x40,
9463 0x00, 0x57, 0x01, 0xea, 0x3c, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12,
9464 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01,
9465 0x3e, 0x01, 0xda, 0x0f, 0x22, 0x10, 0x08, 0x12, 0x02, 0x4a, 0xb9, 0x54,
9466 0x03, 0x58, 0x1b, 0x80, 0x30, 0xe4, 0x4b, 0xe4, 0x20, 0x00, 0x32, 0x00,
9467 0x3e, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01,
9468 0x70, 0x01, 0x72, 0x01, 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x62, 0x0a,
9469 0x92, 0x0c, 0x2c, 0x10, 0x2e, 0x10, 0x06, 0x13, 0x4c, 0x1c, 0xbb, 0x55,
9470 0x3c, 0x56, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0, 0xb1, 0xf0,
9471 0x03, 0xf7, 0x06, 0xf7, 0x03, 0xfc, 0x0f, 0x00, 0x40, 0x00, 0xbe, 0x00,
9472 0x00, 0x01, 0xb0, 0x08, 0x30, 0x13, 0x64, 0x15, 0x32, 0x1c, 0x38, 0x1c,
9473 0x4e, 0x1c, 0x10, 0x44, 0x02, 0x48, 0x00, 0x4c, 0x04, 0xea, 0x5d, 0xf0,
9474 0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00,
9475 0xcc, 0x00, 0x20, 0x01, 0x4e, 0x01, 0x4e, 0x0b, 0x1e, 0x0e, 0x0c, 0x10,
9476 0x0a, 0x12, 0x04, 0x13, 0x40, 0x13, 0x30, 0x1c, 0x00, 0x4e, 0xbd, 0x56,
9477 0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xa7, 0xf0,
9478 0xb8, 0xf0, 0x0e, 0xf7, 0x06, 0x00, 0x19, 0x00, 0x33, 0x00, 0x9b, 0x00,
9479 0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00,
9480 0xde, 0x03, 0x56, 0x0a, 0x14, 0x0e, 0x02, 0x10, 0x04, 0x10, 0x0a, 0x10,
9481 0x36, 0x10, 0x0a, 0x13, 0x12, 0x13, 0x52, 0x13, 0x10, 0x15, 0x14, 0x15,
9482 0xac, 0x16, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44, 0x38, 0x44,
9483 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x83, 0x55,
9484 0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x05, 0xe6, 0x0b, 0xf0, 0x0c, 0xf0,
9485 0x5c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8, 0x05, 0xf8, 0x02, 0xfa, 0x03, 0xfa,
9486 0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00, 0x0a, 0x00, 0x0d, 0x00, 0x1c, 0x00,
9487 0x9e, 0x00, 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00, 0x22, 0x01,
9488 0x26, 0x01, 0x79, 0x01, 0x7a, 0x01, 0xc0, 0x01, 0xc2, 0x01, 0x7c, 0x02,
9489 0x5a, 0x03, 0xea, 0x04, 0xe8, 0x07, 0x68, 0x08, 0x69, 0x08, 0xba, 0x08,
9490 0xe9, 0x09, 0x06, 0x0b, 0x3a, 0x0e, 0x00, 0x10, 0x1a, 0x10, 0xed, 0x10,
9491 0xf1, 0x10, 0x06, 0x12, 0x0c, 0x13, 0x16, 0x13, 0x1e, 0x13, 0x82, 0x13,
9492 0x42, 0x14, 0xd6, 0x14, 0x8a, 0x15, 0xc6, 0x17, 0xd2, 0x17, 0x6b, 0x18,
9493 0x12, 0x1c, 0x46, 0x1c, 0x9c, 0x32, 0x00, 0x40, 0x0e, 0x47, 0x48, 0x47,
9494 0x41, 0x48, 0x89, 0x48, 0x80, 0x4c, 0x00, 0x54, 0x44, 0x55, 0xe5, 0x55,
9495 0x14, 0x56, 0x77, 0x57, 0xbf, 0x57, 0x40, 0x5c, 0x06, 0x80, 0x08, 0x90,
9496 0x03, 0xa1, 0xfe, 0x9c, 0xf0, 0x29, 0x02, 0xfe, 0xb8, 0x0c, 0xff, 0x10,
9497 0x00, 0x00, 0xd0, 0xfe, 0xcc, 0x18, 0x00, 0xcf, 0xfe, 0x80, 0x01, 0xff,
9498 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00,
9499 0x00, 0xfe, 0x57, 0x24, 0x00, 0xfe, 0x48, 0x00, 0x4f, 0xff, 0x04, 0x00,
9500 0x00, 0x10, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08, 0x01, 0x01, 0xff, 0x08,
9501 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x0f,
9502 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00,
9503 0xfe, 0x04, 0xf7, 0xcf, 0x2a, 0x67, 0x0b, 0x01, 0xfe, 0xce, 0x0e, 0xfe,
9504 0x04, 0xf7, 0xcf, 0x67, 0x0b, 0x3c, 0x2a, 0xfe, 0x3d, 0xf0, 0xfe, 0x02,
9505 0x02, 0xfe, 0x20, 0xf0, 0x9c, 0xfe, 0x91, 0xf0, 0xfe, 0xf0, 0x01, 0xfe,
9506 0x90, 0xf0, 0xfe, 0xf0, 0x01, 0xfe, 0x8f, 0xf0, 0x9c, 0x05, 0x51, 0x3b,
9507 0x02, 0xfe, 0xd4, 0x0c, 0x01, 0xfe, 0x44, 0x0d, 0xfe, 0xdd, 0x12, 0xfe,
9508 0xfc, 0x10, 0xfe, 0x28, 0x1c, 0x05, 0xfe, 0xa6, 0x00, 0xfe, 0xd3, 0x12,
9509 0x47, 0x18, 0xfe, 0xa6, 0x00, 0xb5, 0xfe, 0x48, 0xf0, 0xfe, 0x86, 0x02,
9510 0xfe, 0x49, 0xf0, 0xfe, 0xa0, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xbe, 0x02,
9511 0xfe, 0x46, 0xf0, 0xfe, 0x50, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x56, 0x02,
9512 0xfe, 0x43, 0xf0, 0xfe, 0x44, 0x02, 0xfe, 0x44, 0xf0, 0xfe, 0x48, 0x02,
9513 0xfe, 0x45, 0xf0, 0xfe, 0x4c, 0x02, 0x17, 0x0b, 0xa0, 0x17, 0x06, 0x18,
9514 0x96, 0x02, 0x29, 0xfe, 0x00, 0x1c, 0xde, 0xfe, 0x02, 0x1c, 0xdd, 0xfe,
9515 0x1e, 0x1c, 0xfe, 0xe9, 0x10, 0x01, 0xfe, 0x20, 0x17, 0xfe, 0xe7, 0x10,
9516 0xfe, 0x06, 0xfc, 0xc7, 0x0a, 0x6b, 0x01, 0x9e, 0x02, 0x29, 0x14, 0x4d,
9517 0x37, 0x97, 0x01, 0xfe, 0x64, 0x0f, 0x0a, 0x6b, 0x01, 0x82, 0xfe, 0xbd,
9518 0x10, 0x0a, 0x6b, 0x01, 0x82, 0xfe, 0xad, 0x10, 0xfe, 0x16, 0x1c, 0xfe,
9519 0x58, 0x1c, 0x17, 0x06, 0x18, 0x96, 0x2a, 0x25, 0x29, 0xfe, 0x3d, 0xf0,
9520 0xfe, 0x02, 0x02, 0x21, 0xfe, 0x94, 0x02, 0xfe, 0x5a, 0x1c, 0xea, 0xfe,
9521 0x14, 0x1c, 0x14, 0xfe, 0x30, 0x00, 0x37, 0x97, 0x01, 0xfe, 0x54, 0x0f,
9522 0x17, 0x06, 0x18, 0x96, 0x02, 0xd0, 0x1e, 0x20, 0x07, 0x10, 0x34, 0xfe,
9523 0x69, 0x10, 0x17, 0x06, 0x18, 0x96, 0xfe, 0x04, 0xec, 0x20, 0x46, 0x3d,
9524 0x12, 0x20, 0xfe, 0x05, 0xf6, 0xc7, 0x01, 0xfe, 0x52, 0x16, 0x09, 0x4a,
9525 0x4c, 0x35, 0x11, 0x2d, 0x3c, 0x8a, 0x01, 0xe6, 0x02, 0x29, 0x0a, 0x40,
9526 0x01, 0x0e, 0x07, 0x00, 0x5d, 0x01, 0x6f, 0xfe, 0x18, 0x10, 0xfe, 0x41,
9527 0x58, 0x0a, 0x99, 0x01, 0x0e, 0xfe, 0xc8, 0x54, 0x64, 0xfe, 0x0c, 0x03,
9528 0x01, 0xe6, 0x02, 0x29, 0x2a, 0x46, 0xfe, 0x02, 0xe8, 0x27, 0xf8, 0xfe,
9529 0x9e, 0x43, 0xf7, 0xfe, 0x27, 0xf0, 0xfe, 0xdc, 0x01, 0xfe, 0x07, 0x4b,
9530 0xfe, 0x20, 0xf0, 0x9c, 0xfe, 0x40, 0x1c, 0x25, 0xd2, 0xfe, 0x26, 0xf0,
9531 0xfe, 0x56, 0x03, 0xfe, 0xa0, 0xf0, 0xfe, 0x44, 0x03, 0xfe, 0x11, 0xf0,
9532 0x9c, 0xfe, 0xef, 0x10, 0xfe, 0x9f, 0xf0, 0xfe, 0x64, 0x03, 0xeb, 0x0f,
9533 0xfe, 0x11, 0x00, 0x02, 0x5a, 0x2a, 0xfe, 0x48, 0x1c, 0xeb, 0x09, 0x04,
9534 0x1d, 0xfe, 0x18, 0x13, 0x23, 0x1e, 0x98, 0xac, 0x12, 0x98, 0x0a, 0x40,
9535 0x01, 0x0e, 0xac, 0x75, 0x01, 0xfe, 0xbc, 0x15, 0x11, 0xca, 0x25, 0xd2,
9536 0xfe, 0x01, 0xf0, 0xd2, 0xfe, 0x82, 0xf0, 0xfe, 0x92, 0x03, 0xec, 0x11,
9537 0xfe, 0xe4, 0x00, 0x65, 0xfe, 0xa4, 0x03, 0x25, 0x32, 0x1f, 0xfe, 0xb4,
9538 0x03, 0x01, 0x43, 0xfe, 0x06, 0xf0, 0xfe, 0xc4, 0x03, 0x8d, 0x81, 0xfe,
9539 0x0a, 0xf0, 0xfe, 0x7a, 0x06, 0x02, 0x22, 0x05, 0x6b, 0x28, 0x16, 0xfe,
9540 0xf6, 0x04, 0x14, 0x2c, 0x01, 0x33, 0x8f, 0xfe, 0x66, 0x02, 0x02, 0xd1,
9541 0xeb, 0x2a, 0x67, 0x1a, 0xfe, 0x67, 0x1b, 0xf8, 0xf7, 0xfe, 0x48, 0x1c,
9542 0x70, 0x01, 0x6e, 0x87, 0x0a, 0x40, 0x01, 0x0e, 0x07, 0x00, 0x16, 0xd3,
9543 0x0a, 0xca, 0x01, 0x0e, 0x74, 0x60, 0x59, 0x76, 0x27, 0x05, 0x6b, 0x28,
9544 0xfe, 0x10, 0x12, 0x14, 0x2c, 0x01, 0x33, 0x8f, 0xfe, 0x66, 0x02, 0x02,
9545 0xd1, 0xbc, 0x7d, 0xbd, 0x7f, 0x25, 0x22, 0x65, 0xfe, 0x3c, 0x04, 0x1f,
9546 0xfe, 0x38, 0x04, 0x68, 0xfe, 0xa0, 0x00, 0xfe, 0x9b, 0x57, 0xfe, 0x4e,
9547 0x12, 0x2b, 0xff, 0x02, 0x00, 0x10, 0x01, 0x08, 0x1f, 0xfe, 0xe0, 0x04,
9548 0x2b, 0x01, 0x08, 0x1f, 0x22, 0x30, 0x2e, 0xd5, 0xfe, 0x4c, 0x44, 0xfe,
9549 0x4c, 0x12, 0x60, 0xfe, 0x44, 0x48, 0x13, 0x2c, 0xfe, 0x4c, 0x54, 0x64,
9550 0xd3, 0x46, 0x76, 0x27, 0xfa, 0xef, 0xfe, 0x62, 0x13, 0x09, 0x04, 0x1d,
9551 0xfe, 0x2a, 0x13, 0x2f, 0x07, 0x7e, 0xa5, 0xfe, 0x20, 0x10, 0x13, 0x2c,
9552 0xfe, 0x4c, 0x54, 0x64, 0xd3, 0xfa, 0xef, 0x86, 0x09, 0x04, 0x1d, 0xfe,
9553 0x08, 0x13, 0x2f, 0x07, 0x7e, 0x6e, 0x09, 0x04, 0x1d, 0xfe, 0x1c, 0x12,
9554 0x14, 0x92, 0x09, 0x04, 0x06, 0x3b, 0x14, 0xc4, 0x01, 0x33, 0x8f, 0xfe,
9555 0x70, 0x0c, 0x02, 0x22, 0x2b, 0x11, 0xfe, 0xe6, 0x00, 0xfe, 0x1c, 0x90,
9556 0xf9, 0x03, 0x14, 0x92, 0x01, 0x33, 0x02, 0x29, 0xfe, 0x42, 0x5b, 0x67,
9557 0x1a, 0xfe, 0x46, 0x59, 0xf8, 0xf7, 0xfe, 0x87, 0x80, 0xfe, 0x31, 0xe4,
9558 0x4f, 0x09, 0x04, 0x0b, 0xfe, 0x78, 0x13, 0xfe, 0x20, 0x80, 0x07, 0x1a,
9559 0xfe, 0x70, 0x12, 0x49, 0x04, 0x06, 0xfe, 0x60, 0x13, 0x05, 0xfe, 0xa2,
9560 0x00, 0x28, 0x16, 0xfe, 0x80, 0x05, 0xfe, 0x31, 0xe4, 0x6a, 0x49, 0x04,
9561 0x0b, 0xfe, 0x4a, 0x13, 0x05, 0xfe, 0xa0, 0x00, 0x28, 0xfe, 0x42, 0x12,
9562 0x5e, 0x01, 0x08, 0x25, 0x32, 0xf1, 0x01, 0x08, 0x26, 0xfe, 0x98, 0x05,
9563 0x11, 0xfe, 0xe3, 0x00, 0x23, 0x49, 0xfe, 0x4a, 0xf0, 0xfe, 0x6a, 0x05,
9564 0xfe, 0x49, 0xf0, 0xfe, 0x64, 0x05, 0x83, 0x24, 0xfe, 0x21, 0x00, 0xa1,
9565 0x24, 0xfe, 0x22, 0x00, 0xa0, 0x24, 0x4c, 0xfe, 0x09, 0x48, 0x01, 0x08,
9566 0x26, 0xfe, 0x98, 0x05, 0xfe, 0xe2, 0x08, 0x49, 0x04, 0xc5, 0x3b, 0x01,
9567 0x86, 0x24, 0x06, 0x12, 0xcc, 0x37, 0xfe, 0x27, 0x01, 0x09, 0x04, 0x1d,
9568 0xfe, 0x22, 0x12, 0x47, 0x01, 0xa7, 0x14, 0x92, 0x09, 0x04, 0x06, 0x3b,
9569 0x14, 0xc4, 0x01, 0x33, 0x8f, 0xfe, 0x70, 0x0c, 0x02, 0x22, 0x05, 0xfe,
9570 0x9c, 0x00, 0x28, 0xfe, 0x3e, 0x12, 0x05, 0x50, 0x28, 0xfe, 0x36, 0x13,
9571 0x47, 0x01, 0xa7, 0x26, 0xfe, 0x08, 0x06, 0x0a, 0x06, 0x49, 0x04, 0x19,
9572 0xfe, 0x02, 0x12, 0x5f, 0x01, 0xfe, 0xaa, 0x14, 0x1f, 0xfe, 0xfe, 0x05,
9573 0x11, 0x9a, 0x01, 0x43, 0x11, 0xfe, 0xe5, 0x00, 0x05, 0x50, 0xb4, 0x0c,
9574 0x50, 0x05, 0xc6, 0x28, 0xfe, 0x62, 0x12, 0x05, 0x3f, 0x28, 0xfe, 0x5a,
9575 0x13, 0x01, 0xfe, 0x14, 0x18, 0x01, 0xfe, 0x66, 0x18, 0xfe, 0x43, 0x48,
9576 0xb7, 0x19, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0x1c, 0x3d,
9577 0x85, 0xb7, 0x69, 0x47, 0x01, 0xa7, 0x26, 0xfe, 0x72, 0x06, 0x49, 0x04,
9578 0x1b, 0xdf, 0x89, 0x0a, 0x4d, 0x01, 0xfe, 0xd8, 0x14, 0x1f, 0xfe, 0x68,
9579 0x06, 0x11, 0x9a, 0x01, 0x43, 0x11, 0xfe, 0xe5, 0x00, 0x05, 0x3f, 0xb4,
9580 0x0c, 0x3f, 0x17, 0x06, 0x01, 0xa7, 0xec, 0x72, 0x70, 0x01, 0x6e, 0x87,
9581 0x11, 0xfe, 0xe2, 0x00, 0x01, 0x08, 0x25, 0x32, 0xfe, 0x0a, 0xf0, 0xfe,
9582 0xa6, 0x06, 0x8c, 0xfe, 0x5c, 0x07, 0xfe, 0x06, 0xf0, 0xfe, 0x64, 0x07,
9583 0x8d, 0x81, 0x02, 0x22, 0x09, 0x04, 0x0b, 0xfe, 0x2e, 0x12, 0x15, 0x1a,
9584 0x01, 0x08, 0x15, 0x00, 0x01, 0x08, 0x15, 0x00, 0x01, 0x08, 0x15, 0x00,
9585 0x01, 0x08, 0xfe, 0x99, 0xa4, 0x01, 0x08, 0x15, 0x00, 0x02, 0xfe, 0x32,
9586 0x08, 0x61, 0x04, 0x1b, 0xfe, 0x38, 0x12, 0x09, 0x04, 0x1b, 0x6e, 0x15,
9587 0xfe, 0x1b, 0x00, 0x01, 0x08, 0x15, 0x00, 0x01, 0x08, 0x15, 0x00, 0x01,
9588 0x08, 0x15, 0x00, 0x01, 0x08, 0x15, 0x06, 0x01, 0x08, 0x15, 0x00, 0x02,
9589 0xd9, 0x66, 0x4c, 0xfe, 0x3a, 0x55, 0x5f, 0xfe, 0x9a, 0x81, 0x4b, 0x1d,
9590 0xba, 0xfe, 0x32, 0x07, 0x0a, 0x1d, 0xfe, 0x09, 0x6f, 0xaf, 0xfe, 0xca,
9591 0x45, 0xfe, 0x32, 0x12, 0x62, 0x2c, 0x85, 0x66, 0x7b, 0x01, 0x08, 0x25,
9592 0x32, 0xfe, 0x0a, 0xf0, 0xfe, 0x32, 0x07, 0x8d, 0x81, 0x8c, 0xfe, 0x5c,
9593 0x07, 0x02, 0x22, 0x01, 0x43, 0x02, 0xfe, 0x8a, 0x06, 0x15, 0x19, 0x02,
9594 0xfe, 0x8a, 0x06, 0xfe, 0x9c, 0xf7, 0xd4, 0xfe, 0x2c, 0x90, 0xfe, 0xae,
9595 0x90, 0x77, 0xfe, 0xca, 0x07, 0x0c, 0x54, 0x18, 0x55, 0x09, 0x4a, 0x6a,
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9744 0xfe, 0x82, 0x0c, 0x0c, 0x54, 0x18, 0x55, 0x23, 0x0c, 0x7b, 0x0c, 0x7c,
9745 0x01, 0xa8, 0x24, 0x69, 0x73, 0x12, 0x58, 0x01, 0xa5, 0xc0, 0x38, 0xc1,
9746 0x4e, 0xfe, 0x04, 0x55, 0xfe, 0xa5, 0x55, 0xfe, 0x04, 0xfa, 0x38, 0xfe,
9747 0x05, 0xfa, 0x4e, 0xfe, 0x91, 0x10, 0x05, 0x56, 0x31, 0x57, 0xfe, 0x40,
9748 0x56, 0xfe, 0xe1, 0x56, 0x0c, 0x56, 0x18, 0x57, 0x83, 0xc0, 0x38, 0xc1,
9749 0x4e, 0xf4, 0xf5, 0x05, 0x52, 0x31, 0x53, 0xfe, 0x00, 0x56, 0xfe, 0xa1,
9750 0x56, 0x0c, 0x52, 0x18, 0x53, 0x09, 0x04, 0x6a, 0xfe, 0x1e, 0x12, 0x1e,
9751 0x58, 0xfe, 0x1f, 0x40, 0x05, 0x54, 0x31, 0x55, 0xfe, 0x2c, 0x50, 0xfe,
9752 0xae, 0x50, 0x05, 0x56, 0x31, 0x57, 0xfe, 0x44, 0x50, 0xfe, 0xc6, 0x50,
9753 0x05, 0x52, 0x31, 0x53, 0xfe, 0x08, 0x50, 0xfe, 0x8a, 0x50, 0x05, 0x39,
9754 0x31, 0x3a, 0xfe, 0x40, 0x50, 0xfe, 0xc2, 0x50, 0x02, 0x5c, 0x24, 0x06,
9755 0x12, 0xcd, 0x02, 0x5b, 0x2b, 0x01, 0x08, 0x1f, 0x44, 0x30, 0x2e, 0xd5,
9756 0x07, 0x06, 0x21, 0x44, 0x2f, 0x07, 0x9b, 0x21, 0x5b, 0x01, 0x6e, 0x1c,
9757 0x3d, 0x16, 0x44, 0x09, 0x04, 0x0b, 0xe2, 0x79, 0x39, 0x68, 0x3a, 0xfe,
9758 0x0a, 0x55, 0x34, 0xfe, 0x8b, 0x55, 0xbe, 0x39, 0xbf, 0x3a, 0xfe, 0x0c,
9759 0x51, 0xfe, 0x8e, 0x51, 0x02, 0x5b, 0xfe, 0x19, 0x81, 0xaf, 0xfe, 0x19,
9760 0x41, 0x02, 0x5b, 0x2b, 0x01, 0x08, 0x25, 0x32, 0x1f, 0xa2, 0x30, 0x2e,
9761 0xd8, 0x4b, 0x1a, 0xfe, 0xa6, 0x12, 0x4b, 0x0b, 0x3b, 0x02, 0x44, 0x01,
9762 0x08, 0x25, 0x32, 0x1f, 0xa2, 0x30, 0x2e, 0xd6, 0x07, 0x1a, 0x21, 0x44,
9763 0x01, 0x08, 0x1f, 0xa2, 0x30, 0x2e, 0xfe, 0xe8, 0x09, 0xfe, 0xc2, 0x49,
9764 0x60, 0x05, 0xfe, 0x9c, 0x00, 0x28, 0x84, 0x49, 0x04, 0x19, 0x34, 0x9f,
9765 0xfe, 0xbb, 0x45, 0x4b, 0x00, 0x45, 0x3e, 0x06, 0x78, 0x3d, 0xfe, 0xda,
9766 0x14, 0x01, 0x6e, 0x87, 0xfe, 0x4b, 0x45, 0xe2, 0x2f, 0x07, 0x9a, 0xe1,
9767 0x05, 0xc6, 0x28, 0x84, 0x05, 0x3f, 0x28, 0x34, 0x5e, 0x02, 0x5b, 0xfe,
9768 0xc0, 0x5d, 0xfe, 0xf8, 0x14, 0xfe, 0x03, 0x17, 0x05, 0x50, 0xb4, 0x0c,
9769 0x50, 0x5e, 0x2b, 0x01, 0x08, 0x26, 0x5c, 0x01, 0xfe, 0xaa, 0x14, 0x02,
9770 0x5c, 0x01, 0x08, 0x25, 0x32, 0x1f, 0x44, 0x30, 0x2e, 0xd6, 0x07, 0x06,
9771 0x21, 0x44, 0x01, 0xfe, 0x8e, 0x13, 0xfe, 0x42, 0x58, 0xfe, 0x82, 0x14,
9772 0xfe, 0xa4, 0x14, 0x87, 0xfe, 0x4a, 0xf4, 0x0b, 0x16, 0x44, 0xfe, 0x4a,
9773 0xf4, 0x06, 0xfe, 0x0c, 0x12, 0x2f, 0x07, 0x9a, 0x85, 0x02, 0x5b, 0x05,
9774 0x3f, 0xb4, 0x0c, 0x3f, 0x5e, 0x2b, 0x01, 0x08, 0x26, 0x5c, 0x01, 0xfe,
9775 0xd8, 0x14, 0x02, 0x5c, 0x13, 0x06, 0x65, 0xfe, 0xca, 0x12, 0x26, 0xfe,
9776 0xe0, 0x12, 0x72, 0xf1, 0x01, 0x08, 0x23, 0x72, 0x03, 0x8f, 0xfe, 0xdc,
9777 0x12, 0x25, 0xfe, 0xdc, 0x12, 0x1f, 0xfe, 0xca, 0x12, 0x5e, 0x2b, 0x01,
9778 0x08, 0xfe, 0xd5, 0x10, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b,
9779 0x1c, 0xfe, 0xff, 0x7f, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x03, 0x13,
9780 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0x1c, 0x3d, 0xfe, 0x30, 0x56,
9781 0xfe, 0x00, 0x5c, 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b,
9782 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0xfe, 0x0b, 0x58,
9783 0x03, 0x0a, 0x50, 0x01, 0x82, 0x0a, 0x3f, 0x01, 0x82, 0x03, 0xfc, 0x1c,
9784 0x10, 0xff, 0x03, 0x00, 0x54, 0xfe, 0x00, 0xf4, 0x19, 0x48, 0xfe, 0x00,
9785 0x7d, 0xfe, 0x01, 0x7d, 0xfe, 0x02, 0x7d, 0xfe, 0x03, 0x7c, 0x63, 0x27,
9786 0x0c, 0x52, 0x18, 0x53, 0xbe, 0x56, 0xbf, 0x57, 0x03, 0xfe, 0x62, 0x08,
9787 0xfe, 0x82, 0x4a, 0xfe, 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x74, 0x03, 0x01,
9788 0xfe, 0x14, 0x18, 0xfe, 0x42, 0x48, 0x5f, 0x60, 0x89, 0x01, 0x08, 0x1f,
9789 0xfe, 0xa2, 0x14, 0x30, 0x2e, 0xd8, 0x01, 0x08, 0x1f, 0xfe, 0xa2, 0x14,
9790 0x30, 0x2e, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x05, 0xc6, 0x28, 0xfe,
9791 0xcc, 0x12, 0x49, 0x04, 0x1b, 0xfe, 0xc4, 0x13, 0x23, 0x62, 0x1b, 0xe2,
9792 0x4b, 0xc3, 0x64, 0xfe, 0xe8, 0x13, 0x3b, 0x13, 0x06, 0x17, 0xc3, 0x78,
9793 0xdb, 0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xa1, 0xff, 0x02, 0x83,
9794 0x55, 0x62, 0x1a, 0xa4, 0xbb, 0xfe, 0x30, 0x00, 0x8e, 0xe4, 0x17, 0x2c,
9795 0x13, 0x06, 0xfe, 0x56, 0x10, 0x62, 0x0b, 0xe1, 0xbb, 0xfe, 0x64, 0x00,
9796 0x8e, 0xe4, 0x0a, 0xfe, 0x64, 0x00, 0x17, 0x93, 0x13, 0x06, 0xfe, 0x28,
9797 0x10, 0x62, 0x06, 0xfe, 0x60, 0x13, 0xbb, 0xfe, 0xc8, 0x00, 0x8e, 0xe4,
9798 0x0a, 0xfe, 0xc8, 0x00, 0x17, 0x4d, 0x13, 0x06, 0x83, 0xbb, 0xfe, 0x90,
9799 0x01, 0xba, 0xfe, 0x4e, 0x14, 0x89, 0xfe, 0x12, 0x10, 0xfe, 0x43, 0xf4,
9800 0x94, 0xfe, 0x56, 0xf0, 0xfe, 0x60, 0x14, 0xfe, 0x04, 0xf4, 0x6c, 0xfe,
9801 0x43, 0xf4, 0x93, 0xfe, 0xf3, 0x10, 0xf9, 0x01, 0xfe, 0x22, 0x13, 0x1c,
9802 0x3d, 0xfe, 0x10, 0x13, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x69, 0xba,
9803 0xfe, 0x9c, 0x14, 0xb7, 0x69, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe,
9804 0x4d, 0xe4, 0x19, 0xba, 0xfe, 0x9c, 0x14, 0xb7, 0x19, 0x83, 0x60, 0x23,
9805 0xfe, 0x4d, 0xf4, 0x00, 0xdf, 0x89, 0x13, 0x06, 0xfe, 0xb4, 0x56, 0xfe,
9806 0xc3, 0x58, 0x03, 0x60, 0x13, 0x0b, 0x03, 0x15, 0x06, 0x01, 0x08, 0x26,
9807 0xe5, 0x15, 0x0b, 0x01, 0x08, 0x26, 0xe5, 0x15, 0x1a, 0x01, 0x08, 0x26,
9808 0xe5, 0x72, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x03, 0x15, 0x06, 0x01, 0x08,
9809 0x26, 0xa6, 0x15, 0x1a, 0x01, 0x08, 0x26, 0xa6, 0x15, 0x06, 0x01, 0x08,
9810 0x26, 0xa6, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x26, 0xa6, 0x72, 0xfe, 0x89,
9811 0x4a, 0x01, 0x08, 0x03, 0x60, 0x03, 0x1e, 0xcc, 0x07, 0x06, 0xfe, 0x44,
9812 0x13, 0xad, 0x12, 0xcc, 0xfe, 0x49, 0xf4, 0x00, 0x3b, 0x72, 0x9f, 0x5e,
9813 0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01, 0xf1, 0x01, 0x08, 0x2f, 0x07, 0xfe,
9814 0xe3, 0x00, 0xfe, 0x20, 0x13, 0x1f, 0xfe, 0x5a, 0x15, 0x23, 0x12, 0xcd,
9815 0x01, 0x43, 0x1e, 0xcd, 0x07, 0x06, 0x45, 0x09, 0x4a, 0x06, 0x35, 0x03,
9816 0x0a, 0x42, 0x01, 0x0e, 0xed, 0x88, 0x07, 0x10, 0xa4, 0x0a, 0x80, 0x01,
9817 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03, 0x0a, 0x80, 0x01, 0x0e, 0x88,
9818 0xfe, 0x80, 0xe7, 0x10, 0x07, 0x10, 0x84, 0xfe, 0x45, 0x58, 0x01, 0xe3,
9819 0x88, 0x03, 0x0a, 0x42, 0x01, 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03,
9820 0x0a, 0x42, 0x01, 0x0e, 0xfe, 0x80, 0x80, 0xf2, 0xfe, 0x49, 0xe4, 0x10,
9821 0xa4, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x0a, 0x51, 0x01, 0x82, 0x03, 0x17,
9822 0x10, 0x71, 0x66, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde,
9823 0xfe, 0x24, 0x1c, 0xfe, 0x1d, 0xf7, 0x1d, 0x90, 0xfe, 0xf6, 0x15, 0x01,
9824 0xfe, 0xfc, 0x16, 0xe0, 0x91, 0x1d, 0x66, 0xfe, 0x2c, 0x01, 0xfe, 0x2f,
9825 0x19, 0x03, 0xae, 0x21, 0xfe, 0xe6, 0x15, 0xfe, 0xda, 0x10, 0x17, 0x10,
9826 0x71, 0x05, 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x19, 0xfe, 0x18, 0x58,
9827 0x05, 0xfe, 0x66, 0x01, 0xfe, 0x19, 0x58, 0x91, 0x19, 0xfe, 0x3c, 0x90,
9828 0xfe, 0x30, 0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x66, 0xfe, 0x38, 0x00, 0xfe,
9829 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x19, 0x90, 0xfe, 0x40, 0x16, 0xfe, 0xb6,
9830 0x14, 0x34, 0x03, 0xae, 0x21, 0xfe, 0x18, 0x16, 0xfe, 0x9c, 0x10, 0x17,
9831 0x10, 0x71, 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe,
9832 0x1d, 0xf7, 0x38, 0x90, 0xfe, 0x62, 0x16, 0xfe, 0x94, 0x14, 0xfe, 0x10,
9833 0x13, 0x91, 0x38, 0x66, 0x1b, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00,
9834 0x03, 0xae, 0x21, 0xfe, 0x56, 0x16, 0xfe, 0x6c, 0x10, 0x17, 0x10, 0x71,
9835 0xfe, 0x30, 0xbc, 0xfe, 0xb2, 0xbc, 0x91, 0xc5, 0x66, 0x1b, 0xfe, 0x0f,
9836 0x79, 0xfe, 0x1c, 0xf7, 0xc5, 0x90, 0xfe, 0x9a, 0x16, 0xfe, 0x5c, 0x14,
9837 0x34, 0x03, 0xae, 0x21, 0xfe, 0x86, 0x16, 0xfe, 0x42, 0x10, 0xfe, 0x02,
9838 0xf6, 0x10, 0x71, 0xfe, 0x18, 0xfe, 0x54, 0xfe, 0x19, 0xfe, 0x55, 0xfc,
9839 0xfe, 0x1d, 0xf7, 0x4f, 0x90, 0xfe, 0xc0, 0x16, 0xfe, 0x36, 0x14, 0xfe,
9840 0x1c, 0x13, 0x91, 0x4f, 0x47, 0xfe, 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe,
9841 0x80, 0xe7, 0x10, 0xfe, 0x81, 0xe7, 0x10, 0x11, 0xfe, 0xdd, 0x00, 0x63,
9842 0x27, 0x03, 0x63, 0x27, 0xfe, 0x12, 0x45, 0x21, 0xfe, 0xb0, 0x16, 0x14,
9843 0x06, 0x37, 0x95, 0xa9, 0x02, 0x29, 0xfe, 0x39, 0xf0, 0xfe, 0x04, 0x17,
9844 0x23, 0x03, 0xfe, 0x7e, 0x18, 0x1c, 0x1a, 0x5d, 0x13, 0x0d, 0x03, 0x71,
9845 0x05, 0xcb, 0x1c, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x78, 0x2c,
9846 0x46, 0x2f, 0x07, 0x2d, 0xfe, 0x3c, 0x13, 0xfe, 0x82, 0x14, 0xfe, 0x42,
9847 0x13, 0x3c, 0x8a, 0x0a, 0x42, 0x01, 0x0e, 0xb0, 0xfe, 0x3e, 0x12, 0xf0,
9848 0xfe, 0x45, 0x48, 0x01, 0xe3, 0xfe, 0x00, 0xcc, 0xb0, 0xfe, 0xf3, 0x13,
9849 0x3d, 0x75, 0x07, 0x10, 0xa3, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x01, 0x6f,
9850 0xfe, 0x16, 0x10, 0x07, 0x7e, 0x85, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12,
9851 0xf6, 0xfe, 0xd6, 0xf0, 0xfe, 0x24, 0x17, 0x17, 0x0b, 0x03, 0xfe, 0x9c,
9852 0xe7, 0x0b, 0x0f, 0xfe, 0x15, 0x00, 0x59, 0x76, 0x27, 0x01, 0xda, 0x17,
9853 0x06, 0x03, 0x3c, 0x8a, 0x09, 0x4a, 0x1d, 0x35, 0x11, 0x2d, 0x01, 0x6f,
9854 0x17, 0x06, 0x03, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x79, 0xc7, 0x68,
9855 0xc8, 0xfe, 0x48, 0x55, 0x34, 0xfe, 0xc9, 0x55, 0x03, 0x1e, 0x98, 0x73,
9856 0x12, 0x98, 0x03, 0x0a, 0x99, 0x01, 0x0e, 0xf0, 0x0a, 0x40, 0x01, 0x0e,
9857 0xfe, 0x49, 0x44, 0x16, 0xfe, 0xf0, 0x17, 0x73, 0x75, 0x03, 0x0a, 0x42,
9858 0x01, 0x0e, 0x07, 0x10, 0x45, 0x0a, 0x51, 0x01, 0x9e, 0x0a, 0x40, 0x01,
9859 0x0e, 0x73, 0x75, 0x03, 0xfe, 0x4e, 0xe4, 0x1a, 0x64, 0xfe, 0x24, 0x18,
9860 0x05, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0x5b, 0xfe, 0x4e, 0xe4, 0xc2,
9861 0x64, 0xfe, 0x36, 0x18, 0x05, 0xfe, 0x92, 0x00, 0xfe, 0x02, 0xe6, 0x1b,
9862 0xdc, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x64, 0xfe, 0x48, 0x18, 0x05,
9863 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x19, 0xfe, 0x08, 0x10, 0x05, 0xfe,
9864 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x2c, 0xfe, 0x4e, 0x45, 0xfe, 0x0c, 0x12,
9865 0xaf, 0xff, 0x04, 0x68, 0x54, 0xde, 0x1c, 0x69, 0x03, 0x07, 0x7a, 0xfe,
9866 0x5a, 0xf0, 0xfe, 0x74, 0x18, 0x24, 0xfe, 0x09, 0x00, 0xfe, 0x34, 0x10,
9867 0x07, 0x1b, 0xfe, 0x5a, 0xf0, 0xfe, 0x82, 0x18, 0x24, 0xc3, 0xfe, 0x26,
9868 0x10, 0x07, 0x1a, 0x5d, 0x24, 0x2c, 0xdc, 0x07, 0x0b, 0x5d, 0x24, 0x93,
9869 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x5d, 0x24, 0x4d, 0x9f, 0xad, 0x03, 0x14,
9870 0xfe, 0x09, 0x00, 0x01, 0x33, 0xfe, 0x04, 0xfe, 0x7d, 0x05, 0x7f, 0xf9,
9871 0x03, 0x25, 0xfe, 0xca, 0x18, 0xfe, 0x14, 0xf0, 0x08, 0x65, 0xfe, 0xc6,
9872 0x18, 0x03, 0xff, 0x1a, 0x00, 0x00,
9875 static unsigned short _adv_asc3550_size = sizeof(_adv_asc3550_buf); /* 0x13AD */
9876 static ADV_DCNT _adv_asc3550_chksum = 0x04D52DDDUL; /* Expanded little-endian checksum. */
9878 /* Microcode buffer is kept after initialization for error recovery. */
9879 static unsigned char _adv_asc38C0800_buf[] = {
9880 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0xfc, 0x00, 0x16, 0x18, 0xe4,
9881 0x01, 0x00, 0x48, 0xe4, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00, 0xce, 0x19,
9882 0x00, 0xfa, 0xff, 0xff, 0x1c, 0x0f, 0x00, 0xf6, 0x9e, 0xe7, 0xff, 0x00,
9883 0x82, 0xe7, 0x00, 0xea, 0x01, 0xfa, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0,
9884 0x01, 0xf6, 0x03, 0x00, 0x04, 0x00, 0x10, 0x00, 0x1e, 0xf0, 0x85, 0xf0,
9885 0x18, 0xf4, 0x08, 0x00, 0xbc, 0x00, 0x38, 0x54, 0x00, 0xec, 0xd5, 0xf0,
9886 0x82, 0x0d, 0x00, 0xe6, 0x86, 0xf0, 0xb1, 0xf0, 0x98, 0x57, 0x01, 0xfc,
9887 0xb4, 0x00, 0xd4, 0x01, 0x0c, 0x1c, 0x3e, 0x1c, 0x3c, 0x00, 0xbb, 0x00,
9888 0x00, 0x10, 0xba, 0x19, 0x02, 0x80, 0x32, 0xf0, 0x7c, 0x0d, 0x02, 0x13,
9889 0xba, 0x13, 0x18, 0x40, 0x00, 0x57, 0x01, 0xea, 0x02, 0xfc, 0x03, 0xfc,
9890 0x3e, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x74, 0x01, 0x76, 0x01, 0xb9, 0x54,
9891 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01,
9892 0x3e, 0x01, 0x7a, 0x01, 0xca, 0x08, 0xce, 0x10, 0x16, 0x11, 0x04, 0x12,
9893 0x08, 0x12, 0x02, 0x4a, 0xbb, 0x55, 0x3c, 0x56, 0x03, 0x58, 0x1b, 0x80,
9894 0x30, 0xe4, 0x4b, 0xe4, 0x5d, 0xf0, 0x02, 0xfa, 0x20, 0x00, 0x32, 0x00,
9895 0x40, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01,
9896 0x70, 0x01, 0x72, 0x01, 0x78, 0x01, 0x7c, 0x01, 0x62, 0x0a, 0x86, 0x0d,
9897 0x06, 0x13, 0x4c, 0x1c, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0,
9898 0x03, 0xf7, 0x0c, 0x00, 0x0f, 0x00, 0x47, 0x00, 0xbe, 0x00, 0x00, 0x01,
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9963 0xfe, 0x82, 0xf0, 0xfe, 0x96, 0x03, 0xfa, 0x12, 0xfe, 0xe4, 0x00, 0x27,
9964 0xfe, 0xa8, 0x03, 0x1c, 0x34, 0x1d, 0xfe, 0xb8, 0x03, 0x01, 0x4b, 0xfe,
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9975 0x2d, 0x01, 0x0b, 0x1d, 0x24, 0x33, 0x31, 0xde, 0xfe, 0x4c, 0x44, 0xfe,
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9977 0xda, 0x4f, 0x79, 0x2a, 0xfe, 0x06, 0x80, 0xfe, 0x48, 0x47, 0xfe, 0x62,
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9981 0x08, 0x13, 0x32, 0x07, 0x82, 0xfe, 0x30, 0x13, 0x08, 0x05, 0x1b, 0xfe,
9982 0x1c, 0x12, 0x15, 0x9d, 0x08, 0x05, 0x06, 0x4d, 0x15, 0xfe, 0x0d, 0x00,
9983 0x01, 0x36, 0x7b, 0xfe, 0x64, 0x0d, 0x02, 0x24, 0x2d, 0x12, 0xfe, 0xe6,
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9989 0x17, 0xfe, 0x90, 0x05, 0xfe, 0x31, 0xe4, 0x5a, 0x53, 0x05, 0x0a, 0xfe,
9990 0x56, 0x13, 0x03, 0xfe, 0xa0, 0x00, 0x28, 0xfe, 0x4e, 0x12, 0x67, 0xff,
9991 0x02, 0x00, 0x10, 0x27, 0xfe, 0x48, 0x05, 0x1c, 0x34, 0xfe, 0x89, 0x48,
9992 0xff, 0x02, 0x00, 0x10, 0x27, 0xfe, 0x56, 0x05, 0x26, 0xfe, 0xa8, 0x05,
9993 0x12, 0xfe, 0xe3, 0x00, 0x21, 0x53, 0xfe, 0x4a, 0xf0, 0xfe, 0x76, 0x05,
9994 0xfe, 0x49, 0xf0, 0xfe, 0x70, 0x05, 0x88, 0x25, 0xfe, 0x21, 0x00, 0xab,
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9996 0x00, 0x10, 0x27, 0xfe, 0x86, 0x05, 0x26, 0xfe, 0xa8, 0x05, 0xfe, 0xe2,
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9998 0xfe, 0x27, 0x01, 0x08, 0x05, 0x1b, 0xfe, 0x22, 0x12, 0x41, 0x01, 0xb2,
9999 0x15, 0x9d, 0x08, 0x05, 0x06, 0x4d, 0x15, 0xfe, 0x0d, 0x00, 0x01, 0x36,
10000 0x7b, 0xfe, 0x64, 0x0d, 0x02, 0x24, 0x03, 0xfe, 0x9c, 0x00, 0x28, 0xeb,
10001 0x03, 0x5c, 0x28, 0xfe, 0x36, 0x13, 0x41, 0x01, 0xb2, 0x26, 0xfe, 0x18,
10002 0x06, 0x09, 0x06, 0x53, 0x05, 0x1f, 0xfe, 0x02, 0x12, 0x50, 0x01, 0xfe,
10003 0x9e, 0x15, 0x1d, 0xfe, 0x0e, 0x06, 0x12, 0xa5, 0x01, 0x4b, 0x12, 0xfe,
10004 0xe5, 0x00, 0x03, 0x5c, 0xc1, 0x0c, 0x5c, 0x03, 0xcd, 0x28, 0xfe, 0x62,
10005 0x12, 0x03, 0x45, 0x28, 0xfe, 0x5a, 0x13, 0x01, 0xfe, 0x0c, 0x19, 0x01,
10006 0xfe, 0x76, 0x19, 0xfe, 0x43, 0x48, 0xc4, 0xcc, 0x0f, 0x71, 0xff, 0x02,
10007 0x00, 0x57, 0x52, 0x93, 0x1e, 0x43, 0x8b, 0xc4, 0x6e, 0x41, 0x01, 0xb2,
10008 0x26, 0xfe, 0x82, 0x06, 0x53, 0x05, 0x1a, 0xe9, 0x91, 0x09, 0x59, 0x01,
10009 0xfe, 0xcc, 0x15, 0x1d, 0xfe, 0x78, 0x06, 0x12, 0xa5, 0x01, 0x4b, 0x12,
10010 0xfe, 0xe5, 0x00, 0x03, 0x45, 0xc1, 0x0c, 0x45, 0x18, 0x06, 0x01, 0xb2,
10011 0xfa, 0x76, 0x74, 0x01, 0xaf, 0x8c, 0x12, 0xfe, 0xe2, 0x00, 0x27, 0xdb,
10012 0x1c, 0x34, 0xfe, 0x0a, 0xf0, 0xfe, 0xb6, 0x06, 0x94, 0xfe, 0x6c, 0x07,
10013 0xfe, 0x06, 0xf0, 0xfe, 0x74, 0x07, 0x95, 0x86, 0x02, 0x24, 0x08, 0x05,
10014 0x0a, 0xfe, 0x2e, 0x12, 0x16, 0x19, 0x01, 0x0b, 0x16, 0x00, 0x01, 0x0b,
10015 0x16, 0x00, 0x01, 0x0b, 0x16, 0x00, 0x01, 0x0b, 0xfe, 0x99, 0xa4, 0x01,
10016 0x0b, 0x16, 0x00, 0x02, 0xfe, 0x42, 0x08, 0x68, 0x05, 0x1a, 0xfe, 0x38,
10017 0x12, 0x08, 0x05, 0x1a, 0xfe, 0x30, 0x13, 0x16, 0xfe, 0x1b, 0x00, 0x01,
10018 0x0b, 0x16, 0x00, 0x01, 0x0b, 0x16, 0x00, 0x01, 0x0b, 0x16, 0x00, 0x01,
10019 0x0b, 0x16, 0x06, 0x01, 0x0b, 0x16, 0x00, 0x02, 0xe2, 0x6c, 0x58, 0xbe,
10020 0x50, 0xfe, 0x9a, 0x81, 0x55, 0x1b, 0x7a, 0xfe, 0x42, 0x07, 0x09, 0x1b,
10021 0xfe, 0x09, 0x6f, 0xba, 0xfe, 0xca, 0x45, 0xfe, 0x32, 0x12, 0x69, 0x6d,
10022 0x8b, 0x6c, 0x7f, 0x27, 0xfe, 0x54, 0x07, 0x1c, 0x34, 0xfe, 0x0a, 0xf0,
10023 0xfe, 0x42, 0x07, 0x95, 0x86, 0x94, 0xfe, 0x6c, 0x07, 0x02, 0x24, 0x01,
10024 0x4b, 0x02, 0xdb, 0x16, 0x1f, 0x02, 0xdb, 0xfe, 0x9c, 0xf7, 0xdc, 0xfe,
10025 0x2c, 0x90, 0xfe, 0xae, 0x90, 0x56, 0xfe, 0xda, 0x07, 0x0c, 0x60, 0x14,
10026 0x61, 0x08, 0x54, 0x5a, 0x37, 0x22, 0x20, 0x07, 0x11, 0xfe, 0x0e, 0x12,
10027 0x8d, 0xfe, 0x80, 0x80, 0x39, 0x20, 0x6a, 0x2a, 0xfe, 0x06, 0x10, 0xfe,
10028 0x83, 0xe7, 0xfe, 0x48, 0x00, 0xab, 0xfe, 0x03, 0x40, 0x08, 0x54, 0x5b,
10029 0x37, 0x01, 0xb3, 0xb8, 0xfe, 0x1f, 0x40, 0x13, 0x62, 0x01, 0xef, 0xfe,
10030 0x08, 0x50, 0xfe, 0x8a, 0x50, 0xfe, 0x44, 0x51, 0xfe, 0xc6, 0x51, 0x88,
10031 0xfe, 0x08, 0x90, 0xfe, 0x8a, 0x90, 0x0c, 0x5e, 0x14, 0x5f, 0xfe, 0x0c,
10032 0x90, 0xfe, 0x8e, 0x90, 0xfe, 0x40, 0x50, 0xfe, 0xc2, 0x50, 0x0c, 0x3d,
10033 0x14, 0x3e, 0xfe, 0x4a, 0x10, 0x08, 0x05, 0x5a, 0xfe, 0x2a, 0x12, 0xfe,
10034 0x2c, 0x90, 0xfe, 0xae, 0x90, 0x0c, 0x60, 0x14, 0x61, 0x08, 0x05, 0x5b,
10035 0x8b, 0x01, 0xb3, 0xfe, 0x1f, 0x80, 0x13, 0x62, 0xfe, 0x44, 0x90, 0xfe,
10036 0xc6, 0x90, 0x0c, 0x3f, 0x14, 0x40, 0xfe, 0x08, 0x90, 0xfe, 0x8a, 0x90,
10037 0x0c, 0x5e, 0x14, 0x5f, 0xfe, 0x40, 0x90, 0xfe, 0xc2, 0x90, 0x0c, 0x3d,
10038 0x14, 0x3e, 0x0c, 0x2e, 0x14, 0x3c, 0x21, 0x0c, 0x49, 0x0c, 0x63, 0x08,
10039 0x54, 0x1f, 0x37, 0x2c, 0x0f, 0xfe, 0x4e, 0x11, 0x27, 0xdd, 0xfe, 0x9e,
10040 0xf0, 0xfe, 0x76, 0x08, 0xbc, 0x17, 0x34, 0x2c, 0x77, 0xe6, 0xc5, 0xfe,
10041 0x9a, 0x08, 0xc6, 0xfe, 0xb8, 0x08, 0x94, 0xfe, 0x8e, 0x08, 0xfe, 0x06,
10042 0xf0, 0xfe, 0x94, 0x08, 0x95, 0x86, 0x02, 0x24, 0x01, 0x4b, 0xfe, 0xc9,
10043 0x10, 0x16, 0x1f, 0xfe, 0xc9, 0x10, 0x68, 0x05, 0x06, 0xfe, 0x10, 0x12,
10044 0x68, 0x05, 0x0a, 0x4e, 0x08, 0x05, 0x0a, 0xfe, 0x90, 0x12, 0xfe, 0x2e,
10045 0x1c, 0x02, 0xfe, 0x18, 0x0b, 0x68, 0x05, 0x06, 0x4e, 0x68, 0x05, 0x0a,
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10165 0x03, 0xfe, 0xae, 0x00, 0xfe, 0x07, 0x58, 0x03, 0xfe, 0xb0, 0x00, 0xfe,
10166 0x08, 0x58, 0x03, 0xfe, 0xb2, 0x00, 0xfe, 0x09, 0x58, 0xfe, 0x0a, 0x1c,
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10168 0x50, 0x18, 0x1b, 0xfe, 0x90, 0x4d, 0xfe, 0x91, 0x54, 0x23, 0xfe, 0xfc,
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10170 0x91, 0x54, 0x23, 0xe4, 0x25, 0x11, 0x13, 0x20, 0x7c, 0x6f, 0x4f, 0x22,
10171 0x20, 0xfb, 0x79, 0x20, 0x12, 0xcf, 0xfe, 0x14, 0x56, 0xfe, 0xd6, 0xf0,
10172 0xfe, 0x26, 0x10, 0xf8, 0x74, 0xfe, 0x14, 0x1c, 0xfe, 0x10, 0x1c, 0xfe,
10173 0x18, 0x1c, 0x04, 0x42, 0xfe, 0x0c, 0x14, 0xfc, 0xfe, 0x07, 0xe6, 0x1b,
10174 0xfe, 0xce, 0x47, 0xfe, 0xf5, 0x13, 0x04, 0x01, 0xb0, 0x7c, 0x6f, 0x4f,
10175 0xfe, 0x06, 0x80, 0xfe, 0x48, 0x47, 0xfe, 0x42, 0x13, 0x32, 0x07, 0x2f,
10176 0xfe, 0x34, 0x13, 0x09, 0x48, 0x01, 0x0e, 0xbb, 0xfe, 0x36, 0x12, 0xfe,
10177 0x41, 0x48, 0xfe, 0x45, 0x48, 0x01, 0xf0, 0xfe, 0x00, 0xcc, 0xbb, 0xfe,
10178 0xf3, 0x13, 0x43, 0x78, 0x07, 0x11, 0xac, 0x09, 0x84, 0x01, 0x0e, 0xfe,
10179 0x80, 0x5c, 0x01, 0x73, 0xfe, 0x0e, 0x10, 0x07, 0x82, 0x4e, 0xfe, 0x14,
10180 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x60, 0x10, 0x04, 0xfe, 0x44, 0x58, 0x8d,
10181 0xfe, 0x01, 0xec, 0xa2, 0xfe, 0x9e, 0x40, 0xfe, 0x9d, 0xe7, 0x00, 0xfe,
10182 0x9c, 0xe7, 0x1a, 0x79, 0x2a, 0x01, 0xe3, 0xfe, 0xdd, 0x10, 0x2c, 0xc7,
10183 0x81, 0xc8, 0x83, 0x33, 0x31, 0xde, 0x07, 0x1a, 0xfe, 0x48, 0x12, 0x07,
10184 0x0a, 0xfe, 0x56, 0x12, 0x07, 0x19, 0xfe, 0x30, 0x12, 0x07, 0xc9, 0x17,
10185 0xfe, 0x32, 0x12, 0x07, 0xfe, 0x23, 0x00, 0x17, 0xeb, 0x07, 0x06, 0x17,
10186 0xfe, 0x9c, 0x12, 0x07, 0x1f, 0xfe, 0x12, 0x12, 0x07, 0x00, 0x17, 0x24,
10187 0x15, 0xc9, 0x01, 0x36, 0xa9, 0x2d, 0x01, 0x0b, 0x94, 0x4b, 0x04, 0x2d,
10188 0xdd, 0x09, 0xd1, 0x01, 0xfe, 0x26, 0x0f, 0x12, 0x82, 0x02, 0x2b, 0x2d,
10189 0x32, 0x07, 0xa6, 0xfe, 0xd9, 0x13, 0x3a, 0x3d, 0x3b, 0x3e, 0x56, 0xfe,
10190 0xf0, 0x11, 0x08, 0x05, 0x5a, 0xfe, 0x72, 0x12, 0x9b, 0x2e, 0x9c, 0x3c,
10191 0x90, 0xc0, 0x96, 0xfe, 0xba, 0x11, 0x22, 0x62, 0xfe, 0x26, 0x13, 0x03,
10192 0x7f, 0x29, 0x80, 0x56, 0xfe, 0x76, 0x0d, 0x0c, 0x60, 0x14, 0x61, 0x21,
10193 0x0c, 0x7f, 0x0c, 0x80, 0x01, 0xb3, 0x25, 0x6e, 0x77, 0x13, 0x62, 0x01,
10194 0xef, 0x9b, 0x2e, 0x9c, 0x3c, 0xfe, 0x04, 0x55, 0xfe, 0xa5, 0x55, 0xfe,
10195 0x04, 0xfa, 0x2e, 0xfe, 0x05, 0xfa, 0x3c, 0xfe, 0x91, 0x10, 0x03, 0x3f,
10196 0x29, 0x40, 0xfe, 0x40, 0x56, 0xfe, 0xe1, 0x56, 0x0c, 0x3f, 0x14, 0x40,
10197 0x88, 0x9b, 0x2e, 0x9c, 0x3c, 0x90, 0xc0, 0x03, 0x5e, 0x29, 0x5f, 0xfe,
10198 0x00, 0x56, 0xfe, 0xa1, 0x56, 0x0c, 0x5e, 0x14, 0x5f, 0x08, 0x05, 0x5a,
10199 0xfe, 0x1e, 0x12, 0x22, 0x62, 0xfe, 0x1f, 0x40, 0x03, 0x60, 0x29, 0x61,
10200 0xfe, 0x2c, 0x50, 0xfe, 0xae, 0x50, 0x03, 0x3f, 0x29, 0x40, 0xfe, 0x44,
10201 0x50, 0xfe, 0xc6, 0x50, 0x03, 0x5e, 0x29, 0x5f, 0xfe, 0x08, 0x50, 0xfe,
10202 0x8a, 0x50, 0x03, 0x3d, 0x29, 0x3e, 0xfe, 0x40, 0x50, 0xfe, 0xc2, 0x50,
10203 0x02, 0x89, 0x25, 0x06, 0x13, 0xd4, 0x02, 0x72, 0x2d, 0x01, 0x0b, 0x1d,
10204 0x4c, 0x33, 0x31, 0xde, 0x07, 0x06, 0x23, 0x4c, 0x32, 0x07, 0xa6, 0x23,
10205 0x72, 0x01, 0xaf, 0x1e, 0x43, 0x17, 0x4c, 0x08, 0x05, 0x0a, 0xee, 0x3a,
10206 0x3d, 0x3b, 0x3e, 0xfe, 0x0a, 0x55, 0x35, 0xfe, 0x8b, 0x55, 0x57, 0x3d,
10207 0x7d, 0x3e, 0xfe, 0x0c, 0x51, 0xfe, 0x8e, 0x51, 0x02, 0x72, 0xfe, 0x19,
10208 0x81, 0xba, 0xfe, 0x19, 0x41, 0x02, 0x72, 0x2d, 0x01, 0x0b, 0x1c, 0x34,
10209 0x1d, 0xe8, 0x33, 0x31, 0xe1, 0x55, 0x19, 0xfe, 0xa6, 0x12, 0x55, 0x0a,
10210 0x4d, 0x02, 0x4c, 0x01, 0x0b, 0x1c, 0x34, 0x1d, 0xe8, 0x33, 0x31, 0xdf,
10211 0x07, 0x19, 0x23, 0x4c, 0x01, 0x0b, 0x1d, 0xe8, 0x33, 0x31, 0xfe, 0xe8,
10212 0x09, 0xfe, 0xc2, 0x49, 0x51, 0x03, 0xfe, 0x9c, 0x00, 0x28, 0x8a, 0x53,
10213 0x05, 0x1f, 0x35, 0xa9, 0xfe, 0xbb, 0x45, 0x55, 0x00, 0x4e, 0x44, 0x06,
10214 0x7c, 0x43, 0xfe, 0xda, 0x14, 0x01, 0xaf, 0x8c, 0xfe, 0x4b, 0x45, 0xee,
10215 0x32, 0x07, 0xa5, 0xed, 0x03, 0xcd, 0x28, 0x8a, 0x03, 0x45, 0x28, 0x35,
10216 0x67, 0x02, 0x72, 0xfe, 0xc0, 0x5d, 0xfe, 0xf8, 0x14, 0xfe, 0x03, 0x17,
10217 0x03, 0x5c, 0xc1, 0x0c, 0x5c, 0x67, 0x2d, 0x01, 0x0b, 0x26, 0x89, 0x01,
10218 0xfe, 0x9e, 0x15, 0x02, 0x89, 0x01, 0x0b, 0x1c, 0x34, 0x1d, 0x4c, 0x33,
10219 0x31, 0xdf, 0x07, 0x06, 0x23, 0x4c, 0x01, 0xf1, 0xfe, 0x42, 0x58, 0xf1,
10220 0xfe, 0xa4, 0x14, 0x8c, 0xfe, 0x4a, 0xf4, 0x0a, 0x17, 0x4c, 0xfe, 0x4a,
10221 0xf4, 0x06, 0xea, 0x32, 0x07, 0xa5, 0x8b, 0x02, 0x72, 0x03, 0x45, 0xc1,
10222 0x0c, 0x45, 0x67, 0x2d, 0x01, 0x0b, 0x26, 0x89, 0x01, 0xfe, 0xcc, 0x15,
10223 0x02, 0x89, 0x0f, 0x06, 0x27, 0xfe, 0xbe, 0x13, 0x26, 0xfe, 0xd4, 0x13,
10224 0x76, 0xfe, 0x89, 0x48, 0x01, 0x0b, 0x21, 0x76, 0x04, 0x7b, 0xfe, 0xd0,
10225 0x13, 0x1c, 0xfe, 0xd0, 0x13, 0x1d, 0xfe, 0xbe, 0x13, 0x67, 0x2d, 0x01,
10226 0x0b, 0xfe, 0xd5, 0x10, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93,
10227 0x1e, 0xfe, 0xff, 0x7f, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x04, 0x0f,
10228 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93, 0x1e, 0x43, 0xfe, 0x30, 0x56,
10229 0xfe, 0x00, 0x5c, 0x04, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93,
10230 0x04, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93, 0xfe, 0x0b, 0x58,
10231 0x04, 0x09, 0x5c, 0x01, 0x87, 0x09, 0x45, 0x01, 0x87, 0x04, 0xfe, 0x03,
10232 0xa1, 0x1e, 0x11, 0xff, 0x03, 0x00, 0x54, 0xfe, 0x00, 0xf4, 0x1f, 0x52,
10233 0xfe, 0x00, 0x7d, 0xfe, 0x01, 0x7d, 0xfe, 0x02, 0x7d, 0xfe, 0x03, 0x7c,
10234 0x6a, 0x2a, 0x0c, 0x5e, 0x14, 0x5f, 0x57, 0x3f, 0x7d, 0x40, 0x04, 0xdd,
10235 0xfe, 0x82, 0x4a, 0xfe, 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x8d, 0x04, 0x01,
10236 0xfe, 0x0c, 0x19, 0xfe, 0x42, 0x48, 0x50, 0x51, 0x91, 0x01, 0x0b, 0x1d,
10237 0xfe, 0x96, 0x15, 0x33, 0x31, 0xe1, 0x01, 0x0b, 0x1d, 0xfe, 0x96, 0x15,
10238 0x33, 0x31, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x03, 0xcd, 0x28, 0xfe,
10239 0xcc, 0x12, 0x53, 0x05, 0x1a, 0xfe, 0xc4, 0x13, 0x21, 0x69, 0x1a, 0xee,
10240 0x55, 0xca, 0x6b, 0xfe, 0xdc, 0x14, 0x4d, 0x0f, 0x06, 0x18, 0xca, 0x7c,
10241 0x30, 0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xab, 0xff, 0x02, 0x83,
10242 0x55, 0x69, 0x19, 0xae, 0x98, 0xfe, 0x30, 0x00, 0x96, 0xf2, 0x18, 0x6d,
10243 0x0f, 0x06, 0xfe, 0x56, 0x10, 0x69, 0x0a, 0xed, 0x98, 0xfe, 0x64, 0x00,
10244 0x96, 0xf2, 0x09, 0xfe, 0x64, 0x00, 0x18, 0x9e, 0x0f, 0x06, 0xfe, 0x28,
10245 0x10, 0x69, 0x06, 0xfe, 0x60, 0x13, 0x98, 0xfe, 0xc8, 0x00, 0x96, 0xf2,
10246 0x09, 0xfe, 0xc8, 0x00, 0x18, 0x59, 0x0f, 0x06, 0x88, 0x98, 0xfe, 0x90,
10247 0x01, 0x7a, 0xfe, 0x42, 0x15, 0x91, 0xe4, 0xfe, 0x43, 0xf4, 0x9f, 0xfe,
10248 0x56, 0xf0, 0xfe, 0x54, 0x15, 0xfe, 0x04, 0xf4, 0x71, 0xfe, 0x43, 0xf4,
10249 0x9e, 0xfe, 0xf3, 0x10, 0xfe, 0x40, 0x5c, 0x01, 0xfe, 0x16, 0x14, 0x1e,
10250 0x43, 0xec, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x6e, 0x7a, 0xfe, 0x90,
10251 0x15, 0xc4, 0x6e, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4,
10252 0xcc, 0x7a, 0xfe, 0x90, 0x15, 0xc4, 0xcc, 0x88, 0x51, 0x21, 0xfe, 0x4d,
10253 0xf4, 0x00, 0xe9, 0x91, 0x0f, 0x06, 0xfe, 0xb4, 0x56, 0xfe, 0xc3, 0x58,
10254 0x04, 0x51, 0x0f, 0x0a, 0x04, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xf3, 0x16,
10255 0x0a, 0x01, 0x0b, 0x26, 0xf3, 0x16, 0x19, 0x01, 0x0b, 0x26, 0xf3, 0x76,
10256 0xfe, 0x89, 0x49, 0x01, 0x0b, 0x04, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1,
10257 0x16, 0x19, 0x01, 0x0b, 0x26, 0xb1, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1,
10258 0xfe, 0x89, 0x49, 0x01, 0x0b, 0x26, 0xb1, 0x76, 0xfe, 0x89, 0x4a, 0x01,
10259 0x0b, 0x04, 0x51, 0x04, 0x22, 0xd3, 0x07, 0x06, 0xfe, 0x48, 0x13, 0xb8,
10260 0x13, 0xd3, 0xfe, 0x49, 0xf4, 0x00, 0x4d, 0x76, 0xa9, 0x67, 0xfe, 0x01,
10261 0xec, 0xfe, 0x27, 0x01, 0xfe, 0x89, 0x48, 0xff, 0x02, 0x00, 0x10, 0x27,
10262 0xfe, 0x2e, 0x16, 0x32, 0x07, 0xfe, 0xe3, 0x00, 0xfe, 0x20, 0x13, 0x1d,
10263 0xfe, 0x52, 0x16, 0x21, 0x13, 0xd4, 0x01, 0x4b, 0x22, 0xd4, 0x07, 0x06,
10264 0x4e, 0x08, 0x54, 0x06, 0x37, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfb, 0x8e,
10265 0x07, 0x11, 0xae, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0x09, 0x5d, 0x01, 0xa8,
10266 0x04, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0xfe, 0x80, 0xe7, 0x11, 0x07, 0x11,
10267 0x8a, 0xfe, 0x45, 0x58, 0x01, 0xf0, 0x8e, 0x04, 0x09, 0x48, 0x01, 0x0e,
10268 0x8e, 0x09, 0x5d, 0x01, 0xa8, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfe, 0x80,
10269 0x80, 0xfe, 0x80, 0x4c, 0xfe, 0x49, 0xe4, 0x11, 0xae, 0x09, 0x84, 0x01,
10270 0x0e, 0xfe, 0x80, 0x4c, 0x09, 0x5d, 0x01, 0x87, 0x04, 0x18, 0x11, 0x75,
10271 0x6c, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24,
10272 0x1c, 0xfe, 0x1d, 0xf7, 0x1b, 0x97, 0xfe, 0xee, 0x16, 0x01, 0xfe, 0xf4,
10273 0x17, 0xad, 0x9a, 0x1b, 0x6c, 0xfe, 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x04,
10274 0xb9, 0x23, 0xfe, 0xde, 0x16, 0xfe, 0xda, 0x10, 0x18, 0x11, 0x75, 0x03,
10275 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x1f, 0xfe, 0x18, 0x58, 0x03, 0xfe,
10276 0x66, 0x01, 0xfe, 0x19, 0x58, 0x9a, 0x1f, 0xfe, 0x3c, 0x90, 0xfe, 0x30,
10277 0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x6c, 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79,
10278 0xfe, 0x1c, 0xf7, 0x1f, 0x97, 0xfe, 0x38, 0x17, 0xfe, 0xb6, 0x14, 0x35,
10279 0x04, 0xb9, 0x23, 0xfe, 0x10, 0x17, 0xfe, 0x9c, 0x10, 0x18, 0x11, 0x75,
10280 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7,
10281 0x2e, 0x97, 0xfe, 0x5a, 0x17, 0xfe, 0x94, 0x14, 0xec, 0x9a, 0x2e, 0x6c,
10282 0x1a, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00, 0x04, 0xb9, 0x23, 0xfe,
10283 0x4e, 0x17, 0xfe, 0x6c, 0x10, 0x18, 0x11, 0x75, 0xfe, 0x30, 0xbc, 0xfe,
10284 0xb2, 0xbc, 0x9a, 0xcb, 0x6c, 0x1a, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7,
10285 0xcb, 0x97, 0xfe, 0x92, 0x17, 0xfe, 0x5c, 0x14, 0x35, 0x04, 0xb9, 0x23,
10286 0xfe, 0x7e, 0x17, 0xfe, 0x42, 0x10, 0xfe, 0x02, 0xf6, 0x11, 0x75, 0xfe,
10287 0x18, 0xfe, 0x60, 0xfe, 0x19, 0xfe, 0x61, 0xfe, 0x03, 0xa1, 0xfe, 0x1d,
10288 0xf7, 0x5b, 0x97, 0xfe, 0xb8, 0x17, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13,
10289 0x9a, 0x5b, 0x41, 0xfe, 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7,
10290 0x11, 0xfe, 0x81, 0xe7, 0x11, 0x12, 0xfe, 0xdd, 0x00, 0x6a, 0x2a, 0x04,
10291 0x6a, 0x2a, 0xfe, 0x12, 0x45, 0x23, 0xfe, 0xa8, 0x17, 0x15, 0x06, 0x39,
10292 0xa0, 0xb4, 0x02, 0x2b, 0xfe, 0x39, 0xf0, 0xfe, 0xfc, 0x17, 0x21, 0x04,
10293 0xfe, 0x7e, 0x18, 0x1e, 0x19, 0x66, 0x0f, 0x0d, 0x04, 0x75, 0x03, 0xd2,
10294 0x1e, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x7c, 0x6f, 0x4f, 0x32,
10295 0x07, 0x2f, 0xfe, 0x3c, 0x13, 0xf1, 0xfe, 0x42, 0x13, 0x42, 0x92, 0x09,
10296 0x48, 0x01, 0x0e, 0xbb, 0xeb, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48, 0x01,
10297 0xf0, 0xfe, 0x00, 0xcc, 0xbb, 0xfe, 0xf3, 0x13, 0x43, 0x78, 0x07, 0x11,
10298 0xac, 0x09, 0x84, 0x01, 0x0e, 0xfe, 0x80, 0x4c, 0x01, 0x73, 0xfe, 0x16,
10299 0x10, 0x07, 0x82, 0x8b, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12, 0xfe, 0x14,
10300 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x1c, 0x18, 0x18, 0x0a, 0x04, 0xfe, 0x9c,
10301 0xe7, 0x0a, 0x10, 0xfe, 0x15, 0x00, 0x64, 0x79, 0x2a, 0x01, 0xe3, 0x18,
10302 0x06, 0x04, 0x42, 0x92, 0x08, 0x54, 0x1b, 0x37, 0x12, 0x2f, 0x01, 0x73,
10303 0x18, 0x06, 0x04, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x3a, 0xce, 0x3b,
10304 0xcf, 0xfe, 0x48, 0x55, 0x35, 0xfe, 0xc9, 0x55, 0x04, 0x22, 0xa3, 0x77,
10305 0x13, 0xa3, 0x04, 0x09, 0xa4, 0x01, 0x0e, 0xfe, 0x41, 0x48, 0x09, 0x46,
10306 0x01, 0x0e, 0xfe, 0x49, 0x44, 0x17, 0xfe, 0xe8, 0x18, 0x77, 0x78, 0x04,
10307 0x09, 0x48, 0x01, 0x0e, 0x07, 0x11, 0x4e, 0x09, 0x5d, 0x01, 0xa8, 0x09,
10308 0x46, 0x01, 0x0e, 0x77, 0x78, 0x04, 0xfe, 0x4e, 0xe4, 0x19, 0x6b, 0xfe,
10309 0x1c, 0x19, 0x03, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10,
10310 0xfe, 0x4e, 0xe4, 0xc9, 0x6b, 0xfe, 0x2e, 0x19, 0x03, 0xfe, 0x92, 0x00,
10311 0xfe, 0x02, 0xe6, 0x1a, 0xe5, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x6b,
10312 0xfe, 0x40, 0x19, 0x03, 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x1f, 0xfe,
10313 0x08, 0x10, 0x03, 0xfe, 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x6d, 0xfe, 0x4e,
10314 0x45, 0xea, 0xba, 0xff, 0x04, 0x68, 0x54, 0xe7, 0x1e, 0x6e, 0xfe, 0x08,
10315 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c, 0xfe, 0x1a, 0xf4, 0xfe, 0x00,
10316 0x04, 0xea, 0xfe, 0x48, 0xf4, 0x19, 0x7a, 0xfe, 0x74, 0x19, 0x0f, 0x19,
10317 0x04, 0x07, 0x7e, 0xfe, 0x5a, 0xf0, 0xfe, 0x84, 0x19, 0x25, 0xfe, 0x09,
10318 0x00, 0xfe, 0x34, 0x10, 0x07, 0x1a, 0xfe, 0x5a, 0xf0, 0xfe, 0x92, 0x19,
10319 0x25, 0xca, 0xfe, 0x26, 0x10, 0x07, 0x19, 0x66, 0x25, 0x6d, 0xe5, 0x07,
10320 0x0a, 0x66, 0x25, 0x9e, 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x66, 0x25, 0x59,
10321 0xa9, 0xb8, 0x04, 0x15, 0xfe, 0x09, 0x00, 0x01, 0x36, 0xfe, 0x04, 0xfe,
10322 0x81, 0x03, 0x83, 0xfe, 0x40, 0x5c, 0x04, 0x1c, 0xf7, 0xfe, 0x14, 0xf0,
10323 0x0b, 0x27, 0xfe, 0xd6, 0x19, 0x1c, 0xf7, 0x7b, 0xf7, 0xfe, 0x82, 0xf0,
10324 0xfe, 0xda, 0x19, 0x04, 0xff, 0xcc, 0x00, 0x00,
10327 static unsigned short _adv_asc38C0800_size = sizeof(_adv_asc38C0800_buf); /* 0x14E1 */
10328 static ADV_DCNT _adv_asc38C0800_chksum = 0x050D3FD8UL; /* Expanded little-endian checksum. */
10330 /* Microcode buffer is kept after initialization for error recovery. */
10331 static unsigned char _adv_asc38C1600_buf[] = {
10332 0x00, 0x00, 0x00, 0xf2, 0x00, 0x16, 0x00, 0xfc, 0x00, 0x10, 0x00, 0xf0,
10333 0x18, 0xe4, 0x01, 0x00, 0x04, 0x1e, 0x48, 0xe4, 0x03, 0xf6, 0xf7, 0x13,
10334 0x2e, 0x1e, 0x02, 0x00, 0x07, 0x17, 0xc0, 0x5f, 0x00, 0xfa, 0xff, 0xff,
10335 0x04, 0x00, 0x00, 0xf6, 0x09, 0xe7, 0x82, 0xe7, 0x85, 0xf0, 0x86, 0xf0,
10336 0x4e, 0x10, 0x9e, 0xe7, 0xff, 0x00, 0x55, 0xf0, 0x01, 0xf6, 0x03, 0x00,
10337 0x98, 0x57, 0x01, 0xe6, 0x00, 0xea, 0x00, 0xec, 0x01, 0xfa, 0x18, 0xf4,
10338 0x08, 0x00, 0xf0, 0x1d, 0x38, 0x54, 0x32, 0xf0, 0x10, 0x00, 0xc2, 0x0e,
10339 0x1e, 0xf0, 0xd5, 0xf0, 0xbc, 0x00, 0x4b, 0xe4, 0x00, 0xe6, 0xb1, 0xf0,
10340 0xb4, 0x00, 0x02, 0x13, 0x3e, 0x1c, 0xc8, 0x47, 0x3e, 0x00, 0xd8, 0x01,
10341 0x06, 0x13, 0x0c, 0x1c, 0x5e, 0x1e, 0x00, 0x57, 0xc8, 0x57, 0x01, 0xfc,
10342 0xbc, 0x0e, 0xa2, 0x12, 0xb9, 0x54, 0x00, 0x80, 0x62, 0x0a, 0x5a, 0x12,
10343 0xc8, 0x15, 0x3e, 0x1e, 0x18, 0x40, 0xbd, 0x56, 0x03, 0xe6, 0x01, 0xea,
10344 0x5c, 0xf0, 0x0f, 0x00, 0x20, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12,
10345 0x04, 0x13, 0xbb, 0x55, 0x3c, 0x56, 0x3e, 0x57, 0x03, 0x58, 0x4a, 0xe4,
10346 0x40, 0x00, 0xb6, 0x00, 0xbb, 0x00, 0xc0, 0x00, 0x00, 0x01, 0x01, 0x01,
10347 0x3e, 0x01, 0x58, 0x0a, 0x44, 0x10, 0x0a, 0x12, 0x4c, 0x1c, 0x4e, 0x1c,
10348 0x02, 0x4a, 0x30, 0xe4, 0x05, 0xe6, 0x0c, 0x00, 0x3c, 0x00, 0x80, 0x00,
10349 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01,
10350 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x7c, 0x01, 0xc6, 0x0e, 0x0c, 0x10,
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10354 0x18, 0x1a, 0x70, 0x1a, 0x30, 0x1c, 0x38, 0x1c, 0x10, 0x44, 0x00, 0x4c,
10355 0xb0, 0x57, 0x40, 0x5c, 0x4d, 0xe4, 0x04, 0xea, 0x5d, 0xf0, 0xa7, 0xf0,
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10358 0x20, 0x01, 0x4e, 0x01, 0x79, 0x01, 0x3c, 0x09, 0x68, 0x0d, 0x02, 0x10,
10359 0x04, 0x10, 0x3a, 0x10, 0x08, 0x12, 0x0a, 0x13, 0x40, 0x16, 0x50, 0x16,
10360 0x00, 0x17, 0x4a, 0x19, 0x00, 0x4e, 0x00, 0x54, 0x01, 0x58, 0x00, 0xdc,
10361 0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xb8, 0xf0, 0x48, 0xf4, 0x0e, 0xf7,
10362 0x0a, 0x00, 0x9b, 0x00, 0x9c, 0x00, 0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00,
10363 0xd0, 0x00, 0xe7, 0x00, 0xf0, 0x03, 0x69, 0x08, 0xe9, 0x09, 0x5c, 0x0c,
10364 0xb6, 0x12, 0xbc, 0x19, 0xd8, 0x1b, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c,
10365 0x42, 0x1d, 0x08, 0x44, 0x38, 0x44, 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46,
10366 0x89, 0x48, 0x68, 0x54, 0x83, 0x55, 0x83, 0x59, 0x31, 0xe4, 0x02, 0xe6,
10367 0x07, 0xf0, 0x08, 0xf0, 0x0b, 0xf0, 0x0c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8,
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10369 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00, 0xe5, 0x00, 0x22, 0x01,
10370 0x26, 0x01, 0x60, 0x01, 0x7a, 0x01, 0x82, 0x01, 0xc8, 0x01, 0xca, 0x01,
10371 0x86, 0x02, 0x6a, 0x03, 0x18, 0x05, 0xb2, 0x07, 0x68, 0x08, 0x10, 0x0d,
10372 0x06, 0x10, 0x0a, 0x10, 0x0e, 0x10, 0x12, 0x10, 0x60, 0x10, 0xed, 0x10,
10373 0xf3, 0x10, 0x06, 0x12, 0x10, 0x12, 0x1e, 0x12, 0x0c, 0x13, 0x0e, 0x13,
10374 0x10, 0x13, 0xfe, 0x9c, 0xf0, 0x35, 0x05, 0xfe, 0xec, 0x0e, 0xff, 0x10,
10375 0x00, 0x00, 0xe9, 0xfe, 0x34, 0x1f, 0x00, 0xe8, 0xfe, 0x88, 0x01, 0xff,
10376 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00,
10377 0x00, 0xfe, 0x57, 0x24, 0x00, 0xfe, 0x4c, 0x00, 0x65, 0xff, 0x04, 0x00,
10378 0x00, 0x1a, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08, 0x01, 0x01, 0xff, 0x08,
10379 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x13,
10380 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00,
10381 0xfe, 0x04, 0xf7, 0xe8, 0x37, 0x7d, 0x0d, 0x01, 0xfe, 0x4a, 0x11, 0xfe,
10382 0x04, 0xf7, 0xe8, 0x7d, 0x0d, 0x51, 0x37, 0xfe, 0x3d, 0xf0, 0xfe, 0x0c,
10383 0x02, 0xfe, 0x20, 0xf0, 0xbc, 0xfe, 0x91, 0xf0, 0xfe, 0xf8, 0x01, 0xfe,
10384 0x90, 0xf0, 0xfe, 0xf8, 0x01, 0xfe, 0x8f, 0xf0, 0xbc, 0x03, 0x67, 0x4d,
10385 0x05, 0xfe, 0x08, 0x0f, 0x01, 0xfe, 0x78, 0x0f, 0xfe, 0xdd, 0x12, 0x05,
10386 0xfe, 0x0e, 0x03, 0xfe, 0x28, 0x1c, 0x03, 0xfe, 0xa6, 0x00, 0xfe, 0xd1,
10387 0x12, 0x3e, 0x22, 0xfe, 0xa6, 0x00, 0xac, 0xfe, 0x48, 0xf0, 0xfe, 0x90,
10388 0x02, 0xfe, 0x49, 0xf0, 0xfe, 0xaa, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xc8,
10389 0x02, 0xfe, 0x46, 0xf0, 0xfe, 0x5a, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x60,
10390 0x02, 0xfe, 0x43, 0xf0, 0xfe, 0x4e, 0x02, 0xfe, 0x44, 0xf0, 0xfe, 0x52,
10391 0x02, 0xfe, 0x45, 0xf0, 0xfe, 0x56, 0x02, 0x1c, 0x0d, 0xa2, 0x1c, 0x07,
10392 0x22, 0xb7, 0x05, 0x35, 0xfe, 0x00, 0x1c, 0xfe, 0xf1, 0x10, 0xfe, 0x02,
10393 0x1c, 0xf5, 0xfe, 0x1e, 0x1c, 0xfe, 0xe9, 0x10, 0x01, 0x5f, 0xfe, 0xe7,
10394 0x10, 0xfe, 0x06, 0xfc, 0xde, 0x0a, 0x81, 0x01, 0xa3, 0x05, 0x35, 0x1f,
10395 0x95, 0x47, 0xb8, 0x01, 0xfe, 0xe4, 0x11, 0x0a, 0x81, 0x01, 0x5c, 0xfe,
10396 0xbd, 0x10, 0x0a, 0x81, 0x01, 0x5c, 0xfe, 0xad, 0x10, 0xfe, 0x16, 0x1c,
10397 0xfe, 0x58, 0x1c, 0x1c, 0x07, 0x22, 0xb7, 0x37, 0x2a, 0x35, 0xfe, 0x3d,
10398 0xf0, 0xfe, 0x0c, 0x02, 0x2b, 0xfe, 0x9e, 0x02, 0xfe, 0x5a, 0x1c, 0xfe,
10399 0x12, 0x1c, 0xfe, 0x14, 0x1c, 0x1f, 0xfe, 0x30, 0x00, 0x47, 0xb8, 0x01,
10400 0xfe, 0xd4, 0x11, 0x1c, 0x07, 0x22, 0xb7, 0x05, 0xe9, 0x21, 0x2c, 0x09,
10401 0x1a, 0x31, 0xfe, 0x69, 0x10, 0x1c, 0x07, 0x22, 0xb7, 0xfe, 0x04, 0xec,
10402 0x2c, 0x60, 0x01, 0xfe, 0x1e, 0x1e, 0x20, 0x2c, 0xfe, 0x05, 0xf6, 0xde,
10403 0x01, 0xfe, 0x62, 0x1b, 0x01, 0x0c, 0x61, 0x4a, 0x44, 0x15, 0x56, 0x51,
10404 0x01, 0xfe, 0x9e, 0x1e, 0x01, 0xfe, 0x96, 0x1a, 0x05, 0x35, 0x0a, 0x57,
10405 0x01, 0x18, 0x09, 0x00, 0x36, 0x01, 0x85, 0xfe, 0x18, 0x10, 0xfe, 0x41,
10406 0x58, 0x0a, 0xba, 0x01, 0x18, 0xfe, 0xc8, 0x54, 0x7b, 0xfe, 0x1c, 0x03,
10407 0x01, 0xfe, 0x96, 0x1a, 0x05, 0x35, 0x37, 0x60, 0xfe, 0x02, 0xe8, 0x30,
10408 0xfe, 0xbf, 0x57, 0xfe, 0x9e, 0x43, 0xfe, 0x77, 0x57, 0xfe, 0x27, 0xf0,
10409 0xfe, 0xe4, 0x01, 0xfe, 0x07, 0x4b, 0xfe, 0x20, 0xf0, 0xbc, 0xfe, 0x40,
10410 0x1c, 0x2a, 0xeb, 0xfe, 0x26, 0xf0, 0xfe, 0x66, 0x03, 0xfe, 0xa0, 0xf0,
10411 0xfe, 0x54, 0x03, 0xfe, 0x11, 0xf0, 0xbc, 0xfe, 0xef, 0x10, 0xfe, 0x9f,
10412 0xf0, 0xfe, 0x74, 0x03, 0xfe, 0x46, 0x1c, 0x19, 0xfe, 0x11, 0x00, 0x05,
10413 0x70, 0x37, 0xfe, 0x48, 0x1c, 0xfe, 0x46, 0x1c, 0x01, 0x0c, 0x06, 0x28,
10414 0xfe, 0x18, 0x13, 0x26, 0x21, 0xb9, 0xc7, 0x20, 0xb9, 0x0a, 0x57, 0x01,
10415 0x18, 0xc7, 0x89, 0x01, 0xfe, 0xc8, 0x1a, 0x15, 0xe1, 0x2a, 0xeb, 0xfe,
10416 0x01, 0xf0, 0xeb, 0xfe, 0x82, 0xf0, 0xfe, 0xa4, 0x03, 0xfe, 0x9c, 0x32,
10417 0x15, 0xfe, 0xe4, 0x00, 0x2f, 0xfe, 0xb6, 0x03, 0x2a, 0x3c, 0x16, 0xfe,
10418 0xc6, 0x03, 0x01, 0x41, 0xfe, 0x06, 0xf0, 0xfe, 0xd6, 0x03, 0xaf, 0xa0,
10419 0xfe, 0x0a, 0xf0, 0xfe, 0xa2, 0x07, 0x05, 0x29, 0x03, 0x81, 0x1e, 0x1b,
10420 0xfe, 0x24, 0x05, 0x1f, 0x63, 0x01, 0x42, 0x8f, 0xfe, 0x70, 0x02, 0x05,
10421 0xea, 0xfe, 0x46, 0x1c, 0x37, 0x7d, 0x1d, 0xfe, 0x67, 0x1b, 0xfe, 0xbf,
10422 0x57, 0xfe, 0x77, 0x57, 0xfe, 0x48, 0x1c, 0x75, 0x01, 0xa6, 0x86, 0x0a,
10423 0x57, 0x01, 0x18, 0x09, 0x00, 0x1b, 0xec, 0x0a, 0xe1, 0x01, 0x18, 0x77,
10424 0x50, 0x40, 0x8d, 0x30, 0x03, 0x81, 0x1e, 0xf8, 0x1f, 0x63, 0x01, 0x42,
10425 0x8f, 0xfe, 0x70, 0x02, 0x05, 0xea, 0xd7, 0x99, 0xd8, 0x9c, 0x2a, 0x29,
10426 0x2f, 0xfe, 0x4e, 0x04, 0x16, 0xfe, 0x4a, 0x04, 0x7e, 0xfe, 0xa0, 0x00,
10427 0xfe, 0x9b, 0x57, 0xfe, 0x54, 0x12, 0x32, 0xff, 0x02, 0x00, 0x10, 0x01,
10428 0x08, 0x16, 0xfe, 0x02, 0x05, 0x32, 0x01, 0x08, 0x16, 0x29, 0x27, 0x25,
10429 0xee, 0xfe, 0x4c, 0x44, 0xfe, 0x58, 0x12, 0x50, 0xfe, 0x44, 0x48, 0x13,
10430 0x34, 0xfe, 0x4c, 0x54, 0x7b, 0xec, 0x60, 0x8d, 0x30, 0x01, 0xfe, 0x4e,
10431 0x1e, 0xfe, 0x48, 0x47, 0xfe, 0x7c, 0x13, 0x01, 0x0c, 0x06, 0x28, 0xfe,
10432 0x32, 0x13, 0x01, 0x43, 0x09, 0x9b, 0xfe, 0x68, 0x13, 0xfe, 0x26, 0x10,
10433 0x13, 0x34, 0xfe, 0x4c, 0x54, 0x7b, 0xec, 0x01, 0xfe, 0x4e, 0x1e, 0xfe,
10434 0x48, 0x47, 0xfe, 0x54, 0x13, 0x01, 0x0c, 0x06, 0x28, 0xa5, 0x01, 0x43,
10435 0x09, 0x9b, 0xfe, 0x40, 0x13, 0x01, 0x0c, 0x06, 0x28, 0xf9, 0x1f, 0x7f,
10436 0x01, 0x0c, 0x06, 0x07, 0x4d, 0x1f, 0xfe, 0x0d, 0x00, 0x01, 0x42, 0x8f,
10437 0xfe, 0xa4, 0x0e, 0x05, 0x29, 0x32, 0x15, 0xfe, 0xe6, 0x00, 0x0f, 0xfe,
10438 0x1c, 0x90, 0x04, 0xfe, 0x9c, 0x93, 0x3a, 0x0b, 0x0e, 0x8b, 0x02, 0x1f,
10439 0x7f, 0x01, 0x42, 0x05, 0x35, 0xfe, 0x42, 0x5b, 0x7d, 0x1d, 0xfe, 0x46,
10440 0x59, 0xfe, 0xbf, 0x57, 0xfe, 0x77, 0x57, 0x0f, 0xfe, 0x87, 0x80, 0x04,
10441 0xfe, 0x87, 0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0xd0, 0x65, 0x01, 0x0c,
10442 0x06, 0x0d, 0xfe, 0x98, 0x13, 0x0f, 0xfe, 0x20, 0x80, 0x04, 0xfe, 0xa0,
10443 0x83, 0x33, 0x0b, 0x0e, 0x09, 0x1d, 0xfe, 0x84, 0x12, 0x01, 0x38, 0x06,
10444 0x07, 0xfe, 0x70, 0x13, 0x03, 0xfe, 0xa2, 0x00, 0x1e, 0x1b, 0xfe, 0xda,
10445 0x05, 0xd0, 0x54, 0x01, 0x38, 0x06, 0x0d, 0xfe, 0x58, 0x13, 0x03, 0xfe,
10446 0xa0, 0x00, 0x1e, 0xfe, 0x50, 0x12, 0x5e, 0xff, 0x02, 0x00, 0x10, 0x2f,
10447 0xfe, 0x90, 0x05, 0x2a, 0x3c, 0xcc, 0xff, 0x02, 0x00, 0x10, 0x2f, 0xfe,
10448 0x9e, 0x05, 0x17, 0xfe, 0xf4, 0x05, 0x15, 0xfe, 0xe3, 0x00, 0x26, 0x01,
10449 0x38, 0xfe, 0x4a, 0xf0, 0xfe, 0xc0, 0x05, 0xfe, 0x49, 0xf0, 0xfe, 0xba,
10450 0x05, 0x71, 0x2e, 0xfe, 0x21, 0x00, 0xf1, 0x2e, 0xfe, 0x22, 0x00, 0xa2,
10451 0x2e, 0x4a, 0xfe, 0x09, 0x48, 0xff, 0x02, 0x00, 0x10, 0x2f, 0xfe, 0xd0,
10452 0x05, 0x17, 0xfe, 0xf4, 0x05, 0xfe, 0xe2, 0x08, 0x01, 0x38, 0x06, 0xfe,
10453 0x1c, 0x00, 0x4d, 0x01, 0xa7, 0x2e, 0x07, 0x20, 0xe4, 0x47, 0xfe, 0x27,
10454 0x01, 0x01, 0x0c, 0x06, 0x28, 0xfe, 0x24, 0x12, 0x3e, 0x01, 0x84, 0x1f,
10455 0x7f, 0x01, 0x0c, 0x06, 0x07, 0x4d, 0x1f, 0xfe, 0x0d, 0x00, 0x01, 0x42,
10456 0x8f, 0xfe, 0xa4, 0x0e, 0x05, 0x29, 0x03, 0xe6, 0x1e, 0xfe, 0xca, 0x13,
10457 0x03, 0xb6, 0x1e, 0xfe, 0x40, 0x12, 0x03, 0x66, 0x1e, 0xfe, 0x38, 0x13,
10458 0x3e, 0x01, 0x84, 0x17, 0xfe, 0x72, 0x06, 0x0a, 0x07, 0x01, 0x38, 0x06,
10459 0x24, 0xfe, 0x02, 0x12, 0x4f, 0x01, 0xfe, 0x56, 0x19, 0x16, 0xfe, 0x68,
10460 0x06, 0x15, 0x82, 0x01, 0x41, 0x15, 0xe2, 0x03, 0x66, 0x8a, 0x10, 0x66,
10461 0x03, 0x9a, 0x1e, 0xfe, 0x70, 0x12, 0x03, 0x55, 0x1e, 0xfe, 0x68, 0x13,
10462 0x01, 0xc6, 0x09, 0x12, 0x48, 0xfe, 0x92, 0x06, 0x2e, 0x12, 0x01, 0xfe,
10463 0xac, 0x1d, 0xfe, 0x43, 0x48, 0x62, 0x80, 0x13, 0x58, 0xff, 0x02, 0x00,
10464 0x57, 0x52, 0xad, 0x23, 0x3f, 0x4e, 0x62, 0x49, 0x3e, 0x01, 0x84, 0x17,
10465 0xfe, 0xea, 0x06, 0x01, 0x38, 0x06, 0x12, 0xf7, 0x45, 0x0a, 0x95, 0x01,
10466 0xfe, 0x84, 0x19, 0x16, 0xfe, 0xe0, 0x06, 0x15, 0x82, 0x01, 0x41, 0x15,
10467 0xe2, 0x03, 0x55, 0x8a, 0x10, 0x55, 0x1c, 0x07, 0x01, 0x84, 0xfe, 0xae,
10468 0x10, 0x03, 0x6f, 0x1e, 0xfe, 0x9e, 0x13, 0x3e, 0x01, 0x84, 0x03, 0x9a,
10469 0x1e, 0xfe, 0x1a, 0x12, 0x01, 0x38, 0x06, 0x12, 0xfc, 0x01, 0xc6, 0x01,
10470 0xfe, 0xac, 0x1d, 0xfe, 0x43, 0x48, 0x62, 0x80, 0xf0, 0x45, 0x0a, 0x95,
10471 0x03, 0xb6, 0x1e, 0xf8, 0x01, 0x38, 0x06, 0x24, 0x36, 0xfe, 0x02, 0xf6,
10472 0x07, 0x71, 0x78, 0x8c, 0x00, 0x4d, 0x62, 0x49, 0x3e, 0x2d, 0x93, 0x4e,
10473 0xd0, 0x0d, 0x17, 0xfe, 0x9a, 0x07, 0x01, 0xfe, 0xc0, 0x19, 0x16, 0xfe,
10474 0x90, 0x07, 0x26, 0x20, 0x9e, 0x15, 0x82, 0x01, 0x41, 0x15, 0xe2, 0x21,
10475 0x9e, 0x09, 0x07, 0xfb, 0x03, 0xe6, 0xfe, 0x58, 0x57, 0x10, 0xe6, 0x05,
10476 0xfe, 0x2a, 0x06, 0x03, 0x6f, 0x8a, 0x10, 0x6f, 0x1c, 0x07, 0x01, 0x84,
10477 0xfe, 0x9c, 0x32, 0x5f, 0x75, 0x01, 0xa6, 0x86, 0x15, 0xfe, 0xe2, 0x00,
10478 0x2f, 0xed, 0x2a, 0x3c, 0xfe, 0x0a, 0xf0, 0xfe, 0xce, 0x07, 0xae, 0xfe,
10479 0x96, 0x08, 0xfe, 0x06, 0xf0, 0xfe, 0x9e, 0x08, 0xaf, 0xa0, 0x05, 0x29,
10480 0x01, 0x0c, 0x06, 0x0d, 0xfe, 0x2e, 0x12, 0x14, 0x1d, 0x01, 0x08, 0x14,
10481 0x00, 0x01, 0x08, 0x14, 0x00, 0x01, 0x08, 0x14, 0x00, 0x01, 0x08, 0xfe,
10482 0x99, 0xa4, 0x01, 0x08, 0x14, 0x00, 0x05, 0xfe, 0xc6, 0x09, 0x01, 0x76,
10483 0x06, 0x12, 0xfe, 0x3a, 0x12, 0x01, 0x0c, 0x06, 0x12, 0xfe, 0x30, 0x13,
10484 0x14, 0xfe, 0x1b, 0x00, 0x01, 0x08, 0x14, 0x00, 0x01, 0x08, 0x14, 0x00,
10485 0x01, 0x08, 0x14, 0x00, 0x01, 0x08, 0x14, 0x07, 0x01, 0x08, 0x14, 0x00,
10486 0x05, 0xef, 0x7c, 0x4a, 0x78, 0x4f, 0x0f, 0xfe, 0x9a, 0x81, 0x04, 0xfe,
10487 0x9a, 0x83, 0xfe, 0xcb, 0x47, 0x0b, 0x0e, 0x2d, 0x28, 0x48, 0xfe, 0x6c,
10488 0x08, 0x0a, 0x28, 0xfe, 0x09, 0x6f, 0xca, 0xfe, 0xca, 0x45, 0xfe, 0x32,
10489 0x12, 0x53, 0x63, 0x4e, 0x7c, 0x97, 0x2f, 0xfe, 0x7e, 0x08, 0x2a, 0x3c,
10490 0xfe, 0x0a, 0xf0, 0xfe, 0x6c, 0x08, 0xaf, 0xa0, 0xae, 0xfe, 0x96, 0x08,
10491 0x05, 0x29, 0x01, 0x41, 0x05, 0xed, 0x14, 0x24, 0x05, 0xed, 0xfe, 0x9c,
10492 0xf7, 0x9f, 0x01, 0xfe, 0xae, 0x1e, 0xfe, 0x18, 0x58, 0x01, 0xfe, 0xbe,
10493 0x1e, 0xfe, 0x99, 0x58, 0xfe, 0x78, 0x18, 0xfe, 0xf9, 0x18, 0x8e, 0xfe,
10494 0x16, 0x09, 0x10, 0x6a, 0x22, 0x6b, 0x01, 0x0c, 0x61, 0x54, 0x44, 0x21,
10495 0x2c, 0x09, 0x1a, 0xf8, 0x77, 0x01, 0xfe, 0x7e, 0x1e, 0x47, 0x2c, 0x7a,
10496 0x30, 0xf0, 0xfe, 0x83, 0xe7, 0xfe, 0x3f, 0x00, 0x71, 0xfe, 0x03, 0x40,
10497 0x01, 0x0c, 0x61, 0x65, 0x44, 0x01, 0xc2, 0xc8, 0xfe, 0x1f, 0x40, 0x20,
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10795 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7, 0x54, 0xb1,
10796 0xfe, 0x72, 0x1b, 0xfe, 0xb2, 0x14, 0xfc, 0xb3, 0x54, 0x7c, 0x12, 0xfe,
10797 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00, 0x02, 0xc9, 0x2b, 0xfe, 0x66, 0x1b,
10798 0xfe, 0x8a, 0x10, 0x1c, 0x1a, 0x87, 0x8b, 0x0f, 0xfe, 0x30, 0x90, 0x04,
10799 0xfe, 0xb0, 0x93, 0x3a, 0x0b, 0xfe, 0x18, 0x58, 0xfe, 0x32, 0x90, 0x04,
10800 0xfe, 0xb2, 0x93, 0x3a, 0x0b, 0xfe, 0x19, 0x58, 0x0e, 0xa8, 0xb3, 0x4a,
10801 0x7c, 0x12, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x4a, 0xb1, 0xfe, 0xc6,
10802 0x1b, 0xfe, 0x5e, 0x14, 0x31, 0x02, 0xc9, 0x2b, 0xfe, 0x96, 0x1b, 0x5c,
10803 0xfe, 0x02, 0xf6, 0x1a, 0x87, 0xfe, 0x18, 0xfe, 0x6a, 0xfe, 0x19, 0xfe,
10804 0x6b, 0x01, 0xfe, 0x1e, 0x1f, 0xfe, 0x1d, 0xf7, 0x65, 0xb1, 0xfe, 0xee,
10805 0x1b, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13, 0xb3, 0x65, 0x3e, 0xfe, 0x83,
10806 0x58, 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7, 0x1a, 0xfe, 0x81, 0xe7, 0x1a,
10807 0x15, 0xfe, 0xdd, 0x00, 0x7a, 0x30, 0x02, 0x7a, 0x30, 0xfe, 0x12, 0x45,
10808 0x2b, 0xfe, 0xdc, 0x1b, 0x1f, 0x07, 0x47, 0xb5, 0xc3, 0x05, 0x35, 0xfe,
10809 0x39, 0xf0, 0x75, 0x26, 0x02, 0xfe, 0x7e, 0x18, 0x23, 0x1d, 0x36, 0x13,
10810 0x11, 0x02, 0x87, 0x03, 0xe3, 0x23, 0x07, 0xfe, 0xef, 0x12, 0xfe, 0xe1,
10811 0x10, 0x90, 0x34, 0x60, 0xfe, 0x02, 0x80, 0x09, 0x56, 0xfe, 0x3c, 0x13,
10812 0xfe, 0x82, 0x14, 0xfe, 0x42, 0x13, 0x51, 0xfe, 0x06, 0x83, 0x0a, 0x5a,
10813 0x01, 0x18, 0xcb, 0xfe, 0x3e, 0x12, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48,
10814 0x01, 0xfe, 0xb2, 0x16, 0xfe, 0x00, 0xcc, 0xcb, 0xfe, 0xf3, 0x13, 0x3f,
10815 0x89, 0x09, 0x1a, 0xa5, 0x0a, 0x9d, 0x01, 0x18, 0xfe, 0x80, 0x4c, 0x01,
10816 0x85, 0xfe, 0x16, 0x10, 0x09, 0x9b, 0x4e, 0xfe, 0x40, 0x14, 0xfe, 0x24,
10817 0x12, 0xfe, 0x14, 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x52, 0x1c, 0x1c, 0x0d,
10818 0x02, 0xfe, 0x9c, 0xe7, 0x0d, 0x19, 0xfe, 0x15, 0x00, 0x40, 0x8d, 0x30,
10819 0x01, 0xf4, 0x1c, 0x07, 0x02, 0x51, 0xfe, 0x06, 0x83, 0xfe, 0x18, 0x80,
10820 0x61, 0x28, 0x44, 0x15, 0x56, 0x01, 0x85, 0x1c, 0x07, 0x02, 0xfe, 0x38,
10821 0x90, 0xfe, 0xba, 0x90, 0x91, 0xde, 0x7e, 0xdf, 0xfe, 0x48, 0x55, 0x31,
10822 0xfe, 0xc9, 0x55, 0x02, 0x21, 0xb9, 0x88, 0x20, 0xb9, 0x02, 0x0a, 0xba,
10823 0x01, 0x18, 0xfe, 0x41, 0x48, 0x0a, 0x57, 0x01, 0x18, 0xfe, 0x49, 0x44,
10824 0x1b, 0xfe, 0x1e, 0x1d, 0x88, 0x89, 0x02, 0x0a, 0x5a, 0x01, 0x18, 0x09,
10825 0x1a, 0xa4, 0x0a, 0x67, 0x01, 0xa3, 0x0a, 0x57, 0x01, 0x18, 0x88, 0x89,
10826 0x02, 0xfe, 0x4e, 0xe4, 0x1d, 0x7b, 0xfe, 0x52, 0x1d, 0x03, 0xfe, 0x90,
10827 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10, 0xfe, 0x4e, 0xe4, 0xdd, 0x7b,
10828 0xfe, 0x64, 0x1d, 0x03, 0xfe, 0x92, 0x00, 0xd1, 0x12, 0xfe, 0x1a, 0x10,
10829 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x7b, 0xfe, 0x76, 0x1d, 0x03, 0xfe,
10830 0x94, 0x00, 0xd1, 0x24, 0xfe, 0x08, 0x10, 0x03, 0xfe, 0x96, 0x00, 0xd1,
10831 0x63, 0xfe, 0x4e, 0x45, 0x83, 0xca, 0xff, 0x04, 0x68, 0x54, 0xfe, 0xf1,
10832 0x10, 0x23, 0x49, 0xfe, 0x08, 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c,
10833 0xfe, 0x1a, 0xf4, 0xfe, 0x00, 0x04, 0x83, 0xb2, 0x1d, 0x48, 0xfe, 0xaa,
10834 0x1d, 0x13, 0x1d, 0x02, 0x09, 0x92, 0xfe, 0x5a, 0xf0, 0xfe, 0xba, 0x1d,
10835 0x2e, 0x93, 0xfe, 0x34, 0x10, 0x09, 0x12, 0xfe, 0x5a, 0xf0, 0xfe, 0xc8,
10836 0x1d, 0x2e, 0xb4, 0xfe, 0x26, 0x10, 0x09, 0x1d, 0x36, 0x2e, 0x63, 0xfe,
10837 0x1a, 0x10, 0x09, 0x0d, 0x36, 0x2e, 0x94, 0xf2, 0x09, 0x07, 0x36, 0x2e,
10838 0x95, 0xa1, 0xc8, 0x02, 0x1f, 0x93, 0x01, 0x42, 0xfe, 0x04, 0xfe, 0x99,
10839 0x03, 0x9c, 0x8b, 0x02, 0x2a, 0xfe, 0x1c, 0x1e, 0xfe, 0x14, 0xf0, 0x08,
10840 0x2f, 0xfe, 0x0c, 0x1e, 0x2a, 0xfe, 0x1c, 0x1e, 0x8f, 0xfe, 0x1c, 0x1e,
10841 0xfe, 0x82, 0xf0, 0xfe, 0x10, 0x1e, 0x02, 0x0f, 0x3f, 0x04, 0xfe, 0x80,
10842 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x18, 0x80, 0x04, 0xfe, 0x98,
10843 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x02, 0x80, 0x04, 0xfe, 0x82,
10844 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06, 0x80, 0x04, 0xfe, 0x86,
10845 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x1b, 0x80, 0x04, 0xfe, 0x9b,
10846 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x04, 0x80, 0x04, 0xfe, 0x84,
10847 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x80, 0x80, 0x04, 0xfe, 0x80,
10848 0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x19, 0x81, 0x04,
10849 0xfe, 0x99, 0x83, 0xfe, 0xca, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06,
10850 0x83, 0x04, 0xfe, 0x86, 0x83, 0xfe, 0xce, 0x47, 0x0b, 0x0e, 0x02, 0x0f,
10851 0xfe, 0x2c, 0x90, 0x04, 0xfe, 0xac, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
10852 0xfe, 0xae, 0x90, 0x04, 0xfe, 0xae, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
10853 0xfe, 0x08, 0x90, 0x04, 0xfe, 0x88, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
10854 0xfe, 0x8a, 0x90, 0x04, 0xfe, 0x8a, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
10855 0xfe, 0x0c, 0x90, 0x04, 0xfe, 0x8c, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
10856 0xfe, 0x8e, 0x90, 0x04, 0xfe, 0x8e, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
10857 0xfe, 0x3c, 0x90, 0x04, 0xfe, 0xbc, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x8b,
10858 0x0f, 0xfe, 0x03, 0x80, 0x04, 0xfe, 0x83, 0x83, 0x33, 0x0b, 0x77, 0x0e,
10859 0xa8, 0x02, 0xff, 0x66, 0x00, 0x00,
10862 static unsigned short _adv_asc38C1600_size = sizeof(_adv_asc38C1600_buf); /* 0x1673 */
10863 static ADV_DCNT _adv_asc38C1600_chksum = 0x0604EF77UL; /* Expanded little-endian checksum. */
10866 * EEPROM Configuration.
10868 * All drivers should use this structure to set the default EEPROM
10869 * configuration. The BIOS now uses this structure when it is built.
10870 * Additional structure information can be found in a_condor.h where
10871 * the structure is defined.
10873 * The *_Field_IsChar structs are needed to correct for endianness.
10874 * These values are read from the board 16 bits at a time directly
10875 * into the structs. Because some fields are char, the values will be
10876 * in the wrong order. The *_Field_IsChar tells when to flip the
10877 * bytes. Data read and written to PCI memory is automatically swapped
10878 * on big-endian platforms so char fields read as words are actually being
10879 * unswapped on big-endian platforms.
10881 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config __devinitdata = {
10882 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
10883 0x0000, /* cfg_msw */
10884 0xFFFF, /* disc_enable */
10885 0xFFFF, /* wdtr_able */
10886 0xFFFF, /* sdtr_able */
10887 0xFFFF, /* start_motor */
10888 0xFFFF, /* tagqng_able */
10889 0xFFFF, /* bios_scan */
10890 0, /* scam_tolerant */
10891 7, /* adapter_scsi_id */
10892 0, /* bios_boot_delay */
10893 3, /* scsi_reset_delay */
10894 0, /* bios_id_lun */
10895 0, /* termination */
10897 0xFFE7, /* bios_ctrl */
10898 0xFFFF, /* ultra_able */
10900 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
10901 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
10904 0, /* serial_number_word1 */
10905 0, /* serial_number_word2 */
10906 0, /* serial_number_word3 */
10908 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
10909 , /* oem_name[16] */
10910 0, /* dvc_err_code */
10911 0, /* adv_err_code */
10912 0, /* adv_err_addr */
10913 0, /* saved_dvc_err_code */
10914 0, /* saved_adv_err_code */
10915 0, /* saved_adv_err_addr */
10919 static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar __devinitdata = {
10922 0, /* -disc_enable */
10925 0, /* start_motor */
10926 0, /* tagqng_able */
10928 0, /* scam_tolerant */
10929 1, /* adapter_scsi_id */
10930 1, /* bios_boot_delay */
10931 1, /* scsi_reset_delay */
10932 1, /* bios_id_lun */
10933 1, /* termination */
10936 0, /* ultra_able */
10938 1, /* max_host_qng */
10939 1, /* max_dvc_qng */
10942 0, /* serial_number_word1 */
10943 0, /* serial_number_word2 */
10944 0, /* serial_number_word3 */
10946 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
10947 , /* oem_name[16] */
10948 0, /* dvc_err_code */
10949 0, /* adv_err_code */
10950 0, /* adv_err_addr */
10951 0, /* saved_dvc_err_code */
10952 0, /* saved_adv_err_code */
10953 0, /* saved_adv_err_addr */
10957 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config __devinitdata = {
10958 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
10959 0x0000, /* 01 cfg_msw */
10960 0xFFFF, /* 02 disc_enable */
10961 0xFFFF, /* 03 wdtr_able */
10962 0x4444, /* 04 sdtr_speed1 */
10963 0xFFFF, /* 05 start_motor */
10964 0xFFFF, /* 06 tagqng_able */
10965 0xFFFF, /* 07 bios_scan */
10966 0, /* 08 scam_tolerant */
10967 7, /* 09 adapter_scsi_id */
10968 0, /* bios_boot_delay */
10969 3, /* 10 scsi_reset_delay */
10970 0, /* bios_id_lun */
10971 0, /* 11 termination_se */
10972 0, /* termination_lvd */
10973 0xFFE7, /* 12 bios_ctrl */
10974 0x4444, /* 13 sdtr_speed2 */
10975 0x4444, /* 14 sdtr_speed3 */
10976 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
10977 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
10978 0, /* 16 dvc_cntl */
10979 0x4444, /* 17 sdtr_speed4 */
10980 0, /* 18 serial_number_word1 */
10981 0, /* 19 serial_number_word2 */
10982 0, /* 20 serial_number_word3 */
10983 0, /* 21 check_sum */
10984 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
10985 , /* 22-29 oem_name[16] */
10986 0, /* 30 dvc_err_code */
10987 0, /* 31 adv_err_code */
10988 0, /* 32 adv_err_addr */
10989 0, /* 33 saved_dvc_err_code */
10990 0, /* 34 saved_adv_err_code */
10991 0, /* 35 saved_adv_err_addr */
10992 0, /* 36 reserved */
10993 0, /* 37 reserved */
10994 0, /* 38 reserved */
10995 0, /* 39 reserved */
10996 0, /* 40 reserved */
10997 0, /* 41 reserved */
10998 0, /* 42 reserved */
10999 0, /* 43 reserved */
11000 0, /* 44 reserved */
11001 0, /* 45 reserved */
11002 0, /* 46 reserved */
11003 0, /* 47 reserved */
11004 0, /* 48 reserved */
11005 0, /* 49 reserved */
11006 0, /* 50 reserved */
11007 0, /* 51 reserved */
11008 0, /* 52 reserved */
11009 0, /* 53 reserved */
11010 0, /* 54 reserved */
11011 0, /* 55 reserved */
11012 0, /* 56 cisptr_lsw */
11013 0, /* 57 cisprt_msw */
11014 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
11015 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */
11016 0, /* 60 reserved */
11017 0, /* 61 reserved */
11018 0, /* 62 reserved */
11019 0 /* 63 reserved */
11022 static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar __devinitdata = {
11023 0, /* 00 cfg_lsw */
11024 0, /* 01 cfg_msw */
11025 0, /* 02 disc_enable */
11026 0, /* 03 wdtr_able */
11027 0, /* 04 sdtr_speed1 */
11028 0, /* 05 start_motor */
11029 0, /* 06 tagqng_able */
11030 0, /* 07 bios_scan */
11031 0, /* 08 scam_tolerant */
11032 1, /* 09 adapter_scsi_id */
11033 1, /* bios_boot_delay */
11034 1, /* 10 scsi_reset_delay */
11035 1, /* bios_id_lun */
11036 1, /* 11 termination_se */
11037 1, /* termination_lvd */
11038 0, /* 12 bios_ctrl */
11039 0, /* 13 sdtr_speed2 */
11040 0, /* 14 sdtr_speed3 */
11041 1, /* 15 max_host_qng */
11042 1, /* max_dvc_qng */
11043 0, /* 16 dvc_cntl */
11044 0, /* 17 sdtr_speed4 */
11045 0, /* 18 serial_number_word1 */
11046 0, /* 19 serial_number_word2 */
11047 0, /* 20 serial_number_word3 */
11048 0, /* 21 check_sum */
11049 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
11050 , /* 22-29 oem_name[16] */
11051 0, /* 30 dvc_err_code */
11052 0, /* 31 adv_err_code */
11053 0, /* 32 adv_err_addr */
11054 0, /* 33 saved_dvc_err_code */
11055 0, /* 34 saved_adv_err_code */
11056 0, /* 35 saved_adv_err_addr */
11057 0, /* 36 reserved */
11058 0, /* 37 reserved */
11059 0, /* 38 reserved */
11060 0, /* 39 reserved */
11061 0, /* 40 reserved */
11062 0, /* 41 reserved */
11063 0, /* 42 reserved */
11064 0, /* 43 reserved */
11065 0, /* 44 reserved */
11066 0, /* 45 reserved */
11067 0, /* 46 reserved */
11068 0, /* 47 reserved */
11069 0, /* 48 reserved */
11070 0, /* 49 reserved */
11071 0, /* 50 reserved */
11072 0, /* 51 reserved */
11073 0, /* 52 reserved */
11074 0, /* 53 reserved */
11075 0, /* 54 reserved */
11076 0, /* 55 reserved */
11077 0, /* 56 cisptr_lsw */
11078 0, /* 57 cisprt_msw */
11079 0, /* 58 subsysvid */
11080 0, /* 59 subsysid */
11081 0, /* 60 reserved */
11082 0, /* 61 reserved */
11083 0, /* 62 reserved */
11084 0 /* 63 reserved */
11087 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config __devinitdata = {
11088 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
11089 0x0000, /* 01 cfg_msw */
11090 0xFFFF, /* 02 disc_enable */
11091 0xFFFF, /* 03 wdtr_able */
11092 0x5555, /* 04 sdtr_speed1 */
11093 0xFFFF, /* 05 start_motor */
11094 0xFFFF, /* 06 tagqng_able */
11095 0xFFFF, /* 07 bios_scan */
11096 0, /* 08 scam_tolerant */
11097 7, /* 09 adapter_scsi_id */
11098 0, /* bios_boot_delay */
11099 3, /* 10 scsi_reset_delay */
11100 0, /* bios_id_lun */
11101 0, /* 11 termination_se */
11102 0, /* termination_lvd */
11103 0xFFE7, /* 12 bios_ctrl */
11104 0x5555, /* 13 sdtr_speed2 */
11105 0x5555, /* 14 sdtr_speed3 */
11106 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
11107 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
11108 0, /* 16 dvc_cntl */
11109 0x5555, /* 17 sdtr_speed4 */
11110 0, /* 18 serial_number_word1 */
11111 0, /* 19 serial_number_word2 */
11112 0, /* 20 serial_number_word3 */
11113 0, /* 21 check_sum */
11114 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
11115 , /* 22-29 oem_name[16] */
11116 0, /* 30 dvc_err_code */
11117 0, /* 31 adv_err_code */
11118 0, /* 32 adv_err_addr */
11119 0, /* 33 saved_dvc_err_code */
11120 0, /* 34 saved_adv_err_code */
11121 0, /* 35 saved_adv_err_addr */
11122 0, /* 36 reserved */
11123 0, /* 37 reserved */
11124 0, /* 38 reserved */
11125 0, /* 39 reserved */
11126 0, /* 40 reserved */
11127 0, /* 41 reserved */
11128 0, /* 42 reserved */
11129 0, /* 43 reserved */
11130 0, /* 44 reserved */
11131 0, /* 45 reserved */
11132 0, /* 46 reserved */
11133 0, /* 47 reserved */
11134 0, /* 48 reserved */
11135 0, /* 49 reserved */
11136 0, /* 50 reserved */
11137 0, /* 51 reserved */
11138 0, /* 52 reserved */
11139 0, /* 53 reserved */
11140 0, /* 54 reserved */
11141 0, /* 55 reserved */
11142 0, /* 56 cisptr_lsw */
11143 0, /* 57 cisprt_msw */
11144 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
11145 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */
11146 0, /* 60 reserved */
11147 0, /* 61 reserved */
11148 0, /* 62 reserved */
11149 0 /* 63 reserved */
11152 static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar __devinitdata = {
11153 0, /* 00 cfg_lsw */
11154 0, /* 01 cfg_msw */
11155 0, /* 02 disc_enable */
11156 0, /* 03 wdtr_able */
11157 0, /* 04 sdtr_speed1 */
11158 0, /* 05 start_motor */
11159 0, /* 06 tagqng_able */
11160 0, /* 07 bios_scan */
11161 0, /* 08 scam_tolerant */
11162 1, /* 09 adapter_scsi_id */
11163 1, /* bios_boot_delay */
11164 1, /* 10 scsi_reset_delay */
11165 1, /* bios_id_lun */
11166 1, /* 11 termination_se */
11167 1, /* termination_lvd */
11168 0, /* 12 bios_ctrl */
11169 0, /* 13 sdtr_speed2 */
11170 0, /* 14 sdtr_speed3 */
11171 1, /* 15 max_host_qng */
11172 1, /* max_dvc_qng */
11173 0, /* 16 dvc_cntl */
11174 0, /* 17 sdtr_speed4 */
11175 0, /* 18 serial_number_word1 */
11176 0, /* 19 serial_number_word2 */
11177 0, /* 20 serial_number_word3 */
11178 0, /* 21 check_sum */
11179 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
11180 , /* 22-29 oem_name[16] */
11181 0, /* 30 dvc_err_code */
11182 0, /* 31 adv_err_code */
11183 0, /* 32 adv_err_addr */
11184 0, /* 33 saved_dvc_err_code */
11185 0, /* 34 saved_adv_err_code */
11186 0, /* 35 saved_adv_err_addr */
11187 0, /* 36 reserved */
11188 0, /* 37 reserved */
11189 0, /* 38 reserved */
11190 0, /* 39 reserved */
11191 0, /* 40 reserved */
11192 0, /* 41 reserved */
11193 0, /* 42 reserved */
11194 0, /* 43 reserved */
11195 0, /* 44 reserved */
11196 0, /* 45 reserved */
11197 0, /* 46 reserved */
11198 0, /* 47 reserved */
11199 0, /* 48 reserved */
11200 0, /* 49 reserved */
11201 0, /* 50 reserved */
11202 0, /* 51 reserved */
11203 0, /* 52 reserved */
11204 0, /* 53 reserved */
11205 0, /* 54 reserved */
11206 0, /* 55 reserved */
11207 0, /* 56 cisptr_lsw */
11208 0, /* 57 cisprt_msw */
11209 0, /* 58 subsysvid */
11210 0, /* 59 subsysid */
11211 0, /* 60 reserved */
11212 0, /* 61 reserved */
11213 0, /* 62 reserved */
11214 0 /* 63 reserved */
11219 * Initialize the ADV_DVC_VAR structure.
11221 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
11223 * For a non-fatal error return a warning code. If there are no warnings
11224 * then 0 is returned.
11226 static int __devinit
11227 AdvInitGetConfig(struct pci_dev *pdev, asc_board_t *boardp)
11229 ADV_DVC_VAR *asc_dvc = &boardp->dvc_var.adv_dvc_var;
11230 unsigned short warn_code = 0;
11231 AdvPortAddr iop_base = asc_dvc->iop_base;
11235 asc_dvc->err_code = 0;
11238 * Save the state of the PCI Configuration Command Register
11239 * "Parity Error Response Control" Bit. If the bit is clear (0),
11240 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
11241 * DMA parity errors.
11243 asc_dvc->cfg->control_flag = 0;
11244 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
11245 if ((cmd & PCI_COMMAND_PARITY) == 0)
11246 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
11248 asc_dvc->cfg->lib_version = (ADV_LIB_VERSION_MAJOR << 8) |
11249 ADV_LIB_VERSION_MINOR;
11250 asc_dvc->cfg->chip_version =
11251 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
11253 ASC_DBG2(1, "AdvInitGetConfig: iopb_chip_id_1: 0x%x 0x%x\n",
11254 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
11255 (ushort)ADV_CHIP_ID_BYTE);
11257 ASC_DBG2(1, "AdvInitGetConfig: iopw_chip_id_0: 0x%x 0x%x\n",
11258 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
11259 (ushort)ADV_CHIP_ID_WORD);
11262 * Reset the chip to start and allow register writes.
11264 if (AdvFindSignature(iop_base) == 0) {
11265 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11269 * The caller must set 'chip_type' to a valid setting.
11271 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
11272 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
11273 asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
11274 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
11281 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
11282 ADV_CTRL_REG_CMD_RESET);
11284 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
11285 ADV_CTRL_REG_CMD_WR_IO_REG);
11287 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
11288 status = AdvInitFrom38C1600EEP(asc_dvc);
11289 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
11290 status = AdvInitFrom38C0800EEP(asc_dvc);
11292 status = AdvInitFrom3550EEP(asc_dvc);
11294 warn_code |= status;
11297 if (warn_code != 0) {
11298 ASC_PRINT2("AdvInitGetConfig: board %d: warning: 0x%x\n",
11299 boardp->id, warn_code);
11302 if (asc_dvc->err_code) {
11303 ASC_PRINT2("AdvInitGetConfig: board %d error: err_code 0x%x\n",
11304 boardp->id, asc_dvc->err_code);
11307 return asc_dvc->err_code;
11311 static void AdvBuildCarrierFreelist(struct adv_dvc_var *asc_dvc)
11314 ADV_SDCNT buf_size;
11315 ADV_PADDR carr_paddr;
11317 BUG_ON(!asc_dvc->carrier_buf);
11319 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
11320 asc_dvc->carr_freelist = NULL;
11321 if (carrp == asc_dvc->carrier_buf) {
11322 buf_size = ADV_CARRIER_BUFSIZE;
11324 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
11328 /* Get physical address of the carrier 'carrp'. */
11329 ADV_DCNT contig_len = sizeof(ADV_CARR_T);
11330 carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL,
11332 (ADV_SDCNT *)&contig_len,
11333 ADV_IS_CARRIER_FLAG));
11335 buf_size -= sizeof(ADV_CARR_T);
11338 * If the current carrier is not physically contiguous, then
11339 * maybe there was a page crossing. Try the next carrier
11340 * aligned start address.
11342 if (contig_len < sizeof(ADV_CARR_T)) {
11347 carrp->carr_pa = carr_paddr;
11348 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
11351 * Insert the carrier at the beginning of the freelist.
11354 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
11355 asc_dvc->carr_freelist = carrp;
11358 } while (buf_size > 0);
11362 * Load the Microcode
11364 * Write the microcode image to RISC memory starting at address 0.
11366 * The microcode is stored compressed in the following format:
11368 * 254 word (508 byte) table indexed by byte code followed
11369 * by the following byte codes:
11372 * 00: Emit word 0 in table.
11373 * 01: Emit word 1 in table.
11375 * FD: Emit word 253 in table.
11378 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
11379 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
11381 * Returns 0 or an error if the checksum doesn't match
11383 static int AdvLoadMicrocode(AdvPortAddr iop_base, unsigned char *buf, int size,
11384 int memsize, int chksum)
11386 int i, j, end, len = 0;
11389 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
11391 for (i = 253 * 2; i < size; i++) {
11392 if (buf[i] == 0xff) {
11393 unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
11394 for (j = 0; j < buf[i + 1]; j++) {
11395 AdvWriteWordAutoIncLram(iop_base, word);
11399 } else if (buf[i] == 0xfe) {
11400 unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
11401 AdvWriteWordAutoIncLram(iop_base, word);
11405 unsigned char off = buf[i] * 2;
11406 unsigned short word = (buf[off + 1] << 8) | buf[off];
11407 AdvWriteWordAutoIncLram(iop_base, word);
11414 while (len < memsize) {
11415 AdvWriteWordAutoIncLram(iop_base, 0);
11419 /* Verify the microcode checksum. */
11421 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
11423 for (len = 0; len < end; len += 2) {
11424 sum += AdvReadWordAutoIncLram(iop_base);
11428 return ASC_IERR_MCODE_CHKSUM;
11434 * Initialize the ASC-3550.
11436 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
11438 * For a non-fatal error return a warning code. If there are no warnings
11439 * then 0 is returned.
11441 * Needed after initialization for error recovery.
11443 static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
11445 AdvPortAddr iop_base;
11454 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
11455 ushort wdtr_able = 0, sdtr_able, tagqng_able;
11456 uchar max_cmd[ADV_MAX_TID + 1];
11458 /* If there is already an error, don't continue. */
11459 if (asc_dvc->err_code != 0)
11463 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
11465 if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
11466 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
11471 iop_base = asc_dvc->iop_base;
11474 * Save the RISC memory BIOS region before writing the microcode.
11475 * The BIOS may already be loaded and using its RISC LRAM region
11476 * so its region must be saved and restored.
11478 * Note: This code makes the assumption, which is currently true,
11479 * that a chip reset does not clear RISC LRAM.
11481 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
11482 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
11487 * Save current per TID negotiated values.
11489 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
11490 ushort bios_version, major, minor;
11493 bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
11494 major = (bios_version >> 12) & 0xF;
11495 minor = (bios_version >> 8) & 0xF;
11496 if (major < 3 || (major == 3 && minor == 1)) {
11497 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
11498 AdvReadWordLram(iop_base, 0x120, wdtr_able);
11500 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
11503 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
11504 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
11505 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
11506 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
11510 asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc3550_buf,
11511 _adv_asc3550_size, ADV_3550_MEMSIZE,
11512 _adv_asc3550_chksum);
11513 if (asc_dvc->err_code)
11517 * Restore the RISC memory BIOS region.
11519 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
11520 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
11525 * Calculate and write the microcode code checksum to the microcode
11526 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
11528 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
11529 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
11531 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
11532 for (word = begin_addr; word < end_addr; word += 2) {
11533 code_sum += AdvReadWordAutoIncLram(iop_base);
11535 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
11538 * Read and save microcode version and date.
11540 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
11541 asc_dvc->cfg->mcode_date);
11542 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
11543 asc_dvc->cfg->mcode_version);
11546 * Set the chip type to indicate the ASC3550.
11548 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
11551 * If the PCI Configuration Command Register "Parity Error Response
11552 * Control" Bit was clear (0), then set the microcode variable
11553 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
11554 * to ignore DMA parity errors.
11556 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
11557 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
11558 word |= CONTROL_FLAG_IGNORE_PERR;
11559 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
11563 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
11564 * threshold of 128 bytes. This register is only accessible to the host.
11566 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
11567 START_CTL_EMFU | READ_CMD_MRM);
11570 * Microcode operating variables for WDTR, SDTR, and command tag
11571 * queuing will be set in slave_configure() based on what a
11572 * device reports it is capable of in Inquiry byte 7.
11574 * If SCSI Bus Resets have been disabled, then directly set
11575 * SDTR and WDTR from the EEPROM configuration. This will allow
11576 * the BIOS and warm boot to work without a SCSI bus hang on
11577 * the Inquiry caused by host and target mismatched DTR values.
11578 * Without the SCSI Bus Reset, before an Inquiry a device can't
11579 * be assumed to be in Asynchronous, Narrow mode.
11581 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
11582 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
11583 asc_dvc->wdtr_able);
11584 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
11585 asc_dvc->sdtr_able);
11589 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
11590 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
11591 * bitmask. These values determine the maximum SDTR speed negotiated
11594 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
11595 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
11596 * without determining here whether the device supports SDTR.
11598 * 4-bit speed SDTR speed name
11599 * =========== ===============
11600 * 0000b (0x0) SDTR disabled
11601 * 0001b (0x1) 5 Mhz
11602 * 0010b (0x2) 10 Mhz
11603 * 0011b (0x3) 20 Mhz (Ultra)
11604 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
11605 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
11606 * 0110b (0x6) Undefined
11608 * 1111b (0xF) Undefined
11611 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
11612 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
11613 /* Set Ultra speed for TID 'tid'. */
11614 word |= (0x3 << (4 * (tid % 4)));
11616 /* Set Fast speed for TID 'tid'. */
11617 word |= (0x2 << (4 * (tid % 4)));
11619 if (tid == 3) { /* Check if done with sdtr_speed1. */
11620 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
11622 } else if (tid == 7) { /* Check if done with sdtr_speed2. */
11623 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
11625 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
11626 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
11628 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
11629 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
11635 * Set microcode operating variable for the disconnect per TID bitmask.
11637 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
11638 asc_dvc->cfg->disc_enable);
11641 * Set SCSI_CFG0 Microcode Default Value.
11643 * The microcode will set the SCSI_CFG0 register using this value
11644 * after it is started below.
11646 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
11647 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
11648 asc_dvc->chip_scsi_id);
11651 * Determine SCSI_CFG1 Microcode Default Value.
11653 * The microcode will set the SCSI_CFG1 register using this value
11654 * after it is started below.
11657 /* Read current SCSI_CFG1 Register value. */
11658 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
11661 * If all three connectors are in use, return an error.
11663 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
11664 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
11665 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
11670 * If the internal narrow cable is reversed all of the SCSI_CTRL
11671 * register signals will be set. Check for and return an error if
11672 * this condition is found.
11674 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
11675 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
11680 * If this is a differential board and a single-ended device
11681 * is attached to one of the connectors, return an error.
11683 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
11684 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
11689 * If automatic termination control is enabled, then set the
11690 * termination value based on a table listed in a_condor.h.
11692 * If manual termination was specified with an EEPROM setting
11693 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
11694 * is ready to be 'ored' into SCSI_CFG1.
11696 if (asc_dvc->cfg->termination == 0) {
11698 * The software always controls termination by setting TERM_CTL_SEL.
11699 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
11701 asc_dvc->cfg->termination |= TERM_CTL_SEL;
11703 switch (scsi_cfg1 & CABLE_DETECT) {
11704 /* TERM_CTL_H: on, TERM_CTL_L: on */
11711 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
11714 /* TERM_CTL_H: on, TERM_CTL_L: off */
11720 asc_dvc->cfg->termination |= TERM_CTL_H;
11723 /* TERM_CTL_H: off, TERM_CTL_L: off */
11731 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
11733 scsi_cfg1 &= ~TERM_CTL;
11736 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
11737 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
11738 * referenced, because the hardware internally inverts
11739 * the Termination High and Low bits if TERM_POL is set.
11741 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
11744 * Set SCSI_CFG1 Microcode Default Value
11746 * Set filter value and possibly modified termination control
11747 * bits in the Microcode SCSI_CFG1 Register Value.
11749 * The microcode will set the SCSI_CFG1 register using this value
11750 * after it is started below.
11752 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
11753 FLTR_DISABLE | scsi_cfg1);
11756 * Set MEM_CFG Microcode Default Value
11758 * The microcode will set the MEM_CFG register using this value
11759 * after it is started below.
11761 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
11764 * ASC-3550 has 8KB internal memory.
11766 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
11767 BIOS_EN | RAM_SZ_8KB);
11770 * Set SEL_MASK Microcode Default Value
11772 * The microcode will set the SEL_MASK register using this value
11773 * after it is started below.
11775 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
11776 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
11778 AdvBuildCarrierFreelist(asc_dvc);
11781 * Set-up the Host->RISC Initiator Command Queue (ICQ).
11784 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
11785 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
11788 asc_dvc->carr_freelist = (ADV_CARR_T *)
11789 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
11792 * The first command issued will be placed in the stopper carrier.
11794 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
11797 * Set RISC ICQ physical address start value.
11799 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
11802 * Set-up the RISC->Host Initiator Response Queue (IRQ).
11804 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
11805 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
11808 asc_dvc->carr_freelist = (ADV_CARR_T *)
11809 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
11812 * The first command completed by the RISC will be placed in
11815 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
11816 * completed the RISC will set the ASC_RQ_STOPPER bit.
11818 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
11821 * Set RISC IRQ physical address start value.
11823 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
11824 asc_dvc->carr_pending_cnt = 0;
11826 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
11827 (ADV_INTR_ENABLE_HOST_INTR |
11828 ADV_INTR_ENABLE_GLOBAL_INTR));
11830 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
11831 AdvWriteWordRegister(iop_base, IOPW_PC, word);
11833 /* finally, finally, gentlemen, start your engine */
11834 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
11837 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
11838 * Resets should be performed. The RISC has to be running
11839 * to issue a SCSI Bus Reset.
11841 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
11843 * If the BIOS Signature is present in memory, restore the
11844 * BIOS Handshake Configuration Table and do not perform
11845 * a SCSI Bus Reset.
11847 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
11850 * Restore per TID negotiated values.
11852 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
11853 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
11854 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
11856 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
11857 AdvWriteByteLram(iop_base,
11858 ASC_MC_NUMBER_OF_MAX_CMD + tid,
11862 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
11863 warn_code = ASC_WARN_BUSRESET_ERROR;
11872 * Initialize the ASC-38C0800.
11874 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
11876 * For a non-fatal error return a warning code. If there are no warnings
11877 * then 0 is returned.
11879 * Needed after initialization for error recovery.
11881 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
11883 AdvPortAddr iop_base;
11893 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
11894 ushort wdtr_able, sdtr_able, tagqng_able;
11895 uchar max_cmd[ADV_MAX_TID + 1];
11897 /* If there is already an error, don't continue. */
11898 if (asc_dvc->err_code != 0)
11902 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
11904 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
11905 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
11910 iop_base = asc_dvc->iop_base;
11913 * Save the RISC memory BIOS region before writing the microcode.
11914 * The BIOS may already be loaded and using its RISC LRAM region
11915 * so its region must be saved and restored.
11917 * Note: This code makes the assumption, which is currently true,
11918 * that a chip reset does not clear RISC LRAM.
11920 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
11921 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
11926 * Save current per TID negotiated values.
11928 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
11929 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
11930 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
11931 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
11932 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
11937 * RAM BIST (RAM Built-In Self Test)
11939 * Address : I/O base + offset 0x38h register (byte).
11940 * Function: Bit 7-6(RW) : RAM mode
11941 * Normal Mode : 0x00
11942 * Pre-test Mode : 0x40
11943 * RAM Test Mode : 0x80
11945 * Bit 4(RO) : Done bit
11946 * Bit 3-0(RO) : Status
11947 * Host Error : 0x08
11948 * Int_RAM Error : 0x04
11949 * RISC Error : 0x02
11950 * SCSI Error : 0x01
11953 * Note: RAM BIST code should be put right here, before loading the
11954 * microcode and after saving the RISC memory BIOS region.
11960 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
11961 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
11962 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
11963 * to NORMAL_MODE, return an error too.
11965 for (i = 0; i < 2; i++) {
11966 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
11967 mdelay(10); /* Wait for 10ms before reading back. */
11968 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
11969 if ((byte & RAM_TEST_DONE) == 0
11970 || (byte & 0x0F) != PRE_TEST_VALUE) {
11971 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
11975 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
11976 mdelay(10); /* Wait for 10ms before reading back. */
11977 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
11979 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
11985 * LRAM Test - It takes about 1.5 ms to run through the test.
11987 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
11988 * If Done bit not set or Status not 0, save register byte, set the
11989 * err_code, and return an error.
11991 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
11992 mdelay(10); /* Wait for 10ms before checking status. */
11994 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
11995 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
11996 /* Get here if Done bit not set or Status not 0. */
11997 asc_dvc->bist_err_code = byte; /* for BIOS display message */
11998 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
12002 /* We need to reset back to normal mode after LRAM test passes. */
12003 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
12005 asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc38C0800_buf,
12006 _adv_asc38C0800_size, ADV_38C0800_MEMSIZE,
12007 _adv_asc38C0800_chksum);
12008 if (asc_dvc->err_code)
12012 * Restore the RISC memory BIOS region.
12014 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
12015 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
12020 * Calculate and write the microcode code checksum to the microcode
12021 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
12023 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
12024 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
12026 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
12027 for (word = begin_addr; word < end_addr; word += 2) {
12028 code_sum += AdvReadWordAutoIncLram(iop_base);
12030 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
12033 * Read microcode version and date.
12035 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
12036 asc_dvc->cfg->mcode_date);
12037 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
12038 asc_dvc->cfg->mcode_version);
12041 * Set the chip type to indicate the ASC38C0800.
12043 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
12046 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
12047 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
12048 * cable detection and then we are able to read C_DET[3:0].
12050 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
12051 * Microcode Default Value' section below.
12053 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
12054 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
12055 scsi_cfg1 | DIS_TERM_DRV);
12058 * If the PCI Configuration Command Register "Parity Error Response
12059 * Control" Bit was clear (0), then set the microcode variable
12060 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
12061 * to ignore DMA parity errors.
12063 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
12064 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
12065 word |= CONTROL_FLAG_IGNORE_PERR;
12066 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
12070 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
12071 * bits for the default FIFO threshold.
12073 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
12075 * For DMA Errata #4 set the BC_THRESH_ENB bit.
12077 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
12078 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
12082 * Microcode operating variables for WDTR, SDTR, and command tag
12083 * queuing will be set in slave_configure() based on what a
12084 * device reports it is capable of in Inquiry byte 7.
12086 * If SCSI Bus Resets have been disabled, then directly set
12087 * SDTR and WDTR from the EEPROM configuration. This will allow
12088 * the BIOS and warm boot to work without a SCSI bus hang on
12089 * the Inquiry caused by host and target mismatched DTR values.
12090 * Without the SCSI Bus Reset, before an Inquiry a device can't
12091 * be assumed to be in Asynchronous, Narrow mode.
12093 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
12094 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
12095 asc_dvc->wdtr_able);
12096 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
12097 asc_dvc->sdtr_able);
12101 * Set microcode operating variables for DISC and SDTR_SPEED1,
12102 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
12103 * configuration values.
12105 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
12106 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
12107 * without determining here whether the device supports SDTR.
12109 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
12110 asc_dvc->cfg->disc_enable);
12111 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
12112 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
12113 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
12114 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
12117 * Set SCSI_CFG0 Microcode Default Value.
12119 * The microcode will set the SCSI_CFG0 register using this value
12120 * after it is started below.
12122 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
12123 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
12124 asc_dvc->chip_scsi_id);
12127 * Determine SCSI_CFG1 Microcode Default Value.
12129 * The microcode will set the SCSI_CFG1 register using this value
12130 * after it is started below.
12133 /* Read current SCSI_CFG1 Register value. */
12134 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
12137 * If the internal narrow cable is reversed all of the SCSI_CTRL
12138 * register signals will be set. Check for and return an error if
12139 * this condition is found.
12141 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
12142 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
12147 * All kind of combinations of devices attached to one of four
12148 * connectors are acceptable except HVD device attached. For example,
12149 * LVD device can be attached to SE connector while SE device attached
12150 * to LVD connector. If LVD device attached to SE connector, it only
12151 * runs up to Ultra speed.
12153 * If an HVD device is attached to one of LVD connectors, return an
12154 * error. However, there is no way to detect HVD device attached to
12157 if (scsi_cfg1 & HVD) {
12158 asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
12163 * If either SE or LVD automatic termination control is enabled, then
12164 * set the termination value based on a table listed in a_condor.h.
12166 * If manual termination was specified with an EEPROM setting then
12167 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
12168 * to be 'ored' into SCSI_CFG1.
12170 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
12171 /* SE automatic termination control is enabled. */
12172 switch (scsi_cfg1 & C_DET_SE) {
12173 /* TERM_SE_HI: on, TERM_SE_LO: on */
12177 asc_dvc->cfg->termination |= TERM_SE;
12180 /* TERM_SE_HI: on, TERM_SE_LO: off */
12182 asc_dvc->cfg->termination |= TERM_SE_HI;
12187 if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
12188 /* LVD automatic termination control is enabled. */
12189 switch (scsi_cfg1 & C_DET_LVD) {
12190 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
12194 asc_dvc->cfg->termination |= TERM_LVD;
12197 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
12204 * Clear any set TERM_SE and TERM_LVD bits.
12206 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
12209 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
12211 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
12214 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
12215 * bits and set possibly modified termination control bits in the
12216 * Microcode SCSI_CFG1 Register Value.
12218 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
12221 * Set SCSI_CFG1 Microcode Default Value
12223 * Set possibly modified termination control and reset DIS_TERM_DRV
12224 * bits in the Microcode SCSI_CFG1 Register Value.
12226 * The microcode will set the SCSI_CFG1 register using this value
12227 * after it is started below.
12229 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
12232 * Set MEM_CFG Microcode Default Value
12234 * The microcode will set the MEM_CFG register using this value
12235 * after it is started below.
12237 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
12240 * ASC-38C0800 has 16KB internal memory.
12242 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
12243 BIOS_EN | RAM_SZ_16KB);
12246 * Set SEL_MASK Microcode Default Value
12248 * The microcode will set the SEL_MASK register using this value
12249 * after it is started below.
12251 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
12252 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
12254 AdvBuildCarrierFreelist(asc_dvc);
12257 * Set-up the Host->RISC Initiator Command Queue (ICQ).
12260 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
12261 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
12264 asc_dvc->carr_freelist = (ADV_CARR_T *)
12265 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
12268 * The first command issued will be placed in the stopper carrier.
12270 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
12273 * Set RISC ICQ physical address start value.
12274 * carr_pa is LE, must be native before write
12276 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
12279 * Set-up the RISC->Host Initiator Response Queue (IRQ).
12281 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
12282 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
12285 asc_dvc->carr_freelist = (ADV_CARR_T *)
12286 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
12289 * The first command completed by the RISC will be placed in
12292 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
12293 * completed the RISC will set the ASC_RQ_STOPPER bit.
12295 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
12298 * Set RISC IRQ physical address start value.
12300 * carr_pa is LE, must be native before write *
12302 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
12303 asc_dvc->carr_pending_cnt = 0;
12305 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
12306 (ADV_INTR_ENABLE_HOST_INTR |
12307 ADV_INTR_ENABLE_GLOBAL_INTR));
12309 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
12310 AdvWriteWordRegister(iop_base, IOPW_PC, word);
12312 /* finally, finally, gentlemen, start your engine */
12313 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
12316 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
12317 * Resets should be performed. The RISC has to be running
12318 * to issue a SCSI Bus Reset.
12320 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
12322 * If the BIOS Signature is present in memory, restore the
12323 * BIOS Handshake Configuration Table and do not perform
12324 * a SCSI Bus Reset.
12326 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
12329 * Restore per TID negotiated values.
12331 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
12332 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
12333 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
12335 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
12336 AdvWriteByteLram(iop_base,
12337 ASC_MC_NUMBER_OF_MAX_CMD + tid,
12341 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
12342 warn_code = ASC_WARN_BUSRESET_ERROR;
12351 * Initialize the ASC-38C1600.
12353 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
12355 * For a non-fatal error return a warning code. If there are no warnings
12356 * then 0 is returned.
12358 * Needed after initialization for error recovery.
12360 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
12362 AdvPortAddr iop_base;
12372 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
12373 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
12374 uchar max_cmd[ASC_MAX_TID + 1];
12376 /* If there is already an error, don't continue. */
12377 if (asc_dvc->err_code != 0) {
12382 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
12384 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
12385 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
12390 iop_base = asc_dvc->iop_base;
12393 * Save the RISC memory BIOS region before writing the microcode.
12394 * The BIOS may already be loaded and using its RISC LRAM region
12395 * so its region must be saved and restored.
12397 * Note: This code makes the assumption, which is currently true,
12398 * that a chip reset does not clear RISC LRAM.
12400 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
12401 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
12406 * Save current per TID negotiated values.
12408 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
12409 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
12410 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
12411 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
12412 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
12413 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
12418 * RAM BIST (Built-In Self Test)
12420 * Address : I/O base + offset 0x38h register (byte).
12421 * Function: Bit 7-6(RW) : RAM mode
12422 * Normal Mode : 0x00
12423 * Pre-test Mode : 0x40
12424 * RAM Test Mode : 0x80
12426 * Bit 4(RO) : Done bit
12427 * Bit 3-0(RO) : Status
12428 * Host Error : 0x08
12429 * Int_RAM Error : 0x04
12430 * RISC Error : 0x02
12431 * SCSI Error : 0x01
12434 * Note: RAM BIST code should be put right here, before loading the
12435 * microcode and after saving the RISC memory BIOS region.
12441 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
12442 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
12443 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
12444 * to NORMAL_MODE, return an error too.
12446 for (i = 0; i < 2; i++) {
12447 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
12448 mdelay(10); /* Wait for 10ms before reading back. */
12449 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
12450 if ((byte & RAM_TEST_DONE) == 0
12451 || (byte & 0x0F) != PRE_TEST_VALUE) {
12452 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
12456 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
12457 mdelay(10); /* Wait for 10ms before reading back. */
12458 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
12460 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
12466 * LRAM Test - It takes about 1.5 ms to run through the test.
12468 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
12469 * If Done bit not set or Status not 0, save register byte, set the
12470 * err_code, and return an error.
12472 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
12473 mdelay(10); /* Wait for 10ms before checking status. */
12475 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
12476 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
12477 /* Get here if Done bit not set or Status not 0. */
12478 asc_dvc->bist_err_code = byte; /* for BIOS display message */
12479 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
12483 /* We need to reset back to normal mode after LRAM test passes. */
12484 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
12486 asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc38C1600_buf,
12487 _adv_asc38C1600_size, ADV_38C1600_MEMSIZE,
12488 _adv_asc38C1600_chksum);
12489 if (asc_dvc->err_code)
12493 * Restore the RISC memory BIOS region.
12495 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
12496 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
12501 * Calculate and write the microcode code checksum to the microcode
12502 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
12504 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
12505 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
12507 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
12508 for (word = begin_addr; word < end_addr; word += 2) {
12509 code_sum += AdvReadWordAutoIncLram(iop_base);
12511 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
12514 * Read microcode version and date.
12516 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
12517 asc_dvc->cfg->mcode_date);
12518 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
12519 asc_dvc->cfg->mcode_version);
12522 * Set the chip type to indicate the ASC38C1600.
12524 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
12527 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
12528 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
12529 * cable detection and then we are able to read C_DET[3:0].
12531 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
12532 * Microcode Default Value' section below.
12534 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
12535 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
12536 scsi_cfg1 | DIS_TERM_DRV);
12539 * If the PCI Configuration Command Register "Parity Error Response
12540 * Control" Bit was clear (0), then set the microcode variable
12541 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
12542 * to ignore DMA parity errors.
12544 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
12545 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
12546 word |= CONTROL_FLAG_IGNORE_PERR;
12547 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
12551 * If the BIOS control flag AIPP (Asynchronous Information
12552 * Phase Protection) disable bit is not set, then set the firmware
12553 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
12554 * AIPP checking and encoding.
12556 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
12557 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
12558 word |= CONTROL_FLAG_ENABLE_AIPP;
12559 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
12563 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
12564 * and START_CTL_TH [3:2].
12566 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
12567 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
12570 * Microcode operating variables for WDTR, SDTR, and command tag
12571 * queuing will be set in slave_configure() based on what a
12572 * device reports it is capable of in Inquiry byte 7.
12574 * If SCSI Bus Resets have been disabled, then directly set
12575 * SDTR and WDTR from the EEPROM configuration. This will allow
12576 * the BIOS and warm boot to work without a SCSI bus hang on
12577 * the Inquiry caused by host and target mismatched DTR values.
12578 * Without the SCSI Bus Reset, before an Inquiry a device can't
12579 * be assumed to be in Asynchronous, Narrow mode.
12581 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
12582 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
12583 asc_dvc->wdtr_able);
12584 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
12585 asc_dvc->sdtr_able);
12589 * Set microcode operating variables for DISC and SDTR_SPEED1,
12590 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
12591 * configuration values.
12593 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
12594 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
12595 * without determining here whether the device supports SDTR.
12597 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
12598 asc_dvc->cfg->disc_enable);
12599 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
12600 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
12601 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
12602 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
12605 * Set SCSI_CFG0 Microcode Default Value.
12607 * The microcode will set the SCSI_CFG0 register using this value
12608 * after it is started below.
12610 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
12611 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
12612 asc_dvc->chip_scsi_id);
12615 * Calculate SCSI_CFG1 Microcode Default Value.
12617 * The microcode will set the SCSI_CFG1 register using this value
12618 * after it is started below.
12620 * Each ASC-38C1600 function has only two cable detect bits.
12621 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
12623 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
12626 * If the cable is reversed all of the SCSI_CTRL register signals
12627 * will be set. Check for and return an error if this condition is
12630 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
12631 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
12636 * Each ASC-38C1600 function has two connectors. Only an HVD device
12637 * can not be connected to either connector. An LVD device or SE device
12638 * may be connected to either connecor. If an SE device is connected,
12639 * then at most Ultra speed (20 Mhz) can be used on both connectors.
12641 * If an HVD device is attached, return an error.
12643 if (scsi_cfg1 & HVD) {
12644 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
12649 * Each function in the ASC-38C1600 uses only the SE cable detect and
12650 * termination because there are two connectors for each function. Each
12651 * function may use either LVD or SE mode. Corresponding the SE automatic
12652 * termination control EEPROM bits are used for each function. Each
12653 * function has its own EEPROM. If SE automatic control is enabled for
12654 * the function, then set the termination value based on a table listed
12657 * If manual termination is specified in the EEPROM for the function,
12658 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
12659 * ready to be 'ored' into SCSI_CFG1.
12661 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
12662 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
12663 /* SE automatic termination control is enabled. */
12664 switch (scsi_cfg1 & C_DET_SE) {
12665 /* TERM_SE_HI: on, TERM_SE_LO: on */
12669 asc_dvc->cfg->termination |= TERM_SE;
12673 if (PCI_FUNC(pdev->devfn) == 0) {
12674 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
12676 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
12677 asc_dvc->cfg->termination |= TERM_SE_HI;
12684 * Clear any set TERM_SE bits.
12686 scsi_cfg1 &= ~TERM_SE;
12689 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
12691 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
12694 * Clear Big Endian and Terminator Polarity bits and set possibly
12695 * modified termination control bits in the Microcode SCSI_CFG1
12698 * Big Endian bit is not used even on big endian machines.
12700 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
12703 * Set SCSI_CFG1 Microcode Default Value
12705 * Set possibly modified termination control bits in the Microcode
12706 * SCSI_CFG1 Register Value.
12708 * The microcode will set the SCSI_CFG1 register using this value
12709 * after it is started below.
12711 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
12714 * Set MEM_CFG Microcode Default Value
12716 * The microcode will set the MEM_CFG register using this value
12717 * after it is started below.
12719 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
12722 * ASC-38C1600 has 32KB internal memory.
12724 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
12725 * out a special 16K Adv Library and Microcode version. After the issue
12726 * resolved, we should turn back to the 32K support. Both a_condor.h and
12727 * mcode.sas files also need to be updated.
12729 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
12730 * BIOS_EN | RAM_SZ_32KB);
12732 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
12733 BIOS_EN | RAM_SZ_16KB);
12736 * Set SEL_MASK Microcode Default Value
12738 * The microcode will set the SEL_MASK register using this value
12739 * after it is started below.
12741 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
12742 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
12744 AdvBuildCarrierFreelist(asc_dvc);
12747 * Set-up the Host->RISC Initiator Command Queue (ICQ).
12749 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
12750 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
12753 asc_dvc->carr_freelist = (ADV_CARR_T *)
12754 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
12757 * The first command issued will be placed in the stopper carrier.
12759 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
12762 * Set RISC ICQ physical address start value. Initialize the
12763 * COMMA register to the same value otherwise the RISC will
12764 * prematurely detect a command is available.
12766 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
12767 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
12768 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
12771 * Set-up the RISC->Host Initiator Response Queue (IRQ).
12773 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
12774 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
12777 asc_dvc->carr_freelist = (ADV_CARR_T *)
12778 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
12781 * The first command completed by the RISC will be placed in
12784 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
12785 * completed the RISC will set the ASC_RQ_STOPPER bit.
12787 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
12790 * Set RISC IRQ physical address start value.
12792 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
12793 asc_dvc->carr_pending_cnt = 0;
12795 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
12796 (ADV_INTR_ENABLE_HOST_INTR |
12797 ADV_INTR_ENABLE_GLOBAL_INTR));
12798 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
12799 AdvWriteWordRegister(iop_base, IOPW_PC, word);
12801 /* finally, finally, gentlemen, start your engine */
12802 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
12805 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
12806 * Resets should be performed. The RISC has to be running
12807 * to issue a SCSI Bus Reset.
12809 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
12811 * If the BIOS Signature is present in memory, restore the
12812 * per TID microcode operating variables.
12814 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
12817 * Restore per TID negotiated values.
12819 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
12820 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
12821 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
12822 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
12824 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
12825 AdvWriteByteLram(iop_base,
12826 ASC_MC_NUMBER_OF_MAX_CMD + tid,
12830 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
12831 warn_code = ASC_WARN_BUSRESET_ERROR;
12840 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
12841 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
12842 * all of this is done.
12844 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
12846 * For a non-fatal error return a warning code. If there are no warnings
12847 * then 0 is returned.
12849 * Note: Chip is stopped on entry.
12851 static int __devinit AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
12853 AdvPortAddr iop_base;
12855 ADVEEP_3550_CONFIG eep_config;
12857 iop_base = asc_dvc->iop_base;
12862 * Read the board's EEPROM configuration.
12864 * Set default values if a bad checksum is found.
12866 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
12867 warn_code |= ASC_WARN_EEPROM_CHKSUM;
12870 * Set EEPROM default values.
12872 memcpy(&eep_config, &Default_3550_EEPROM_Config,
12873 sizeof(ADVEEP_3550_CONFIG));
12876 * Assume the 6 byte board serial number that was read from
12877 * EEPROM is correct even if the EEPROM checksum failed.
12879 eep_config.serial_number_word3 =
12880 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
12882 eep_config.serial_number_word2 =
12883 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
12885 eep_config.serial_number_word1 =
12886 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
12888 AdvSet3550EEPConfig(iop_base, &eep_config);
12891 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
12892 * EEPROM configuration that was read.
12894 * This is the mapping of EEPROM fields to Adv Library fields.
12896 asc_dvc->wdtr_able = eep_config.wdtr_able;
12897 asc_dvc->sdtr_able = eep_config.sdtr_able;
12898 asc_dvc->ultra_able = eep_config.ultra_able;
12899 asc_dvc->tagqng_able = eep_config.tagqng_able;
12900 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
12901 asc_dvc->max_host_qng = eep_config.max_host_qng;
12902 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
12903 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
12904 asc_dvc->start_motor = eep_config.start_motor;
12905 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
12906 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
12907 asc_dvc->no_scam = eep_config.scam_tolerant;
12908 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
12909 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
12910 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
12913 * Set the host maximum queuing (max. 253, min. 16) and the per device
12914 * maximum queuing (max. 63, min. 4).
12916 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
12917 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
12918 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
12919 /* If the value is zero, assume it is uninitialized. */
12920 if (eep_config.max_host_qng == 0) {
12921 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
12923 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
12927 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
12928 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
12929 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
12930 /* If the value is zero, assume it is uninitialized. */
12931 if (eep_config.max_dvc_qng == 0) {
12932 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
12934 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
12939 * If 'max_dvc_qng' is greater than 'max_host_qng', then
12940 * set 'max_dvc_qng' to 'max_host_qng'.
12942 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
12943 eep_config.max_dvc_qng = eep_config.max_host_qng;
12947 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
12948 * values based on possibly adjusted EEPROM values.
12950 asc_dvc->max_host_qng = eep_config.max_host_qng;
12951 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
12954 * If the EEPROM 'termination' field is set to automatic (0), then set
12955 * the ADV_DVC_CFG 'termination' field to automatic also.
12957 * If the termination is specified with a non-zero 'termination'
12958 * value check that a legal value is set and set the ADV_DVC_CFG
12959 * 'termination' field appropriately.
12961 if (eep_config.termination == 0) {
12962 asc_dvc->cfg->termination = 0; /* auto termination */
12964 /* Enable manual control with low off / high off. */
12965 if (eep_config.termination == 1) {
12966 asc_dvc->cfg->termination = TERM_CTL_SEL;
12968 /* Enable manual control with low off / high on. */
12969 } else if (eep_config.termination == 2) {
12970 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
12972 /* Enable manual control with low on / high on. */
12973 } else if (eep_config.termination == 3) {
12974 asc_dvc->cfg->termination =
12975 TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
12978 * The EEPROM 'termination' field contains a bad value. Use
12979 * automatic termination instead.
12981 asc_dvc->cfg->termination = 0;
12982 warn_code |= ASC_WARN_EEPROM_TERMINATION;
12990 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
12991 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
12992 * all of this is done.
12994 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
12996 * For a non-fatal error return a warning code. If there are no warnings
12997 * then 0 is returned.
12999 * Note: Chip is stopped on entry.
13001 static int __devinit AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
13003 AdvPortAddr iop_base;
13005 ADVEEP_38C0800_CONFIG eep_config;
13006 uchar tid, termination;
13007 ushort sdtr_speed = 0;
13009 iop_base = asc_dvc->iop_base;
13014 * Read the board's EEPROM configuration.
13016 * Set default values if a bad checksum is found.
13018 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
13019 eep_config.check_sum) {
13020 warn_code |= ASC_WARN_EEPROM_CHKSUM;
13023 * Set EEPROM default values.
13025 memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
13026 sizeof(ADVEEP_38C0800_CONFIG));
13029 * Assume the 6 byte board serial number that was read from
13030 * EEPROM is correct even if the EEPROM checksum failed.
13032 eep_config.serial_number_word3 =
13033 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
13035 eep_config.serial_number_word2 =
13036 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
13038 eep_config.serial_number_word1 =
13039 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
13041 AdvSet38C0800EEPConfig(iop_base, &eep_config);
13044 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
13045 * EEPROM configuration that was read.
13047 * This is the mapping of EEPROM fields to Adv Library fields.
13049 asc_dvc->wdtr_able = eep_config.wdtr_able;
13050 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
13051 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
13052 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
13053 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
13054 asc_dvc->tagqng_able = eep_config.tagqng_able;
13055 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
13056 asc_dvc->max_host_qng = eep_config.max_host_qng;
13057 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13058 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
13059 asc_dvc->start_motor = eep_config.start_motor;
13060 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
13061 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
13062 asc_dvc->no_scam = eep_config.scam_tolerant;
13063 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
13064 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
13065 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
13068 * For every Target ID if any of its 'sdtr_speed[1234]' bits
13069 * are set, then set an 'sdtr_able' bit for it.
13071 asc_dvc->sdtr_able = 0;
13072 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
13074 sdtr_speed = asc_dvc->sdtr_speed1;
13075 } else if (tid == 4) {
13076 sdtr_speed = asc_dvc->sdtr_speed2;
13077 } else if (tid == 8) {
13078 sdtr_speed = asc_dvc->sdtr_speed3;
13079 } else if (tid == 12) {
13080 sdtr_speed = asc_dvc->sdtr_speed4;
13082 if (sdtr_speed & ADV_MAX_TID) {
13083 asc_dvc->sdtr_able |= (1 << tid);
13089 * Set the host maximum queuing (max. 253, min. 16) and the per device
13090 * maximum queuing (max. 63, min. 4).
13092 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
13093 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13094 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
13095 /* If the value is zero, assume it is uninitialized. */
13096 if (eep_config.max_host_qng == 0) {
13097 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13099 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
13103 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
13104 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13105 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
13106 /* If the value is zero, assume it is uninitialized. */
13107 if (eep_config.max_dvc_qng == 0) {
13108 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13110 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
13115 * If 'max_dvc_qng' is greater than 'max_host_qng', then
13116 * set 'max_dvc_qng' to 'max_host_qng'.
13118 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
13119 eep_config.max_dvc_qng = eep_config.max_host_qng;
13123 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
13124 * values based on possibly adjusted EEPROM values.
13126 asc_dvc->max_host_qng = eep_config.max_host_qng;
13127 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13130 * If the EEPROM 'termination' field is set to automatic (0), then set
13131 * the ADV_DVC_CFG 'termination' field to automatic also.
13133 * If the termination is specified with a non-zero 'termination'
13134 * value check that a legal value is set and set the ADV_DVC_CFG
13135 * 'termination' field appropriately.
13137 if (eep_config.termination_se == 0) {
13138 termination = 0; /* auto termination for SE */
13140 /* Enable manual control with low off / high off. */
13141 if (eep_config.termination_se == 1) {
13144 /* Enable manual control with low off / high on. */
13145 } else if (eep_config.termination_se == 2) {
13146 termination = TERM_SE_HI;
13148 /* Enable manual control with low on / high on. */
13149 } else if (eep_config.termination_se == 3) {
13150 termination = TERM_SE;
13153 * The EEPROM 'termination_se' field contains a bad value.
13154 * Use automatic termination instead.
13157 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13161 if (eep_config.termination_lvd == 0) {
13162 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
13164 /* Enable manual control with low off / high off. */
13165 if (eep_config.termination_lvd == 1) {
13166 asc_dvc->cfg->termination = termination;
13168 /* Enable manual control with low off / high on. */
13169 } else if (eep_config.termination_lvd == 2) {
13170 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
13172 /* Enable manual control with low on / high on. */
13173 } else if (eep_config.termination_lvd == 3) {
13174 asc_dvc->cfg->termination = termination | TERM_LVD;
13177 * The EEPROM 'termination_lvd' field contains a bad value.
13178 * Use automatic termination instead.
13180 asc_dvc->cfg->termination = termination;
13181 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13189 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
13190 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
13191 * all of this is done.
13193 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
13195 * For a non-fatal error return a warning code. If there are no warnings
13196 * then 0 is returned.
13198 * Note: Chip is stopped on entry.
13200 static int __devinit AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
13202 AdvPortAddr iop_base;
13204 ADVEEP_38C1600_CONFIG eep_config;
13205 uchar tid, termination;
13206 ushort sdtr_speed = 0;
13208 iop_base = asc_dvc->iop_base;
13213 * Read the board's EEPROM configuration.
13215 * Set default values if a bad checksum is found.
13217 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
13218 eep_config.check_sum) {
13219 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
13220 warn_code |= ASC_WARN_EEPROM_CHKSUM;
13223 * Set EEPROM default values.
13225 memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
13226 sizeof(ADVEEP_38C1600_CONFIG));
13228 if (PCI_FUNC(pdev->devfn) != 0) {
13231 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
13232 * and old Mac system booting problem. The Expansion
13233 * ROM must be disabled in Function 1 for these systems
13235 eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
13237 * Clear the INTAB (bit 11) if the GPIO 0 input
13238 * indicates the Function 1 interrupt line is wired
13241 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
13242 * 1 - Function 1 interrupt line wired to INT A.
13243 * 0 - Function 1 interrupt line wired to INT B.
13245 * Note: Function 0 is always wired to INTA.
13246 * Put all 5 GPIO bits in input mode and then read
13247 * their input values.
13249 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
13250 ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
13251 if ((ints & 0x01) == 0)
13252 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
13256 * Assume the 6 byte board serial number that was read from
13257 * EEPROM is correct even if the EEPROM checksum failed.
13259 eep_config.serial_number_word3 =
13260 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
13261 eep_config.serial_number_word2 =
13262 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
13263 eep_config.serial_number_word1 =
13264 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
13266 AdvSet38C1600EEPConfig(iop_base, &eep_config);
13270 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
13271 * EEPROM configuration that was read.
13273 * This is the mapping of EEPROM fields to Adv Library fields.
13275 asc_dvc->wdtr_able = eep_config.wdtr_able;
13276 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
13277 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
13278 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
13279 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
13280 asc_dvc->ppr_able = 0;
13281 asc_dvc->tagqng_able = eep_config.tagqng_able;
13282 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
13283 asc_dvc->max_host_qng = eep_config.max_host_qng;
13284 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13285 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
13286 asc_dvc->start_motor = eep_config.start_motor;
13287 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
13288 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
13289 asc_dvc->no_scam = eep_config.scam_tolerant;
13292 * For every Target ID if any of its 'sdtr_speed[1234]' bits
13293 * are set, then set an 'sdtr_able' bit for it.
13295 asc_dvc->sdtr_able = 0;
13296 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
13298 sdtr_speed = asc_dvc->sdtr_speed1;
13299 } else if (tid == 4) {
13300 sdtr_speed = asc_dvc->sdtr_speed2;
13301 } else if (tid == 8) {
13302 sdtr_speed = asc_dvc->sdtr_speed3;
13303 } else if (tid == 12) {
13304 sdtr_speed = asc_dvc->sdtr_speed4;
13306 if (sdtr_speed & ASC_MAX_TID) {
13307 asc_dvc->sdtr_able |= (1 << tid);
13313 * Set the host maximum queuing (max. 253, min. 16) and the per device
13314 * maximum queuing (max. 63, min. 4).
13316 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
13317 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13318 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
13319 /* If the value is zero, assume it is uninitialized. */
13320 if (eep_config.max_host_qng == 0) {
13321 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13323 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
13327 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
13328 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13329 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
13330 /* If the value is zero, assume it is uninitialized. */
13331 if (eep_config.max_dvc_qng == 0) {
13332 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13334 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
13339 * If 'max_dvc_qng' is greater than 'max_host_qng', then
13340 * set 'max_dvc_qng' to 'max_host_qng'.
13342 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
13343 eep_config.max_dvc_qng = eep_config.max_host_qng;
13347 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
13348 * values based on possibly adjusted EEPROM values.
13350 asc_dvc->max_host_qng = eep_config.max_host_qng;
13351 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13354 * If the EEPROM 'termination' field is set to automatic (0), then set
13355 * the ASC_DVC_CFG 'termination' field to automatic also.
13357 * If the termination is specified with a non-zero 'termination'
13358 * value check that a legal value is set and set the ASC_DVC_CFG
13359 * 'termination' field appropriately.
13361 if (eep_config.termination_se == 0) {
13362 termination = 0; /* auto termination for SE */
13364 /* Enable manual control with low off / high off. */
13365 if (eep_config.termination_se == 1) {
13368 /* Enable manual control with low off / high on. */
13369 } else if (eep_config.termination_se == 2) {
13370 termination = TERM_SE_HI;
13372 /* Enable manual control with low on / high on. */
13373 } else if (eep_config.termination_se == 3) {
13374 termination = TERM_SE;
13377 * The EEPROM 'termination_se' field contains a bad value.
13378 * Use automatic termination instead.
13381 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13385 if (eep_config.termination_lvd == 0) {
13386 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
13388 /* Enable manual control with low off / high off. */
13389 if (eep_config.termination_lvd == 1) {
13390 asc_dvc->cfg->termination = termination;
13392 /* Enable manual control with low off / high on. */
13393 } else if (eep_config.termination_lvd == 2) {
13394 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
13396 /* Enable manual control with low on / high on. */
13397 } else if (eep_config.termination_lvd == 3) {
13398 asc_dvc->cfg->termination = termination | TERM_LVD;
13401 * The EEPROM 'termination_lvd' field contains a bad value.
13402 * Use automatic termination instead.
13404 asc_dvc->cfg->termination = termination;
13405 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13413 * Read EEPROM configuration into the specified buffer.
13415 * Return a checksum based on the EEPROM configuration read.
13417 static ushort __devinit
13418 AdvGet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
13420 ushort wval, chksum;
13423 ushort *charfields;
13425 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
13426 wbuf = (ushort *)cfg_buf;
13429 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
13430 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
13431 wval = AdvReadEEPWord(iop_base, eep_addr);
13432 chksum += wval; /* Checksum is calculated from word values. */
13433 if (*charfields++) {
13434 *wbuf = le16_to_cpu(wval);
13439 /* Read checksum word. */
13440 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
13444 /* Read rest of EEPROM not covered by the checksum. */
13445 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
13446 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
13447 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
13448 if (*charfields++) {
13449 *wbuf = le16_to_cpu(*wbuf);
13456 * Read EEPROM configuration into the specified buffer.
13458 * Return a checksum based on the EEPROM configuration read.
13460 static ushort __devinit
13461 AdvGet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf)
13463 ushort wval, chksum;
13466 ushort *charfields;
13468 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
13469 wbuf = (ushort *)cfg_buf;
13472 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
13473 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
13474 wval = AdvReadEEPWord(iop_base, eep_addr);
13475 chksum += wval; /* Checksum is calculated from word values. */
13476 if (*charfields++) {
13477 *wbuf = le16_to_cpu(wval);
13482 /* Read checksum word. */
13483 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
13487 /* Read rest of EEPROM not covered by the checksum. */
13488 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
13489 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
13490 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
13491 if (*charfields++) {
13492 *wbuf = le16_to_cpu(*wbuf);
13499 * Read EEPROM configuration into the specified buffer.
13501 * Return a checksum based on the EEPROM configuration read.
13503 static ushort __devinit
13504 AdvGet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf)
13506 ushort wval, chksum;
13509 ushort *charfields;
13511 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
13512 wbuf = (ushort *)cfg_buf;
13515 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
13516 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
13517 wval = AdvReadEEPWord(iop_base, eep_addr);
13518 chksum += wval; /* Checksum is calculated from word values. */
13519 if (*charfields++) {
13520 *wbuf = le16_to_cpu(wval);
13525 /* Read checksum word. */
13526 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
13530 /* Read rest of EEPROM not covered by the checksum. */
13531 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
13532 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
13533 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
13534 if (*charfields++) {
13535 *wbuf = le16_to_cpu(*wbuf);
13542 * Read the EEPROM from specified location
13544 static ushort __devinit AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
13546 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
13547 ASC_EEP_CMD_READ | eep_word_addr);
13548 AdvWaitEEPCmd(iop_base);
13549 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
13553 * Wait for EEPROM command to complete
13555 static void __devinit AdvWaitEEPCmd(AdvPortAddr iop_base)
13559 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
13560 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
13561 ASC_EEP_CMD_DONE) {
13566 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
13573 * Write the EEPROM from 'cfg_buf'.
13576 AdvSet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
13579 ushort addr, chksum;
13580 ushort *charfields;
13582 wbuf = (ushort *)cfg_buf;
13583 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
13586 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
13587 AdvWaitEEPCmd(iop_base);
13590 * Write EEPROM from word 0 to word 20.
13592 for (addr = ADV_EEP_DVC_CFG_BEGIN;
13593 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
13596 if (*charfields++) {
13597 word = cpu_to_le16(*wbuf);
13601 chksum += *wbuf; /* Checksum is calculated from word values. */
13602 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
13603 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
13604 ASC_EEP_CMD_WRITE | addr);
13605 AdvWaitEEPCmd(iop_base);
13606 mdelay(ADV_EEP_DELAY_MS);
13610 * Write EEPROM checksum at word 21.
13612 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
13613 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
13614 AdvWaitEEPCmd(iop_base);
13619 * Write EEPROM OEM name at words 22 to 29.
13621 for (addr = ADV_EEP_DVC_CTL_BEGIN;
13622 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
13625 if (*charfields++) {
13626 word = cpu_to_le16(*wbuf);
13630 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
13631 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
13632 ASC_EEP_CMD_WRITE | addr);
13633 AdvWaitEEPCmd(iop_base);
13635 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
13636 AdvWaitEEPCmd(iop_base);
13641 * Write the EEPROM from 'cfg_buf'.
13644 AdvSet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf)
13647 ushort *charfields;
13648 ushort addr, chksum;
13650 wbuf = (ushort *)cfg_buf;
13651 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
13654 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
13655 AdvWaitEEPCmd(iop_base);
13658 * Write EEPROM from word 0 to word 20.
13660 for (addr = ADV_EEP_DVC_CFG_BEGIN;
13661 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
13664 if (*charfields++) {
13665 word = cpu_to_le16(*wbuf);
13669 chksum += *wbuf; /* Checksum is calculated from word values. */
13670 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
13671 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
13672 ASC_EEP_CMD_WRITE | addr);
13673 AdvWaitEEPCmd(iop_base);
13674 mdelay(ADV_EEP_DELAY_MS);
13678 * Write EEPROM checksum at word 21.
13680 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
13681 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
13682 AdvWaitEEPCmd(iop_base);
13687 * Write EEPROM OEM name at words 22 to 29.
13689 for (addr = ADV_EEP_DVC_CTL_BEGIN;
13690 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
13693 if (*charfields++) {
13694 word = cpu_to_le16(*wbuf);
13698 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
13699 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
13700 ASC_EEP_CMD_WRITE | addr);
13701 AdvWaitEEPCmd(iop_base);
13703 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
13704 AdvWaitEEPCmd(iop_base);
13709 * Write the EEPROM from 'cfg_buf'.
13712 AdvSet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf)
13715 ushort *charfields;
13716 ushort addr, chksum;
13718 wbuf = (ushort *)cfg_buf;
13719 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
13722 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
13723 AdvWaitEEPCmd(iop_base);
13726 * Write EEPROM from word 0 to word 20.
13728 for (addr = ADV_EEP_DVC_CFG_BEGIN;
13729 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
13732 if (*charfields++) {
13733 word = cpu_to_le16(*wbuf);
13737 chksum += *wbuf; /* Checksum is calculated from word values. */
13738 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
13739 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
13740 ASC_EEP_CMD_WRITE | addr);
13741 AdvWaitEEPCmd(iop_base);
13742 mdelay(ADV_EEP_DELAY_MS);
13746 * Write EEPROM checksum at word 21.
13748 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
13749 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
13750 AdvWaitEEPCmd(iop_base);
13755 * Write EEPROM OEM name at words 22 to 29.
13757 for (addr = ADV_EEP_DVC_CTL_BEGIN;
13758 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
13761 if (*charfields++) {
13762 word = cpu_to_le16(*wbuf);
13766 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
13767 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
13768 ASC_EEP_CMD_WRITE | addr);
13769 AdvWaitEEPCmd(iop_base);
13771 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
13772 AdvWaitEEPCmd(iop_base);
13778 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
13780 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
13781 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
13782 * RISC to notify it a new command is ready to be executed.
13784 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
13785 * set to SCSI_MAX_RETRY.
13787 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
13788 * for DMA addresses or math operations are byte swapped to little-endian
13792 * ADV_SUCCESS(1) - The request was successfully queued.
13793 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
13794 * request completes.
13795 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
13798 static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq)
13800 AdvPortAddr iop_base;
13802 ADV_PADDR req_paddr;
13803 ADV_CARR_T *new_carrp;
13806 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
13808 if (scsiq->target_id > ADV_MAX_TID) {
13809 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
13810 scsiq->done_status = QD_WITH_ERROR;
13814 iop_base = asc_dvc->iop_base;
13817 * Allocate a carrier ensuring at least one carrier always
13818 * remains on the freelist and initialize fields.
13820 if ((new_carrp = asc_dvc->carr_freelist) == NULL) {
13823 asc_dvc->carr_freelist = (ADV_CARR_T *)
13824 ADV_U32_TO_VADDR(le32_to_cpu(new_carrp->next_vpa));
13825 asc_dvc->carr_pending_cnt++;
13828 * Set the carrier to be a stopper by setting 'next_vpa'
13829 * to the stopper value. The current stopper will be changed
13830 * below to point to the new stopper.
13832 new_carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
13835 * Clear the ADV_SCSI_REQ_Q done flag.
13837 scsiq->a_flag &= ~ADV_SCSIQ_DONE;
13839 req_size = sizeof(ADV_SCSI_REQ_Q);
13840 req_paddr = DvcGetPhyAddr(asc_dvc, scsiq, (uchar *)scsiq,
13841 (ADV_SDCNT *)&req_size, ADV_IS_SCSIQ_FLAG);
13843 BUG_ON(req_paddr & 31);
13844 BUG_ON(req_size < sizeof(ADV_SCSI_REQ_Q));
13846 /* Wait for assertion before making little-endian */
13847 req_paddr = cpu_to_le32(req_paddr);
13849 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
13850 scsiq->scsiq_ptr = cpu_to_le32(ADV_VADDR_TO_U32(scsiq));
13851 scsiq->scsiq_rptr = req_paddr;
13853 scsiq->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->icq_sp));
13855 * Every ADV_CARR_T.carr_pa is byte swapped to little-endian
13856 * order during initialization.
13858 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
13861 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
13862 * the microcode. The newly allocated stopper will become the new
13865 asc_dvc->icq_sp->areq_vpa = req_paddr;
13868 * Set the 'next_vpa' pointer for the old stopper to be the
13869 * physical address of the new stopper. The RISC can only
13870 * follow physical addresses.
13872 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
13875 * Set the host adapter stopper pointer to point to the new carrier.
13877 asc_dvc->icq_sp = new_carrp;
13879 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
13880 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
13882 * Tickle the RISC to tell it to read its Command Queue Head pointer.
13884 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
13885 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
13887 * Clear the tickle value. In the ASC-3550 the RISC flag
13888 * command 'clr_tickle_a' does not work unless the host
13889 * value is cleared.
13891 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
13894 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
13896 * Notify the RISC a carrier is ready by writing the physical
13897 * address of the new carrier stopper to the COMMA register.
13899 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
13900 le32_to_cpu(new_carrp->carr_pa));
13903 return ADV_SUCCESS;
13907 * Reset SCSI Bus and purge all outstanding requests.
13910 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
13911 * ADV_FALSE(0) - Microcode command failed.
13912 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
13913 * may be hung which requires driver recovery.
13915 static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
13920 * Send the SCSI Bus Reset idle start idle command which asserts
13921 * the SCSI Bus Reset signal.
13923 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
13924 if (status != ADV_TRUE) {
13929 * Delay for the specified SCSI Bus Reset hold time.
13931 * The hold time delay is done on the host because the RISC has no
13932 * microsecond accurate timer.
13934 udelay(ASC_SCSI_RESET_HOLD_TIME_US);
13937 * Send the SCSI Bus Reset end idle command which de-asserts
13938 * the SCSI Bus Reset signal and purges any pending requests.
13940 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
13941 if (status != ADV_TRUE) {
13945 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
13951 * Reset chip and SCSI Bus.
13954 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
13955 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
13957 static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
13960 ushort wdtr_able, sdtr_able, tagqng_able;
13961 ushort ppr_able = 0;
13962 uchar tid, max_cmd[ADV_MAX_TID + 1];
13963 AdvPortAddr iop_base;
13966 iop_base = asc_dvc->iop_base;
13969 * Save current per TID negotiated values.
13971 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
13972 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
13973 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
13974 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
13976 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
13977 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
13978 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
13983 * Force the AdvInitAsc3550/38C0800Driver() function to
13984 * perform a SCSI Bus Reset by clearing the BIOS signature word.
13985 * The initialization functions assumes a SCSI Bus Reset is not
13986 * needed if the BIOS signature word is present.
13988 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
13989 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
13992 * Stop chip and reset it.
13994 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
13995 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
13997 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
13998 ADV_CTRL_REG_CMD_WR_IO_REG);
14001 * Reset Adv Library error code, if any, and try
14002 * re-initializing the chip.
14004 asc_dvc->err_code = 0;
14005 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
14006 status = AdvInitAsc38C1600Driver(asc_dvc);
14007 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
14008 status = AdvInitAsc38C0800Driver(asc_dvc);
14010 status = AdvInitAsc3550Driver(asc_dvc);
14013 /* Translate initialization return value to status value. */
14017 status = ADV_FALSE;
14021 * Restore the BIOS signature word.
14023 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
14026 * Restore per TID negotiated values.
14028 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
14029 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
14030 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
14031 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
14033 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
14034 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
14035 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
14043 * Adv Library Interrupt Service Routine
14045 * This function is called by a driver's interrupt service routine.
14046 * The function disables and re-enables interrupts.
14048 * When a microcode idle command is completed, the ADV_DVC_VAR
14049 * 'idle_cmd_done' field is set to ADV_TRUE.
14051 * Note: AdvISR() can be called when interrupts are disabled or even
14052 * when there is no hardware interrupt condition present. It will
14053 * always check for completed idle commands and microcode requests.
14054 * This is an important feature that shouldn't be changed because it
14055 * allows commands to be completed from polling mode loops.
14058 * ADV_TRUE(1) - interrupt was pending
14059 * ADV_FALSE(0) - no interrupt was pending
14061 static int AdvISR(ADV_DVC_VAR *asc_dvc)
14063 AdvPortAddr iop_base;
14066 ADV_CARR_T *free_carrp;
14067 ADV_VADDR irq_next_vpa;
14068 ADV_SCSI_REQ_Q *scsiq;
14070 iop_base = asc_dvc->iop_base;
14072 /* Reading the register clears the interrupt. */
14073 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
14075 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
14076 ADV_INTR_STATUS_INTRC)) == 0) {
14081 * Notify the driver of an asynchronous microcode condition by
14082 * calling the adv_async_callback function. The function
14083 * is passed the microcode ASC_MC_INTRB_CODE byte value.
14085 if (int_stat & ADV_INTR_STATUS_INTRB) {
14088 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
14090 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
14091 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
14092 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
14093 asc_dvc->carr_pending_cnt != 0) {
14094 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
14096 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
14097 AdvWriteByteRegister(iop_base,
14104 adv_async_callback(asc_dvc, intrb_code);
14108 * Check if the IRQ stopper carrier contains a completed request.
14110 while (((irq_next_vpa =
14111 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) {
14113 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
14114 * The RISC will have set 'areq_vpa' to a virtual address.
14116 * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
14117 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
14118 * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
14119 * in AdvExeScsiQueue().
14121 scsiq = (ADV_SCSI_REQ_Q *)
14122 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->areq_vpa));
14125 * Request finished with good status and the queue was not
14126 * DMAed to host memory by the firmware. Set all status fields
14127 * to indicate good status.
14129 if ((irq_next_vpa & ASC_RQ_GOOD) != 0) {
14130 scsiq->done_status = QD_NO_ERROR;
14131 scsiq->host_status = scsiq->scsi_status = 0;
14132 scsiq->data_cnt = 0L;
14136 * Advance the stopper pointer to the next carrier
14137 * ignoring the lower four bits. Free the previous
14140 free_carrp = asc_dvc->irq_sp;
14141 asc_dvc->irq_sp = (ADV_CARR_T *)
14142 ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa));
14144 free_carrp->next_vpa =
14145 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
14146 asc_dvc->carr_freelist = free_carrp;
14147 asc_dvc->carr_pending_cnt--;
14149 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
14152 * Clear request microcode control flag.
14157 * Notify the driver of the completed request by passing
14158 * the ADV_SCSI_REQ_Q pointer to its callback function.
14160 scsiq->a_flag |= ADV_SCSIQ_DONE;
14161 adv_isr_callback(asc_dvc, scsiq);
14163 * Note: After the driver callback function is called, 'scsiq'
14164 * can no longer be referenced.
14166 * Fall through and continue processing other completed
14174 * Send an idle command to the chip and wait for completion.
14176 * Command completion is polled for once per microsecond.
14178 * The function can be called from anywhere including an interrupt handler.
14179 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
14180 * functions to prevent reentrancy.
14183 * ADV_TRUE - command completed successfully
14184 * ADV_FALSE - command failed
14185 * ADV_ERROR - command timed out
14188 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
14189 ushort idle_cmd, ADV_DCNT idle_cmd_parameter)
14193 AdvPortAddr iop_base;
14195 iop_base = asc_dvc->iop_base;
14198 * Clear the idle command status which is set by the microcode
14199 * to a non-zero value to indicate when the command is completed.
14200 * The non-zero result is one of the IDLE_CMD_STATUS_* values
14201 * defined in a_advlib.h.
14203 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
14206 * Write the idle command value after the idle command parameter
14207 * has been written to avoid a race condition. If the order is not
14208 * followed, the microcode may process the idle command before the
14209 * parameters have been written to LRAM.
14211 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
14212 cpu_to_le32(idle_cmd_parameter));
14213 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
14216 * Tickle the RISC to tell it to process the idle command.
14218 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
14219 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
14221 * Clear the tickle value. In the ASC-3550 the RISC flag
14222 * command 'clr_tickle_b' does not work unless the host
14223 * value is cleared.
14225 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
14228 /* Wait for up to 100 millisecond for the idle command to timeout. */
14229 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
14230 /* Poll once each microsecond for command completion. */
14231 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
14232 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
14240 BUG(); /* The idle command should never timeout. */
14244 static int __devinit
14245 advansys_wide_init_chip(asc_board_t *boardp, ADV_DVC_VAR *adv_dvc_varp)
14248 adv_req_t *reqp = NULL;
14251 int warn_code, err_code;
14254 * Allocate buffer carrier structures. The total size
14255 * is about 4 KB, so allocate all at once.
14257 boardp->carrp = kmalloc(ADV_CARRIER_BUFSIZE, GFP_KERNEL);
14258 ASC_DBG1(1, "advansys_wide_init_chip: carrp 0x%p\n", boardp->carrp);
14260 if (!boardp->carrp)
14261 goto kmalloc_failed;
14264 * Allocate up to 'max_host_qng' request structures for the Wide
14265 * board. The total size is about 16 KB, so allocate all at once.
14266 * If the allocation fails decrement and try again.
14268 for (req_cnt = adv_dvc_varp->max_host_qng; req_cnt > 0; req_cnt--) {
14269 reqp = kmalloc(sizeof(adv_req_t) * req_cnt, GFP_KERNEL);
14271 ASC_DBG3(1, "advansys_wide_init_chip: reqp 0x%p, req_cnt %d, "
14272 "bytes %lu\n", reqp, req_cnt,
14273 (ulong)sizeof(adv_req_t) * req_cnt);
14280 goto kmalloc_failed;
14282 boardp->orig_reqp = reqp;
14285 * Allocate up to ADV_TOT_SG_BLOCK request structures for
14286 * the Wide board. Each structure is about 136 bytes.
14288 boardp->adv_sgblkp = NULL;
14289 for (sg_cnt = 0; sg_cnt < ADV_TOT_SG_BLOCK; sg_cnt++) {
14290 sgp = kmalloc(sizeof(adv_sgblk_t), GFP_KERNEL);
14295 sgp->next_sgblkp = boardp->adv_sgblkp;
14296 boardp->adv_sgblkp = sgp;
14300 ASC_DBG3(1, "advansys_wide_init_chip: sg_cnt %d * %u = %u bytes\n",
14301 sg_cnt, sizeof(adv_sgblk_t),
14302 (unsigned)(sizeof(adv_sgblk_t) * sg_cnt));
14304 if (!boardp->adv_sgblkp)
14305 goto kmalloc_failed;
14307 adv_dvc_varp->carrier_buf = boardp->carrp;
14310 * Point 'adv_reqp' to the request structures and
14311 * link them together.
14314 reqp[req_cnt].next_reqp = NULL;
14315 for (; req_cnt > 0; req_cnt--) {
14316 reqp[req_cnt - 1].next_reqp = &reqp[req_cnt];
14318 boardp->adv_reqp = &reqp[0];
14320 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
14321 ASC_DBG(2, "advansys_wide_init_chip: AdvInitAsc3550Driver()\n");
14322 warn_code = AdvInitAsc3550Driver(adv_dvc_varp);
14323 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
14324 ASC_DBG(2, "advansys_wide_init_chip: AdvInitAsc38C0800Driver()"
14326 warn_code = AdvInitAsc38C0800Driver(adv_dvc_varp);
14328 ASC_DBG(2, "advansys_wide_init_chip: AdvInitAsc38C1600Driver()"
14330 warn_code = AdvInitAsc38C1600Driver(adv_dvc_varp);
14332 err_code = adv_dvc_varp->err_code;
14334 if (warn_code || err_code) {
14335 ASC_PRINT3("advansys_wide_init_chip: board %d error: warn 0x%x,"
14336 " error 0x%x\n", boardp->id, warn_code, err_code);
14342 ASC_PRINT1("advansys_wide_init_chip: board %d error: kmalloc() "
14343 "failed\n", boardp->id);
14344 err_code = ADV_ERROR;
14349 static void advansys_wide_free_mem(asc_board_t *boardp)
14351 kfree(boardp->carrp);
14352 boardp->carrp = NULL;
14353 kfree(boardp->orig_reqp);
14354 boardp->orig_reqp = boardp->adv_reqp = NULL;
14355 while (boardp->adv_sgblkp) {
14356 adv_sgblk_t *sgp = boardp->adv_sgblkp;
14357 boardp->adv_sgblkp = sgp->next_sgblkp;
14362 static struct Scsi_Host *__devinit
14363 advansys_board_found(int iop, struct device *dev, int bus_type)
14365 struct Scsi_Host *shost;
14366 struct pci_dev *pdev = bus_type == ASC_IS_PCI ? to_pci_dev(dev) : NULL;
14367 asc_board_t *boardp;
14368 ASC_DVC_VAR *asc_dvc_varp = NULL;
14369 ADV_DVC_VAR *adv_dvc_varp = NULL;
14371 int warn_code, err_code;
14375 * Register the adapter, get its configuration, and
14378 ASC_DBG(2, "advansys_board_found: scsi_host_alloc()\n");
14379 shost = scsi_host_alloc(&advansys_template, sizeof(asc_board_t));
14383 /* Initialize private per board data */
14384 boardp = ASC_BOARDP(shost);
14385 memset(boardp, 0, sizeof(asc_board_t));
14386 boardp->id = asc_board_count++;
14387 spin_lock_init(&boardp->lock);
14391 * Handle both narrow and wide boards.
14393 * If a Wide board was detected, set the board structure
14394 * wide board flag. Set-up the board structure based on
14398 if (bus_type == ASC_IS_PCI &&
14399 (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
14400 pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
14401 pdev->device == PCI_DEVICE_ID_38C1600_REV1)) {
14402 boardp->flags |= ASC_IS_WIDE_BOARD;
14404 #endif /* CONFIG_PCI */
14406 if (ASC_NARROW_BOARD(boardp)) {
14407 ASC_DBG(1, "advansys_board_found: narrow board\n");
14408 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
14409 asc_dvc_varp->bus_type = bus_type;
14410 asc_dvc_varp->drv_ptr = boardp;
14411 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
14412 asc_dvc_varp->cfg->overrun_buf = &overrun_buf[0];
14413 asc_dvc_varp->iop_base = iop;
14416 ASC_DBG(1, "advansys_board_found: wide board\n");
14417 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
14418 adv_dvc_varp->drv_ptr = boardp;
14419 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
14420 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
14421 ASC_DBG(1, "advansys_board_found: ASC-3550\n");
14422 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
14423 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
14424 ASC_DBG(1, "advansys_board_found: ASC-38C0800\n");
14425 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
14427 ASC_DBG(1, "advansys_board_found: ASC-38C1600\n");
14428 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
14431 boardp->asc_n_io_port = pci_resource_len(pdev, 1);
14432 boardp->ioremap_addr = ioremap(pci_resource_start(pdev, 1),
14433 boardp->asc_n_io_port);
14434 if (!boardp->ioremap_addr) {
14436 ("advansys_board_found: board %d: ioremap(%x, %d) returned NULL\n",
14437 boardp->id, pci_resource_start(pdev, 1),
14438 boardp->asc_n_io_port);
14441 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr
14442 ASC_DBG1(1, "advansys_board_found: iop_base: 0x%lx\n",
14443 adv_dvc_varp->iop_base);
14446 * Even though it isn't used to access wide boards, other
14447 * than for the debug line below, save I/O Port address so
14448 * that it can be reported.
14450 boardp->ioport = iop;
14452 ASC_DBG2(1, "advansys_board_found: iopb_chip_id_1 0x%x, "
14453 "iopw_chip_id_0 0x%x\n", (ushort)inp(iop + 1),
14454 (ushort)inpw(iop));
14455 #endif /* CONFIG_PCI */
14458 #ifdef CONFIG_PROC_FS
14460 * Allocate buffer for printing information from
14461 * /proc/scsi/advansys/[0...].
14463 boardp->prtbuf = kmalloc(ASC_PRTBUF_SIZE, GFP_KERNEL);
14464 if (!boardp->prtbuf) {
14465 ASC_PRINT2("advansys_board_found: board %d: kmalloc(%d) "
14466 "returned NULL\n", boardp->id, ASC_PRTBUF_SIZE);
14469 #endif /* CONFIG_PROC_FS */
14471 if (ASC_NARROW_BOARD(boardp)) {
14473 * Set the board bus type and PCI IRQ before
14474 * calling AscInitGetConfig().
14476 switch (asc_dvc_varp->bus_type) {
14479 shost->unchecked_isa_dma = TRUE;
14483 shost->unchecked_isa_dma = FALSE;
14487 shost->unchecked_isa_dma = FALSE;
14488 share_irq = IRQF_SHARED;
14490 #endif /* CONFIG_ISA */
14493 shost->irq = asc_dvc_varp->irq_no = pdev->irq;
14494 shost->unchecked_isa_dma = FALSE;
14495 share_irq = IRQF_SHARED;
14497 #endif /* CONFIG_PCI */
14500 ("advansys_board_found: board %d: unknown adapter type: %d\n",
14501 boardp->id, asc_dvc_varp->bus_type);
14502 shost->unchecked_isa_dma = TRUE;
14508 * NOTE: AscInitGetConfig() may change the board's
14509 * bus_type value. The bus_type value should no
14510 * longer be used. If the bus_type field must be
14511 * referenced only use the bit-wise AND operator "&".
14513 ASC_DBG(2, "advansys_board_found: AscInitGetConfig()\n");
14514 err_code = AscInitGetConfig(boardp);
14518 * For Wide boards set PCI information before calling
14519 * AdvInitGetConfig().
14521 shost->irq = adv_dvc_varp->irq_no = pdev->irq;
14522 shost->unchecked_isa_dma = FALSE;
14523 share_irq = IRQF_SHARED;
14524 ASC_DBG(2, "advansys_board_found: AdvInitGetConfig()\n");
14526 err_code = AdvInitGetConfig(pdev, boardp);
14527 #endif /* CONFIG_PCI */
14531 goto err_free_proc;
14534 * Save the EEPROM configuration so that it can be displayed
14535 * from /proc/scsi/advansys/[0...].
14537 if (ASC_NARROW_BOARD(boardp)) {
14542 * Set the adapter's target id bit in the 'init_tidmask' field.
14544 boardp->init_tidmask |=
14545 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
14548 * Save EEPROM settings for the board.
14550 ep = &boardp->eep_config.asc_eep;
14552 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
14553 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
14554 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
14555 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
14556 ep->start_motor = asc_dvc_varp->start_motor;
14557 ep->cntl = asc_dvc_varp->dvc_cntl;
14558 ep->no_scam = asc_dvc_varp->no_scam;
14559 ep->max_total_qng = asc_dvc_varp->max_total_qng;
14560 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
14561 /* 'max_tag_qng' is set to the same value for every device. */
14562 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
14563 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
14564 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
14565 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
14566 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
14567 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
14568 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
14571 * Modify board configuration.
14573 ASC_DBG(2, "advansys_board_found: AscInitSetConfig()\n");
14574 err_code = AscInitSetConfig(pdev, boardp);
14576 goto err_free_proc;
14579 * Finish initializing the 'Scsi_Host' structure.
14581 /* AscInitSetConfig() will set the IRQ for non-PCI boards. */
14582 if ((asc_dvc_varp->bus_type & ASC_IS_PCI) == 0) {
14583 shost->irq = asc_dvc_varp->irq_no;
14586 ADVEEP_3550_CONFIG *ep_3550;
14587 ADVEEP_38C0800_CONFIG *ep_38C0800;
14588 ADVEEP_38C1600_CONFIG *ep_38C1600;
14591 * Save Wide EEP Configuration Information.
14593 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
14594 ep_3550 = &boardp->eep_config.adv_3550_eep;
14596 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
14597 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
14598 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
14599 ep_3550->termination = adv_dvc_varp->cfg->termination;
14600 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
14601 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
14602 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
14603 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
14604 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
14605 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
14606 ep_3550->start_motor = adv_dvc_varp->start_motor;
14607 ep_3550->scsi_reset_delay =
14608 adv_dvc_varp->scsi_reset_wait;
14609 ep_3550->serial_number_word1 =
14610 adv_dvc_varp->cfg->serial1;
14611 ep_3550->serial_number_word2 =
14612 adv_dvc_varp->cfg->serial2;
14613 ep_3550->serial_number_word3 =
14614 adv_dvc_varp->cfg->serial3;
14615 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
14616 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
14618 ep_38C0800->adapter_scsi_id =
14619 adv_dvc_varp->chip_scsi_id;
14620 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
14621 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
14622 ep_38C0800->termination_lvd =
14623 adv_dvc_varp->cfg->termination;
14624 ep_38C0800->disc_enable =
14625 adv_dvc_varp->cfg->disc_enable;
14626 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
14627 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
14628 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
14629 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
14630 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
14631 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
14632 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
14633 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
14634 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
14635 ep_38C0800->scsi_reset_delay =
14636 adv_dvc_varp->scsi_reset_wait;
14637 ep_38C0800->serial_number_word1 =
14638 adv_dvc_varp->cfg->serial1;
14639 ep_38C0800->serial_number_word2 =
14640 adv_dvc_varp->cfg->serial2;
14641 ep_38C0800->serial_number_word3 =
14642 adv_dvc_varp->cfg->serial3;
14644 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
14646 ep_38C1600->adapter_scsi_id =
14647 adv_dvc_varp->chip_scsi_id;
14648 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
14649 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
14650 ep_38C1600->termination_lvd =
14651 adv_dvc_varp->cfg->termination;
14652 ep_38C1600->disc_enable =
14653 adv_dvc_varp->cfg->disc_enable;
14654 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
14655 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
14656 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
14657 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
14658 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
14659 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
14660 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
14661 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
14662 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
14663 ep_38C1600->scsi_reset_delay =
14664 adv_dvc_varp->scsi_reset_wait;
14665 ep_38C1600->serial_number_word1 =
14666 adv_dvc_varp->cfg->serial1;
14667 ep_38C1600->serial_number_word2 =
14668 adv_dvc_varp->cfg->serial2;
14669 ep_38C1600->serial_number_word3 =
14670 adv_dvc_varp->cfg->serial3;
14674 * Set the adapter's target id bit in the 'init_tidmask' field.
14676 boardp->init_tidmask |=
14677 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
14681 * Channels are numbered beginning with 0. For AdvanSys one host
14682 * structure supports one channel. Multi-channel boards have a
14683 * separate host structure for each channel.
14685 shost->max_channel = 0;
14686 if (ASC_NARROW_BOARD(boardp)) {
14687 shost->max_id = ASC_MAX_TID + 1;
14688 shost->max_lun = ASC_MAX_LUN + 1;
14689 shost->max_cmd_len = ASC_MAX_CDB_LEN;
14691 shost->io_port = asc_dvc_varp->iop_base;
14692 boardp->asc_n_io_port = ASC_IOADR_GAP;
14693 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
14695 /* Set maximum number of queues the adapter can handle. */
14696 shost->can_queue = asc_dvc_varp->max_total_qng;
14698 shost->max_id = ADV_MAX_TID + 1;
14699 shost->max_lun = ADV_MAX_LUN + 1;
14700 shost->max_cmd_len = ADV_MAX_CDB_LEN;
14703 * Save the I/O Port address and length even though
14704 * I/O ports are not used to access Wide boards.
14705 * Instead the Wide boards are accessed with
14706 * PCI Memory Mapped I/O.
14708 shost->io_port = iop;
14710 shost->this_id = adv_dvc_varp->chip_scsi_id;
14712 /* Set maximum number of queues the adapter can handle. */
14713 shost->can_queue = adv_dvc_varp->max_host_qng;
14717 * Following v1.3.89, 'cmd_per_lun' is no longer needed
14718 * and should be set to zero.
14720 * But because of a bug introduced in v1.3.89 if the driver is
14721 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
14722 * SCSI function 'allocate_device' will panic. To allow the driver
14723 * to work as a module in these kernels set 'cmd_per_lun' to 1.
14725 * Note: This is wrong. cmd_per_lun should be set to the depth
14726 * you want on untagged devices always.
14729 shost->cmd_per_lun = 1;
14731 shost->cmd_per_lun = 0;
14735 * Set the maximum number of scatter-gather elements the
14736 * adapter can handle.
14738 if (ASC_NARROW_BOARD(boardp)) {
14740 * Allow two commands with 'sg_tablesize' scatter-gather
14741 * elements to be executed simultaneously. This value is
14742 * the theoretical hardware limit. It may be decreased
14745 shost->sg_tablesize =
14746 (((asc_dvc_varp->max_total_qng - 2) / 2) *
14747 ASC_SG_LIST_PER_Q) + 1;
14749 shost->sg_tablesize = ADV_MAX_SG_LIST;
14753 * The value of 'sg_tablesize' can not exceed the SCSI
14754 * mid-level driver definition of SG_ALL. SG_ALL also
14755 * must not be exceeded, because it is used to define the
14756 * size of the scatter-gather table in 'struct asc_sg_head'.
14758 if (shost->sg_tablesize > SG_ALL) {
14759 shost->sg_tablesize = SG_ALL;
14762 ASC_DBG1(1, "advansys_board_found: sg_tablesize: %d\n", shost->sg_tablesize);
14764 /* BIOS start address. */
14765 if (ASC_NARROW_BOARD(boardp)) {
14766 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
14767 asc_dvc_varp->bus_type);
14770 * Fill-in BIOS board variables. The Wide BIOS saves
14771 * information in LRAM that is used by the driver.
14773 AdvReadWordLram(adv_dvc_varp->iop_base,
14774 BIOS_SIGNATURE, boardp->bios_signature);
14775 AdvReadWordLram(adv_dvc_varp->iop_base,
14776 BIOS_VERSION, boardp->bios_version);
14777 AdvReadWordLram(adv_dvc_varp->iop_base,
14778 BIOS_CODESEG, boardp->bios_codeseg);
14779 AdvReadWordLram(adv_dvc_varp->iop_base,
14780 BIOS_CODELEN, boardp->bios_codelen);
14783 "advansys_board_found: bios_signature 0x%x, bios_version 0x%x\n",
14784 boardp->bios_signature, boardp->bios_version);
14787 "advansys_board_found: bios_codeseg 0x%x, bios_codelen 0x%x\n",
14788 boardp->bios_codeseg, boardp->bios_codelen);
14791 * If the BIOS saved a valid signature, then fill in
14792 * the BIOS code segment base address.
14794 if (boardp->bios_signature == 0x55AA) {
14796 * Convert x86 realmode code segment to a linear
14797 * address by shifting left 4.
14799 shost->base = ((ulong)boardp->bios_codeseg << 4);
14806 * Register Board Resources - I/O Port, DMA, IRQ
14809 /* Register DMA Channel for Narrow boards. */
14810 shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
14812 if (ASC_NARROW_BOARD(boardp)) {
14813 /* Register DMA channel for ISA bus. */
14814 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
14815 shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
14816 ret = request_dma(shost->dma_channel, "advansys");
14819 ("advansys_board_found: board %d: request_dma() %d failed %d\n",
14820 boardp->id, shost->dma_channel, ret);
14821 goto err_free_proc;
14823 AscEnableIsaDma(shost->dma_channel);
14826 #endif /* CONFIG_ISA */
14828 /* Register IRQ Number. */
14829 ASC_DBG1(2, "advansys_board_found: request_irq() %d\n", shost->irq);
14831 ret = request_irq(shost->irq, advansys_interrupt, share_irq,
14832 "advansys", shost);
14835 if (ret == -EBUSY) {
14837 ("advansys_board_found: board %d: request_irq(): IRQ 0x%x already in use.\n",
14838 boardp->id, shost->irq);
14839 } else if (ret == -EINVAL) {
14841 ("advansys_board_found: board %d: request_irq(): IRQ 0x%x not valid.\n",
14842 boardp->id, shost->irq);
14845 ("advansys_board_found: board %d: request_irq(): IRQ 0x%x failed with %d\n",
14846 boardp->id, shost->irq, ret);
14852 * Initialize board RISC chip and enable interrupts.
14854 if (ASC_NARROW_BOARD(boardp)) {
14855 ASC_DBG(2, "advansys_board_found: AscInitAsc1000Driver()\n");
14856 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
14857 err_code = asc_dvc_varp->err_code;
14859 if (warn_code || err_code) {
14861 ("advansys_board_found: board %d error: init_state 0x%x, warn 0x%x, error 0x%x\n",
14863 asc_dvc_varp->init_state, warn_code, err_code);
14866 err_code = advansys_wide_init_chip(boardp, adv_dvc_varp);
14870 goto err_free_wide_mem;
14872 ASC_DBG_PRT_SCSI_HOST(2, shost);
14874 ret = scsi_add_host(shost, dev);
14876 goto err_free_wide_mem;
14878 scsi_scan_host(shost);
14882 advansys_wide_free_mem(boardp);
14883 free_irq(shost->irq, shost);
14885 if (shost->dma_channel != NO_ISA_DMA)
14886 free_dma(shost->dma_channel);
14888 kfree(boardp->prtbuf);
14890 if (boardp->ioremap_addr)
14891 iounmap(boardp->ioremap_addr);
14893 scsi_host_put(shost);
14898 * advansys_release()
14900 * Release resources allocated for a single AdvanSys adapter.
14902 static int advansys_release(struct Scsi_Host *shost)
14904 asc_board_t *boardp;
14906 ASC_DBG(1, "advansys_release: begin\n");
14907 scsi_remove_host(shost);
14908 boardp = ASC_BOARDP(shost);
14909 free_irq(shost->irq, shost);
14910 if (shost->dma_channel != NO_ISA_DMA) {
14911 ASC_DBG(1, "advansys_release: free_dma()\n");
14912 free_dma(shost->dma_channel);
14914 if (ASC_WIDE_BOARD(boardp)) {
14915 iounmap(boardp->ioremap_addr);
14916 advansys_wide_free_mem(boardp);
14918 kfree(boardp->prtbuf);
14919 scsi_host_put(shost);
14920 ASC_DBG(1, "advansys_release: end\n");
14924 static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] __devinitdata = {
14925 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
14926 0x0210, 0x0230, 0x0250, 0x0330
14929 static int __devinit advansys_isa_probe(struct device *dev, unsigned int id)
14931 PortAddr iop_base = _asc_def_iop_base[id];
14932 struct Scsi_Host *shost;
14934 if (!request_region(iop_base, ASC_IOADR_GAP, "advansys")) {
14935 ASC_DBG1(1, "advansys_isa_match: I/O port 0x%x busy\n",
14939 ASC_DBG1(1, "advansys_isa_match: probing I/O port 0x%x\n", iop_base);
14940 if (!AscFindSignature(iop_base))
14942 if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT))
14945 shost = advansys_board_found(iop_base, dev, ASC_IS_ISA);
14949 dev_set_drvdata(dev, shost);
14953 release_region(iop_base, ASC_IOADR_GAP);
14957 static int __devexit advansys_isa_remove(struct device *dev, unsigned int id)
14959 int ioport = _asc_def_iop_base[id];
14960 advansys_release(dev_get_drvdata(dev));
14961 release_region(ioport, ASC_IOADR_GAP);
14965 static struct isa_driver advansys_isa_driver = {
14966 .probe = advansys_isa_probe,
14967 .remove = __devexit_p(advansys_isa_remove),
14969 .owner = THIS_MODULE,
14970 .name = "advansys",
14974 static int __devinit advansys_vlb_probe(struct device *dev, unsigned int id)
14976 PortAddr iop_base = _asc_def_iop_base[id];
14977 struct Scsi_Host *shost;
14979 if (!request_region(iop_base, ASC_IOADR_GAP, "advansys")) {
14980 ASC_DBG1(1, "advansys_vlb_match: I/O port 0x%x busy\n",
14984 ASC_DBG1(1, "advansys_vlb_match: probing I/O port 0x%x\n", iop_base);
14985 if (!AscFindSignature(iop_base))
14988 * I don't think this condition can actually happen, but the old
14989 * driver did it, and the chances of finding a VLB setup in 2007
14990 * to do testing with is slight to none.
14992 if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
14995 shost = advansys_board_found(iop_base, dev, ASC_IS_VL);
14999 dev_set_drvdata(dev, shost);
15003 release_region(iop_base, ASC_IOADR_GAP);
15007 static struct isa_driver advansys_vlb_driver = {
15008 .probe = advansys_vlb_probe,
15009 .remove = __devexit_p(advansys_isa_remove),
15011 .owner = THIS_MODULE,
15012 .name = "advansys_vlb",
15016 static struct eisa_device_id advansys_eisa_table[] __devinitdata = {
15022 MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
15025 * EISA is a little more tricky than PCI; each EISA device may have two
15026 * channels, and this driver is written to make each channel its own Scsi_Host
15028 struct eisa_scsi_data {
15029 struct Scsi_Host *host[2];
15032 static int __devinit advansys_eisa_probe(struct device *dev)
15036 struct eisa_device *edev = to_eisa_device(dev);
15037 struct eisa_scsi_data *data;
15040 data = kzalloc(sizeof(*data), GFP_KERNEL);
15043 ioport = edev->base_addr + 0xc30;
15046 for (i = 0; i < 2; i++, ioport += 0x20) {
15047 if (!request_region(ioport, ASC_IOADR_GAP, "advansys")) {
15048 printk(KERN_WARNING "Region %x-%x busy\n", ioport,
15049 ioport + ASC_IOADR_GAP - 1);
15052 if (!AscFindSignature(ioport)) {
15053 release_region(ioport, ASC_IOADR_GAP);
15058 * I don't know why we need to do this for EISA chips, but
15059 * not for any others. It looks to be equivalent to
15060 * AscGetChipCfgMsw, but I may have overlooked something,
15061 * so I'm not converting it until I get an EISA board to
15065 data->host[i] = advansys_board_found(ioport, dev, ASC_IS_EISA);
15066 if (data->host[i]) {
15069 release_region(ioport, ASC_IOADR_GAP);
15076 dev_set_drvdata(dev, data);
15083 static __devexit int advansys_eisa_remove(struct device *dev)
15086 struct eisa_scsi_data *data = dev_get_drvdata(dev);
15088 for (i = 0; i < 2; i++) {
15090 struct Scsi_Host *shost = data->host[i];
15093 ioport = shost->io_port;
15094 advansys_release(shost);
15095 release_region(ioport, ASC_IOADR_GAP);
15102 static struct eisa_driver advansys_eisa_driver = {
15103 .id_table = advansys_eisa_table,
15105 .name = "advansys",
15106 .probe = advansys_eisa_probe,
15107 .remove = __devexit_p(advansys_eisa_remove),
15111 /* PCI Devices supported by this driver */
15112 static struct pci_device_id advansys_pci_tbl[] __devinitdata = {
15113 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
15114 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
15115 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
15116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
15117 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
15118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
15119 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
15120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
15121 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
15122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
15123 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
15124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
15128 MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
15130 static void __devinit advansys_set_latency(struct pci_dev *pdev)
15132 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
15133 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
15134 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
15137 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
15138 if (latency < 0x20)
15139 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
15143 static int __devinit
15144 advansys_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
15147 struct Scsi_Host *shost;
15149 err = pci_enable_device(pdev);
15152 err = pci_request_regions(pdev, "advansys");
15154 goto disable_device;
15155 pci_set_master(pdev);
15156 advansys_set_latency(pdev);
15158 if (pci_resource_len(pdev, 0) == 0)
15161 ioport = pci_resource_start(pdev, 0);
15162 shost = advansys_board_found(ioport, &pdev->dev, ASC_IS_PCI);
15167 pci_set_drvdata(pdev, shost);
15172 pci_release_regions(pdev);
15174 pci_disable_device(pdev);
15179 static void __devexit advansys_pci_remove(struct pci_dev *pdev)
15181 advansys_release(pci_get_drvdata(pdev));
15182 pci_release_regions(pdev);
15183 pci_disable_device(pdev);
15186 static struct pci_driver advansys_pci_driver = {
15187 .name = "advansys",
15188 .id_table = advansys_pci_tbl,
15189 .probe = advansys_pci_probe,
15190 .remove = __devexit_p(advansys_pci_remove),
15193 static int __init advansys_init(void)
15197 error = isa_register_driver(&advansys_isa_driver,
15198 ASC_IOADR_TABLE_MAX_IX);
15202 error = isa_register_driver(&advansys_vlb_driver,
15203 ASC_IOADR_TABLE_MAX_IX);
15205 goto unregister_isa;
15207 error = eisa_driver_register(&advansys_eisa_driver);
15209 goto unregister_vlb;
15211 error = pci_register_driver(&advansys_pci_driver);
15213 goto unregister_eisa;
15218 eisa_driver_unregister(&advansys_eisa_driver);
15220 isa_unregister_driver(&advansys_vlb_driver);
15222 isa_unregister_driver(&advansys_isa_driver);
15227 static void __exit advansys_exit(void)
15229 pci_unregister_driver(&advansys_pci_driver);
15230 eisa_driver_unregister(&advansys_eisa_driver);
15231 isa_unregister_driver(&advansys_vlb_driver);
15232 isa_unregister_driver(&advansys_isa_driver);
15235 module_init(advansys_init);
15236 module_exit(advansys_exit);
15238 MODULE_LICENSE("GPL");