2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
13 #include <acpi/acpi_hest.h>
16 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
17 #define CARDBUS_RESERVE_BUSNR 3
19 /* Ugh. Need to stop exporting this to modules. */
20 LIST_HEAD(pci_root_buses);
21 EXPORT_SYMBOL(pci_root_buses);
24 static int find_anything(struct device *dev, void *data)
30 * Some device drivers need know if pci is initiated.
31 * Basically, we think pci is not initiated when there
32 * is no device to be found on the pci_bus_type.
34 int no_pci_devices(void)
39 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
40 no_devices = (dev == NULL);
44 EXPORT_SYMBOL(no_pci_devices);
47 * PCI Bus Class Devices
49 static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
51 struct device_attribute *attr,
55 const struct cpumask *cpumask;
57 cpumask = cpumask_of_pcibus(to_pci_bus(dev));
59 cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask) :
60 cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask);
66 static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev,
67 struct device_attribute *attr,
70 return pci_bus_show_cpuaffinity(dev, 0, attr, buf);
73 static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev,
74 struct device_attribute *attr,
77 return pci_bus_show_cpuaffinity(dev, 1, attr, buf);
80 DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL);
81 DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL);
86 static void release_pcibus_dev(struct device *dev)
88 struct pci_bus *pci_bus = to_pci_bus(dev);
91 put_device(pci_bus->bridge);
95 static struct class pcibus_class = {
97 .dev_release = &release_pcibus_dev,
100 static int __init pcibus_class_init(void)
102 return class_register(&pcibus_class);
104 postcore_initcall(pcibus_class_init);
107 * Translate the low bits of the PCI base
108 * to the resource type
110 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
112 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
113 return IORESOURCE_IO;
115 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
116 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
118 return IORESOURCE_MEM;
121 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
123 u64 size = mask & maxbase; /* Find the significant bits */
127 /* Get the lowest of them to find the decode size, and
128 from that the extent. */
129 size = (size & ~(size-1)) - 1;
131 /* base == maxbase can be valid only if the BAR has
132 already been programmed with all 1s. */
133 if (base == maxbase && ((base | size) & mask) != mask)
139 static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
141 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
142 res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
146 res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
148 if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
149 return pci_bar_mem64;
150 return pci_bar_mem32;
154 * pci_read_base - read a PCI BAR
155 * @dev: the PCI device
156 * @type: type of the BAR
157 * @res: resource buffer to be filled in
158 * @pos: BAR position in the config space
160 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
162 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
163 struct resource *res, unsigned int pos)
167 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
169 res->name = pci_name(dev);
171 pci_read_config_dword(dev, pos, &l);
172 pci_write_config_dword(dev, pos, l | mask);
173 pci_read_config_dword(dev, pos, &sz);
174 pci_write_config_dword(dev, pos, l);
177 * All bits set in sz means the device isn't working properly.
178 * If the BAR isn't implemented, all bits must be 0. If it's a
179 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
182 if (!sz || sz == 0xffffffff)
186 * I don't know how l can have all bits set. Copied from old code.
187 * Maybe it fixes a bug on some ancient platform.
192 if (type == pci_bar_unknown) {
193 type = decode_bar(res, l);
194 res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
195 if (type == pci_bar_io) {
196 l &= PCI_BASE_ADDRESS_IO_MASK;
197 mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT;
199 l &= PCI_BASE_ADDRESS_MEM_MASK;
200 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
203 res->flags |= (l & IORESOURCE_ROM_ENABLE);
204 l &= PCI_ROM_ADDRESS_MASK;
205 mask = (u32)PCI_ROM_ADDRESS_MASK;
208 if (type == pci_bar_mem64) {
211 u64 mask64 = mask | (u64)~0 << 32;
213 pci_read_config_dword(dev, pos + 4, &l);
214 pci_write_config_dword(dev, pos + 4, ~0);
215 pci_read_config_dword(dev, pos + 4, &sz);
216 pci_write_config_dword(dev, pos + 4, l);
218 l64 |= ((u64)l << 32);
219 sz64 |= ((u64)sz << 32);
221 sz64 = pci_size(l64, sz64, mask64);
226 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
227 dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n",
232 res->flags |= IORESOURCE_MEM_64;
233 if ((sizeof(resource_size_t) < 8) && l) {
234 /* Address above 32-bit boundary; disable the BAR */
235 pci_write_config_dword(dev, pos, 0);
236 pci_write_config_dword(dev, pos + 4, 0);
241 res->end = l64 + sz64;
242 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n",
246 sz = pci_size(l, sz, mask);
254 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res);
258 return (type == pci_bar_mem64) ? 1 : 0;
264 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
266 unsigned int pos, reg;
268 for (pos = 0; pos < howmany; pos++) {
269 struct resource *res = &dev->resource[pos];
270 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
271 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
275 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
276 dev->rom_base_reg = rom;
277 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
278 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
279 IORESOURCE_SIZEALIGN;
280 __pci_read_base(dev, pci_bar_mem32, res, rom);
284 static void __devinit pci_read_bridge_io(struct pci_bus *child)
286 struct pci_dev *dev = child->self;
287 u8 io_base_lo, io_limit_lo;
288 unsigned long base, limit;
289 struct resource *res;
291 res = child->resource[0];
292 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
293 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
294 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
295 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
297 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
298 u16 io_base_hi, io_limit_hi;
299 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
300 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
301 base |= (io_base_hi << 16);
302 limit |= (io_limit_hi << 16);
305 if (base && base <= limit) {
306 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
310 res->end = limit + 0xfff;
311 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
313 dev_printk(KERN_DEBUG, &dev->dev,
314 " bridge window [io %04lx - %04lx] reg reading\n",
319 static void __devinit pci_read_bridge_mmio(struct pci_bus *child)
321 struct pci_dev *dev = child->self;
322 u16 mem_base_lo, mem_limit_lo;
323 unsigned long base, limit;
324 struct resource *res;
326 res = child->resource[1];
327 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
328 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
329 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
330 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
331 if (base && base <= limit) {
332 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
334 res->end = limit + 0xfffff;
335 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
337 dev_printk(KERN_DEBUG, &dev->dev,
338 " bridge window [mem 0x%08lx - 0x%08lx] reg reading\n",
339 base, limit + 0xfffff);
343 static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child)
345 struct pci_dev *dev = child->self;
346 u16 mem_base_lo, mem_limit_lo;
347 unsigned long base, limit;
348 struct resource *res;
350 res = child->resource[2];
351 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
352 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
353 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
354 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
356 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
357 u32 mem_base_hi, mem_limit_hi;
358 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
359 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
362 * Some bridges set the base > limit by default, and some
363 * (broken) BIOSes do not initialize them. If we find
364 * this, just assume they are not being used.
366 if (mem_base_hi <= mem_limit_hi) {
367 #if BITS_PER_LONG == 64
368 base |= ((long) mem_base_hi) << 32;
369 limit |= ((long) mem_limit_hi) << 32;
371 if (mem_base_hi || mem_limit_hi) {
372 dev_err(&dev->dev, "can't handle 64-bit "
373 "address space for bridge\n");
379 if (base && base <= limit) {
380 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
381 IORESOURCE_MEM | IORESOURCE_PREFETCH;
382 if (res->flags & PCI_PREF_RANGE_TYPE_64)
383 res->flags |= IORESOURCE_MEM_64;
385 res->end = limit + 0xfffff;
386 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
388 dev_printk(KERN_DEBUG, &dev->dev,
389 " bridge window [mem 0x%08lx - %08lx pref] reg reading\n",
390 base, limit + 0xfffff);
394 void __devinit pci_read_bridge_bases(struct pci_bus *child)
396 struct pci_dev *dev = child->self;
399 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
402 dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n",
403 child->secondary, child->subordinate,
404 dev->transparent ? " (subtractive decode)" : "");
406 if (dev->transparent) {
407 for (i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
408 child->resource[i] = child->parent->resource[i - 3];
411 pci_read_bridge_io(child);
412 pci_read_bridge_mmio(child);
413 pci_read_bridge_mmio_pref(child);
416 static struct pci_bus * pci_alloc_bus(void)
420 b = kzalloc(sizeof(*b), GFP_KERNEL);
422 INIT_LIST_HEAD(&b->node);
423 INIT_LIST_HEAD(&b->children);
424 INIT_LIST_HEAD(&b->devices);
425 INIT_LIST_HEAD(&b->slots);
426 b->max_bus_speed = PCI_SPEED_UNKNOWN;
427 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
432 static unsigned char pcix_bus_speed[] = {
433 PCI_SPEED_UNKNOWN, /* 0 */
434 PCI_SPEED_66MHz_PCIX, /* 1 */
435 PCI_SPEED_100MHz_PCIX, /* 2 */
436 PCI_SPEED_133MHz_PCIX, /* 3 */
437 PCI_SPEED_UNKNOWN, /* 4 */
438 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
439 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
440 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
441 PCI_SPEED_UNKNOWN, /* 8 */
442 PCI_SPEED_66MHz_PCIX_266, /* 9 */
443 PCI_SPEED_100MHz_PCIX_266, /* A */
444 PCI_SPEED_133MHz_PCIX_266, /* B */
445 PCI_SPEED_UNKNOWN, /* C */
446 PCI_SPEED_66MHz_PCIX_533, /* D */
447 PCI_SPEED_100MHz_PCIX_533, /* E */
448 PCI_SPEED_133MHz_PCIX_533 /* F */
451 static unsigned char pcie_link_speed[] = {
452 PCI_SPEED_UNKNOWN, /* 0 */
453 PCIE_SPEED_2_5GT, /* 1 */
454 PCIE_SPEED_5_0GT, /* 2 */
455 PCIE_SPEED_8_0GT, /* 3 */
456 PCI_SPEED_UNKNOWN, /* 4 */
457 PCI_SPEED_UNKNOWN, /* 5 */
458 PCI_SPEED_UNKNOWN, /* 6 */
459 PCI_SPEED_UNKNOWN, /* 7 */
460 PCI_SPEED_UNKNOWN, /* 8 */
461 PCI_SPEED_UNKNOWN, /* 9 */
462 PCI_SPEED_UNKNOWN, /* A */
463 PCI_SPEED_UNKNOWN, /* B */
464 PCI_SPEED_UNKNOWN, /* C */
465 PCI_SPEED_UNKNOWN, /* D */
466 PCI_SPEED_UNKNOWN, /* E */
467 PCI_SPEED_UNKNOWN /* F */
470 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
472 bus->cur_bus_speed = pcie_link_speed[linksta & 0xf];
474 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
476 static unsigned char agp_speeds[] = {
484 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
490 else if (agpstat & 2)
492 else if (agpstat & 1)
504 return agp_speeds[index];
508 static void pci_set_bus_speed(struct pci_bus *bus)
510 struct pci_dev *bridge = bus->self;
513 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
515 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
519 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
520 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
522 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
523 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
526 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
529 enum pci_bus_speed max;
530 pci_read_config_word(bridge, pos + 2, &status);
532 if (status & 0x8000) {
533 max = PCI_SPEED_133MHz_PCIX_533;
534 } else if (status & 0x4000) {
535 max = PCI_SPEED_133MHz_PCIX_266;
536 } else if (status & 0x0002) {
537 if (((status >> 12) & 0x3) == 2) {
538 max = PCI_SPEED_133MHz_PCIX_ECC;
540 max = PCI_SPEED_133MHz_PCIX;
543 max = PCI_SPEED_66MHz_PCIX;
546 bus->max_bus_speed = max;
547 bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];
552 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
557 pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);
558 bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
560 pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);
561 pcie_update_link_speed(bus, linksta);
566 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
567 struct pci_dev *bridge, int busnr)
569 struct pci_bus *child;
573 * Allocate a new bus, and inherit stuff from the parent..
575 child = pci_alloc_bus();
579 child->parent = parent;
580 child->ops = parent->ops;
581 child->sysdata = parent->sysdata;
582 child->bus_flags = parent->bus_flags;
584 /* initialize some portions of the bus device, but don't register it
585 * now as the parent is not properly set up yet. This device will get
586 * registered later in pci_bus_add_devices()
588 child->dev.class = &pcibus_class;
589 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
592 * Set up the primary, secondary and subordinate
595 child->number = child->secondary = busnr;
596 child->primary = parent->secondary;
597 child->subordinate = 0xff;
602 child->self = bridge;
603 child->bridge = get_device(&bridge->dev);
605 pci_set_bus_speed(child);
607 /* Set up default resource pointers and names.. */
608 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
609 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
610 child->resource[i]->name = child->name;
612 bridge->subordinate = child;
617 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
619 struct pci_bus *child;
621 child = pci_alloc_child_bus(parent, dev, busnr);
623 down_write(&pci_bus_sem);
624 list_add_tail(&child->node, &parent->children);
625 up_write(&pci_bus_sem);
630 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
632 struct pci_bus *parent = child->parent;
634 /* Attempts to fix that up are really dangerous unless
635 we're going to re-assign all bus numbers. */
636 if (!pcibios_assign_all_busses())
639 while (parent->parent && parent->subordinate < max) {
640 parent->subordinate = max;
641 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
642 parent = parent->parent;
647 * If it's a bridge, configure it and scan the bus behind it.
648 * For CardBus bridges, we don't scan behind as the devices will
649 * be handled by the bridge driver itself.
651 * We need to process bridges in two passes -- first we scan those
652 * already configured by the BIOS and after we are done with all of
653 * them, we proceed to assigning numbers to the remaining buses in
654 * order to avoid overlaps between old and new bus numbers.
656 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
658 struct pci_bus *child;
659 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
664 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
666 dev_dbg(&dev->dev, "scanning behind bridge, config %06x, pass %d\n",
667 buses & 0xffffff, pass);
669 /* Check if setup is sensible at all */
671 ((buses & 0xff) != bus->number || ((buses >> 8) & 0xff) <= bus->number)) {
672 dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n");
676 /* Disable MasterAbortMode during probing to avoid reporting
677 of bus errors (in some architectures) */
678 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
679 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
680 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
682 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus && !broken) {
683 unsigned int cmax, busnr;
685 * Bus already configured by firmware, process it in the first
686 * pass and just note the configuration.
690 busnr = (buses >> 8) & 0xFF;
693 * If we already got to this bus through a different bridge,
694 * don't re-add it. This can happen with the i450NX chipset.
696 * However, we continue to descend down the hierarchy and
697 * scan remaining child buses.
699 child = pci_find_bus(pci_domain_nr(bus), busnr);
701 child = pci_add_new_bus(bus, dev, busnr);
704 child->primary = buses & 0xFF;
705 child->subordinate = (buses >> 16) & 0xFF;
706 child->bridge_ctl = bctl;
709 cmax = pci_scan_child_bus(child);
712 if (child->subordinate > max)
713 max = child->subordinate;
716 * We need to assign a number to this bus which we always
717 * do in the second pass.
720 if (pcibios_assign_all_busses() || broken)
721 /* Temporarily disable forwarding of the
722 configuration cycles on all bridges in
723 this bus segment to avoid possible
724 conflicts in the second pass between two
725 bridges programmed with overlapping
727 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
733 pci_write_config_word(dev, PCI_STATUS, 0xffff);
735 /* Prevent assigning a bus number that already exists.
736 * This can happen when a bridge is hot-plugged */
737 if (pci_find_bus(pci_domain_nr(bus), max+1))
739 child = pci_add_new_bus(bus, dev, ++max);
740 buses = (buses & 0xff000000)
741 | ((unsigned int)(child->primary) << 0)
742 | ((unsigned int)(child->secondary) << 8)
743 | ((unsigned int)(child->subordinate) << 16);
746 * yenta.c forces a secondary latency timer of 176.
747 * Copy that behaviour here.
750 buses &= ~0xff000000;
751 buses |= CARDBUS_LATENCY_TIMER << 24;
755 * We need to blast all three values with a single write.
757 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
760 child->bridge_ctl = bctl;
762 * Adjust subordinate busnr in parent buses.
763 * We do this before scanning for children because
764 * some devices may not be detected if the bios
767 pci_fixup_parent_subordinate_busnr(child, max);
768 /* Now we can scan all subordinate buses... */
769 max = pci_scan_child_bus(child);
771 * now fix it up again since we have found
772 * the real value of max.
774 pci_fixup_parent_subordinate_busnr(child, max);
777 * For CardBus bridges, we leave 4 bus numbers
778 * as cards with a PCI-to-PCI bridge can be
781 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
782 struct pci_bus *parent = bus;
783 if (pci_find_bus(pci_domain_nr(bus),
786 while (parent->parent) {
787 if ((!pcibios_assign_all_busses()) &&
788 (parent->subordinate > max) &&
789 (parent->subordinate <= max+i)) {
792 parent = parent->parent;
796 * Often, there are two cardbus bridges
797 * -- try to leave one valid bus number
805 pci_fixup_parent_subordinate_busnr(child, max);
808 * Set the subordinate bus number to its real value.
810 child->subordinate = max;
811 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
815 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
816 pci_domain_nr(bus), child->number);
818 /* Has only triggered on CardBus, fixup is in yenta_socket */
819 while (bus->parent) {
820 if ((child->subordinate > bus->subordinate) ||
821 (child->number > bus->subordinate) ||
822 (child->number < bus->number) ||
823 (child->subordinate < bus->number)) {
824 dev_info(&child->dev, "[bus %02x-%02x] %s "
825 "hidden behind%s bridge %s [bus %02x-%02x]\n",
826 child->number, child->subordinate,
827 (bus->number > child->subordinate &&
828 bus->subordinate < child->number) ?
829 "wholly" : "partially",
830 bus->self->transparent ? " transparent" : "",
832 bus->number, bus->subordinate);
838 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
844 * Read interrupt line and base address registers.
845 * The architecture-dependent code can tweak these, of course.
847 static void pci_read_irq(struct pci_dev *dev)
851 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
854 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
858 void set_pcie_port_type(struct pci_dev *pdev)
863 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
867 pdev->pcie_cap = pos;
868 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
869 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
872 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
878 pos = pci_pcie_cap(pdev);
881 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
882 if (!(reg16 & PCI_EXP_FLAGS_SLOT))
884 pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, ®32);
885 if (reg32 & PCI_EXP_SLTCAP_HPC)
886 pdev->is_hotplug_bridge = 1;
889 static void set_pci_aer_firmware_first(struct pci_dev *pdev)
891 if (acpi_hest_firmware_first_pci(pdev))
892 pdev->aer_firmware_first = 1;
895 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
898 * pci_setup_device - fill in class and map information of a device
899 * @dev: the device structure to fill
901 * Initialize the device structure with information about the device's
902 * vendor,class,memory and IO-space addresses,IRQ lines etc.
903 * Called at initialisation of the PCI subsystem and by CardBus services.
904 * Returns 0 on success and negative if unknown type of device (not normal,
905 * bridge or CardBus).
907 int pci_setup_device(struct pci_dev *dev)
911 struct pci_slot *slot;
914 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
917 dev->sysdata = dev->bus->sysdata;
918 dev->dev.parent = dev->bus->bridge;
919 dev->dev.bus = &pci_bus_type;
920 dev->hdr_type = hdr_type & 0x7f;
921 dev->multifunction = !!(hdr_type & 0x80);
922 dev->error_state = pci_channel_io_normal;
923 set_pcie_port_type(dev);
924 set_pci_aer_firmware_first(dev);
926 list_for_each_entry(slot, &dev->bus->slots, list)
927 if (PCI_SLOT(dev->devfn) == slot->number)
930 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
931 set this higher, assuming the system even supports it. */
932 dev->dma_mask = 0xffffffff;
934 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
935 dev->bus->number, PCI_SLOT(dev->devfn),
936 PCI_FUNC(dev->devfn));
938 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
939 dev->revision = class & 0xff;
940 class >>= 8; /* upper 3 bytes */
944 dev_dbg(&dev->dev, "found [%04x:%04x] class %06x header type %02x\n",
945 dev->vendor, dev->device, class, dev->hdr_type);
947 /* need to have dev->class ready */
948 dev->cfg_size = pci_cfg_space_size(dev);
950 /* "Unknown power state" */
951 dev->current_state = PCI_UNKNOWN;
953 /* Early fixups, before probing the BARs */
954 pci_fixup_device(pci_fixup_early, dev);
955 /* device class may be changed after fixup */
956 class = dev->class >> 8;
958 switch (dev->hdr_type) { /* header type */
959 case PCI_HEADER_TYPE_NORMAL: /* standard header */
960 if (class == PCI_CLASS_BRIDGE_PCI)
963 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
964 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
965 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
968 * Do the ugly legacy mode stuff here rather than broken chip
969 * quirk code. Legacy mode ATA controllers have fixed
970 * addresses. These are not always echoed in BAR0-3, and
971 * BAR0-3 in a few cases contain junk!
973 if (class == PCI_CLASS_STORAGE_IDE) {
975 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
976 if ((progif & 1) == 0) {
977 dev->resource[0].start = 0x1F0;
978 dev->resource[0].end = 0x1F7;
979 dev->resource[0].flags = LEGACY_IO_RESOURCE;
980 dev->resource[1].start = 0x3F6;
981 dev->resource[1].end = 0x3F6;
982 dev->resource[1].flags = LEGACY_IO_RESOURCE;
984 if ((progif & 4) == 0) {
985 dev->resource[2].start = 0x170;
986 dev->resource[2].end = 0x177;
987 dev->resource[2].flags = LEGACY_IO_RESOURCE;
988 dev->resource[3].start = 0x376;
989 dev->resource[3].end = 0x376;
990 dev->resource[3].flags = LEGACY_IO_RESOURCE;
995 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
996 if (class != PCI_CLASS_BRIDGE_PCI)
998 /* The PCI-to-PCI bridge spec requires that subtractive
999 decoding (i.e. transparent) bridge must have programming
1000 interface code of 0x01. */
1002 dev->transparent = ((dev->class & 0xff) == 1);
1003 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1004 set_pcie_hotplug_bridge(dev);
1005 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1007 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1008 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1012 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1013 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1016 pci_read_bases(dev, 1, 0);
1017 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1018 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1021 default: /* unknown header */
1022 dev_err(&dev->dev, "unknown header type %02x, "
1023 "ignoring device\n", dev->hdr_type);
1027 dev_err(&dev->dev, "ignoring class %02x (doesn't match header "
1028 "type %02x)\n", class, dev->hdr_type);
1029 dev->class = PCI_CLASS_NOT_DEFINED;
1032 /* We found a fine healthy device, go go go... */
1036 static void pci_release_capabilities(struct pci_dev *dev)
1038 pci_vpd_release(dev);
1039 pci_iov_release(dev);
1043 * pci_release_dev - free a pci device structure when all users of it are finished.
1044 * @dev: device that's been disconnected
1046 * Will be called only by the device core when all users of this pci device are
1049 static void pci_release_dev(struct device *dev)
1051 struct pci_dev *pci_dev;
1053 pci_dev = to_pci_dev(dev);
1054 pci_release_capabilities(pci_dev);
1059 * pci_cfg_space_size - get the configuration space size of the PCI device.
1062 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1063 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1064 * access it. Maybe we don't have a way to generate extended config space
1065 * accesses, or the device is behind a reverse Express bridge. So we try
1066 * reading the dword at 0x100 which must either be 0 or a valid extended
1067 * capability header.
1069 int pci_cfg_space_size_ext(struct pci_dev *dev)
1072 int pos = PCI_CFG_SPACE_SIZE;
1074 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1076 if (status == 0xffffffff)
1079 return PCI_CFG_SPACE_EXP_SIZE;
1082 return PCI_CFG_SPACE_SIZE;
1085 int pci_cfg_space_size(struct pci_dev *dev)
1091 class = dev->class >> 8;
1092 if (class == PCI_CLASS_BRIDGE_HOST)
1093 return pci_cfg_space_size_ext(dev);
1095 pos = pci_pcie_cap(dev);
1097 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1101 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1102 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1106 return pci_cfg_space_size_ext(dev);
1109 return PCI_CFG_SPACE_SIZE;
1112 static void pci_release_bus_bridge_dev(struct device *dev)
1117 struct pci_dev *alloc_pci_dev(void)
1119 struct pci_dev *dev;
1121 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1125 INIT_LIST_HEAD(&dev->bus_list);
1129 EXPORT_SYMBOL(alloc_pci_dev);
1132 * Read the config data for a PCI device, sanity-check it
1133 * and fill in the dev structure...
1135 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1137 struct pci_dev *dev;
1141 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
1144 /* some broken boards return 0 or ~0 if a slot is empty: */
1145 if (l == 0xffffffff || l == 0x00000000 ||
1146 l == 0x0000ffff || l == 0xffff0000)
1149 /* Configuration request Retry Status */
1150 while (l == 0xffff0001) {
1153 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
1155 /* Card hasn't responded in 60 seconds? Must be stuck. */
1156 if (delay > 60 * 1000) {
1157 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
1158 "responding\n", pci_domain_nr(bus),
1159 bus->number, PCI_SLOT(devfn),
1165 dev = alloc_pci_dev();
1171 dev->vendor = l & 0xffff;
1172 dev->device = (l >> 16) & 0xffff;
1174 if (pci_setup_device(dev)) {
1182 static void pci_init_capabilities(struct pci_dev *dev)
1184 /* MSI/MSI-X list */
1185 pci_msi_init_pci_dev(dev);
1187 /* Buffers for saving PCIe and PCI-X capabilities */
1188 pci_allocate_cap_save_buffers(dev);
1190 /* Power Management */
1192 platform_pci_wakeup_init(dev);
1194 /* Vital Product Data */
1195 pci_vpd_pci22_init(dev);
1197 /* Alternative Routing-ID Forwarding */
1198 pci_enable_ari(dev);
1200 /* Single Root I/O Virtualization */
1203 /* Enable ACS P2P upstream forwarding */
1204 pci_enable_acs(dev);
1207 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1209 device_initialize(&dev->dev);
1210 dev->dev.release = pci_release_dev;
1213 dev->dev.dma_mask = &dev->dma_mask;
1214 dev->dev.dma_parms = &dev->dma_parms;
1215 dev->dev.coherent_dma_mask = 0xffffffffull;
1217 pci_set_dma_max_seg_size(dev, 65536);
1218 pci_set_dma_seg_boundary(dev, 0xffffffff);
1220 /* Fix up broken headers */
1221 pci_fixup_device(pci_fixup_header, dev);
1223 /* Clear the state_saved flag. */
1224 dev->state_saved = false;
1226 /* Initialize various capabilities */
1227 pci_init_capabilities(dev);
1230 * Add the device to our list of discovered devices
1231 * and the bus list for fixup functions, etc.
1233 down_write(&pci_bus_sem);
1234 list_add_tail(&dev->bus_list, &bus->devices);
1235 up_write(&pci_bus_sem);
1238 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1240 struct pci_dev *dev;
1242 dev = pci_get_slot(bus, devfn);
1248 dev = pci_scan_device(bus, devfn);
1252 pci_device_add(dev, bus);
1256 EXPORT_SYMBOL(pci_scan_single_device);
1258 static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn)
1261 unsigned pos, next_fn;
1266 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1269 pci_read_config_word(dev, pos + 4, &cap);
1276 static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn)
1278 return (fn + 1) % 8;
1281 static unsigned no_next_fn(struct pci_dev *dev, unsigned fn)
1286 static int only_one_child(struct pci_bus *bus)
1288 struct pci_dev *parent = bus->self;
1289 if (!parent || !pci_is_pcie(parent))
1291 if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
1292 parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
1298 * pci_scan_slot - scan a PCI slot on a bus for devices.
1299 * @bus: PCI bus to scan
1300 * @devfn: slot number to scan (must have zero function.)
1302 * Scan a PCI slot on the specified PCI bus for devices, adding
1303 * discovered devices to the @bus->devices list. New devices
1304 * will not have is_added set.
1306 * Returns the number of new devices found.
1308 int pci_scan_slot(struct pci_bus *bus, int devfn)
1310 unsigned fn, nr = 0;
1311 struct pci_dev *dev;
1312 unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn;
1314 if (only_one_child(bus) && (devfn > 0))
1315 return 0; /* Already scanned the entire slot */
1317 dev = pci_scan_single_device(bus, devfn);
1323 if (pci_ari_enabled(bus))
1324 next_fn = next_ari_fn;
1325 else if (dev->multifunction)
1326 next_fn = next_trad_fn;
1328 for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) {
1329 dev = pci_scan_single_device(bus, devfn + fn);
1333 dev->multifunction = 1;
1337 /* only one slot has pcie device */
1338 if (bus->self && nr)
1339 pcie_aspm_init_link_state(bus->self);
1344 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1346 unsigned int devfn, pass, max = bus->secondary;
1347 struct pci_dev *dev;
1349 dev_dbg(&bus->dev, "scanning bus\n");
1351 /* Go find them, Rover! */
1352 for (devfn = 0; devfn < 0x100; devfn += 8)
1353 pci_scan_slot(bus, devfn);
1355 /* Reserve buses for SR-IOV capability. */
1356 max += pci_iov_bus_range(bus);
1359 * After performing arch-dependent fixup of the bus, look behind
1360 * all PCI-to-PCI bridges on this bus.
1362 if (!bus->is_added) {
1363 dev_dbg(&bus->dev, "fixups for bus\n");
1364 pcibios_fixup_bus(bus);
1365 if (pci_is_root_bus(bus))
1369 for (pass=0; pass < 2; pass++)
1370 list_for_each_entry(dev, &bus->devices, bus_list) {
1371 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1372 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1373 max = pci_scan_bridge(bus, dev, max, pass);
1377 * We've scanned the bus and so we know all about what's on
1378 * the other side of any bridges that may be on this bus plus
1381 * Return how far we've got finding sub-buses.
1383 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
1387 struct pci_bus * pci_create_bus(struct device *parent,
1388 int bus, struct pci_ops *ops, void *sysdata)
1391 struct pci_bus *b, *b2;
1394 b = pci_alloc_bus();
1398 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1404 b->sysdata = sysdata;
1407 b2 = pci_find_bus(pci_domain_nr(b), bus);
1409 /* If we already got to this bus through a different bridge, ignore it */
1410 dev_dbg(&b2->dev, "bus already known\n");
1414 down_write(&pci_bus_sem);
1415 list_add_tail(&b->node, &pci_root_buses);
1416 up_write(&pci_bus_sem);
1418 dev->parent = parent;
1419 dev->release = pci_release_bus_bridge_dev;
1420 dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1421 error = device_register(dev);
1424 b->bridge = get_device(dev);
1427 set_dev_node(b->bridge, pcibus_to_node(b));
1429 b->dev.class = &pcibus_class;
1430 b->dev.parent = b->bridge;
1431 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1432 error = device_register(&b->dev);
1434 goto class_dev_reg_err;
1435 error = device_create_file(&b->dev, &dev_attr_cpuaffinity);
1437 goto dev_create_file_err;
1439 /* Create legacy_io and legacy_mem files for this bus */
1440 pci_create_legacy_files(b);
1442 b->number = b->secondary = bus;
1443 b->resource[0] = &ioport_resource;
1444 b->resource[1] = &iomem_resource;
1448 dev_create_file_err:
1449 device_unregister(&b->dev);
1451 device_unregister(dev);
1453 down_write(&pci_bus_sem);
1455 up_write(&pci_bus_sem);
1462 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1463 int bus, struct pci_ops *ops, void *sysdata)
1467 b = pci_create_bus(parent, bus, ops, sysdata);
1469 b->subordinate = pci_scan_child_bus(b);
1472 EXPORT_SYMBOL(pci_scan_bus_parented);
1474 #ifdef CONFIG_HOTPLUG
1476 * pci_rescan_bus - scan a PCI bus for devices.
1477 * @bus: PCI bus to scan
1479 * Scan a PCI bus and child buses for new devices, adds them,
1482 * Returns the max number of subordinate bus discovered.
1484 unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
1487 struct pci_dev *dev;
1489 max = pci_scan_child_bus(bus);
1491 down_read(&pci_bus_sem);
1492 list_for_each_entry(dev, &bus->devices, bus_list)
1493 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1494 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1495 if (dev->subordinate)
1496 pci_bus_size_bridges(dev->subordinate);
1497 up_read(&pci_bus_sem);
1499 pci_bus_assign_resources(bus);
1500 pci_enable_bridges(bus);
1501 pci_bus_add_devices(bus);
1505 EXPORT_SYMBOL_GPL(pci_rescan_bus);
1507 EXPORT_SYMBOL(pci_add_new_bus);
1508 EXPORT_SYMBOL(pci_scan_slot);
1509 EXPORT_SYMBOL(pci_scan_bridge);
1510 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1513 static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
1515 const struct pci_dev *a = to_pci_dev(d_a);
1516 const struct pci_dev *b = to_pci_dev(d_b);
1518 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1519 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1521 if (a->bus->number < b->bus->number) return -1;
1522 else if (a->bus->number > b->bus->number) return 1;
1524 if (a->devfn < b->devfn) return -1;
1525 else if (a->devfn > b->devfn) return 1;
1530 void __init pci_sort_breadthfirst(void)
1532 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);