2 * File: drivers/pci/pcie/aspm.c
3 * Enabling PCIE link L0s/L1 state and Clock Power Management
5 * Copyright (C) 2007 Intel
6 * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
7 * Copyright (C) Shaohua Li (shaohua.li@intel.com)
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/pci_regs.h>
15 #include <linux/errno.h>
17 #include <linux/init.h>
18 #include <linux/slab.h>
19 #include <linux/jiffies.h>
20 #include <linux/delay.h>
21 #include <linux/pci-aspm.h>
24 #ifdef MODULE_PARAM_PREFIX
25 #undef MODULE_PARAM_PREFIX
27 #define MODULE_PARAM_PREFIX "pcie_aspm."
29 struct endpoint_state {
30 unsigned int l0s_acceptable_latency;
31 unsigned int l1_acceptable_latency;
34 struct pcie_link_state {
35 struct list_head sibling;
37 bool downstream_has_switch;
39 struct pcie_link_state *parent;
40 struct list_head children;
41 struct list_head link;
44 u32 aspm_support:2; /* Supported ASPM state */
45 u32 aspm_enabled:2; /* Enabled ASPM state */
46 u32 aspm_default:2; /* Default ASPM state by BIOS */
48 /* upstream component */
49 unsigned int l0s_upper_latency;
50 unsigned int l1_upper_latency;
51 /* downstream component */
52 unsigned int l0s_down_latency;
53 unsigned int l1_down_latency;
55 unsigned int clk_pm_capable;
56 unsigned int clk_pm_enabled;
57 unsigned int bios_clk_state;
60 * A pcie downstream port only has one slot under it, so at most there
63 struct endpoint_state endpoints[8];
66 static int aspm_disabled, aspm_force;
67 static DEFINE_MUTEX(aspm_lock);
68 static LIST_HEAD(link_list);
70 #define POLICY_DEFAULT 0 /* BIOS default setting */
71 #define POLICY_PERFORMANCE 1 /* high performance */
72 #define POLICY_POWERSAVE 2 /* high power saving */
73 static int aspm_policy;
74 static const char *policy_str[] = {
75 [POLICY_DEFAULT] = "default",
76 [POLICY_PERFORMANCE] = "performance",
77 [POLICY_POWERSAVE] = "powersave"
80 #define LINK_RETRAIN_TIMEOUT HZ
82 static int policy_to_aspm_state(struct pci_dev *pdev)
84 struct pcie_link_state *link_state = pdev->link_state;
86 switch (aspm_policy) {
87 case POLICY_PERFORMANCE:
88 /* Disable ASPM and Clock PM */
90 case POLICY_POWERSAVE:
91 /* Enable ASPM L0s/L1 */
92 return PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1;
94 return link_state->aspm_default;
99 static int policy_to_clkpm_state(struct pci_dev *pdev)
101 struct pcie_link_state *link_state = pdev->link_state;
103 switch (aspm_policy) {
104 case POLICY_PERFORMANCE:
105 /* Disable ASPM and Clock PM */
107 case POLICY_POWERSAVE:
108 /* Disable Clock PM */
111 return link_state->bios_clk_state;
116 static void pcie_set_clock_pm(struct pci_dev *pdev, int enable)
118 struct pci_dev *child_dev;
121 struct pcie_link_state *link_state = pdev->link_state;
123 list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
124 pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
127 pci_read_config_word(child_dev, pos + PCI_EXP_LNKCTL, ®16);
129 reg16 |= PCI_EXP_LNKCTL_CLKREQ_EN;
131 reg16 &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
132 pci_write_config_word(child_dev, pos + PCI_EXP_LNKCTL, reg16);
134 link_state->clk_pm_enabled = !!enable;
137 static void pcie_check_clock_pm(struct pci_dev *pdev, int blacklist)
142 int capable = 1, enabled = 1;
143 struct pci_dev *child_dev;
144 struct pcie_link_state *link_state = pdev->link_state;
146 /* All functions should have the same cap and state, take the worst */
147 list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
148 pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
151 pci_read_config_dword(child_dev, pos + PCI_EXP_LNKCAP, ®32);
152 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
157 pci_read_config_word(child_dev, pos + PCI_EXP_LNKCTL, ®16);
158 if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
161 link_state->clk_pm_enabled = enabled;
162 link_state->bios_clk_state = enabled;
164 link_state->clk_pm_capable = capable;
165 pcie_set_clock_pm(pdev, policy_to_clkpm_state(pdev));
167 link_state->clk_pm_capable = 0;
168 pcie_set_clock_pm(pdev, 0);
172 static bool pcie_aspm_downstream_has_switch(struct pci_dev *pdev)
174 struct pci_dev *child_dev;
176 list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
177 if (child_dev->pcie_type == PCI_EXP_TYPE_UPSTREAM)
184 * pcie_aspm_configure_common_clock: check if the 2 ends of a link
185 * could use common clock. If they are, configure them to use the
186 * common clock. That will reduce the ASPM state exit latency.
188 static void pcie_aspm_configure_common_clock(struct pci_dev *pdev)
190 int pos, child_pos, i = 0;
192 struct pci_dev *child_dev;
194 unsigned long start_jiffies;
195 u16 child_regs[8], parent_reg;
197 * all functions of a slot should have the same Slot Clock
198 * Configuration, so just check one function
200 child_dev = list_entry(pdev->subordinate->devices.next, struct pci_dev,
202 BUG_ON(!child_dev->is_pcie);
204 /* Check downstream component if bit Slot Clock Configuration is 1 */
205 child_pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
206 pci_read_config_word(child_dev, child_pos + PCI_EXP_LNKSTA, ®16);
207 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
210 /* Check upstream component if bit Slot Clock Configuration is 1 */
211 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
212 pci_read_config_word(pdev, pos + PCI_EXP_LNKSTA, ®16);
213 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
216 /* Configure downstream component, all functions */
217 list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
218 child_pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
219 pci_read_config_word(child_dev, child_pos + PCI_EXP_LNKCTL,
221 child_regs[i] = reg16;
223 reg16 |= PCI_EXP_LNKCTL_CCC;
225 reg16 &= ~PCI_EXP_LNKCTL_CCC;
226 pci_write_config_word(child_dev, child_pos + PCI_EXP_LNKCTL,
231 /* Configure upstream component */
232 pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16);
235 reg16 |= PCI_EXP_LNKCTL_CCC;
237 reg16 &= ~PCI_EXP_LNKCTL_CCC;
238 pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
241 reg16 |= PCI_EXP_LNKCTL_RL;
242 pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
244 /* Wait for link training end */
245 /* break out after waiting for timeout */
246 start_jiffies = jiffies;
248 pci_read_config_word(pdev, pos + PCI_EXP_LNKSTA, ®16);
249 if (!(reg16 & PCI_EXP_LNKSTA_LT))
251 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
255 /* training failed -> recover */
256 if (reg16 & PCI_EXP_LNKSTA_LT) {
257 dev_printk (KERN_ERR, &pdev->dev, "ASPM: Could not configure"
260 list_for_each_entry(child_dev, &pdev->subordinate->devices,
262 child_pos = pci_find_capability(child_dev,
264 pci_write_config_word(child_dev,
265 child_pos + PCI_EXP_LNKCTL,
269 pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, parent_reg);
274 * calc_L0S_latency: Convert L0s latency encoding to ns
276 static unsigned int calc_L0S_latency(unsigned int latency_encoding, int ac)
278 unsigned int ns = 64;
280 if (latency_encoding == 0x7) {
284 ns = 5*1000; /* > 4us */
286 ns *= (1 << latency_encoding);
291 * calc_L1_latency: Convert L1 latency encoding to ns
293 static unsigned int calc_L1_latency(unsigned int latency_encoding, int ac)
295 unsigned int ns = 1000;
297 if (latency_encoding == 0x7) {
301 ns = 65*1000; /* > 64us */
303 ns *= (1 << latency_encoding);
307 static void pcie_aspm_get_cap_device(struct pci_dev *pdev, u32 *state,
308 unsigned int *l0s, unsigned int *l1, unsigned int *enabled)
313 unsigned int latency;
315 *l0s = *l1 = *enabled = 0;
316 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
317 pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, ®32);
318 *state = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
319 if (*state != PCIE_LINK_STATE_L0S &&
320 *state != (PCIE_LINK_STATE_L1|PCIE_LINK_STATE_L0S))
325 latency = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
326 *l0s = calc_L0S_latency(latency, 0);
327 if (*state & PCIE_LINK_STATE_L1) {
328 latency = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
329 *l1 = calc_L1_latency(latency, 0);
331 pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16);
332 *enabled = reg16 & (PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1);
335 static void pcie_aspm_cap_init(struct pci_dev *pdev)
337 struct pci_dev *child_dev;
338 u32 support, l0s, l1, enabled;
339 struct pcie_link_state *link_state = pdev->link_state;
341 /* upstream component states */
342 pcie_aspm_get_cap_device(pdev, &support, &l0s, &l1, &enabled);
343 link_state->aspm_support = support;
344 link_state->l0s_upper_latency = l0s;
345 link_state->l1_upper_latency = l1;
346 link_state->aspm_enabled = enabled;
348 /* downstream component states, all functions have the same setting */
349 child_dev = list_entry(pdev->subordinate->devices.next, struct pci_dev,
351 pcie_aspm_get_cap_device(child_dev, &support, &l0s, &l1, &enabled);
352 link_state->aspm_support &= support;
353 link_state->l0s_down_latency = l0s;
354 link_state->l1_down_latency = l1;
356 if (!link_state->aspm_support)
359 link_state->aspm_enabled &= link_state->aspm_support;
360 link_state->aspm_default = link_state->aspm_enabled;
363 list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
366 unsigned int latency;
367 struct endpoint_state *ep_state =
368 &link_state->endpoints[PCI_FUNC(child_dev->devfn)];
370 if (child_dev->pcie_type != PCI_EXP_TYPE_ENDPOINT &&
371 child_dev->pcie_type != PCI_EXP_TYPE_LEG_END)
374 pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
375 pci_read_config_dword(child_dev, pos + PCI_EXP_DEVCAP, ®32);
376 latency = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
377 latency = calc_L0S_latency(latency, 1);
378 ep_state->l0s_acceptable_latency = latency;
379 if (link_state->aspm_support & PCIE_LINK_STATE_L1) {
380 latency = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
381 latency = calc_L1_latency(latency, 1);
382 ep_state->l1_acceptable_latency = latency;
387 static unsigned int __pcie_aspm_check_state_one(struct pci_dev *pdev,
390 struct pci_dev *parent_dev, *tmp_dev;
391 unsigned int latency, l1_latency = 0;
392 struct pcie_link_state *link_state;
393 struct endpoint_state *ep_state;
395 parent_dev = pdev->bus->self;
396 link_state = parent_dev->link_state;
397 state &= link_state->aspm_support;
400 ep_state = &link_state->endpoints[PCI_FUNC(pdev->devfn)];
403 * Check latency for endpoint device.
404 * TBD: The latency from the endpoint to root complex vary per
405 * switch's upstream link state above the device. Here we just do a
406 * simple check which assumes all links above the device can be in L1
407 * state, that is we just consider the worst case. If switch's upstream
408 * link can't be put into L0S/L1, then our check is too strictly.
411 while (state & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) {
412 parent_dev = tmp_dev->bus->self;
413 link_state = parent_dev->link_state;
414 if (state & PCIE_LINK_STATE_L0S) {
415 latency = max_t(unsigned int,
416 link_state->l0s_upper_latency,
417 link_state->l0s_down_latency);
418 if (latency > ep_state->l0s_acceptable_latency)
419 state &= ~PCIE_LINK_STATE_L0S;
421 if (state & PCIE_LINK_STATE_L1) {
422 latency = max_t(unsigned int,
423 link_state->l1_upper_latency,
424 link_state->l1_down_latency);
425 if (latency + l1_latency >
426 ep_state->l1_acceptable_latency)
427 state &= ~PCIE_LINK_STATE_L1;
429 if (!parent_dev->bus->self) /* parent_dev is a root port */
433 * parent_dev is the downstream port of a switch, make
434 * tmp_dev the upstream port of the switch
436 tmp_dev = parent_dev->bus->self;
438 * every switch on the path to root complex need 1 more
439 * microsecond for L1. Spec doesn't mention L0S.
441 if (state & PCIE_LINK_STATE_L1)
448 static unsigned int pcie_aspm_check_state(struct pci_dev *pdev,
451 struct pci_dev *child_dev;
453 /* If no child, ignore the link */
454 if (list_empty(&pdev->subordinate->devices))
456 list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
457 if (child_dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) {
459 * If downstream component of a link is pci bridge, we
460 * disable ASPM for now for the link
465 if ((child_dev->pcie_type != PCI_EXP_TYPE_ENDPOINT &&
466 child_dev->pcie_type != PCI_EXP_TYPE_LEG_END))
468 /* Device not in D0 doesn't need check latency */
469 if (child_dev->current_state == PCI_D1 ||
470 child_dev->current_state == PCI_D2 ||
471 child_dev->current_state == PCI_D3hot ||
472 child_dev->current_state == PCI_D3cold)
474 state = __pcie_aspm_check_state_one(child_dev, state);
479 static void __pcie_aspm_config_one_dev(struct pci_dev *pdev, unsigned int state)
482 int pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
484 pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16);
487 pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
490 static void __pcie_aspm_config_link(struct pci_dev *pdev, unsigned int state)
492 struct pci_dev *child_dev;
494 struct pcie_link_state *link_state = pdev->link_state;
496 /* If no child, disable the link */
497 if (list_empty(&pdev->subordinate->devices))
500 * if the downstream component has pci bridge function, don't do ASPM
503 list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
504 if (child_dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) {
513 * spec 2.0 suggests all functions should be configured the same
514 * setting for ASPM. Enabling ASPM L1 should be done in upstream
515 * component first and then downstream, and vice versa for disabling
516 * ASPM L1. Spec doesn't mention L0S.
518 if (state & PCIE_LINK_STATE_L1)
519 __pcie_aspm_config_one_dev(pdev, state);
521 list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list)
522 __pcie_aspm_config_one_dev(child_dev, state);
524 if (!(state & PCIE_LINK_STATE_L1))
525 __pcie_aspm_config_one_dev(pdev, state);
527 link_state->aspm_enabled = state;
530 static struct pcie_link_state *get_root_port_link(struct pcie_link_state *link)
532 struct pcie_link_state *root_port_link = link;
533 while (root_port_link->parent)
534 root_port_link = root_port_link->parent;
535 return root_port_link;
538 /* check the whole hierarchy, and configure each link in the hierarchy */
539 static void __pcie_aspm_configure_link_state(struct pci_dev *pdev,
542 struct pcie_link_state *link_state = pdev->link_state;
543 struct pcie_link_state *root_port_link = get_root_port_link(link_state);
544 struct pcie_link_state *leaf;
546 state &= PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1;
548 /* check all links who have specific root port link */
549 list_for_each_entry(leaf, &link_list, sibling) {
550 if (!list_empty(&leaf->children) ||
551 get_root_port_link(leaf) != root_port_link)
553 state = pcie_aspm_check_state(leaf->pdev, state);
555 /* check root port link too in case it hasn't children */
556 state = pcie_aspm_check_state(root_port_link->pdev, state);
558 if (link_state->aspm_enabled == state)
562 * we must change the hierarchy. See comments in
563 * __pcie_aspm_config_link for the order
565 if (state & PCIE_LINK_STATE_L1) {
566 list_for_each_entry(leaf, &link_list, sibling) {
567 if (get_root_port_link(leaf) == root_port_link)
568 __pcie_aspm_config_link(leaf->pdev, state);
571 list_for_each_entry_reverse(leaf, &link_list, sibling) {
572 if (get_root_port_link(leaf) == root_port_link)
573 __pcie_aspm_config_link(leaf->pdev, state);
579 * pcie_aspm_configure_link_state: enable/disable PCI express link state
580 * @pdev: the root port or switch downstream port
582 static void pcie_aspm_configure_link_state(struct pci_dev *pdev,
585 down_read(&pci_bus_sem);
586 mutex_lock(&aspm_lock);
587 __pcie_aspm_configure_link_state(pdev, state);
588 mutex_unlock(&aspm_lock);
589 up_read(&pci_bus_sem);
592 static void free_link_state(struct pci_dev *pdev)
594 kfree(pdev->link_state);
595 pdev->link_state = NULL;
598 static int pcie_aspm_sanity_check(struct pci_dev *pdev)
600 struct pci_dev *child_dev;
605 * Some functions in a slot might not all be PCIE functions, very
606 * strange. Disable ASPM for the whole slot
608 list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
609 child_pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
614 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
615 * RBER bit to determine if a function is 1.1 version device
617 pci_read_config_dword(child_dev, child_pos + PCI_EXP_DEVCAP,
619 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
620 dev_printk(KERN_INFO, &child_dev->dev, "disabling ASPM"
621 " on pre-1.1 PCIe device. You can enable it"
622 " with 'pcie_aspm=force'\n");
630 * pcie_aspm_init_link_state: Initiate PCI express link state.
631 * It is called after the pcie and its children devices are scaned.
632 * @pdev: the root port or switch downstream port
634 void pcie_aspm_init_link_state(struct pci_dev *pdev)
637 struct pcie_link_state *link_state;
641 if (aspm_disabled || !pdev->is_pcie || pdev->link_state)
643 if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
644 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)
646 /* VIA has a strange chipset, root port is under a bridge */
647 if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT &&
650 down_read(&pci_bus_sem);
651 if (list_empty(&pdev->subordinate->devices))
654 blacklist = !!pcie_aspm_sanity_check(pdev);
656 mutex_lock(&aspm_lock);
658 link_state = kzalloc(sizeof(*link_state), GFP_KERNEL);
662 link_state->downstream_has_switch = pcie_aspm_downstream_has_switch(pdev);
663 INIT_LIST_HEAD(&link_state->children);
664 INIT_LIST_HEAD(&link_state->link);
665 if (pdev->bus->self) {/* this is a switch */
666 struct pcie_link_state *parent_link_state;
668 parent_link_state = pdev->bus->parent->self->link_state;
669 if (!parent_link_state) {
673 list_add(&link_state->link, &parent_link_state->children);
674 link_state->parent = parent_link_state;
677 pdev->link_state = link_state;
680 pcie_aspm_configure_common_clock(pdev);
681 pcie_aspm_cap_init(pdev);
683 link_state->aspm_enabled =
684 (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
685 link_state->aspm_default = 0;
686 /* Set support state to 0, so we will disable ASPM later */
687 link_state->aspm_support = 0;
690 link_state->pdev = pdev;
691 list_add(&link_state->sibling, &link_list);
693 if (link_state->downstream_has_switch) {
695 * If link has switch, delay the link config. The leaf link
696 * initialization will config the whole hierarchy. but we must
697 * make sure BIOS doesn't set unsupported link state
699 state = pcie_aspm_check_state(pdev, link_state->aspm_default);
700 __pcie_aspm_config_link(pdev, state);
702 __pcie_aspm_configure_link_state(pdev,
703 policy_to_aspm_state(pdev));
705 pcie_check_clock_pm(pdev, blacklist);
709 free_link_state(pdev);
710 mutex_unlock(&aspm_lock);
712 up_read(&pci_bus_sem);
715 /* @pdev: the endpoint device */
716 void pcie_aspm_exit_link_state(struct pci_dev *pdev)
718 struct pci_dev *parent = pdev->bus->self;
719 struct pcie_link_state *link_state = parent->link_state;
721 if (aspm_disabled || !pdev->is_pcie || !parent || !link_state)
723 if (parent->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
724 parent->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)
726 down_read(&pci_bus_sem);
727 mutex_lock(&aspm_lock);
730 * All PCIe functions are in one slot, remove one function will remove
731 * the whole slot, so just wait until we are the last function left.
733 if (!list_is_last(&pdev->bus_list, &parent->subordinate->devices))
736 /* All functions are removed, so just disable ASPM for the link */
737 __pcie_aspm_config_one_dev(parent, 0);
738 list_del(&link_state->sibling);
739 list_del(&link_state->link);
740 /* Clock PM is for endpoint device */
742 free_link_state(parent);
744 mutex_unlock(&aspm_lock);
745 up_read(&pci_bus_sem);
748 /* @pdev: the root port or switch downstream port */
749 void pcie_aspm_pm_state_change(struct pci_dev *pdev)
751 struct pcie_link_state *link_state = pdev->link_state;
753 if (aspm_disabled || !pdev->is_pcie || !pdev->link_state)
755 if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
756 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)
759 * devices changed PM state, we should recheck if latency meets all
760 * functions' requirement
762 pcie_aspm_configure_link_state(pdev, link_state->aspm_enabled);
766 * pci_disable_link_state - disable pci device's link state, so the link will
767 * never enter specific states
769 void pci_disable_link_state(struct pci_dev *pdev, int state)
771 struct pci_dev *parent = pdev->bus->self;
772 struct pcie_link_state *link_state;
774 if (aspm_disabled || !pdev->is_pcie)
776 if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
777 pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
779 if (!parent || !parent->link_state)
782 down_read(&pci_bus_sem);
783 mutex_lock(&aspm_lock);
784 link_state = parent->link_state;
785 link_state->aspm_support &= ~state;
786 if (state & PCIE_LINK_STATE_CLKPM)
787 link_state->clk_pm_capable = 0;
789 __pcie_aspm_configure_link_state(parent, link_state->aspm_enabled);
790 if (!link_state->clk_pm_capable && link_state->clk_pm_enabled)
791 pcie_set_clock_pm(parent, 0);
792 mutex_unlock(&aspm_lock);
793 up_read(&pci_bus_sem);
795 EXPORT_SYMBOL(pci_disable_link_state);
797 static int pcie_aspm_set_policy(const char *val, struct kernel_param *kp)
800 struct pci_dev *pdev;
801 struct pcie_link_state *link_state;
803 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
804 if (!strncmp(val, policy_str[i], strlen(policy_str[i])))
806 if (i >= ARRAY_SIZE(policy_str))
808 if (i == aspm_policy)
811 down_read(&pci_bus_sem);
812 mutex_lock(&aspm_lock);
814 list_for_each_entry(link_state, &link_list, sibling) {
815 pdev = link_state->pdev;
816 __pcie_aspm_configure_link_state(pdev,
817 policy_to_aspm_state(pdev));
818 if (link_state->clk_pm_capable &&
819 link_state->clk_pm_enabled != policy_to_clkpm_state(pdev))
820 pcie_set_clock_pm(pdev, policy_to_clkpm_state(pdev));
823 mutex_unlock(&aspm_lock);
824 up_read(&pci_bus_sem);
828 static int pcie_aspm_get_policy(char *buffer, struct kernel_param *kp)
831 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
832 if (i == aspm_policy)
833 cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
835 cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
839 module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
842 #ifdef CONFIG_PCIEASPM_DEBUG
843 static ssize_t link_state_show(struct device *dev,
844 struct device_attribute *attr,
847 struct pci_dev *pci_device = to_pci_dev(dev);
848 struct pcie_link_state *link_state = pci_device->link_state;
850 return sprintf(buf, "%d\n", link_state->aspm_enabled);
853 static ssize_t link_state_store(struct device *dev,
854 struct device_attribute *attr,
858 struct pci_dev *pci_device = to_pci_dev(dev);
864 if (state >= 0 && state <= 3) {
865 /* setup link aspm state */
866 pcie_aspm_configure_link_state(pci_device, state);
873 static ssize_t clk_ctl_show(struct device *dev,
874 struct device_attribute *attr,
877 struct pci_dev *pci_device = to_pci_dev(dev);
878 struct pcie_link_state *link_state = pci_device->link_state;
880 return sprintf(buf, "%d\n", link_state->clk_pm_enabled);
883 static ssize_t clk_ctl_store(struct device *dev,
884 struct device_attribute *attr,
888 struct pci_dev *pci_device = to_pci_dev(dev);
895 down_read(&pci_bus_sem);
896 mutex_lock(&aspm_lock);
897 pcie_set_clock_pm(pci_device, !!state);
898 mutex_unlock(&aspm_lock);
899 up_read(&pci_bus_sem);
904 static DEVICE_ATTR(link_state, 0644, link_state_show, link_state_store);
905 static DEVICE_ATTR(clk_ctl, 0644, clk_ctl_show, clk_ctl_store);
907 static char power_group[] = "power";
908 void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
910 struct pcie_link_state *link_state = pdev->link_state;
912 if (!pdev->is_pcie || (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
913 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state)
916 if (link_state->aspm_support)
917 sysfs_add_file_to_group(&pdev->dev.kobj,
918 &dev_attr_link_state.attr, power_group);
919 if (link_state->clk_pm_capable)
920 sysfs_add_file_to_group(&pdev->dev.kobj,
921 &dev_attr_clk_ctl.attr, power_group);
924 void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
926 struct pcie_link_state *link_state = pdev->link_state;
928 if (!pdev->is_pcie || (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
929 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state)
932 if (link_state->aspm_support)
933 sysfs_remove_file_from_group(&pdev->dev.kobj,
934 &dev_attr_link_state.attr, power_group);
935 if (link_state->clk_pm_capable)
936 sysfs_remove_file_from_group(&pdev->dev.kobj,
937 &dev_attr_clk_ctl.attr, power_group);
941 static int __init pcie_aspm_disable(char *str)
943 if (!strcmp(str, "off")) {
945 printk(KERN_INFO "PCIe ASPM is disabled\n");
946 } else if (!strcmp(str, "force")) {
948 printk(KERN_INFO "PCIe ASPM is forcedly enabled\n");
953 __setup("pcie_aspm=", pcie_aspm_disable);
955 void pcie_no_aspm(void)
962 * pcie_aspm_enabled - is PCIe ASPM enabled?
964 * Returns true if ASPM has not been disabled by the command-line option
967 int pcie_aspm_enabled(void)
969 return !aspm_disabled;
971 EXPORT_SYMBOL(pcie_aspm_enabled);