2 * File: drivers/pci/pcie/aspm.c
3 * Enabling PCIE link L0s/L1 state and Clock Power Management
5 * Copyright (C) 2007 Intel
6 * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
7 * Copyright (C) Shaohua Li (shaohua.li@intel.com)
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/pci_regs.h>
15 #include <linux/errno.h>
17 #include <linux/init.h>
18 #include <linux/slab.h>
19 #include <linux/jiffies.h>
20 #include <linux/delay.h>
21 #include <linux/pci-aspm.h>
24 #ifdef MODULE_PARAM_PREFIX
25 #undef MODULE_PARAM_PREFIX
27 #define MODULE_PARAM_PREFIX "pcie_aspm."
30 u32 l0s; /* L0s latency (nsec) */
31 u32 l1; /* L1 latency (nsec) */
34 struct pcie_link_state {
35 struct pci_dev *pdev; /* Upstream component of the Link */
36 struct pcie_link_state *root; /* pointer to the root port link */
37 struct pcie_link_state *parent; /* pointer to the parent Link state */
38 struct list_head sibling; /* node in link_list */
39 struct list_head children; /* list of child link states */
40 struct list_head link; /* node in parent's children list */
43 u32 aspm_support:2; /* Supported ASPM state */
44 u32 aspm_enabled:2; /* Enabled ASPM state */
45 u32 aspm_default:2; /* Default ASPM state by BIOS */
48 u32 clkpm_capable:1; /* Clock PM capable? */
49 u32 clkpm_enabled:1; /* Current Clock PM state */
50 u32 clkpm_default:1; /* Default Clock PM state by BIOS */
53 struct aspm_latency latency; /* Exit latency */
55 * Endpoint acceptable latencies. A pcie downstream port only
56 * has one slot under it, so at most there are 8 functions.
58 struct aspm_latency acceptable[8];
61 static int aspm_disabled, aspm_force;
62 static DEFINE_MUTEX(aspm_lock);
63 static LIST_HEAD(link_list);
65 #define POLICY_DEFAULT 0 /* BIOS default setting */
66 #define POLICY_PERFORMANCE 1 /* high performance */
67 #define POLICY_POWERSAVE 2 /* high power saving */
68 static int aspm_policy;
69 static const char *policy_str[] = {
70 [POLICY_DEFAULT] = "default",
71 [POLICY_PERFORMANCE] = "performance",
72 [POLICY_POWERSAVE] = "powersave"
75 #define LINK_RETRAIN_TIMEOUT HZ
77 static int policy_to_aspm_state(struct pcie_link_state *link)
79 switch (aspm_policy) {
80 case POLICY_PERFORMANCE:
81 /* Disable ASPM and Clock PM */
83 case POLICY_POWERSAVE:
84 /* Enable ASPM L0s/L1 */
85 return PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1;
87 return link->aspm_default;
92 static int policy_to_clkpm_state(struct pcie_link_state *link)
94 switch (aspm_policy) {
95 case POLICY_PERFORMANCE:
96 /* Disable ASPM and Clock PM */
98 case POLICY_POWERSAVE:
99 /* Disable Clock PM */
102 return link->clkpm_default;
107 static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
111 struct pci_dev *child;
112 struct pci_bus *linkbus = link->pdev->subordinate;
114 list_for_each_entry(child, &linkbus->devices, bus_list) {
115 pos = pci_find_capability(child, PCI_CAP_ID_EXP);
118 pci_read_config_word(child, pos + PCI_EXP_LNKCTL, ®16);
120 reg16 |= PCI_EXP_LNKCTL_CLKREQ_EN;
122 reg16 &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
123 pci_write_config_word(child, pos + PCI_EXP_LNKCTL, reg16);
125 link->clkpm_enabled = !!enable;
128 static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
130 /* Don't enable Clock PM if the link is not Clock PM capable */
131 if (!link->clkpm_capable && enable)
133 /* Need nothing if the specified equals to current state */
134 if (link->clkpm_enabled == enable)
136 pcie_set_clkpm_nocheck(link, enable);
139 static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
141 int pos, capable = 1, enabled = 1;
144 struct pci_dev *child;
145 struct pci_bus *linkbus = link->pdev->subordinate;
147 /* All functions should have the same cap and state, take the worst */
148 list_for_each_entry(child, &linkbus->devices, bus_list) {
149 pos = pci_find_capability(child, PCI_CAP_ID_EXP);
152 pci_read_config_dword(child, pos + PCI_EXP_LNKCAP, ®32);
153 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
158 pci_read_config_word(child, pos + PCI_EXP_LNKCTL, ®16);
159 if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
162 link->clkpm_enabled = enabled;
163 link->clkpm_default = enabled;
164 link->clkpm_capable = (blacklist) ? 0 : capable;
167 static bool pcie_aspm_downstream_has_switch(struct pcie_link_state *link)
169 struct pci_dev *child;
170 struct pci_bus *linkbus = link->pdev->subordinate;
172 list_for_each_entry(child, &linkbus->devices, bus_list) {
173 if (child->pcie_type == PCI_EXP_TYPE_UPSTREAM)
180 * pcie_aspm_configure_common_clock: check if the 2 ends of a link
181 * could use common clock. If they are, configure them to use the
182 * common clock. That will reduce the ASPM state exit latency.
184 static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
186 int ppos, cpos, same_clock = 1;
187 u16 reg16, parent_reg, child_reg[8];
188 unsigned long start_jiffies;
189 struct pci_dev *child, *parent = link->pdev;
190 struct pci_bus *linkbus = parent->subordinate;
192 * All functions of a slot should have the same Slot Clock
193 * Configuration, so just check one function
195 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
196 BUG_ON(!child->is_pcie);
198 /* Check downstream component if bit Slot Clock Configuration is 1 */
199 cpos = pci_find_capability(child, PCI_CAP_ID_EXP);
200 pci_read_config_word(child, cpos + PCI_EXP_LNKSTA, ®16);
201 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
204 /* Check upstream component if bit Slot Clock Configuration is 1 */
205 ppos = pci_find_capability(parent, PCI_CAP_ID_EXP);
206 pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, ®16);
207 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
210 /* Configure downstream component, all functions */
211 list_for_each_entry(child, &linkbus->devices, bus_list) {
212 cpos = pci_find_capability(child, PCI_CAP_ID_EXP);
213 pci_read_config_word(child, cpos + PCI_EXP_LNKCTL, ®16);
214 child_reg[PCI_FUNC(child->devfn)] = reg16;
216 reg16 |= PCI_EXP_LNKCTL_CCC;
218 reg16 &= ~PCI_EXP_LNKCTL_CCC;
219 pci_write_config_word(child, cpos + PCI_EXP_LNKCTL, reg16);
222 /* Configure upstream component */
223 pci_read_config_word(parent, ppos + PCI_EXP_LNKCTL, ®16);
226 reg16 |= PCI_EXP_LNKCTL_CCC;
228 reg16 &= ~PCI_EXP_LNKCTL_CCC;
229 pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16);
232 reg16 |= PCI_EXP_LNKCTL_RL;
233 pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16);
235 /* Wait for link training end. Break out after waiting for timeout */
236 start_jiffies = jiffies;
238 pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, ®16);
239 if (!(reg16 & PCI_EXP_LNKSTA_LT))
241 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
245 if (!(reg16 & PCI_EXP_LNKSTA_LT))
248 /* Training failed. Restore common clock configurations */
249 dev_printk(KERN_ERR, &parent->dev,
250 "ASPM: Could not configure common clock\n");
251 list_for_each_entry(child, &linkbus->devices, bus_list) {
252 cpos = pci_find_capability(child, PCI_CAP_ID_EXP);
253 pci_write_config_word(child, cpos + PCI_EXP_LNKCTL,
254 child_reg[PCI_FUNC(child->devfn)]);
256 pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, parent_reg);
259 /* Convert L0s latency encoding to ns */
260 static u32 calc_l0s_latency(u32 encoding)
263 return (5 * 1000); /* > 4us */
264 return (64 << encoding);
267 /* Convert L0s acceptable latency encoding to ns */
268 static u32 calc_l0s_acceptable(u32 encoding)
272 return (64 << encoding);
275 /* Convert L1 latency encoding to ns */
276 static u32 calc_l1_latency(u32 encoding)
279 return (65 * 1000); /* > 64us */
280 return (1000 << encoding);
283 /* Convert L1 acceptable latency encoding to ns */
284 static u32 calc_l1_acceptable(u32 encoding)
288 return (1000 << encoding);
291 static void pcie_aspm_get_cap_device(struct pci_dev *pdev, u32 *state,
292 u32 *l0s, u32 *l1, u32 *enabled)
298 *l0s = *l1 = *enabled = 0;
299 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
300 pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, ®32);
301 *state = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
302 if (*state != PCIE_LINK_STATE_L0S &&
303 *state != (PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_L0S))
308 encoding = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
309 *l0s = calc_l0s_latency(encoding);
310 if (*state & PCIE_LINK_STATE_L1) {
311 encoding = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
312 *l1 = calc_l1_latency(encoding);
314 pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16);
315 *enabled = reg16 & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
318 static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
320 u32 support, l0s, l1, enabled;
321 struct pci_dev *child, *parent = link->pdev;
322 struct pci_bus *linkbus = parent->subordinate;
325 /* Set support state to 0, so we will disable ASPM later */
326 link->aspm_support = 0;
327 link->aspm_default = 0;
328 link->aspm_enabled = PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1;
332 /* Configure common clock before checking latencies */
333 pcie_aspm_configure_common_clock(link);
335 /* upstream component states */
336 pcie_aspm_get_cap_device(parent, &support, &l0s, &l1, &enabled);
337 link->aspm_support = support;
338 link->latency.l0s = l0s;
339 link->latency.l1 = l1;
340 link->aspm_enabled = enabled;
342 /* downstream component states, all functions have the same setting */
343 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
344 pcie_aspm_get_cap_device(child, &support, &l0s, &l1, &enabled);
345 link->aspm_support &= support;
346 link->latency.l0s = max_t(u32, link->latency.l0s, l0s);
347 link->latency.l1 = max_t(u32, link->latency.l1, l1);
349 /* Save default state */
350 link->aspm_default = link->aspm_enabled;
352 if (!link->aspm_support)
356 list_for_each_entry(child, &linkbus->devices, bus_list) {
359 struct aspm_latency *acceptable =
360 &link->acceptable[PCI_FUNC(child->devfn)];
362 if (child->pcie_type != PCI_EXP_TYPE_ENDPOINT &&
363 child->pcie_type != PCI_EXP_TYPE_LEG_END)
366 pos = pci_find_capability(child, PCI_CAP_ID_EXP);
367 pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, ®32);
368 encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
369 acceptable->l0s = calc_l0s_acceptable(encoding);
370 if (link->aspm_support & PCIE_LINK_STATE_L1) {
371 encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
372 acceptable->l1 = calc_l1_acceptable(encoding);
378 * __pcie_aspm_check_state_one - check latency for endpoint device.
379 * @endpoint: pointer to the struct pci_dev of endpoint device
381 * TBD: The latency from the endpoint to root complex vary per switch's
382 * upstream link state above the device. Here we just do a simple check
383 * which assumes all links above the device can be in L1 state, that
384 * is we just consider the worst case. If switch's upstream link can't
385 * be put into L0S/L1, then our check is too strictly.
387 static u32 __pcie_aspm_check_state_one(struct pci_dev *endpoint, u32 state)
389 u32 l1_switch_latency = 0;
390 struct aspm_latency *acceptable;
391 struct pcie_link_state *link;
393 link = endpoint->bus->self->link_state;
394 state &= link->aspm_support;
395 acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)];
397 while (link && state) {
398 if ((state & PCIE_LINK_STATE_L0S) &&
399 (link->latency.l0s > acceptable->l0s))
400 state &= ~PCIE_LINK_STATE_L0S;
401 if ((state & PCIE_LINK_STATE_L1) &&
402 (link->latency.l1 + l1_switch_latency > acceptable->l1))
403 state &= ~PCIE_LINK_STATE_L1;
406 * Every switch on the path to root complex need 1
407 * more microsecond for L1. Spec doesn't mention L0s.
409 l1_switch_latency += 1000;
414 static u32 pcie_aspm_check_state(struct pcie_link_state *link, u32 state)
416 pci_power_t power_state;
417 struct pci_dev *child;
418 struct pci_bus *linkbus = link->pdev->subordinate;
420 /* If no child, ignore the link */
421 if (list_empty(&linkbus->devices))
424 list_for_each_entry(child, &linkbus->devices, bus_list) {
426 * If downstream component of a link is pci bridge, we
427 * disable ASPM for now for the link
429 if (child->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
432 if ((child->pcie_type != PCI_EXP_TYPE_ENDPOINT &&
433 child->pcie_type != PCI_EXP_TYPE_LEG_END))
435 /* Device not in D0 doesn't need check latency */
436 power_state = child->current_state;
437 if (power_state == PCI_D1 || power_state == PCI_D2 ||
438 power_state == PCI_D3hot || power_state == PCI_D3cold)
440 state = __pcie_aspm_check_state_one(child, state);
445 static void __pcie_aspm_config_one_dev(struct pci_dev *pdev, unsigned int state)
448 int pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
450 pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16);
453 pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
456 static void __pcie_aspm_config_link(struct pcie_link_state *link, u32 state)
458 struct pci_dev *child, *parent = link->pdev;
459 struct pci_bus *linkbus = parent->subordinate;
462 * If the downstream component has pci bridge function, don't
465 list_for_each_entry(child, &linkbus->devices, bus_list) {
466 if (child->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
470 * Spec 2.0 suggests all functions should be configured the
471 * same setting for ASPM. Enabling ASPM L1 should be done in
472 * upstream component first and then downstream, and vice
473 * versa for disabling ASPM L1. Spec doesn't mention L0S.
475 if (state & PCIE_LINK_STATE_L1)
476 __pcie_aspm_config_one_dev(parent, state);
478 list_for_each_entry(child, &linkbus->devices, bus_list)
479 __pcie_aspm_config_one_dev(child, state);
481 if (!(state & PCIE_LINK_STATE_L1))
482 __pcie_aspm_config_one_dev(parent, state);
484 link->aspm_enabled = state;
487 /* Check the whole hierarchy, and configure each link in the hierarchy */
488 static void __pcie_aspm_configure_link_state(struct pcie_link_state *link,
491 struct pcie_link_state *leaf, *root = link->root;
493 state &= (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
495 /* Check all links who have specific root port link */
496 list_for_each_entry(leaf, &link_list, sibling) {
497 if (!list_empty(&leaf->children) || (leaf->root != root))
499 state = pcie_aspm_check_state(leaf, state);
501 /* Check root port link too in case it hasn't children */
502 state = pcie_aspm_check_state(root, state);
503 if (link->aspm_enabled == state)
506 * We must change the hierarchy. See comments in
507 * __pcie_aspm_config_link for the order
509 if (state & PCIE_LINK_STATE_L1) {
510 list_for_each_entry(leaf, &link_list, sibling) {
511 if (leaf->root == root)
512 __pcie_aspm_config_link(leaf, state);
515 list_for_each_entry_reverse(leaf, &link_list, sibling) {
516 if (leaf->root == root)
517 __pcie_aspm_config_link(leaf, state);
523 * pcie_aspm_configure_link_state: enable/disable PCI express link state
524 * @pdev: the root port or switch downstream port
526 static void pcie_aspm_configure_link_state(struct pcie_link_state *link,
529 down_read(&pci_bus_sem);
530 mutex_lock(&aspm_lock);
531 __pcie_aspm_configure_link_state(link, state);
532 mutex_unlock(&aspm_lock);
533 up_read(&pci_bus_sem);
536 static void free_link_state(struct pcie_link_state *link)
538 link->pdev->link_state = NULL;
542 static int pcie_aspm_sanity_check(struct pci_dev *pdev)
544 struct pci_dev *child;
548 * Some functions in a slot might not all be PCIE functions,
549 * very strange. Disable ASPM for the whole slot
551 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
552 pos = pci_find_capability(child, PCI_CAP_ID_EXP);
556 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
557 * RBER bit to determine if a function is 1.1 version device
559 pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, ®32);
560 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
561 dev_printk(KERN_INFO, &child->dev, "disabling ASPM"
562 " on pre-1.1 PCIe device. You can enable it"
563 " with 'pcie_aspm=force'\n");
570 static struct pcie_link_state *pcie_aspm_setup_link_state(struct pci_dev *pdev)
572 struct pcie_link_state *link;
573 int blacklist = !!pcie_aspm_sanity_check(pdev);
575 link = kzalloc(sizeof(*link), GFP_KERNEL);
578 INIT_LIST_HEAD(&link->sibling);
579 INIT_LIST_HEAD(&link->children);
580 INIT_LIST_HEAD(&link->link);
582 if (pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) {
583 struct pcie_link_state *parent;
584 parent = pdev->bus->parent->self->link_state;
589 link->parent = parent;
590 list_add(&link->link, &parent->children);
592 /* Setup a pointer to the root port link */
596 link->root = link->parent->root;
598 list_add(&link->sibling, &link_list);
600 pdev->link_state = link;
602 /* Check ASPM capability */
603 pcie_aspm_cap_init(link, blacklist);
605 /* Check Clock PM capability */
606 pcie_clkpm_cap_init(link, blacklist);
612 * pcie_aspm_init_link_state: Initiate PCI express link state.
613 * It is called after the pcie and its children devices are scaned.
614 * @pdev: the root port or switch downstream port
616 void pcie_aspm_init_link_state(struct pci_dev *pdev)
619 struct pcie_link_state *link;
621 if (aspm_disabled || !pdev->is_pcie || pdev->link_state)
623 if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
624 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)
627 /* VIA has a strange chipset, root port is under a bridge */
628 if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT &&
632 down_read(&pci_bus_sem);
633 if (list_empty(&pdev->subordinate->devices))
636 mutex_lock(&aspm_lock);
637 link = pcie_aspm_setup_link_state(pdev);
641 * Setup initial ASPM state
643 * If link has switch, delay the link config. The leaf link
644 * initialization will config the whole hierarchy. But we must
645 * make sure BIOS doesn't set unsupported link state.
647 if (pcie_aspm_downstream_has_switch(link)) {
648 state = pcie_aspm_check_state(link, link->aspm_default);
649 __pcie_aspm_config_link(link, state);
651 state = policy_to_aspm_state(link);
652 __pcie_aspm_configure_link_state(link, state);
655 /* Setup initial Clock PM state */
656 state = (link->clkpm_capable) ? policy_to_clkpm_state(link) : 0;
657 pcie_set_clkpm(link, state);
659 mutex_unlock(&aspm_lock);
661 up_read(&pci_bus_sem);
664 /* @pdev: the endpoint device */
665 void pcie_aspm_exit_link_state(struct pci_dev *pdev)
667 struct pci_dev *parent = pdev->bus->self;
668 struct pcie_link_state *link_state = parent->link_state;
670 if (aspm_disabled || !pdev->is_pcie || !parent || !link_state)
672 if (parent->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
673 parent->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)
675 down_read(&pci_bus_sem);
676 mutex_lock(&aspm_lock);
679 * All PCIe functions are in one slot, remove one function will remove
680 * the whole slot, so just wait until we are the last function left.
682 if (!list_is_last(&pdev->bus_list, &parent->subordinate->devices))
685 /* All functions are removed, so just disable ASPM for the link */
686 __pcie_aspm_config_one_dev(parent, 0);
687 list_del(&link_state->sibling);
688 list_del(&link_state->link);
689 /* Clock PM is for endpoint device */
691 free_link_state(link_state);
693 mutex_unlock(&aspm_lock);
694 up_read(&pci_bus_sem);
697 /* @pdev: the root port or switch downstream port */
698 void pcie_aspm_pm_state_change(struct pci_dev *pdev)
700 struct pcie_link_state *link_state = pdev->link_state;
702 if (aspm_disabled || !pdev->is_pcie || !pdev->link_state)
704 if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
705 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)
708 * devices changed PM state, we should recheck if latency meets all
709 * functions' requirement
711 pcie_aspm_configure_link_state(link_state, link_state->aspm_enabled);
715 * pci_disable_link_state - disable pci device's link state, so the link will
716 * never enter specific states
718 void pci_disable_link_state(struct pci_dev *pdev, int state)
720 struct pci_dev *parent = pdev->bus->self;
721 struct pcie_link_state *link_state;
723 if (aspm_disabled || !pdev->is_pcie)
725 if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
726 pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
728 if (!parent || !parent->link_state)
731 down_read(&pci_bus_sem);
732 mutex_lock(&aspm_lock);
733 link_state = parent->link_state;
734 link_state->aspm_support &= ~state;
735 __pcie_aspm_configure_link_state(link_state, link_state->aspm_enabled);
736 if (state & PCIE_LINK_STATE_CLKPM) {
737 link_state->clkpm_capable = 0;
738 pcie_set_clkpm(link_state, 0);
740 mutex_unlock(&aspm_lock);
741 up_read(&pci_bus_sem);
743 EXPORT_SYMBOL(pci_disable_link_state);
745 static int pcie_aspm_set_policy(const char *val, struct kernel_param *kp)
748 struct pcie_link_state *link_state;
750 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
751 if (!strncmp(val, policy_str[i], strlen(policy_str[i])))
753 if (i >= ARRAY_SIZE(policy_str))
755 if (i == aspm_policy)
758 down_read(&pci_bus_sem);
759 mutex_lock(&aspm_lock);
761 list_for_each_entry(link_state, &link_list, sibling) {
762 __pcie_aspm_configure_link_state(link_state,
763 policy_to_aspm_state(link_state));
764 pcie_set_clkpm(link_state, policy_to_clkpm_state(link_state));
766 mutex_unlock(&aspm_lock);
767 up_read(&pci_bus_sem);
771 static int pcie_aspm_get_policy(char *buffer, struct kernel_param *kp)
774 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
775 if (i == aspm_policy)
776 cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
778 cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
782 module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
785 #ifdef CONFIG_PCIEASPM_DEBUG
786 static ssize_t link_state_show(struct device *dev,
787 struct device_attribute *attr,
790 struct pci_dev *pci_device = to_pci_dev(dev);
791 struct pcie_link_state *link_state = pci_device->link_state;
793 return sprintf(buf, "%d\n", link_state->aspm_enabled);
796 static ssize_t link_state_store(struct device *dev,
797 struct device_attribute *attr,
801 struct pci_dev *pdev = to_pci_dev(dev);
807 if (state >= 0 && state <= 3) {
808 /* setup link aspm state */
809 pcie_aspm_configure_link_state(pdev->link_state, state);
816 static ssize_t clk_ctl_show(struct device *dev,
817 struct device_attribute *attr,
820 struct pci_dev *pci_device = to_pci_dev(dev);
821 struct pcie_link_state *link_state = pci_device->link_state;
823 return sprintf(buf, "%d\n", link_state->clkpm_enabled);
826 static ssize_t clk_ctl_store(struct device *dev,
827 struct device_attribute *attr,
831 struct pci_dev *pdev = to_pci_dev(dev);
838 down_read(&pci_bus_sem);
839 mutex_lock(&aspm_lock);
840 pcie_set_clkpm_nocheck(pdev->link_state, !!state);
841 mutex_unlock(&aspm_lock);
842 up_read(&pci_bus_sem);
847 static DEVICE_ATTR(link_state, 0644, link_state_show, link_state_store);
848 static DEVICE_ATTR(clk_ctl, 0644, clk_ctl_show, clk_ctl_store);
850 static char power_group[] = "power";
851 void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
853 struct pcie_link_state *link_state = pdev->link_state;
855 if (!pdev->is_pcie || (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
856 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state)
859 if (link_state->aspm_support)
860 sysfs_add_file_to_group(&pdev->dev.kobj,
861 &dev_attr_link_state.attr, power_group);
862 if (link_state->clkpm_capable)
863 sysfs_add_file_to_group(&pdev->dev.kobj,
864 &dev_attr_clk_ctl.attr, power_group);
867 void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
869 struct pcie_link_state *link_state = pdev->link_state;
871 if (!pdev->is_pcie || (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
872 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state)
875 if (link_state->aspm_support)
876 sysfs_remove_file_from_group(&pdev->dev.kobj,
877 &dev_attr_link_state.attr, power_group);
878 if (link_state->clkpm_capable)
879 sysfs_remove_file_from_group(&pdev->dev.kobj,
880 &dev_attr_clk_ctl.attr, power_group);
884 static int __init pcie_aspm_disable(char *str)
886 if (!strcmp(str, "off")) {
888 printk(KERN_INFO "PCIe ASPM is disabled\n");
889 } else if (!strcmp(str, "force")) {
891 printk(KERN_INFO "PCIe ASPM is forcedly enabled\n");
896 __setup("pcie_aspm=", pcie_aspm_disable);
898 void pcie_no_aspm(void)
905 * pcie_aspm_enabled - is PCIe ASPM enabled?
907 * Returns true if ASPM has not been disabled by the command-line option
910 int pcie_aspm_enabled(void)
912 return !aspm_disabled;
914 EXPORT_SYMBOL(pcie_aspm_enabled);