2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/string.h>
18 #include <linux/log2.h>
19 #include <linux/pci-aspm.h>
20 #include <linux/pm_wakeup.h>
21 #include <linux/interrupt.h>
22 #include <linux/device.h>
23 #include <linux/pm_runtime.h>
24 #include <asm/setup.h>
27 const char *pci_power_names[] = {
28 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
30 EXPORT_SYMBOL_GPL(pci_power_names);
32 int isa_dma_bridge_buggy;
33 EXPORT_SYMBOL(isa_dma_bridge_buggy);
36 EXPORT_SYMBOL(pci_pci_problems);
38 unsigned int pci_pm_d3_delay;
40 static void pci_dev_d3_sleep(struct pci_dev *dev)
42 unsigned int delay = dev->d3_delay;
44 if (delay < pci_pm_d3_delay)
45 delay = pci_pm_d3_delay;
50 #ifdef CONFIG_PCI_DOMAINS
51 int pci_domains_supported = 1;
54 #define DEFAULT_CARDBUS_IO_SIZE (256)
55 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
56 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
57 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
58 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
60 #define DEFAULT_HOTPLUG_IO_SIZE (256)
61 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
62 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
63 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
64 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
67 * The default CLS is used if arch didn't set CLS explicitly and not
68 * all pci devices agree on the same value. Arch can override either
69 * the dfl or actual value as it sees fit. Don't forget this is
70 * measured in 32-bit words, not bytes.
72 u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
73 u8 pci_cache_line_size;
76 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
77 * @bus: pointer to PCI bus structure to search
79 * Given a PCI bus, returns the highest PCI bus number present in the set
80 * including the given PCI bus and its list of child PCI buses.
82 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
84 struct list_head *tmp;
87 max = bus->subordinate;
88 list_for_each(tmp, &bus->children) {
89 n = pci_bus_max_busnr(pci_bus_b(tmp));
95 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
97 #ifdef CONFIG_HAS_IOMEM
98 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
101 * Make sure the BAR is actually a memory resource, not an IO resource
103 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
107 return ioremap_nocache(pci_resource_start(pdev, bar),
108 pci_resource_len(pdev, bar));
110 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
115 * pci_max_busnr - returns maximum PCI bus number
117 * Returns the highest PCI bus number present in the system global list of
120 unsigned char __devinit
123 struct pci_bus *bus = NULL;
124 unsigned char max, n;
127 while ((bus = pci_find_next_bus(bus)) != NULL) {
128 n = pci_bus_max_busnr(bus);
137 #define PCI_FIND_CAP_TTL 48
139 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
140 u8 pos, int cap, int *ttl)
145 pci_bus_read_config_byte(bus, devfn, pos, &pos);
149 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
155 pos += PCI_CAP_LIST_NEXT;
160 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
163 int ttl = PCI_FIND_CAP_TTL;
165 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
168 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
170 return __pci_find_next_cap(dev->bus, dev->devfn,
171 pos + PCI_CAP_LIST_NEXT, cap);
173 EXPORT_SYMBOL_GPL(pci_find_next_capability);
175 static int __pci_bus_find_cap_start(struct pci_bus *bus,
176 unsigned int devfn, u8 hdr_type)
180 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
181 if (!(status & PCI_STATUS_CAP_LIST))
185 case PCI_HEADER_TYPE_NORMAL:
186 case PCI_HEADER_TYPE_BRIDGE:
187 return PCI_CAPABILITY_LIST;
188 case PCI_HEADER_TYPE_CARDBUS:
189 return PCI_CB_CAPABILITY_LIST;
198 * pci_find_capability - query for devices' capabilities
199 * @dev: PCI device to query
200 * @cap: capability code
202 * Tell if a device supports a given PCI capability.
203 * Returns the address of the requested capability structure within the
204 * device's PCI configuration space or 0 in case the device does not
205 * support it. Possible values for @cap:
207 * %PCI_CAP_ID_PM Power Management
208 * %PCI_CAP_ID_AGP Accelerated Graphics Port
209 * %PCI_CAP_ID_VPD Vital Product Data
210 * %PCI_CAP_ID_SLOTID Slot Identification
211 * %PCI_CAP_ID_MSI Message Signalled Interrupts
212 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
213 * %PCI_CAP_ID_PCIX PCI-X
214 * %PCI_CAP_ID_EXP PCI Express
216 int pci_find_capability(struct pci_dev *dev, int cap)
220 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
222 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
228 * pci_bus_find_capability - query for devices' capabilities
229 * @bus: the PCI bus to query
230 * @devfn: PCI device to query
231 * @cap: capability code
233 * Like pci_find_capability() but works for pci devices that do not have a
234 * pci_dev structure set up yet.
236 * Returns the address of the requested capability structure within the
237 * device's PCI configuration space or 0 in case the device does not
240 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
245 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
247 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
249 pos = __pci_find_next_cap(bus, devfn, pos, cap);
255 * pci_find_ext_capability - Find an extended capability
256 * @dev: PCI device to query
257 * @cap: capability code
259 * Returns the address of the requested extended capability structure
260 * within the device's PCI configuration space or 0 if the device does
261 * not support it. Possible values for @cap:
263 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
264 * %PCI_EXT_CAP_ID_VC Virtual Channel
265 * %PCI_EXT_CAP_ID_DSN Device Serial Number
266 * %PCI_EXT_CAP_ID_PWR Power Budgeting
268 int pci_find_ext_capability(struct pci_dev *dev, int cap)
272 int pos = PCI_CFG_SPACE_SIZE;
274 /* minimum 8 bytes per capability */
275 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
277 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
280 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
284 * If we have no capabilities, this is indicated by cap ID,
285 * cap version and next pointer all being 0.
291 if (PCI_EXT_CAP_ID(header) == cap)
294 pos = PCI_EXT_CAP_NEXT(header);
295 if (pos < PCI_CFG_SPACE_SIZE)
298 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
304 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
306 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
308 int rc, ttl = PCI_FIND_CAP_TTL;
311 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
312 mask = HT_3BIT_CAP_MASK;
314 mask = HT_5BIT_CAP_MASK;
316 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
317 PCI_CAP_ID_HT, &ttl);
319 rc = pci_read_config_byte(dev, pos + 3, &cap);
320 if (rc != PCIBIOS_SUCCESSFUL)
323 if ((cap & mask) == ht_cap)
326 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
327 pos + PCI_CAP_LIST_NEXT,
328 PCI_CAP_ID_HT, &ttl);
334 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
335 * @dev: PCI device to query
336 * @pos: Position from which to continue searching
337 * @ht_cap: Hypertransport capability code
339 * To be used in conjunction with pci_find_ht_capability() to search for
340 * all capabilities matching @ht_cap. @pos should always be a value returned
341 * from pci_find_ht_capability().
343 * NB. To be 100% safe against broken PCI devices, the caller should take
344 * steps to avoid an infinite loop.
346 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
348 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
350 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
353 * pci_find_ht_capability - query a device's Hypertransport capabilities
354 * @dev: PCI device to query
355 * @ht_cap: Hypertransport capability code
357 * Tell if a device supports a given Hypertransport capability.
358 * Returns an address within the device's PCI configuration space
359 * or 0 in case the device does not support the request capability.
360 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
361 * which has a Hypertransport capability matching @ht_cap.
363 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
367 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
369 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
373 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
376 * pci_find_parent_resource - return resource region of parent bus of given region
377 * @dev: PCI device structure contains resources to be searched
378 * @res: child resource record for which parent is sought
380 * For given resource region of given device, return the resource
381 * region of parent bus the given region is contained in or where
382 * it should be allocated from.
385 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
387 const struct pci_bus *bus = dev->bus;
389 struct resource *best = NULL;
391 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
392 struct resource *r = bus->resource[i];
395 if (res->start && !(res->start >= r->start && res->end <= r->end))
396 continue; /* Not contained */
397 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
398 continue; /* Wrong type */
399 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
400 return r; /* Exact match */
401 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
402 if (r->flags & IORESOURCE_PREFETCH)
404 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
412 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
413 * @dev: PCI device to have its BARs restored
415 * Restore the BAR values for a given device, so as to make it
416 * accessible by its driver.
419 pci_restore_bars(struct pci_dev *dev)
423 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
424 pci_update_resource(dev, i);
427 static struct pci_platform_pm_ops *pci_platform_pm;
429 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
431 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
432 || !ops->sleep_wake || !ops->can_wakeup)
434 pci_platform_pm = ops;
438 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
440 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
443 static inline int platform_pci_set_power_state(struct pci_dev *dev,
446 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
449 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
451 return pci_platform_pm ?
452 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
455 static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
457 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
460 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
462 return pci_platform_pm ?
463 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
466 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
468 return pci_platform_pm ?
469 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
473 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
475 * @dev: PCI device to handle.
476 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
479 * -EINVAL if the requested state is invalid.
480 * -EIO if device does not support PCI PM or its PM capabilities register has a
481 * wrong version, or device doesn't support the requested state.
482 * 0 if device already is in the requested state.
483 * 0 if device's power state has been successfully changed.
485 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
488 bool need_restore = false;
490 /* Check if we're already there */
491 if (dev->current_state == state)
497 if (state < PCI_D0 || state > PCI_D3hot)
500 /* Validate current state:
501 * Can enter D0 from any state, but if we can only go deeper
502 * to sleep if we're already in a low power state
504 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
505 && dev->current_state > state) {
506 dev_err(&dev->dev, "invalid power transition "
507 "(from state %d to %d)\n", dev->current_state, state);
511 /* check if this device supports the desired state */
512 if ((state == PCI_D1 && !dev->d1_support)
513 || (state == PCI_D2 && !dev->d2_support))
516 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
518 /* If we're (effectively) in D3, force entire word to 0.
519 * This doesn't affect PME_Status, disables PME_En, and
520 * sets PowerState to 0.
522 switch (dev->current_state) {
526 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
531 case PCI_UNKNOWN: /* Boot-up */
532 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
533 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
535 /* Fall-through: force to D0 */
541 /* enter specified state */
542 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
544 /* Mandatory power management transition delays */
545 /* see PCI PM 1.1 5.6.1 table 18 */
546 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
547 pci_dev_d3_sleep(dev);
548 else if (state == PCI_D2 || dev->current_state == PCI_D2)
549 udelay(PCI_PM_D2_DELAY);
551 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
552 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
553 if (dev->current_state != state && printk_ratelimit())
554 dev_info(&dev->dev, "Refused to change power state, "
555 "currently in D%d\n", dev->current_state);
557 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
558 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
559 * from D3hot to D0 _may_ perform an internal reset, thereby
560 * going to "D0 Uninitialized" rather than "D0 Initialized".
561 * For example, at least some versions of the 3c905B and the
562 * 3c556B exhibit this behaviour.
564 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
565 * devices in a D3hot state at boot. Consequently, we need to
566 * restore at least the BARs so that the device will be
567 * accessible to its driver.
570 pci_restore_bars(dev);
573 pcie_aspm_pm_state_change(dev->bus->self);
579 * pci_update_current_state - Read PCI power state of given device from its
580 * PCI PM registers and cache it
581 * @dev: PCI device to handle.
582 * @state: State to cache in case the device doesn't have the PM capability
584 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
589 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
590 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
592 dev->current_state = state;
597 * pci_platform_power_transition - Use platform to change device power state
598 * @dev: PCI device to handle.
599 * @state: State to put the device into.
601 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
605 if (platform_pci_power_manageable(dev)) {
606 error = platform_pci_set_power_state(dev, state);
608 pci_update_current_state(dev, state);
611 /* Fall back to PCI_D0 if native PM is not supported */
613 dev->current_state = PCI_D0;
620 * __pci_start_power_transition - Start power transition of a PCI device
621 * @dev: PCI device to handle.
622 * @state: State to put the device into.
624 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
627 pci_platform_power_transition(dev, PCI_D0);
631 * __pci_complete_power_transition - Complete power transition of a PCI device
632 * @dev: PCI device to handle.
633 * @state: State to put the device into.
635 * This function should not be called directly by device drivers.
637 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
639 return state > PCI_D0 ?
640 pci_platform_power_transition(dev, state) : -EINVAL;
642 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
645 * pci_set_power_state - Set the power state of a PCI device
646 * @dev: PCI device to handle.
647 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
649 * Transition a device to a new power state, using the platform firmware and/or
650 * the device's PCI PM registers.
653 * -EINVAL if the requested state is invalid.
654 * -EIO if device does not support PCI PM or its PM capabilities register has a
655 * wrong version, or device doesn't support the requested state.
656 * 0 if device already is in the requested state.
657 * 0 if device's power state has been successfully changed.
659 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
663 /* bound the state we're entering */
664 if (state > PCI_D3hot)
666 else if (state < PCI_D0)
668 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
670 * If the device or the parent bridge do not support PCI PM,
671 * ignore the request if we're doing anything other than putting
672 * it into D0 (which would only happen on boot).
676 /* Check if we're already there */
677 if (dev->current_state == state)
680 __pci_start_power_transition(dev, state);
682 /* This device is quirked not to be put into D3, so
683 don't put it in D3 */
684 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
687 error = pci_raw_set_power_state(dev, state);
689 if (!__pci_complete_power_transition(dev, state))
696 * pci_choose_state - Choose the power state of a PCI device
697 * @dev: PCI device to be suspended
698 * @state: target sleep state for the whole system. This is the value
699 * that is passed to suspend() function.
701 * Returns PCI power state suitable for given device and given system
705 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
709 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
712 ret = platform_pci_choose_state(dev);
713 if (ret != PCI_POWER_ERROR)
716 switch (state.event) {
719 case PM_EVENT_FREEZE:
720 case PM_EVENT_PRETHAW:
721 /* REVISIT both freeze and pre-thaw "should" use D0 */
722 case PM_EVENT_SUSPEND:
723 case PM_EVENT_HIBERNATE:
726 dev_info(&dev->dev, "unrecognized suspend event %d\n",
733 EXPORT_SYMBOL(pci_choose_state);
735 #define PCI_EXP_SAVE_REGS 7
737 #define pcie_cap_has_devctl(type, flags) 1
738 #define pcie_cap_has_lnkctl(type, flags) \
739 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
740 (type == PCI_EXP_TYPE_ROOT_PORT || \
741 type == PCI_EXP_TYPE_ENDPOINT || \
742 type == PCI_EXP_TYPE_LEG_END))
743 #define pcie_cap_has_sltctl(type, flags) \
744 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
745 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
746 (type == PCI_EXP_TYPE_DOWNSTREAM && \
747 (flags & PCI_EXP_FLAGS_SLOT))))
748 #define pcie_cap_has_rtctl(type, flags) \
749 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
750 (type == PCI_EXP_TYPE_ROOT_PORT || \
751 type == PCI_EXP_TYPE_RC_EC))
752 #define pcie_cap_has_devctl2(type, flags) \
753 ((flags & PCI_EXP_FLAGS_VERS) > 1)
754 #define pcie_cap_has_lnkctl2(type, flags) \
755 ((flags & PCI_EXP_FLAGS_VERS) > 1)
756 #define pcie_cap_has_sltctl2(type, flags) \
757 ((flags & PCI_EXP_FLAGS_VERS) > 1)
759 static int pci_save_pcie_state(struct pci_dev *dev)
762 struct pci_cap_saved_state *save_state;
766 pos = pci_pcie_cap(dev);
770 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
772 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
775 cap = (u16 *)&save_state->data[0];
777 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
779 if (pcie_cap_has_devctl(dev->pcie_type, flags))
780 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
781 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
782 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
783 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
784 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
785 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
786 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
787 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
788 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
789 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
790 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
791 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
792 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
797 static void pci_restore_pcie_state(struct pci_dev *dev)
800 struct pci_cap_saved_state *save_state;
804 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
805 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
806 if (!save_state || pos <= 0)
808 cap = (u16 *)&save_state->data[0];
810 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
812 if (pcie_cap_has_devctl(dev->pcie_type, flags))
813 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
814 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
815 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
816 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
817 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
818 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
819 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
820 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
821 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
822 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
823 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
824 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
825 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
829 static int pci_save_pcix_state(struct pci_dev *dev)
832 struct pci_cap_saved_state *save_state;
834 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
838 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
840 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
844 pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data);
849 static void pci_restore_pcix_state(struct pci_dev *dev)
852 struct pci_cap_saved_state *save_state;
855 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
856 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
857 if (!save_state || pos <= 0)
859 cap = (u16 *)&save_state->data[0];
861 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
866 * pci_save_state - save the PCI configuration space of a device before suspending
867 * @dev: - PCI device that we're dealing with
870 pci_save_state(struct pci_dev *dev)
873 /* XXX: 100% dword access ok here? */
874 for (i = 0; i < 16; i++)
875 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
876 dev->state_saved = true;
877 if ((i = pci_save_pcie_state(dev)) != 0)
879 if ((i = pci_save_pcix_state(dev)) != 0)
885 * pci_restore_state - Restore the saved state of a PCI device
886 * @dev: - PCI device that we're dealing with
889 pci_restore_state(struct pci_dev *dev)
894 if (!dev->state_saved)
897 /* PCI Express register must be restored first */
898 pci_restore_pcie_state(dev);
901 * The Base Address register should be programmed before the command
904 for (i = 15; i >= 0; i--) {
905 pci_read_config_dword(dev, i * 4, &val);
906 if (val != dev->saved_config_space[i]) {
907 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
908 "space at offset %#x (was %#x, writing %#x)\n",
909 i, val, (int)dev->saved_config_space[i]);
910 pci_write_config_dword(dev,i * 4,
911 dev->saved_config_space[i]);
914 pci_restore_pcix_state(dev);
915 pci_restore_msi_state(dev);
916 pci_restore_iov_state(dev);
918 dev->state_saved = false;
923 static int do_pci_enable_device(struct pci_dev *dev, int bars)
927 err = pci_set_power_state(dev, PCI_D0);
928 if (err < 0 && err != -EIO)
930 err = pcibios_enable_device(dev, bars);
933 pci_fixup_device(pci_fixup_enable, dev);
939 * pci_reenable_device - Resume abandoned device
940 * @dev: PCI device to be resumed
942 * Note this function is a backend of pci_default_resume and is not supposed
943 * to be called by normal code, write proper resume handler and use it instead.
945 int pci_reenable_device(struct pci_dev *dev)
947 if (pci_is_enabled(dev))
948 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
952 static int __pci_enable_device_flags(struct pci_dev *dev,
953 resource_size_t flags)
958 if (atomic_add_return(1, &dev->enable_cnt) > 1)
959 return 0; /* already enabled */
961 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
962 if (dev->resource[i].flags & flags)
965 err = do_pci_enable_device(dev, bars);
967 atomic_dec(&dev->enable_cnt);
972 * pci_enable_device_io - Initialize a device for use with IO space
973 * @dev: PCI device to be initialized
975 * Initialize device before it's used by a driver. Ask low-level code
976 * to enable I/O resources. Wake up the device if it was suspended.
977 * Beware, this function can fail.
979 int pci_enable_device_io(struct pci_dev *dev)
981 return __pci_enable_device_flags(dev, IORESOURCE_IO);
985 * pci_enable_device_mem - Initialize a device for use with Memory space
986 * @dev: PCI device to be initialized
988 * Initialize device before it's used by a driver. Ask low-level code
989 * to enable Memory resources. Wake up the device if it was suspended.
990 * Beware, this function can fail.
992 int pci_enable_device_mem(struct pci_dev *dev)
994 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
998 * pci_enable_device - Initialize device before it's used by a driver.
999 * @dev: PCI device to be initialized
1001 * Initialize device before it's used by a driver. Ask low-level code
1002 * to enable I/O and memory. Wake up the device if it was suspended.
1003 * Beware, this function can fail.
1005 * Note we don't actually enable the device many times if we call
1006 * this function repeatedly (we just increment the count).
1008 int pci_enable_device(struct pci_dev *dev)
1010 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1014 * Managed PCI resources. This manages device on/off, intx/msi/msix
1015 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1016 * there's no need to track it separately. pci_devres is initialized
1017 * when a device is enabled using managed PCI device enable interface.
1020 unsigned int enabled:1;
1021 unsigned int pinned:1;
1022 unsigned int orig_intx:1;
1023 unsigned int restore_intx:1;
1027 static void pcim_release(struct device *gendev, void *res)
1029 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1030 struct pci_devres *this = res;
1033 if (dev->msi_enabled)
1034 pci_disable_msi(dev);
1035 if (dev->msix_enabled)
1036 pci_disable_msix(dev);
1038 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1039 if (this->region_mask & (1 << i))
1040 pci_release_region(dev, i);
1042 if (this->restore_intx)
1043 pci_intx(dev, this->orig_intx);
1045 if (this->enabled && !this->pinned)
1046 pci_disable_device(dev);
1049 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1051 struct pci_devres *dr, *new_dr;
1053 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1057 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1060 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1063 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1065 if (pci_is_managed(pdev))
1066 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1071 * pcim_enable_device - Managed pci_enable_device()
1072 * @pdev: PCI device to be initialized
1074 * Managed pci_enable_device().
1076 int pcim_enable_device(struct pci_dev *pdev)
1078 struct pci_devres *dr;
1081 dr = get_pci_dr(pdev);
1087 rc = pci_enable_device(pdev);
1089 pdev->is_managed = 1;
1096 * pcim_pin_device - Pin managed PCI device
1097 * @pdev: PCI device to pin
1099 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1100 * driver detach. @pdev must have been enabled with
1101 * pcim_enable_device().
1103 void pcim_pin_device(struct pci_dev *pdev)
1105 struct pci_devres *dr;
1107 dr = find_pci_dr(pdev);
1108 WARN_ON(!dr || !dr->enabled);
1114 * pcibios_disable_device - disable arch specific PCI resources for device dev
1115 * @dev: the PCI device to disable
1117 * Disables architecture specific PCI resources for the device. This
1118 * is the default implementation. Architecture implementations can
1121 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
1123 static void do_pci_disable_device(struct pci_dev *dev)
1127 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1128 if (pci_command & PCI_COMMAND_MASTER) {
1129 pci_command &= ~PCI_COMMAND_MASTER;
1130 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1133 pcibios_disable_device(dev);
1137 * pci_disable_enabled_device - Disable device without updating enable_cnt
1138 * @dev: PCI device to disable
1140 * NOTE: This function is a backend of PCI power management routines and is
1141 * not supposed to be called drivers.
1143 void pci_disable_enabled_device(struct pci_dev *dev)
1145 if (pci_is_enabled(dev))
1146 do_pci_disable_device(dev);
1150 * pci_disable_device - Disable PCI device after use
1151 * @dev: PCI device to be disabled
1153 * Signal to the system that the PCI device is not in use by the system
1154 * anymore. This only involves disabling PCI bus-mastering, if active.
1156 * Note we don't actually disable the device until all callers of
1157 * pci_device_enable() have called pci_device_disable().
1160 pci_disable_device(struct pci_dev *dev)
1162 struct pci_devres *dr;
1164 dr = find_pci_dr(dev);
1168 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1171 do_pci_disable_device(dev);
1173 dev->is_busmaster = 0;
1177 * pcibios_set_pcie_reset_state - set reset state for device dev
1178 * @dev: the PCIe device reset
1179 * @state: Reset state to enter into
1182 * Sets the PCIe reset state for the device. This is the default
1183 * implementation. Architecture implementations can override this.
1185 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1186 enum pcie_reset_state state)
1192 * pci_set_pcie_reset_state - set reset state for device dev
1193 * @dev: the PCIe device reset
1194 * @state: Reset state to enter into
1197 * Sets the PCI reset state for the device.
1199 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1201 return pcibios_set_pcie_reset_state(dev, state);
1205 * pci_check_pme_status - Check if given device has generated PME.
1206 * @dev: Device to check.
1208 * Check the PME status of the device and if set, clear it and clear PME enable
1209 * (if set). Return 'true' if PME status and PME enable were both set or
1210 * 'false' otherwise.
1212 bool pci_check_pme_status(struct pci_dev *dev)
1221 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1222 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1223 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1226 /* Clear PME status. */
1227 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1228 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1229 /* Disable PME to avoid interrupt flood. */
1230 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1234 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1240 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1241 * @dev: Device to handle.
1244 * Check if @dev has generated PME and queue a resume request for it in that
1247 static int pci_pme_wakeup(struct pci_dev *dev, void *ign)
1249 if (pci_check_pme_status(dev))
1250 pm_request_resume(&dev->dev);
1255 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1256 * @bus: Top bus of the subtree to walk.
1258 void pci_pme_wakeup_bus(struct pci_bus *bus)
1261 pci_walk_bus(bus, pci_pme_wakeup, NULL);
1265 * pci_pme_capable - check the capability of PCI device to generate PME#
1266 * @dev: PCI device to handle.
1267 * @state: PCI state from which device will issue PME#.
1269 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1274 return !!(dev->pme_support & (1 << state));
1278 * pci_pme_active - enable or disable PCI device's PME# function
1279 * @dev: PCI device to handle.
1280 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1282 * The caller must verify that the device is capable of generating PME# before
1283 * calling this function with @enable equal to 'true'.
1285 void pci_pme_active(struct pci_dev *dev, bool enable)
1292 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1293 /* Clear PME_Status by writing 1 to it and enable PME# */
1294 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1296 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1298 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1300 dev_printk(KERN_DEBUG, &dev->dev, "PME# %s\n",
1301 enable ? "enabled" : "disabled");
1305 * pci_enable_wake - enable PCI device as wakeup event source
1306 * @dev: PCI device affected
1307 * @state: PCI state from which device will issue wakeup events
1308 * @enable: True to enable event generation; false to disable
1310 * This enables the device as a wakeup event source, or disables it.
1311 * When such events involves platform-specific hooks, those hooks are
1312 * called automatically by this routine.
1314 * Devices with legacy power management (no standard PCI PM capabilities)
1315 * always require such platform hooks.
1318 * 0 is returned on success
1319 * -EINVAL is returned if device is not supposed to wake up the system
1320 * Error code depending on the platform is returned if both the platform and
1321 * the native mechanism fail to enable the generation of wake-up events
1323 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
1327 if (enable && !device_may_wakeup(&dev->dev))
1330 /* Don't do the same thing twice in a row for one device. */
1331 if (!!enable == !!dev->wakeup_prepared)
1335 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1336 * Anderson we should be doing PME# wake enable followed by ACPI wake
1337 * enable. To disable wake-up we call the platform first, for symmetry.
1343 if (pci_pme_capable(dev, state))
1344 pci_pme_active(dev, true);
1347 error = platform_pci_sleep_wake(dev, true);
1351 dev->wakeup_prepared = true;
1353 platform_pci_sleep_wake(dev, false);
1354 pci_pme_active(dev, false);
1355 dev->wakeup_prepared = false;
1362 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1363 * @dev: PCI device to prepare
1364 * @enable: True to enable wake-up event generation; false to disable
1366 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1367 * and this function allows them to set that up cleanly - pci_enable_wake()
1368 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1369 * ordering constraints.
1371 * This function only returns error code if the device is not capable of
1372 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1373 * enable wake-up power for it.
1375 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1377 return pci_pme_capable(dev, PCI_D3cold) ?
1378 pci_enable_wake(dev, PCI_D3cold, enable) :
1379 pci_enable_wake(dev, PCI_D3hot, enable);
1383 * pci_target_state - find an appropriate low power state for a given PCI dev
1386 * Use underlying platform code to find a supported low power state for @dev.
1387 * If the platform can't manage @dev, return the deepest state from which it
1388 * can generate wake events, based on any available PME info.
1390 pci_power_t pci_target_state(struct pci_dev *dev)
1392 pci_power_t target_state = PCI_D3hot;
1394 if (platform_pci_power_manageable(dev)) {
1396 * Call the platform to choose the target state of the device
1397 * and enable wake-up from this state if supported.
1399 pci_power_t state = platform_pci_choose_state(dev);
1402 case PCI_POWER_ERROR:
1407 if (pci_no_d1d2(dev))
1410 target_state = state;
1412 } else if (!dev->pm_cap) {
1413 target_state = PCI_D0;
1414 } else if (device_may_wakeup(&dev->dev)) {
1416 * Find the deepest state from which the device can generate
1417 * wake-up events, make it the target state and enable device
1420 if (dev->pme_support) {
1422 && !(dev->pme_support & (1 << target_state)))
1427 return target_state;
1431 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1432 * @dev: Device to handle.
1434 * Choose the power state appropriate for the device depending on whether
1435 * it can wake up the system and/or is power manageable by the platform
1436 * (PCI_D3hot is the default) and put the device into that state.
1438 int pci_prepare_to_sleep(struct pci_dev *dev)
1440 pci_power_t target_state = pci_target_state(dev);
1443 if (target_state == PCI_POWER_ERROR)
1446 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1448 error = pci_set_power_state(dev, target_state);
1451 pci_enable_wake(dev, target_state, false);
1457 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1458 * @dev: Device to handle.
1460 * Disable device's sytem wake-up capability and put it into D0.
1462 int pci_back_from_sleep(struct pci_dev *dev)
1464 pci_enable_wake(dev, PCI_D0, false);
1465 return pci_set_power_state(dev, PCI_D0);
1469 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1470 * @dev: Device to check.
1472 * Return true if the device itself is cabable of generating wake-up events
1473 * (through the platform or using the native PCIe PME) or if the device supports
1474 * PME and one of its upstream bridges can generate wake-up events.
1476 bool pci_dev_run_wake(struct pci_dev *dev)
1478 struct pci_bus *bus = dev->bus;
1480 if (device_run_wake(&dev->dev))
1483 if (!dev->pme_support)
1486 while (bus->parent) {
1487 struct pci_dev *bridge = bus->self;
1489 if (device_run_wake(&bridge->dev))
1495 /* We have reached the root bus. */
1497 return device_run_wake(bus->bridge);
1501 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1504 * pci_pm_init - Initialize PM functions of given PCI device
1505 * @dev: PCI device to handle.
1507 void pci_pm_init(struct pci_dev *dev)
1512 dev->wakeup_prepared = false;
1515 /* find PCI PM capability in list */
1516 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1519 /* Check device's ability to generate PME# */
1520 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1522 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1523 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1524 pmc & PCI_PM_CAP_VER_MASK);
1529 dev->d3_delay = PCI_PM_D3_WAIT;
1531 dev->d1_support = false;
1532 dev->d2_support = false;
1533 if (!pci_no_d1d2(dev)) {
1534 if (pmc & PCI_PM_CAP_D1)
1535 dev->d1_support = true;
1536 if (pmc & PCI_PM_CAP_D2)
1537 dev->d2_support = true;
1539 if (dev->d1_support || dev->d2_support)
1540 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1541 dev->d1_support ? " D1" : "",
1542 dev->d2_support ? " D2" : "");
1545 pmc &= PCI_PM_CAP_PME_MASK;
1547 dev_printk(KERN_DEBUG, &dev->dev,
1548 "PME# supported from%s%s%s%s%s\n",
1549 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1550 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1551 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1552 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1553 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1554 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1556 * Make device's PM flags reflect the wake-up capability, but
1557 * let the user space enable it to wake up the system as needed.
1559 device_set_wakeup_capable(&dev->dev, true);
1560 device_set_wakeup_enable(&dev->dev, false);
1561 /* Disable the PME# generation functionality */
1562 pci_pme_active(dev, false);
1564 dev->pme_support = 0;
1569 * platform_pci_wakeup_init - init platform wakeup if present
1572 * Some devices don't have PCI PM caps but can still generate wakeup
1573 * events through platform methods (like ACPI events). If @dev supports
1574 * platform wakeup events, set the device flag to indicate as much. This
1575 * may be redundant if the device also supports PCI PM caps, but double
1576 * initialization should be safe in that case.
1578 void platform_pci_wakeup_init(struct pci_dev *dev)
1580 if (!platform_pci_can_wakeup(dev))
1583 device_set_wakeup_capable(&dev->dev, true);
1584 device_set_wakeup_enable(&dev->dev, false);
1585 platform_pci_sleep_wake(dev, false);
1589 * pci_add_save_buffer - allocate buffer for saving given capability registers
1590 * @dev: the PCI device
1591 * @cap: the capability to allocate the buffer for
1592 * @size: requested size of the buffer
1594 static int pci_add_cap_save_buffer(
1595 struct pci_dev *dev, char cap, unsigned int size)
1598 struct pci_cap_saved_state *save_state;
1600 pos = pci_find_capability(dev, cap);
1604 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1608 save_state->cap_nr = cap;
1609 pci_add_saved_cap(dev, save_state);
1615 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1616 * @dev: the PCI device
1618 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1622 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
1623 PCI_EXP_SAVE_REGS * sizeof(u16));
1626 "unable to preallocate PCI Express save buffer\n");
1628 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1631 "unable to preallocate PCI-X save buffer\n");
1635 * pci_enable_ari - enable ARI forwarding if hardware support it
1636 * @dev: the PCI device
1638 void pci_enable_ari(struct pci_dev *dev)
1643 struct pci_dev *bridge;
1645 if (!pci_is_pcie(dev) || dev->devfn)
1648 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1652 bridge = dev->bus->self;
1653 if (!bridge || !pci_is_pcie(bridge))
1656 pos = pci_pcie_cap(bridge);
1660 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
1661 if (!(cap & PCI_EXP_DEVCAP2_ARI))
1664 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
1665 ctrl |= PCI_EXP_DEVCTL2_ARI;
1666 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
1668 bridge->ari_enabled = 1;
1671 static int pci_acs_enable;
1674 * pci_request_acs - ask for ACS to be enabled if supported
1676 void pci_request_acs(void)
1682 * pci_enable_acs - enable ACS if hardware support it
1683 * @dev: the PCI device
1685 void pci_enable_acs(struct pci_dev *dev)
1691 if (!pci_acs_enable)
1694 if (!pci_is_pcie(dev))
1697 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
1701 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
1702 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
1704 /* Source Validation */
1705 ctrl |= (cap & PCI_ACS_SV);
1707 /* P2P Request Redirect */
1708 ctrl |= (cap & PCI_ACS_RR);
1710 /* P2P Completion Redirect */
1711 ctrl |= (cap & PCI_ACS_CR);
1713 /* Upstream Forwarding */
1714 ctrl |= (cap & PCI_ACS_UF);
1716 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
1720 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1721 * @dev: the PCI device
1722 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1724 * Perform INTx swizzling for a device behind one level of bridge. This is
1725 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1726 * behind bridges on add-in cards. For devices with ARI enabled, the slot
1727 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
1728 * the PCI Express Base Specification, Revision 2.1)
1730 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
1734 if (pci_ari_enabled(dev->bus))
1737 slot = PCI_SLOT(dev->devfn);
1739 return (((pin - 1) + slot) % 4) + 1;
1743 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
1751 while (!pci_is_root_bus(dev->bus)) {
1752 pin = pci_swizzle_interrupt_pin(dev, pin);
1753 dev = dev->bus->self;
1760 * pci_common_swizzle - swizzle INTx all the way to root bridge
1761 * @dev: the PCI device
1762 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1764 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
1765 * bridges all the way up to a PCI root bus.
1767 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
1771 while (!pci_is_root_bus(dev->bus)) {
1772 pin = pci_swizzle_interrupt_pin(dev, pin);
1773 dev = dev->bus->self;
1776 return PCI_SLOT(dev->devfn);
1780 * pci_release_region - Release a PCI bar
1781 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1782 * @bar: BAR to release
1784 * Releases the PCI I/O and memory resources previously reserved by a
1785 * successful call to pci_request_region. Call this function only
1786 * after all use of the PCI regions has ceased.
1788 void pci_release_region(struct pci_dev *pdev, int bar)
1790 struct pci_devres *dr;
1792 if (pci_resource_len(pdev, bar) == 0)
1794 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1795 release_region(pci_resource_start(pdev, bar),
1796 pci_resource_len(pdev, bar));
1797 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1798 release_mem_region(pci_resource_start(pdev, bar),
1799 pci_resource_len(pdev, bar));
1801 dr = find_pci_dr(pdev);
1803 dr->region_mask &= ~(1 << bar);
1807 * __pci_request_region - Reserved PCI I/O and memory resource
1808 * @pdev: PCI device whose resources are to be reserved
1809 * @bar: BAR to be reserved
1810 * @res_name: Name to be associated with resource.
1811 * @exclusive: whether the region access is exclusive or not
1813 * Mark the PCI region associated with PCI device @pdev BR @bar as
1814 * being reserved by owner @res_name. Do not access any
1815 * address inside the PCI regions unless this call returns
1818 * If @exclusive is set, then the region is marked so that userspace
1819 * is explicitly not allowed to map the resource via /dev/mem or
1820 * sysfs MMIO access.
1822 * Returns 0 on success, or %EBUSY on error. A warning
1823 * message is also printed on failure.
1825 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
1828 struct pci_devres *dr;
1830 if (pci_resource_len(pdev, bar) == 0)
1833 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1834 if (!request_region(pci_resource_start(pdev, bar),
1835 pci_resource_len(pdev, bar), res_name))
1838 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
1839 if (!__request_mem_region(pci_resource_start(pdev, bar),
1840 pci_resource_len(pdev, bar), res_name,
1845 dr = find_pci_dr(pdev);
1847 dr->region_mask |= 1 << bar;
1852 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
1853 &pdev->resource[bar]);
1858 * pci_request_region - Reserve PCI I/O and memory resource
1859 * @pdev: PCI device whose resources are to be reserved
1860 * @bar: BAR to be reserved
1861 * @res_name: Name to be associated with resource
1863 * Mark the PCI region associated with PCI device @pdev BAR @bar as
1864 * being reserved by owner @res_name. Do not access any
1865 * address inside the PCI regions unless this call returns
1868 * Returns 0 on success, or %EBUSY on error. A warning
1869 * message is also printed on failure.
1871 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
1873 return __pci_request_region(pdev, bar, res_name, 0);
1877 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
1878 * @pdev: PCI device whose resources are to be reserved
1879 * @bar: BAR to be reserved
1880 * @res_name: Name to be associated with resource.
1882 * Mark the PCI region associated with PCI device @pdev BR @bar as
1883 * being reserved by owner @res_name. Do not access any
1884 * address inside the PCI regions unless this call returns
1887 * Returns 0 on success, or %EBUSY on error. A warning
1888 * message is also printed on failure.
1890 * The key difference that _exclusive makes it that userspace is
1891 * explicitly not allowed to map the resource via /dev/mem or
1894 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
1896 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
1899 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1900 * @pdev: PCI device whose resources were previously reserved
1901 * @bars: Bitmask of BARs to be released
1903 * Release selected PCI I/O and memory resources previously reserved.
1904 * Call this function only after all use of the PCI regions has ceased.
1906 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1910 for (i = 0; i < 6; i++)
1911 if (bars & (1 << i))
1912 pci_release_region(pdev, i);
1915 int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
1916 const char *res_name, int excl)
1920 for (i = 0; i < 6; i++)
1921 if (bars & (1 << i))
1922 if (__pci_request_region(pdev, i, res_name, excl))
1928 if (bars & (1 << i))
1929 pci_release_region(pdev, i);
1936 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1937 * @pdev: PCI device whose resources are to be reserved
1938 * @bars: Bitmask of BARs to be requested
1939 * @res_name: Name to be associated with resource
1941 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
1942 const char *res_name)
1944 return __pci_request_selected_regions(pdev, bars, res_name, 0);
1947 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
1948 int bars, const char *res_name)
1950 return __pci_request_selected_regions(pdev, bars, res_name,
1951 IORESOURCE_EXCLUSIVE);
1955 * pci_release_regions - Release reserved PCI I/O and memory resources
1956 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1958 * Releases all PCI I/O and memory resources previously reserved by a
1959 * successful call to pci_request_regions. Call this function only
1960 * after all use of the PCI regions has ceased.
1963 void pci_release_regions(struct pci_dev *pdev)
1965 pci_release_selected_regions(pdev, (1 << 6) - 1);
1969 * pci_request_regions - Reserved PCI I/O and memory resources
1970 * @pdev: PCI device whose resources are to be reserved
1971 * @res_name: Name to be associated with resource.
1973 * Mark all PCI regions associated with PCI device @pdev as
1974 * being reserved by owner @res_name. Do not access any
1975 * address inside the PCI regions unless this call returns
1978 * Returns 0 on success, or %EBUSY on error. A warning
1979 * message is also printed on failure.
1981 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
1983 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
1987 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
1988 * @pdev: PCI device whose resources are to be reserved
1989 * @res_name: Name to be associated with resource.
1991 * Mark all PCI regions associated with PCI device @pdev as
1992 * being reserved by owner @res_name. Do not access any
1993 * address inside the PCI regions unless this call returns
1996 * pci_request_regions_exclusive() will mark the region so that
1997 * /dev/mem and the sysfs MMIO access will not be allowed.
1999 * Returns 0 on success, or %EBUSY on error. A warning
2000 * message is also printed on failure.
2002 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2004 return pci_request_selected_regions_exclusive(pdev,
2005 ((1 << 6) - 1), res_name);
2008 static void __pci_set_master(struct pci_dev *dev, bool enable)
2012 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2014 cmd = old_cmd | PCI_COMMAND_MASTER;
2016 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2017 if (cmd != old_cmd) {
2018 dev_dbg(&dev->dev, "%s bus mastering\n",
2019 enable ? "enabling" : "disabling");
2020 pci_write_config_word(dev, PCI_COMMAND, cmd);
2022 dev->is_busmaster = enable;
2026 * pci_set_master - enables bus-mastering for device dev
2027 * @dev: the PCI device to enable
2029 * Enables bus-mastering on the device and calls pcibios_set_master()
2030 * to do the needed arch specific settings.
2032 void pci_set_master(struct pci_dev *dev)
2034 __pci_set_master(dev, true);
2035 pcibios_set_master(dev);
2039 * pci_clear_master - disables bus-mastering for device dev
2040 * @dev: the PCI device to disable
2042 void pci_clear_master(struct pci_dev *dev)
2044 __pci_set_master(dev, false);
2048 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2049 * @dev: the PCI device for which MWI is to be enabled
2051 * Helper function for pci_set_mwi.
2052 * Originally copied from drivers/net/acenic.c.
2053 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2055 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2057 int pci_set_cacheline_size(struct pci_dev *dev)
2061 if (!pci_cache_line_size)
2064 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2065 equal to or multiple of the right value. */
2066 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2067 if (cacheline_size >= pci_cache_line_size &&
2068 (cacheline_size % pci_cache_line_size) == 0)
2071 /* Write the correct value. */
2072 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2074 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2075 if (cacheline_size == pci_cache_line_size)
2078 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2079 "supported\n", pci_cache_line_size << 2);
2083 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2085 #ifdef PCI_DISABLE_MWI
2086 int pci_set_mwi(struct pci_dev *dev)
2091 int pci_try_set_mwi(struct pci_dev *dev)
2096 void pci_clear_mwi(struct pci_dev *dev)
2103 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2104 * @dev: the PCI device for which MWI is enabled
2106 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2108 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2111 pci_set_mwi(struct pci_dev *dev)
2116 rc = pci_set_cacheline_size(dev);
2120 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2121 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2122 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2123 cmd |= PCI_COMMAND_INVALIDATE;
2124 pci_write_config_word(dev, PCI_COMMAND, cmd);
2131 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2132 * @dev: the PCI device for which MWI is enabled
2134 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2135 * Callers are not required to check the return value.
2137 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2139 int pci_try_set_mwi(struct pci_dev *dev)
2141 int rc = pci_set_mwi(dev);
2146 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2147 * @dev: the PCI device to disable
2149 * Disables PCI Memory-Write-Invalidate transaction on the device
2152 pci_clear_mwi(struct pci_dev *dev)
2156 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2157 if (cmd & PCI_COMMAND_INVALIDATE) {
2158 cmd &= ~PCI_COMMAND_INVALIDATE;
2159 pci_write_config_word(dev, PCI_COMMAND, cmd);
2162 #endif /* ! PCI_DISABLE_MWI */
2165 * pci_intx - enables/disables PCI INTx for device dev
2166 * @pdev: the PCI device to operate on
2167 * @enable: boolean: whether to enable or disable PCI INTx
2169 * Enables/disables PCI INTx for device dev
2172 pci_intx(struct pci_dev *pdev, int enable)
2174 u16 pci_command, new;
2176 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2179 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2181 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2184 if (new != pci_command) {
2185 struct pci_devres *dr;
2187 pci_write_config_word(pdev, PCI_COMMAND, new);
2189 dr = find_pci_dr(pdev);
2190 if (dr && !dr->restore_intx) {
2191 dr->restore_intx = 1;
2192 dr->orig_intx = !enable;
2198 * pci_msi_off - disables any msi or msix capabilities
2199 * @dev: the PCI device to operate on
2201 * If you want to use msi see pci_enable_msi and friends.
2202 * This is a lower level primitive that allows us to disable
2203 * msi operation at the device level.
2205 void pci_msi_off(struct pci_dev *dev)
2210 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2212 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2213 control &= ~PCI_MSI_FLAGS_ENABLE;
2214 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2216 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2218 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2219 control &= ~PCI_MSIX_FLAGS_ENABLE;
2220 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2224 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
2226 * These can be overridden by arch-specific implementations
2229 pci_set_dma_mask(struct pci_dev *dev, u64 mask)
2231 if (!pci_dma_supported(dev, mask))
2234 dev->dma_mask = mask;
2235 dev_dbg(&dev->dev, "using %dbit DMA mask\n", fls64(mask));
2241 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
2243 if (!pci_dma_supported(dev, mask))
2246 dev->dev.coherent_dma_mask = mask;
2247 dev_dbg(&dev->dev, "using %dbit consistent DMA mask\n", fls64(mask));
2253 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
2254 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
2256 return dma_set_max_seg_size(&dev->dev, size);
2258 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
2261 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
2262 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
2264 return dma_set_seg_boundary(&dev->dev, mask);
2266 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
2269 static int pcie_flr(struct pci_dev *dev, int probe)
2274 u16 status, control;
2276 pos = pci_pcie_cap(dev);
2280 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
2281 if (!(cap & PCI_EXP_DEVCAP_FLR))
2287 /* Wait for Transaction Pending bit clean */
2288 for (i = 0; i < 4; i++) {
2290 msleep((1 << (i - 1)) * 100);
2292 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
2293 if (!(status & PCI_EXP_DEVSTA_TRPND))
2297 dev_err(&dev->dev, "transaction is not cleared; "
2298 "proceeding with reset anyway\n");
2301 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
2302 control |= PCI_EXP_DEVCTL_BCR_FLR;
2303 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
2310 static int pci_af_flr(struct pci_dev *dev, int probe)
2317 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
2321 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
2322 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
2328 /* Wait for Transaction Pending bit clean */
2329 for (i = 0; i < 4; i++) {
2331 msleep((1 << (i - 1)) * 100);
2333 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
2334 if (!(status & PCI_AF_STATUS_TP))
2338 dev_err(&dev->dev, "transaction is not cleared; "
2339 "proceeding with reset anyway\n");
2342 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
2348 static int pci_pm_reset(struct pci_dev *dev, int probe)
2355 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
2356 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
2362 if (dev->current_state != PCI_D0)
2365 csr &= ~PCI_PM_CTRL_STATE_MASK;
2367 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2368 pci_dev_d3_sleep(dev);
2370 csr &= ~PCI_PM_CTRL_STATE_MASK;
2372 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2373 pci_dev_d3_sleep(dev);
2378 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
2381 struct pci_dev *pdev;
2383 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
2386 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
2393 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
2394 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
2395 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2398 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
2399 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2405 static int pci_dev_reset(struct pci_dev *dev, int probe)
2412 pci_block_user_cfg_access(dev);
2413 /* block PM suspend, driver probe, etc. */
2414 down(&dev->dev.sem);
2417 rc = pci_dev_specific_reset(dev, probe);
2421 rc = pcie_flr(dev, probe);
2425 rc = pci_af_flr(dev, probe);
2429 rc = pci_pm_reset(dev, probe);
2433 rc = pci_parent_bus_reset(dev, probe);
2437 pci_unblock_user_cfg_access(dev);
2444 * __pci_reset_function - reset a PCI device function
2445 * @dev: PCI device to reset
2447 * Some devices allow an individual function to be reset without affecting
2448 * other functions in the same device. The PCI device must be responsive
2449 * to PCI config space in order to use this function.
2451 * The device function is presumed to be unused when this function is called.
2452 * Resetting the device will make the contents of PCI configuration space
2453 * random, so any caller of this must be prepared to reinitialise the
2454 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2457 * Returns 0 if the device function was successfully reset or negative if the
2458 * device doesn't support resetting a single function.
2460 int __pci_reset_function(struct pci_dev *dev)
2462 return pci_dev_reset(dev, 0);
2464 EXPORT_SYMBOL_GPL(__pci_reset_function);
2467 * pci_probe_reset_function - check whether the device can be safely reset
2468 * @dev: PCI device to reset
2470 * Some devices allow an individual function to be reset without affecting
2471 * other functions in the same device. The PCI device must be responsive
2472 * to PCI config space in order to use this function.
2474 * Returns 0 if the device function can be reset or negative if the
2475 * device doesn't support resetting a single function.
2477 int pci_probe_reset_function(struct pci_dev *dev)
2479 return pci_dev_reset(dev, 1);
2483 * pci_reset_function - quiesce and reset a PCI device function
2484 * @dev: PCI device to reset
2486 * Some devices allow an individual function to be reset without affecting
2487 * other functions in the same device. The PCI device must be responsive
2488 * to PCI config space in order to use this function.
2490 * This function does not just reset the PCI portion of a device, but
2491 * clears all the state associated with the device. This function differs
2492 * from __pci_reset_function in that it saves and restores device state
2495 * Returns 0 if the device function was successfully reset or negative if the
2496 * device doesn't support resetting a single function.
2498 int pci_reset_function(struct pci_dev *dev)
2502 rc = pci_dev_reset(dev, 1);
2506 pci_save_state(dev);
2509 * both INTx and MSI are disabled after the Interrupt Disable bit
2510 * is set and the Bus Master bit is cleared.
2512 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
2514 rc = pci_dev_reset(dev, 0);
2516 pci_restore_state(dev);
2520 EXPORT_SYMBOL_GPL(pci_reset_function);
2523 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2524 * @dev: PCI device to query
2526 * Returns mmrbc: maximum designed memory read count in bytes
2527 * or appropriate error value.
2529 int pcix_get_max_mmrbc(struct pci_dev *dev)
2534 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2538 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
2542 return (stat & PCI_X_STATUS_MAX_READ) >> 12;
2544 EXPORT_SYMBOL(pcix_get_max_mmrbc);
2547 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2548 * @dev: PCI device to query
2550 * Returns mmrbc: maximum memory read count in bytes
2551 * or appropriate error value.
2553 int pcix_get_mmrbc(struct pci_dev *dev)
2558 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2562 ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
2564 ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
2568 EXPORT_SYMBOL(pcix_get_mmrbc);
2571 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2572 * @dev: PCI device to query
2573 * @mmrbc: maximum memory read count in bytes
2574 * valid values are 512, 1024, 2048, 4096
2576 * If possible sets maximum memory read byte count, some bridges have erratas
2577 * that prevent this.
2579 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
2581 int cap, err = -EINVAL;
2582 u32 stat, cmd, v, o;
2584 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
2587 v = ffs(mmrbc) - 10;
2589 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2593 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
2597 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
2600 err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
2604 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
2606 if (v > o && dev->bus &&
2607 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
2610 cmd &= ~PCI_X_CMD_MAX_READ;
2612 err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
2617 EXPORT_SYMBOL(pcix_set_mmrbc);
2620 * pcie_get_readrq - get PCI Express read request size
2621 * @dev: PCI device to query
2623 * Returns maximum memory read request in bytes
2624 * or appropriate error value.
2626 int pcie_get_readrq(struct pci_dev *dev)
2631 cap = pci_pcie_cap(dev);
2635 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2637 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
2641 EXPORT_SYMBOL(pcie_get_readrq);
2644 * pcie_set_readrq - set PCI Express maximum memory read request
2645 * @dev: PCI device to query
2646 * @rq: maximum memory read count in bytes
2647 * valid values are 128, 256, 512, 1024, 2048, 4096
2649 * If possible sets maximum read byte count
2651 int pcie_set_readrq(struct pci_dev *dev, int rq)
2653 int cap, err = -EINVAL;
2656 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
2659 v = (ffs(rq) - 8) << 12;
2661 cap = pci_pcie_cap(dev);
2665 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2669 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
2670 ctl &= ~PCI_EXP_DEVCTL_READRQ;
2672 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
2678 EXPORT_SYMBOL(pcie_set_readrq);
2681 * pci_select_bars - Make BAR mask from the type of resource
2682 * @dev: the PCI device for which BAR mask is made
2683 * @flags: resource type mask to be selected
2685 * This helper routine makes bar mask from the type of resource.
2687 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
2690 for (i = 0; i < PCI_NUM_RESOURCES; i++)
2691 if (pci_resource_flags(dev, i) & flags)
2697 * pci_resource_bar - get position of the BAR associated with a resource
2698 * @dev: the PCI device
2699 * @resno: the resource number
2700 * @type: the BAR type to be filled in
2702 * Returns BAR position in config space, or 0 if the BAR is invalid.
2704 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
2708 if (resno < PCI_ROM_RESOURCE) {
2709 *type = pci_bar_unknown;
2710 return PCI_BASE_ADDRESS_0 + 4 * resno;
2711 } else if (resno == PCI_ROM_RESOURCE) {
2712 *type = pci_bar_mem32;
2713 return dev->rom_base_reg;
2714 } else if (resno < PCI_BRIDGE_RESOURCES) {
2715 /* device specific resource */
2716 reg = pci_iov_resource_bar(dev, resno, type);
2721 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
2726 * pci_set_vga_state - set VGA decode state on device and parents if requested
2727 * @dev: the PCI device
2728 * @decode: true = enable decoding, false = disable decoding
2729 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
2730 * @change_bridge: traverse ancestors and change bridges
2732 int pci_set_vga_state(struct pci_dev *dev, bool decode,
2733 unsigned int command_bits, bool change_bridge)
2735 struct pci_bus *bus;
2736 struct pci_dev *bridge;
2739 WARN_ON(command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY));
2741 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2743 cmd |= command_bits;
2745 cmd &= ~command_bits;
2746 pci_write_config_word(dev, PCI_COMMAND, cmd);
2748 if (change_bridge == false)
2755 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
2758 cmd |= PCI_BRIDGE_CTL_VGA;
2760 cmd &= ~PCI_BRIDGE_CTL_VGA;
2761 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
2769 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
2770 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
2771 static DEFINE_SPINLOCK(resource_alignment_lock);
2774 * pci_specified_resource_alignment - get resource alignment specified by user.
2775 * @dev: the PCI device to get
2777 * RETURNS: Resource alignment if it is specified.
2778 * Zero if it is not specified.
2780 resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
2782 int seg, bus, slot, func, align_order, count;
2783 resource_size_t align = 0;
2786 spin_lock(&resource_alignment_lock);
2787 p = resource_alignment_param;
2790 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
2796 if (sscanf(p, "%x:%x:%x.%x%n",
2797 &seg, &bus, &slot, &func, &count) != 4) {
2799 if (sscanf(p, "%x:%x.%x%n",
2800 &bus, &slot, &func, &count) != 3) {
2801 /* Invalid format */
2802 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
2808 if (seg == pci_domain_nr(dev->bus) &&
2809 bus == dev->bus->number &&
2810 slot == PCI_SLOT(dev->devfn) &&
2811 func == PCI_FUNC(dev->devfn)) {
2812 if (align_order == -1) {
2815 align = 1 << align_order;
2820 if (*p != ';' && *p != ',') {
2821 /* End of param or invalid format */
2826 spin_unlock(&resource_alignment_lock);
2831 * pci_is_reassigndev - check if specified PCI is target device to reassign
2832 * @dev: the PCI device to check
2834 * RETURNS: non-zero for PCI device is a target device to reassign,
2837 int pci_is_reassigndev(struct pci_dev *dev)
2839 return (pci_specified_resource_alignment(dev) != 0);
2842 ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
2844 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
2845 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
2846 spin_lock(&resource_alignment_lock);
2847 strncpy(resource_alignment_param, buf, count);
2848 resource_alignment_param[count] = '\0';
2849 spin_unlock(&resource_alignment_lock);
2853 ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
2856 spin_lock(&resource_alignment_lock);
2857 count = snprintf(buf, size, "%s", resource_alignment_param);
2858 spin_unlock(&resource_alignment_lock);
2862 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
2864 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
2867 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
2868 const char *buf, size_t count)
2870 return pci_set_resource_alignment_param(buf, count);
2873 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
2874 pci_resource_alignment_store);
2876 static int __init pci_resource_alignment_sysfs_init(void)
2878 return bus_create_file(&pci_bus_type,
2879 &bus_attr_resource_alignment);
2882 late_initcall(pci_resource_alignment_sysfs_init);
2884 static void __devinit pci_no_domains(void)
2886 #ifdef CONFIG_PCI_DOMAINS
2887 pci_domains_supported = 0;
2892 * pci_ext_cfg_enabled - can we access extended PCI config space?
2893 * @dev: The PCI device of the root bridge.
2895 * Returns 1 if we can access PCI extended config space (offsets
2896 * greater than 0xff). This is the default implementation. Architecture
2897 * implementations can override this.
2899 int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
2904 void __weak pci_fixup_cardbus(struct pci_bus *bus)
2907 EXPORT_SYMBOL(pci_fixup_cardbus);
2909 static int __init pci_setup(char *str)
2912 char *k = strchr(str, ',');
2915 if (*str && (str = pcibios_setup(str)) && *str) {
2916 if (!strcmp(str, "nomsi")) {
2918 } else if (!strcmp(str, "noaer")) {
2920 } else if (!strcmp(str, "nodomains")) {
2922 } else if (!strncmp(str, "cbiosize=", 9)) {
2923 pci_cardbus_io_size = memparse(str + 9, &str);
2924 } else if (!strncmp(str, "cbmemsize=", 10)) {
2925 pci_cardbus_mem_size = memparse(str + 10, &str);
2926 } else if (!strncmp(str, "resource_alignment=", 19)) {
2927 pci_set_resource_alignment_param(str + 19,
2929 } else if (!strncmp(str, "ecrc=", 5)) {
2930 pcie_ecrc_get_policy(str + 5);
2931 } else if (!strncmp(str, "hpiosize=", 9)) {
2932 pci_hotplug_io_size = memparse(str + 9, &str);
2933 } else if (!strncmp(str, "hpmemsize=", 10)) {
2934 pci_hotplug_mem_size = memparse(str + 10, &str);
2936 printk(KERN_ERR "PCI: Unknown option `%s'\n",
2944 early_param("pci", pci_setup);
2946 EXPORT_SYMBOL(pci_reenable_device);
2947 EXPORT_SYMBOL(pci_enable_device_io);
2948 EXPORT_SYMBOL(pci_enable_device_mem);
2949 EXPORT_SYMBOL(pci_enable_device);
2950 EXPORT_SYMBOL(pcim_enable_device);
2951 EXPORT_SYMBOL(pcim_pin_device);
2952 EXPORT_SYMBOL(pci_disable_device);
2953 EXPORT_SYMBOL(pci_find_capability);
2954 EXPORT_SYMBOL(pci_bus_find_capability);
2955 EXPORT_SYMBOL(pci_release_regions);
2956 EXPORT_SYMBOL(pci_request_regions);
2957 EXPORT_SYMBOL(pci_request_regions_exclusive);
2958 EXPORT_SYMBOL(pci_release_region);
2959 EXPORT_SYMBOL(pci_request_region);
2960 EXPORT_SYMBOL(pci_request_region_exclusive);
2961 EXPORT_SYMBOL(pci_release_selected_regions);
2962 EXPORT_SYMBOL(pci_request_selected_regions);
2963 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
2964 EXPORT_SYMBOL(pci_set_master);
2965 EXPORT_SYMBOL(pci_clear_master);
2966 EXPORT_SYMBOL(pci_set_mwi);
2967 EXPORT_SYMBOL(pci_try_set_mwi);
2968 EXPORT_SYMBOL(pci_clear_mwi);
2969 EXPORT_SYMBOL_GPL(pci_intx);
2970 EXPORT_SYMBOL(pci_set_dma_mask);
2971 EXPORT_SYMBOL(pci_set_consistent_dma_mask);
2972 EXPORT_SYMBOL(pci_assign_resource);
2973 EXPORT_SYMBOL(pci_find_parent_resource);
2974 EXPORT_SYMBOL(pci_select_bars);
2976 EXPORT_SYMBOL(pci_set_power_state);
2977 EXPORT_SYMBOL(pci_save_state);
2978 EXPORT_SYMBOL(pci_restore_state);
2979 EXPORT_SYMBOL(pci_pme_capable);
2980 EXPORT_SYMBOL(pci_pme_active);
2981 EXPORT_SYMBOL(pci_enable_wake);
2982 EXPORT_SYMBOL(pci_wake_from_d3);
2983 EXPORT_SYMBOL(pci_target_state);
2984 EXPORT_SYMBOL(pci_prepare_to_sleep);
2985 EXPORT_SYMBOL(pci_back_from_sleep);
2986 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);