2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/string.h>
18 #include <linux/log2.h>
19 #include <linux/pci-aspm.h>
20 #include <linux/pm_wakeup.h>
21 #include <linux/interrupt.h>
22 #include <asm/dma.h> /* isa_dma_bridge_buggy */
23 #include <linux/device.h>
24 #include <asm/setup.h>
27 const char *pci_power_names[] = {
28 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
30 EXPORT_SYMBOL_GPL(pci_power_names);
32 unsigned int pci_pm_d3_delay = PCI_PM_D3_WAIT;
34 #ifdef CONFIG_PCI_DOMAINS
35 int pci_domains_supported = 1;
38 #define DEFAULT_CARDBUS_IO_SIZE (256)
39 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
40 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
41 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
42 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
44 #define DEFAULT_HOTPLUG_IO_SIZE (256)
45 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
46 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
47 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
48 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
51 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
52 * @bus: pointer to PCI bus structure to search
54 * Given a PCI bus, returns the highest PCI bus number present in the set
55 * including the given PCI bus and its list of child PCI buses.
57 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
59 struct list_head *tmp;
62 max = bus->subordinate;
63 list_for_each(tmp, &bus->children) {
64 n = pci_bus_max_busnr(pci_bus_b(tmp));
70 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
72 #ifdef CONFIG_HAS_IOMEM
73 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
76 * Make sure the BAR is actually a memory resource, not an IO resource
78 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
82 return ioremap_nocache(pci_resource_start(pdev, bar),
83 pci_resource_len(pdev, bar));
85 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
90 * pci_max_busnr - returns maximum PCI bus number
92 * Returns the highest PCI bus number present in the system global list of
95 unsigned char __devinit
98 struct pci_bus *bus = NULL;
102 while ((bus = pci_find_next_bus(bus)) != NULL) {
103 n = pci_bus_max_busnr(bus);
112 #define PCI_FIND_CAP_TTL 48
114 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
115 u8 pos, int cap, int *ttl)
120 pci_bus_read_config_byte(bus, devfn, pos, &pos);
124 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
130 pos += PCI_CAP_LIST_NEXT;
135 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
138 int ttl = PCI_FIND_CAP_TTL;
140 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
143 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
145 return __pci_find_next_cap(dev->bus, dev->devfn,
146 pos + PCI_CAP_LIST_NEXT, cap);
148 EXPORT_SYMBOL_GPL(pci_find_next_capability);
150 static int __pci_bus_find_cap_start(struct pci_bus *bus,
151 unsigned int devfn, u8 hdr_type)
155 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
156 if (!(status & PCI_STATUS_CAP_LIST))
160 case PCI_HEADER_TYPE_NORMAL:
161 case PCI_HEADER_TYPE_BRIDGE:
162 return PCI_CAPABILITY_LIST;
163 case PCI_HEADER_TYPE_CARDBUS:
164 return PCI_CB_CAPABILITY_LIST;
173 * pci_find_capability - query for devices' capabilities
174 * @dev: PCI device to query
175 * @cap: capability code
177 * Tell if a device supports a given PCI capability.
178 * Returns the address of the requested capability structure within the
179 * device's PCI configuration space or 0 in case the device does not
180 * support it. Possible values for @cap:
182 * %PCI_CAP_ID_PM Power Management
183 * %PCI_CAP_ID_AGP Accelerated Graphics Port
184 * %PCI_CAP_ID_VPD Vital Product Data
185 * %PCI_CAP_ID_SLOTID Slot Identification
186 * %PCI_CAP_ID_MSI Message Signalled Interrupts
187 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
188 * %PCI_CAP_ID_PCIX PCI-X
189 * %PCI_CAP_ID_EXP PCI Express
191 int pci_find_capability(struct pci_dev *dev, int cap)
195 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
197 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
203 * pci_bus_find_capability - query for devices' capabilities
204 * @bus: the PCI bus to query
205 * @devfn: PCI device to query
206 * @cap: capability code
208 * Like pci_find_capability() but works for pci devices that do not have a
209 * pci_dev structure set up yet.
211 * Returns the address of the requested capability structure within the
212 * device's PCI configuration space or 0 in case the device does not
215 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
220 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
222 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
224 pos = __pci_find_next_cap(bus, devfn, pos, cap);
230 * pci_find_ext_capability - Find an extended capability
231 * @dev: PCI device to query
232 * @cap: capability code
234 * Returns the address of the requested extended capability structure
235 * within the device's PCI configuration space or 0 if the device does
236 * not support it. Possible values for @cap:
238 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
239 * %PCI_EXT_CAP_ID_VC Virtual Channel
240 * %PCI_EXT_CAP_ID_DSN Device Serial Number
241 * %PCI_EXT_CAP_ID_PWR Power Budgeting
243 int pci_find_ext_capability(struct pci_dev *dev, int cap)
247 int pos = PCI_CFG_SPACE_SIZE;
249 /* minimum 8 bytes per capability */
250 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
252 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
255 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
259 * If we have no capabilities, this is indicated by cap ID,
260 * cap version and next pointer all being 0.
266 if (PCI_EXT_CAP_ID(header) == cap)
269 pos = PCI_EXT_CAP_NEXT(header);
270 if (pos < PCI_CFG_SPACE_SIZE)
273 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
279 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
281 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
283 int rc, ttl = PCI_FIND_CAP_TTL;
286 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
287 mask = HT_3BIT_CAP_MASK;
289 mask = HT_5BIT_CAP_MASK;
291 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
292 PCI_CAP_ID_HT, &ttl);
294 rc = pci_read_config_byte(dev, pos + 3, &cap);
295 if (rc != PCIBIOS_SUCCESSFUL)
298 if ((cap & mask) == ht_cap)
301 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
302 pos + PCI_CAP_LIST_NEXT,
303 PCI_CAP_ID_HT, &ttl);
309 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
310 * @dev: PCI device to query
311 * @pos: Position from which to continue searching
312 * @ht_cap: Hypertransport capability code
314 * To be used in conjunction with pci_find_ht_capability() to search for
315 * all capabilities matching @ht_cap. @pos should always be a value returned
316 * from pci_find_ht_capability().
318 * NB. To be 100% safe against broken PCI devices, the caller should take
319 * steps to avoid an infinite loop.
321 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
323 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
325 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
328 * pci_find_ht_capability - query a device's Hypertransport capabilities
329 * @dev: PCI device to query
330 * @ht_cap: Hypertransport capability code
332 * Tell if a device supports a given Hypertransport capability.
333 * Returns an address within the device's PCI configuration space
334 * or 0 in case the device does not support the request capability.
335 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
336 * which has a Hypertransport capability matching @ht_cap.
338 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
342 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
344 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
348 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
351 * pci_find_parent_resource - return resource region of parent bus of given region
352 * @dev: PCI device structure contains resources to be searched
353 * @res: child resource record for which parent is sought
355 * For given resource region of given device, return the resource
356 * region of parent bus the given region is contained in or where
357 * it should be allocated from.
360 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
362 const struct pci_bus *bus = dev->bus;
364 struct resource *best = NULL;
366 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
367 struct resource *r = bus->resource[i];
370 if (res->start && !(res->start >= r->start && res->end <= r->end))
371 continue; /* Not contained */
372 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
373 continue; /* Wrong type */
374 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
375 return r; /* Exact match */
376 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
377 best = r; /* Approximating prefetchable by non-prefetchable */
383 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
384 * @dev: PCI device to have its BARs restored
386 * Restore the BAR values for a given device, so as to make it
387 * accessible by its driver.
390 pci_restore_bars(struct pci_dev *dev)
394 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
395 pci_update_resource(dev, i);
398 static struct pci_platform_pm_ops *pci_platform_pm;
400 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
402 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
403 || !ops->sleep_wake || !ops->can_wakeup)
405 pci_platform_pm = ops;
409 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
411 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
414 static inline int platform_pci_set_power_state(struct pci_dev *dev,
417 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
420 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
422 return pci_platform_pm ?
423 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
426 static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
428 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
431 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
433 return pci_platform_pm ?
434 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
438 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
440 * @dev: PCI device to handle.
441 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
444 * -EINVAL if the requested state is invalid.
445 * -EIO if device does not support PCI PM or its PM capabilities register has a
446 * wrong version, or device doesn't support the requested state.
447 * 0 if device already is in the requested state.
448 * 0 if device's power state has been successfully changed.
450 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
453 bool need_restore = false;
455 /* Check if we're already there */
456 if (dev->current_state == state)
462 if (state < PCI_D0 || state > PCI_D3hot)
465 /* Validate current state:
466 * Can enter D0 from any state, but if we can only go deeper
467 * to sleep if we're already in a low power state
469 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
470 && dev->current_state > state) {
471 dev_err(&dev->dev, "invalid power transition "
472 "(from state %d to %d)\n", dev->current_state, state);
476 /* check if this device supports the desired state */
477 if ((state == PCI_D1 && !dev->d1_support)
478 || (state == PCI_D2 && !dev->d2_support))
481 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
483 /* If we're (effectively) in D3, force entire word to 0.
484 * This doesn't affect PME_Status, disables PME_En, and
485 * sets PowerState to 0.
487 switch (dev->current_state) {
491 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
496 case PCI_UNKNOWN: /* Boot-up */
497 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
498 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
500 /* Fall-through: force to D0 */
506 /* enter specified state */
507 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
509 /* Mandatory power management transition delays */
510 /* see PCI PM 1.1 5.6.1 table 18 */
511 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
512 msleep(pci_pm_d3_delay);
513 else if (state == PCI_D2 || dev->current_state == PCI_D2)
514 udelay(PCI_PM_D2_DELAY);
516 dev->current_state = state;
518 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
519 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
520 * from D3hot to D0 _may_ perform an internal reset, thereby
521 * going to "D0 Uninitialized" rather than "D0 Initialized".
522 * For example, at least some versions of the 3c905B and the
523 * 3c556B exhibit this behaviour.
525 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
526 * devices in a D3hot state at boot. Consequently, we need to
527 * restore at least the BARs so that the device will be
528 * accessible to its driver.
531 pci_restore_bars(dev);
534 pcie_aspm_pm_state_change(dev->bus->self);
540 * pci_update_current_state - Read PCI power state of given device from its
541 * PCI PM registers and cache it
542 * @dev: PCI device to handle.
543 * @state: State to cache in case the device doesn't have the PM capability
545 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
550 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
551 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
553 dev->current_state = state;
558 * pci_platform_power_transition - Use platform to change device power state
559 * @dev: PCI device to handle.
560 * @state: State to put the device into.
562 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
566 if (platform_pci_power_manageable(dev)) {
567 error = platform_pci_set_power_state(dev, state);
569 pci_update_current_state(dev, state);
572 /* Fall back to PCI_D0 if native PM is not supported */
574 dev->current_state = PCI_D0;
581 * __pci_start_power_transition - Start power transition of a PCI device
582 * @dev: PCI device to handle.
583 * @state: State to put the device into.
585 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
588 pci_platform_power_transition(dev, PCI_D0);
592 * __pci_complete_power_transition - Complete power transition of a PCI device
593 * @dev: PCI device to handle.
594 * @state: State to put the device into.
596 * This function should not be called directly by device drivers.
598 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
600 return state > PCI_D0 ?
601 pci_platform_power_transition(dev, state) : -EINVAL;
603 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
606 * pci_set_power_state - Set the power state of a PCI device
607 * @dev: PCI device to handle.
608 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
610 * Transition a device to a new power state, using the platform firmware and/or
611 * the device's PCI PM registers.
614 * -EINVAL if the requested state is invalid.
615 * -EIO if device does not support PCI PM or its PM capabilities register has a
616 * wrong version, or device doesn't support the requested state.
617 * 0 if device already is in the requested state.
618 * 0 if device's power state has been successfully changed.
620 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
624 /* bound the state we're entering */
625 if (state > PCI_D3hot)
627 else if (state < PCI_D0)
629 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
631 * If the device or the parent bridge do not support PCI PM,
632 * ignore the request if we're doing anything other than putting
633 * it into D0 (which would only happen on boot).
637 /* Check if we're already there */
638 if (dev->current_state == state)
641 __pci_start_power_transition(dev, state);
643 /* This device is quirked not to be put into D3, so
644 don't put it in D3 */
645 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
648 error = pci_raw_set_power_state(dev, state);
650 if (!__pci_complete_power_transition(dev, state))
657 * pci_choose_state - Choose the power state of a PCI device
658 * @dev: PCI device to be suspended
659 * @state: target sleep state for the whole system. This is the value
660 * that is passed to suspend() function.
662 * Returns PCI power state suitable for given device and given system
666 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
670 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
673 ret = platform_pci_choose_state(dev);
674 if (ret != PCI_POWER_ERROR)
677 switch (state.event) {
680 case PM_EVENT_FREEZE:
681 case PM_EVENT_PRETHAW:
682 /* REVISIT both freeze and pre-thaw "should" use D0 */
683 case PM_EVENT_SUSPEND:
684 case PM_EVENT_HIBERNATE:
687 dev_info(&dev->dev, "unrecognized suspend event %d\n",
694 EXPORT_SYMBOL(pci_choose_state);
696 #define PCI_EXP_SAVE_REGS 7
698 #define pcie_cap_has_devctl(type, flags) 1
699 #define pcie_cap_has_lnkctl(type, flags) \
700 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
701 (type == PCI_EXP_TYPE_ROOT_PORT || \
702 type == PCI_EXP_TYPE_ENDPOINT || \
703 type == PCI_EXP_TYPE_LEG_END))
704 #define pcie_cap_has_sltctl(type, flags) \
705 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
706 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
707 (type == PCI_EXP_TYPE_DOWNSTREAM && \
708 (flags & PCI_EXP_FLAGS_SLOT))))
709 #define pcie_cap_has_rtctl(type, flags) \
710 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
711 (type == PCI_EXP_TYPE_ROOT_PORT || \
712 type == PCI_EXP_TYPE_RC_EC))
713 #define pcie_cap_has_devctl2(type, flags) \
714 ((flags & PCI_EXP_FLAGS_VERS) > 1)
715 #define pcie_cap_has_lnkctl2(type, flags) \
716 ((flags & PCI_EXP_FLAGS_VERS) > 1)
717 #define pcie_cap_has_sltctl2(type, flags) \
718 ((flags & PCI_EXP_FLAGS_VERS) > 1)
720 static int pci_save_pcie_state(struct pci_dev *dev)
723 struct pci_cap_saved_state *save_state;
727 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
731 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
733 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
736 cap = (u16 *)&save_state->data[0];
738 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
740 if (pcie_cap_has_devctl(dev->pcie_type, flags))
741 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
742 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
743 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
744 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
745 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
746 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
747 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
748 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
749 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
750 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
751 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
752 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
753 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
758 static void pci_restore_pcie_state(struct pci_dev *dev)
761 struct pci_cap_saved_state *save_state;
765 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
766 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
767 if (!save_state || pos <= 0)
769 cap = (u16 *)&save_state->data[0];
771 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
773 if (pcie_cap_has_devctl(dev->pcie_type, flags))
774 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
775 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
776 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
777 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
778 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
779 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
780 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
781 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
782 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
783 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
784 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
785 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
786 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
790 static int pci_save_pcix_state(struct pci_dev *dev)
793 struct pci_cap_saved_state *save_state;
795 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
799 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
801 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
805 pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data);
810 static void pci_restore_pcix_state(struct pci_dev *dev)
813 struct pci_cap_saved_state *save_state;
816 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
817 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
818 if (!save_state || pos <= 0)
820 cap = (u16 *)&save_state->data[0];
822 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
827 * pci_save_state - save the PCI configuration space of a device before suspending
828 * @dev: - PCI device that we're dealing with
831 pci_save_state(struct pci_dev *dev)
834 /* XXX: 100% dword access ok here? */
835 for (i = 0; i < 16; i++)
836 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
837 dev->state_saved = true;
838 if ((i = pci_save_pcie_state(dev)) != 0)
840 if ((i = pci_save_pcix_state(dev)) != 0)
846 * pci_restore_state - Restore the saved state of a PCI device
847 * @dev: - PCI device that we're dealing with
850 pci_restore_state(struct pci_dev *dev)
855 if (!dev->state_saved)
857 /* PCI Express register must be restored first */
858 pci_restore_pcie_state(dev);
861 * The Base Address register should be programmed before the command
864 for (i = 15; i >= 0; i--) {
865 pci_read_config_dword(dev, i * 4, &val);
866 if (val != dev->saved_config_space[i]) {
867 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
868 "space at offset %#x (was %#x, writing %#x)\n",
869 i, val, (int)dev->saved_config_space[i]);
870 pci_write_config_dword(dev,i * 4,
871 dev->saved_config_space[i]);
874 pci_restore_pcix_state(dev);
875 pci_restore_msi_state(dev);
876 pci_restore_iov_state(dev);
881 static int do_pci_enable_device(struct pci_dev *dev, int bars)
885 err = pci_set_power_state(dev, PCI_D0);
886 if (err < 0 && err != -EIO)
888 err = pcibios_enable_device(dev, bars);
891 pci_fixup_device(pci_fixup_enable, dev);
897 * pci_reenable_device - Resume abandoned device
898 * @dev: PCI device to be resumed
900 * Note this function is a backend of pci_default_resume and is not supposed
901 * to be called by normal code, write proper resume handler and use it instead.
903 int pci_reenable_device(struct pci_dev *dev)
905 if (pci_is_enabled(dev))
906 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
910 static int __pci_enable_device_flags(struct pci_dev *dev,
911 resource_size_t flags)
916 if (atomic_add_return(1, &dev->enable_cnt) > 1)
917 return 0; /* already enabled */
919 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
920 if (dev->resource[i].flags & flags)
923 err = do_pci_enable_device(dev, bars);
925 atomic_dec(&dev->enable_cnt);
930 * pci_enable_device_io - Initialize a device for use with IO space
931 * @dev: PCI device to be initialized
933 * Initialize device before it's used by a driver. Ask low-level code
934 * to enable I/O resources. Wake up the device if it was suspended.
935 * Beware, this function can fail.
937 int pci_enable_device_io(struct pci_dev *dev)
939 return __pci_enable_device_flags(dev, IORESOURCE_IO);
943 * pci_enable_device_mem - Initialize a device for use with Memory space
944 * @dev: PCI device to be initialized
946 * Initialize device before it's used by a driver. Ask low-level code
947 * to enable Memory resources. Wake up the device if it was suspended.
948 * Beware, this function can fail.
950 int pci_enable_device_mem(struct pci_dev *dev)
952 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
956 * pci_enable_device - Initialize device before it's used by a driver.
957 * @dev: PCI device to be initialized
959 * Initialize device before it's used by a driver. Ask low-level code
960 * to enable I/O and memory. Wake up the device if it was suspended.
961 * Beware, this function can fail.
963 * Note we don't actually enable the device many times if we call
964 * this function repeatedly (we just increment the count).
966 int pci_enable_device(struct pci_dev *dev)
968 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
972 * Managed PCI resources. This manages device on/off, intx/msi/msix
973 * on/off and BAR regions. pci_dev itself records msi/msix status, so
974 * there's no need to track it separately. pci_devres is initialized
975 * when a device is enabled using managed PCI device enable interface.
978 unsigned int enabled:1;
979 unsigned int pinned:1;
980 unsigned int orig_intx:1;
981 unsigned int restore_intx:1;
985 static void pcim_release(struct device *gendev, void *res)
987 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
988 struct pci_devres *this = res;
991 if (dev->msi_enabled)
992 pci_disable_msi(dev);
993 if (dev->msix_enabled)
994 pci_disable_msix(dev);
996 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
997 if (this->region_mask & (1 << i))
998 pci_release_region(dev, i);
1000 if (this->restore_intx)
1001 pci_intx(dev, this->orig_intx);
1003 if (this->enabled && !this->pinned)
1004 pci_disable_device(dev);
1007 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1009 struct pci_devres *dr, *new_dr;
1011 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1015 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1018 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1021 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1023 if (pci_is_managed(pdev))
1024 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1029 * pcim_enable_device - Managed pci_enable_device()
1030 * @pdev: PCI device to be initialized
1032 * Managed pci_enable_device().
1034 int pcim_enable_device(struct pci_dev *pdev)
1036 struct pci_devres *dr;
1039 dr = get_pci_dr(pdev);
1045 rc = pci_enable_device(pdev);
1047 pdev->is_managed = 1;
1054 * pcim_pin_device - Pin managed PCI device
1055 * @pdev: PCI device to pin
1057 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1058 * driver detach. @pdev must have been enabled with
1059 * pcim_enable_device().
1061 void pcim_pin_device(struct pci_dev *pdev)
1063 struct pci_devres *dr;
1065 dr = find_pci_dr(pdev);
1066 WARN_ON(!dr || !dr->enabled);
1072 * pcibios_disable_device - disable arch specific PCI resources for device dev
1073 * @dev: the PCI device to disable
1075 * Disables architecture specific PCI resources for the device. This
1076 * is the default implementation. Architecture implementations can
1079 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
1081 static void do_pci_disable_device(struct pci_dev *dev)
1085 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1086 if (pci_command & PCI_COMMAND_MASTER) {
1087 pci_command &= ~PCI_COMMAND_MASTER;
1088 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1091 pcibios_disable_device(dev);
1095 * pci_disable_enabled_device - Disable device without updating enable_cnt
1096 * @dev: PCI device to disable
1098 * NOTE: This function is a backend of PCI power management routines and is
1099 * not supposed to be called drivers.
1101 void pci_disable_enabled_device(struct pci_dev *dev)
1103 if (pci_is_enabled(dev))
1104 do_pci_disable_device(dev);
1108 * pci_disable_device - Disable PCI device after use
1109 * @dev: PCI device to be disabled
1111 * Signal to the system that the PCI device is not in use by the system
1112 * anymore. This only involves disabling PCI bus-mastering, if active.
1114 * Note we don't actually disable the device until all callers of
1115 * pci_device_enable() have called pci_device_disable().
1118 pci_disable_device(struct pci_dev *dev)
1120 struct pci_devres *dr;
1122 dr = find_pci_dr(dev);
1126 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1129 do_pci_disable_device(dev);
1131 dev->is_busmaster = 0;
1135 * pcibios_set_pcie_reset_state - set reset state for device dev
1136 * @dev: the PCI-E device reset
1137 * @state: Reset state to enter into
1140 * Sets the PCI-E reset state for the device. This is the default
1141 * implementation. Architecture implementations can override this.
1143 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1144 enum pcie_reset_state state)
1150 * pci_set_pcie_reset_state - set reset state for device dev
1151 * @dev: the PCI-E device reset
1152 * @state: Reset state to enter into
1155 * Sets the PCI reset state for the device.
1157 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1159 return pcibios_set_pcie_reset_state(dev, state);
1163 * pci_pme_capable - check the capability of PCI device to generate PME#
1164 * @dev: PCI device to handle.
1165 * @state: PCI state from which device will issue PME#.
1167 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1172 return !!(dev->pme_support & (1 << state));
1176 * pci_pme_active - enable or disable PCI device's PME# function
1177 * @dev: PCI device to handle.
1178 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1180 * The caller must verify that the device is capable of generating PME# before
1181 * calling this function with @enable equal to 'true'.
1183 void pci_pme_active(struct pci_dev *dev, bool enable)
1190 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1191 /* Clear PME_Status by writing 1 to it and enable PME# */
1192 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1194 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1196 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1198 dev_printk(KERN_INFO, &dev->dev, "PME# %s\n",
1199 enable ? "enabled" : "disabled");
1203 * pci_enable_wake - enable PCI device as wakeup event source
1204 * @dev: PCI device affected
1205 * @state: PCI state from which device will issue wakeup events
1206 * @enable: True to enable event generation; false to disable
1208 * This enables the device as a wakeup event source, or disables it.
1209 * When such events involves platform-specific hooks, those hooks are
1210 * called automatically by this routine.
1212 * Devices with legacy power management (no standard PCI PM capabilities)
1213 * always require such platform hooks.
1216 * 0 is returned on success
1217 * -EINVAL is returned if device is not supposed to wake up the system
1218 * Error code depending on the platform is returned if both the platform and
1219 * the native mechanism fail to enable the generation of wake-up events
1221 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
1225 if (enable && !device_may_wakeup(&dev->dev))
1229 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1230 * Anderson we should be doing PME# wake enable followed by ACPI wake
1231 * enable. To disable wake-up we call the platform first, for symmetry.
1237 if (pci_pme_capable(dev, state))
1238 pci_pme_active(dev, true);
1241 error = platform_pci_sleep_wake(dev, true);
1245 platform_pci_sleep_wake(dev, false);
1246 pci_pme_active(dev, false);
1253 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1254 * @dev: PCI device to prepare
1255 * @enable: True to enable wake-up event generation; false to disable
1257 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1258 * and this function allows them to set that up cleanly - pci_enable_wake()
1259 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1260 * ordering constraints.
1262 * This function only returns error code if the device is not capable of
1263 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1264 * enable wake-up power for it.
1266 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1268 return pci_pme_capable(dev, PCI_D3cold) ?
1269 pci_enable_wake(dev, PCI_D3cold, enable) :
1270 pci_enable_wake(dev, PCI_D3hot, enable);
1274 * pci_target_state - find an appropriate low power state for a given PCI dev
1277 * Use underlying platform code to find a supported low power state for @dev.
1278 * If the platform can't manage @dev, return the deepest state from which it
1279 * can generate wake events, based on any available PME info.
1281 pci_power_t pci_target_state(struct pci_dev *dev)
1283 pci_power_t target_state = PCI_D3hot;
1285 if (platform_pci_power_manageable(dev)) {
1287 * Call the platform to choose the target state of the device
1288 * and enable wake-up from this state if supported.
1290 pci_power_t state = platform_pci_choose_state(dev);
1293 case PCI_POWER_ERROR:
1298 if (pci_no_d1d2(dev))
1301 target_state = state;
1303 } else if (!dev->pm_cap) {
1304 target_state = PCI_D0;
1305 } else if (device_may_wakeup(&dev->dev)) {
1307 * Find the deepest state from which the device can generate
1308 * wake-up events, make it the target state and enable device
1311 if (dev->pme_support) {
1313 && !(dev->pme_support & (1 << target_state)))
1318 return target_state;
1322 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1323 * @dev: Device to handle.
1325 * Choose the power state appropriate for the device depending on whether
1326 * it can wake up the system and/or is power manageable by the platform
1327 * (PCI_D3hot is the default) and put the device into that state.
1329 int pci_prepare_to_sleep(struct pci_dev *dev)
1331 pci_power_t target_state = pci_target_state(dev);
1334 if (target_state == PCI_POWER_ERROR)
1337 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1339 error = pci_set_power_state(dev, target_state);
1342 pci_enable_wake(dev, target_state, false);
1348 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1349 * @dev: Device to handle.
1351 * Disable device's sytem wake-up capability and put it into D0.
1353 int pci_back_from_sleep(struct pci_dev *dev)
1355 pci_enable_wake(dev, PCI_D0, false);
1356 return pci_set_power_state(dev, PCI_D0);
1360 * pci_pm_init - Initialize PM functions of given PCI device
1361 * @dev: PCI device to handle.
1363 void pci_pm_init(struct pci_dev *dev)
1370 /* find PCI PM capability in list */
1371 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1374 /* Check device's ability to generate PME# */
1375 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1377 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1378 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1379 pmc & PCI_PM_CAP_VER_MASK);
1385 dev->d1_support = false;
1386 dev->d2_support = false;
1387 if (!pci_no_d1d2(dev)) {
1388 if (pmc & PCI_PM_CAP_D1)
1389 dev->d1_support = true;
1390 if (pmc & PCI_PM_CAP_D2)
1391 dev->d2_support = true;
1393 if (dev->d1_support || dev->d2_support)
1394 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1395 dev->d1_support ? " D1" : "",
1396 dev->d2_support ? " D2" : "");
1399 pmc &= PCI_PM_CAP_PME_MASK;
1401 dev_info(&dev->dev, "PME# supported from%s%s%s%s%s\n",
1402 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1403 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1404 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1405 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1406 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1407 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1409 * Make device's PM flags reflect the wake-up capability, but
1410 * let the user space enable it to wake up the system as needed.
1412 device_set_wakeup_capable(&dev->dev, true);
1413 device_set_wakeup_enable(&dev->dev, false);
1414 /* Disable the PME# generation functionality */
1415 pci_pme_active(dev, false);
1417 dev->pme_support = 0;
1422 * platform_pci_wakeup_init - init platform wakeup if present
1425 * Some devices don't have PCI PM caps but can still generate wakeup
1426 * events through platform methods (like ACPI events). If @dev supports
1427 * platform wakeup events, set the device flag to indicate as much. This
1428 * may be redundant if the device also supports PCI PM caps, but double
1429 * initialization should be safe in that case.
1431 void platform_pci_wakeup_init(struct pci_dev *dev)
1433 if (!platform_pci_can_wakeup(dev))
1436 device_set_wakeup_capable(&dev->dev, true);
1437 device_set_wakeup_enable(&dev->dev, false);
1438 platform_pci_sleep_wake(dev, false);
1442 * pci_add_save_buffer - allocate buffer for saving given capability registers
1443 * @dev: the PCI device
1444 * @cap: the capability to allocate the buffer for
1445 * @size: requested size of the buffer
1447 static int pci_add_cap_save_buffer(
1448 struct pci_dev *dev, char cap, unsigned int size)
1451 struct pci_cap_saved_state *save_state;
1453 pos = pci_find_capability(dev, cap);
1457 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1461 save_state->cap_nr = cap;
1462 pci_add_saved_cap(dev, save_state);
1468 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1469 * @dev: the PCI device
1471 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1475 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
1476 PCI_EXP_SAVE_REGS * sizeof(u16));
1479 "unable to preallocate PCI Express save buffer\n");
1481 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1484 "unable to preallocate PCI-X save buffer\n");
1488 * pci_enable_ari - enable ARI forwarding if hardware support it
1489 * @dev: the PCI device
1491 void pci_enable_ari(struct pci_dev *dev)
1496 struct pci_dev *bridge;
1498 if (!dev->is_pcie || dev->devfn)
1501 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1505 bridge = dev->bus->self;
1506 if (!bridge || !bridge->is_pcie)
1509 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
1513 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
1514 if (!(cap & PCI_EXP_DEVCAP2_ARI))
1517 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
1518 ctrl |= PCI_EXP_DEVCTL2_ARI;
1519 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
1521 bridge->ari_enabled = 1;
1525 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1526 * @dev: the PCI device
1527 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1529 * Perform INTx swizzling for a device behind one level of bridge. This is
1530 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1531 * behind bridges on add-in cards. For devices with ARI enabled, the slot
1532 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
1533 * the PCI Express Base Specification, Revision 2.1)
1535 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
1539 if (pci_ari_enabled(dev->bus))
1542 slot = PCI_SLOT(dev->devfn);
1544 return (((pin - 1) + slot) % 4) + 1;
1548 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
1556 while (!pci_is_root_bus(dev->bus)) {
1557 pin = pci_swizzle_interrupt_pin(dev, pin);
1558 dev = dev->bus->self;
1565 * pci_common_swizzle - swizzle INTx all the way to root bridge
1566 * @dev: the PCI device
1567 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1569 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
1570 * bridges all the way up to a PCI root bus.
1572 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
1576 while (!pci_is_root_bus(dev->bus)) {
1577 pin = pci_swizzle_interrupt_pin(dev, pin);
1578 dev = dev->bus->self;
1581 return PCI_SLOT(dev->devfn);
1585 * pci_release_region - Release a PCI bar
1586 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1587 * @bar: BAR to release
1589 * Releases the PCI I/O and memory resources previously reserved by a
1590 * successful call to pci_request_region. Call this function only
1591 * after all use of the PCI regions has ceased.
1593 void pci_release_region(struct pci_dev *pdev, int bar)
1595 struct pci_devres *dr;
1597 if (pci_resource_len(pdev, bar) == 0)
1599 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1600 release_region(pci_resource_start(pdev, bar),
1601 pci_resource_len(pdev, bar));
1602 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1603 release_mem_region(pci_resource_start(pdev, bar),
1604 pci_resource_len(pdev, bar));
1606 dr = find_pci_dr(pdev);
1608 dr->region_mask &= ~(1 << bar);
1612 * __pci_request_region - Reserved PCI I/O and memory resource
1613 * @pdev: PCI device whose resources are to be reserved
1614 * @bar: BAR to be reserved
1615 * @res_name: Name to be associated with resource.
1616 * @exclusive: whether the region access is exclusive or not
1618 * Mark the PCI region associated with PCI device @pdev BR @bar as
1619 * being reserved by owner @res_name. Do not access any
1620 * address inside the PCI regions unless this call returns
1623 * If @exclusive is set, then the region is marked so that userspace
1624 * is explicitly not allowed to map the resource via /dev/mem or
1625 * sysfs MMIO access.
1627 * Returns 0 on success, or %EBUSY on error. A warning
1628 * message is also printed on failure.
1630 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
1633 struct pci_devres *dr;
1635 if (pci_resource_len(pdev, bar) == 0)
1638 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1639 if (!request_region(pci_resource_start(pdev, bar),
1640 pci_resource_len(pdev, bar), res_name))
1643 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
1644 if (!__request_mem_region(pci_resource_start(pdev, bar),
1645 pci_resource_len(pdev, bar), res_name,
1650 dr = find_pci_dr(pdev);
1652 dr->region_mask |= 1 << bar;
1657 dev_warn(&pdev->dev, "BAR %d: can't reserve %s region %pR\n",
1659 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
1660 &pdev->resource[bar]);
1665 * pci_request_region - Reserve PCI I/O and memory resource
1666 * @pdev: PCI device whose resources are to be reserved
1667 * @bar: BAR to be reserved
1668 * @res_name: Name to be associated with resource
1670 * Mark the PCI region associated with PCI device @pdev BAR @bar as
1671 * being reserved by owner @res_name. Do not access any
1672 * address inside the PCI regions unless this call returns
1675 * Returns 0 on success, or %EBUSY on error. A warning
1676 * message is also printed on failure.
1678 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
1680 return __pci_request_region(pdev, bar, res_name, 0);
1684 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
1685 * @pdev: PCI device whose resources are to be reserved
1686 * @bar: BAR to be reserved
1687 * @res_name: Name to be associated with resource.
1689 * Mark the PCI region associated with PCI device @pdev BR @bar as
1690 * being reserved by owner @res_name. Do not access any
1691 * address inside the PCI regions unless this call returns
1694 * Returns 0 on success, or %EBUSY on error. A warning
1695 * message is also printed on failure.
1697 * The key difference that _exclusive makes it that userspace is
1698 * explicitly not allowed to map the resource via /dev/mem or
1701 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
1703 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
1706 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1707 * @pdev: PCI device whose resources were previously reserved
1708 * @bars: Bitmask of BARs to be released
1710 * Release selected PCI I/O and memory resources previously reserved.
1711 * Call this function only after all use of the PCI regions has ceased.
1713 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1717 for (i = 0; i < 6; i++)
1718 if (bars & (1 << i))
1719 pci_release_region(pdev, i);
1722 int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
1723 const char *res_name, int excl)
1727 for (i = 0; i < 6; i++)
1728 if (bars & (1 << i))
1729 if (__pci_request_region(pdev, i, res_name, excl))
1735 if (bars & (1 << i))
1736 pci_release_region(pdev, i);
1743 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1744 * @pdev: PCI device whose resources are to be reserved
1745 * @bars: Bitmask of BARs to be requested
1746 * @res_name: Name to be associated with resource
1748 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
1749 const char *res_name)
1751 return __pci_request_selected_regions(pdev, bars, res_name, 0);
1754 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
1755 int bars, const char *res_name)
1757 return __pci_request_selected_regions(pdev, bars, res_name,
1758 IORESOURCE_EXCLUSIVE);
1762 * pci_release_regions - Release reserved PCI I/O and memory resources
1763 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1765 * Releases all PCI I/O and memory resources previously reserved by a
1766 * successful call to pci_request_regions. Call this function only
1767 * after all use of the PCI regions has ceased.
1770 void pci_release_regions(struct pci_dev *pdev)
1772 pci_release_selected_regions(pdev, (1 << 6) - 1);
1776 * pci_request_regions - Reserved PCI I/O and memory resources
1777 * @pdev: PCI device whose resources are to be reserved
1778 * @res_name: Name to be associated with resource.
1780 * Mark all PCI regions associated with PCI device @pdev as
1781 * being reserved by owner @res_name. Do not access any
1782 * address inside the PCI regions unless this call returns
1785 * Returns 0 on success, or %EBUSY on error. A warning
1786 * message is also printed on failure.
1788 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
1790 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
1794 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
1795 * @pdev: PCI device whose resources are to be reserved
1796 * @res_name: Name to be associated with resource.
1798 * Mark all PCI regions associated with PCI device @pdev as
1799 * being reserved by owner @res_name. Do not access any
1800 * address inside the PCI regions unless this call returns
1803 * pci_request_regions_exclusive() will mark the region so that
1804 * /dev/mem and the sysfs MMIO access will not be allowed.
1806 * Returns 0 on success, or %EBUSY on error. A warning
1807 * message is also printed on failure.
1809 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
1811 return pci_request_selected_regions_exclusive(pdev,
1812 ((1 << 6) - 1), res_name);
1815 static void __pci_set_master(struct pci_dev *dev, bool enable)
1819 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
1821 cmd = old_cmd | PCI_COMMAND_MASTER;
1823 cmd = old_cmd & ~PCI_COMMAND_MASTER;
1824 if (cmd != old_cmd) {
1825 dev_dbg(&dev->dev, "%s bus mastering\n",
1826 enable ? "enabling" : "disabling");
1827 pci_write_config_word(dev, PCI_COMMAND, cmd);
1829 dev->is_busmaster = enable;
1833 * pci_set_master - enables bus-mastering for device dev
1834 * @dev: the PCI device to enable
1836 * Enables bus-mastering on the device and calls pcibios_set_master()
1837 * to do the needed arch specific settings.
1839 void pci_set_master(struct pci_dev *dev)
1841 __pci_set_master(dev, true);
1842 pcibios_set_master(dev);
1846 * pci_clear_master - disables bus-mastering for device dev
1847 * @dev: the PCI device to disable
1849 void pci_clear_master(struct pci_dev *dev)
1851 __pci_set_master(dev, false);
1854 #ifdef PCI_DISABLE_MWI
1855 int pci_set_mwi(struct pci_dev *dev)
1860 int pci_try_set_mwi(struct pci_dev *dev)
1865 void pci_clear_mwi(struct pci_dev *dev)
1871 #ifndef PCI_CACHE_LINE_BYTES
1872 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1875 /* This can be overridden by arch code. */
1876 /* Don't forget this is measured in 32-bit words, not bytes */
1877 u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
1880 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1881 * @dev: the PCI device for which MWI is to be enabled
1883 * Helper function for pci_set_mwi.
1884 * Originally copied from drivers/net/acenic.c.
1885 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1887 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1890 pci_set_cacheline_size(struct pci_dev *dev)
1894 if (!pci_cache_line_size)
1895 return -EINVAL; /* The system doesn't support MWI. */
1897 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1898 equal to or multiple of the right value. */
1899 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1900 if (cacheline_size >= pci_cache_line_size &&
1901 (cacheline_size % pci_cache_line_size) == 0)
1904 /* Write the correct value. */
1905 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
1907 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1908 if (cacheline_size == pci_cache_line_size)
1911 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
1912 "supported\n", pci_cache_line_size << 2);
1918 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1919 * @dev: the PCI device for which MWI is enabled
1921 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1923 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1926 pci_set_mwi(struct pci_dev *dev)
1931 rc = pci_set_cacheline_size(dev);
1935 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1936 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
1937 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
1938 cmd |= PCI_COMMAND_INVALIDATE;
1939 pci_write_config_word(dev, PCI_COMMAND, cmd);
1946 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1947 * @dev: the PCI device for which MWI is enabled
1949 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1950 * Callers are not required to check the return value.
1952 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1954 int pci_try_set_mwi(struct pci_dev *dev)
1956 int rc = pci_set_mwi(dev);
1961 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1962 * @dev: the PCI device to disable
1964 * Disables PCI Memory-Write-Invalidate transaction on the device
1967 pci_clear_mwi(struct pci_dev *dev)
1971 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1972 if (cmd & PCI_COMMAND_INVALIDATE) {
1973 cmd &= ~PCI_COMMAND_INVALIDATE;
1974 pci_write_config_word(dev, PCI_COMMAND, cmd);
1977 #endif /* ! PCI_DISABLE_MWI */
1980 * pci_intx - enables/disables PCI INTx for device dev
1981 * @pdev: the PCI device to operate on
1982 * @enable: boolean: whether to enable or disable PCI INTx
1984 * Enables/disables PCI INTx for device dev
1987 pci_intx(struct pci_dev *pdev, int enable)
1989 u16 pci_command, new;
1991 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1994 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
1996 new = pci_command | PCI_COMMAND_INTX_DISABLE;
1999 if (new != pci_command) {
2000 struct pci_devres *dr;
2002 pci_write_config_word(pdev, PCI_COMMAND, new);
2004 dr = find_pci_dr(pdev);
2005 if (dr && !dr->restore_intx) {
2006 dr->restore_intx = 1;
2007 dr->orig_intx = !enable;
2013 * pci_msi_off - disables any msi or msix capabilities
2014 * @dev: the PCI device to operate on
2016 * If you want to use msi see pci_enable_msi and friends.
2017 * This is a lower level primitive that allows us to disable
2018 * msi operation at the device level.
2020 void pci_msi_off(struct pci_dev *dev)
2025 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2027 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2028 control &= ~PCI_MSI_FLAGS_ENABLE;
2029 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2031 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2033 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2034 control &= ~PCI_MSIX_FLAGS_ENABLE;
2035 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2039 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
2041 * These can be overridden by arch-specific implementations
2044 pci_set_dma_mask(struct pci_dev *dev, u64 mask)
2046 if (!pci_dma_supported(dev, mask))
2049 dev->dma_mask = mask;
2055 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
2057 if (!pci_dma_supported(dev, mask))
2060 dev->dev.coherent_dma_mask = mask;
2066 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
2067 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
2069 return dma_set_max_seg_size(&dev->dev, size);
2071 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
2074 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
2075 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
2077 return dma_set_seg_boundary(&dev->dev, mask);
2079 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
2082 static int pcie_flr(struct pci_dev *dev, int probe)
2089 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
2093 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
2094 if (!(cap & PCI_EXP_DEVCAP_FLR))
2100 /* Wait for Transaction Pending bit clean */
2101 for (i = 0; i < 4; i++) {
2103 msleep((1 << (i - 1)) * 100);
2105 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
2106 if (!(status & PCI_EXP_DEVSTA_TRPND))
2110 dev_err(&dev->dev, "transaction is not cleared; "
2111 "proceeding with reset anyway\n");
2114 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
2115 PCI_EXP_DEVCTL_BCR_FLR);
2121 static int pci_af_flr(struct pci_dev *dev, int probe)
2128 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
2132 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
2133 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
2139 /* Wait for Transaction Pending bit clean */
2140 for (i = 0; i < 4; i++) {
2142 msleep((1 << (i - 1)) * 100);
2144 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
2145 if (!(status & PCI_AF_STATUS_TP))
2149 dev_err(&dev->dev, "transaction is not cleared; "
2150 "proceeding with reset anyway\n");
2153 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
2159 static int pci_pm_reset(struct pci_dev *dev, int probe)
2166 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
2167 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
2173 if (dev->current_state != PCI_D0)
2176 csr &= ~PCI_PM_CTRL_STATE_MASK;
2178 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2179 msleep(pci_pm_d3_delay);
2181 csr &= ~PCI_PM_CTRL_STATE_MASK;
2183 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2184 msleep(pci_pm_d3_delay);
2189 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
2192 struct pci_dev *pdev;
2194 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
2197 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
2204 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
2205 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
2206 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2209 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
2210 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2216 static int pci_dev_reset(struct pci_dev *dev, int probe)
2223 pci_block_user_cfg_access(dev);
2224 /* block PM suspend, driver probe, etc. */
2225 down(&dev->dev.sem);
2228 rc = pcie_flr(dev, probe);
2232 rc = pci_af_flr(dev, probe);
2236 rc = pci_pm_reset(dev, probe);
2240 rc = pci_parent_bus_reset(dev, probe);
2244 pci_unblock_user_cfg_access(dev);
2251 * __pci_reset_function - reset a PCI device function
2252 * @dev: PCI device to reset
2254 * Some devices allow an individual function to be reset without affecting
2255 * other functions in the same device. The PCI device must be responsive
2256 * to PCI config space in order to use this function.
2258 * The device function is presumed to be unused when this function is called.
2259 * Resetting the device will make the contents of PCI configuration space
2260 * random, so any caller of this must be prepared to reinitialise the
2261 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2264 * Returns 0 if the device function was successfully reset or negative if the
2265 * device doesn't support resetting a single function.
2267 int __pci_reset_function(struct pci_dev *dev)
2269 return pci_dev_reset(dev, 0);
2271 EXPORT_SYMBOL_GPL(__pci_reset_function);
2274 * pci_probe_reset_function - check whether the device can be safely reset
2275 * @dev: PCI device to reset
2277 * Some devices allow an individual function to be reset without affecting
2278 * other functions in the same device. The PCI device must be responsive
2279 * to PCI config space in order to use this function.
2281 * Returns 0 if the device function can be reset or negative if the
2282 * device doesn't support resetting a single function.
2284 int pci_probe_reset_function(struct pci_dev *dev)
2286 return pci_dev_reset(dev, 1);
2290 * pci_reset_function - quiesce and reset a PCI device function
2291 * @dev: PCI device to reset
2293 * Some devices allow an individual function to be reset without affecting
2294 * other functions in the same device. The PCI device must be responsive
2295 * to PCI config space in order to use this function.
2297 * This function does not just reset the PCI portion of a device, but
2298 * clears all the state associated with the device. This function differs
2299 * from __pci_reset_function in that it saves and restores device state
2302 * Returns 0 if the device function was successfully reset or negative if the
2303 * device doesn't support resetting a single function.
2305 int pci_reset_function(struct pci_dev *dev)
2309 rc = pci_dev_reset(dev, 1);
2313 pci_save_state(dev);
2316 * both INTx and MSI are disabled after the Interrupt Disable bit
2317 * is set and the Bus Master bit is cleared.
2319 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
2321 rc = pci_dev_reset(dev, 0);
2323 pci_restore_state(dev);
2327 EXPORT_SYMBOL_GPL(pci_reset_function);
2330 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2331 * @dev: PCI device to query
2333 * Returns mmrbc: maximum designed memory read count in bytes
2334 * or appropriate error value.
2336 int pcix_get_max_mmrbc(struct pci_dev *dev)
2341 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2345 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
2349 return (stat & PCI_X_STATUS_MAX_READ) >> 12;
2351 EXPORT_SYMBOL(pcix_get_max_mmrbc);
2354 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2355 * @dev: PCI device to query
2357 * Returns mmrbc: maximum memory read count in bytes
2358 * or appropriate error value.
2360 int pcix_get_mmrbc(struct pci_dev *dev)
2365 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2369 ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
2371 ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
2375 EXPORT_SYMBOL(pcix_get_mmrbc);
2378 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2379 * @dev: PCI device to query
2380 * @mmrbc: maximum memory read count in bytes
2381 * valid values are 512, 1024, 2048, 4096
2383 * If possible sets maximum memory read byte count, some bridges have erratas
2384 * that prevent this.
2386 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
2388 int cap, err = -EINVAL;
2389 u32 stat, cmd, v, o;
2391 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
2394 v = ffs(mmrbc) - 10;
2396 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2400 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
2404 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
2407 err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
2411 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
2413 if (v > o && dev->bus &&
2414 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
2417 cmd &= ~PCI_X_CMD_MAX_READ;
2419 err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
2424 EXPORT_SYMBOL(pcix_set_mmrbc);
2427 * pcie_get_readrq - get PCI Express read request size
2428 * @dev: PCI device to query
2430 * Returns maximum memory read request in bytes
2431 * or appropriate error value.
2433 int pcie_get_readrq(struct pci_dev *dev)
2438 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
2442 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2444 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
2448 EXPORT_SYMBOL(pcie_get_readrq);
2451 * pcie_set_readrq - set PCI Express maximum memory read request
2452 * @dev: PCI device to query
2453 * @rq: maximum memory read count in bytes
2454 * valid values are 128, 256, 512, 1024, 2048, 4096
2456 * If possible sets maximum read byte count
2458 int pcie_set_readrq(struct pci_dev *dev, int rq)
2460 int cap, err = -EINVAL;
2463 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
2466 v = (ffs(rq) - 8) << 12;
2468 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
2472 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2476 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
2477 ctl &= ~PCI_EXP_DEVCTL_READRQ;
2479 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
2485 EXPORT_SYMBOL(pcie_set_readrq);
2488 * pci_select_bars - Make BAR mask from the type of resource
2489 * @dev: the PCI device for which BAR mask is made
2490 * @flags: resource type mask to be selected
2492 * This helper routine makes bar mask from the type of resource.
2494 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
2497 for (i = 0; i < PCI_NUM_RESOURCES; i++)
2498 if (pci_resource_flags(dev, i) & flags)
2504 * pci_resource_bar - get position of the BAR associated with a resource
2505 * @dev: the PCI device
2506 * @resno: the resource number
2507 * @type: the BAR type to be filled in
2509 * Returns BAR position in config space, or 0 if the BAR is invalid.
2511 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
2515 if (resno < PCI_ROM_RESOURCE) {
2516 *type = pci_bar_unknown;
2517 return PCI_BASE_ADDRESS_0 + 4 * resno;
2518 } else if (resno == PCI_ROM_RESOURCE) {
2519 *type = pci_bar_mem32;
2520 return dev->rom_base_reg;
2521 } else if (resno < PCI_BRIDGE_RESOURCES) {
2522 /* device specific resource */
2523 reg = pci_iov_resource_bar(dev, resno, type);
2528 dev_err(&dev->dev, "BAR: invalid resource #%d\n", resno);
2533 * pci_set_vga_state - set VGA decode state on device and parents if requested
2534 * @dev the PCI device
2535 * @decode - true = enable decoding, false = disable decoding
2536 * @command_bits PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
2537 * @change_bridge - traverse ancestors and change bridges
2539 int pci_set_vga_state(struct pci_dev *dev, bool decode,
2540 unsigned int command_bits, bool change_bridge)
2542 struct pci_bus *bus;
2543 struct pci_dev *bridge;
2546 WARN_ON(command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY));
2548 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2550 cmd |= command_bits;
2552 cmd &= ~command_bits;
2553 pci_write_config_word(dev, PCI_COMMAND, cmd);
2555 if (change_bridge == false)
2562 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
2565 cmd |= PCI_BRIDGE_CTL_VGA;
2567 cmd &= ~PCI_BRIDGE_CTL_VGA;
2568 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
2576 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
2577 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
2578 spinlock_t resource_alignment_lock = SPIN_LOCK_UNLOCKED;
2581 * pci_specified_resource_alignment - get resource alignment specified by user.
2582 * @dev: the PCI device to get
2584 * RETURNS: Resource alignment if it is specified.
2585 * Zero if it is not specified.
2587 resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
2589 int seg, bus, slot, func, align_order, count;
2590 resource_size_t align = 0;
2593 spin_lock(&resource_alignment_lock);
2594 p = resource_alignment_param;
2597 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
2603 if (sscanf(p, "%x:%x:%x.%x%n",
2604 &seg, &bus, &slot, &func, &count) != 4) {
2606 if (sscanf(p, "%x:%x.%x%n",
2607 &bus, &slot, &func, &count) != 3) {
2608 /* Invalid format */
2609 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
2615 if (seg == pci_domain_nr(dev->bus) &&
2616 bus == dev->bus->number &&
2617 slot == PCI_SLOT(dev->devfn) &&
2618 func == PCI_FUNC(dev->devfn)) {
2619 if (align_order == -1) {
2622 align = 1 << align_order;
2627 if (*p != ';' && *p != ',') {
2628 /* End of param or invalid format */
2633 spin_unlock(&resource_alignment_lock);
2638 * pci_is_reassigndev - check if specified PCI is target device to reassign
2639 * @dev: the PCI device to check
2641 * RETURNS: non-zero for PCI device is a target device to reassign,
2644 int pci_is_reassigndev(struct pci_dev *dev)
2646 return (pci_specified_resource_alignment(dev) != 0);
2649 ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
2651 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
2652 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
2653 spin_lock(&resource_alignment_lock);
2654 strncpy(resource_alignment_param, buf, count);
2655 resource_alignment_param[count] = '\0';
2656 spin_unlock(&resource_alignment_lock);
2660 ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
2663 spin_lock(&resource_alignment_lock);
2664 count = snprintf(buf, size, "%s", resource_alignment_param);
2665 spin_unlock(&resource_alignment_lock);
2669 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
2671 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
2674 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
2675 const char *buf, size_t count)
2677 return pci_set_resource_alignment_param(buf, count);
2680 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
2681 pci_resource_alignment_store);
2683 static int __init pci_resource_alignment_sysfs_init(void)
2685 return bus_create_file(&pci_bus_type,
2686 &bus_attr_resource_alignment);
2689 late_initcall(pci_resource_alignment_sysfs_init);
2691 static void __devinit pci_no_domains(void)
2693 #ifdef CONFIG_PCI_DOMAINS
2694 pci_domains_supported = 0;
2699 * pci_ext_cfg_enabled - can we access extended PCI config space?
2700 * @dev: The PCI device of the root bridge.
2702 * Returns 1 if we can access PCI extended config space (offsets
2703 * greater than 0xff). This is the default implementation. Architecture
2704 * implementations can override this.
2706 int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
2711 static int __devinit pci_init(void)
2713 struct pci_dev *dev = NULL;
2715 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2716 pci_fixup_device(pci_fixup_final, dev);
2722 static int __init pci_setup(char *str)
2725 char *k = strchr(str, ',');
2728 if (*str && (str = pcibios_setup(str)) && *str) {
2729 if (!strcmp(str, "nomsi")) {
2731 } else if (!strcmp(str, "noaer")) {
2733 } else if (!strcmp(str, "nodomains")) {
2735 } else if (!strncmp(str, "cbiosize=", 9)) {
2736 pci_cardbus_io_size = memparse(str + 9, &str);
2737 } else if (!strncmp(str, "cbmemsize=", 10)) {
2738 pci_cardbus_mem_size = memparse(str + 10, &str);
2739 } else if (!strncmp(str, "resource_alignment=", 19)) {
2740 pci_set_resource_alignment_param(str + 19,
2742 } else if (!strncmp(str, "ecrc=", 5)) {
2743 pcie_ecrc_get_policy(str + 5);
2744 } else if (!strncmp(str, "hpiosize=", 9)) {
2745 pci_hotplug_io_size = memparse(str + 9, &str);
2746 } else if (!strncmp(str, "hpmemsize=", 10)) {
2747 pci_hotplug_mem_size = memparse(str + 10, &str);
2749 printk(KERN_ERR "PCI: Unknown option `%s'\n",
2757 early_param("pci", pci_setup);
2759 device_initcall(pci_init);
2761 EXPORT_SYMBOL(pci_reenable_device);
2762 EXPORT_SYMBOL(pci_enable_device_io);
2763 EXPORT_SYMBOL(pci_enable_device_mem);
2764 EXPORT_SYMBOL(pci_enable_device);
2765 EXPORT_SYMBOL(pcim_enable_device);
2766 EXPORT_SYMBOL(pcim_pin_device);
2767 EXPORT_SYMBOL(pci_disable_device);
2768 EXPORT_SYMBOL(pci_find_capability);
2769 EXPORT_SYMBOL(pci_bus_find_capability);
2770 EXPORT_SYMBOL(pci_release_regions);
2771 EXPORT_SYMBOL(pci_request_regions);
2772 EXPORT_SYMBOL(pci_request_regions_exclusive);
2773 EXPORT_SYMBOL(pci_release_region);
2774 EXPORT_SYMBOL(pci_request_region);
2775 EXPORT_SYMBOL(pci_request_region_exclusive);
2776 EXPORT_SYMBOL(pci_release_selected_regions);
2777 EXPORT_SYMBOL(pci_request_selected_regions);
2778 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
2779 EXPORT_SYMBOL(pci_set_master);
2780 EXPORT_SYMBOL(pci_clear_master);
2781 EXPORT_SYMBOL(pci_set_mwi);
2782 EXPORT_SYMBOL(pci_try_set_mwi);
2783 EXPORT_SYMBOL(pci_clear_mwi);
2784 EXPORT_SYMBOL_GPL(pci_intx);
2785 EXPORT_SYMBOL(pci_set_dma_mask);
2786 EXPORT_SYMBOL(pci_set_consistent_dma_mask);
2787 EXPORT_SYMBOL(pci_assign_resource);
2788 EXPORT_SYMBOL(pci_find_parent_resource);
2789 EXPORT_SYMBOL(pci_select_bars);
2791 EXPORT_SYMBOL(pci_set_power_state);
2792 EXPORT_SYMBOL(pci_save_state);
2793 EXPORT_SYMBOL(pci_restore_state);
2794 EXPORT_SYMBOL(pci_pme_capable);
2795 EXPORT_SYMBOL(pci_pme_active);
2796 EXPORT_SYMBOL(pci_enable_wake);
2797 EXPORT_SYMBOL(pci_wake_from_d3);
2798 EXPORT_SYMBOL(pci_target_state);
2799 EXPORT_SYMBOL(pci_prepare_to_sleep);
2800 EXPORT_SYMBOL(pci_back_from_sleep);
2801 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);