2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <asm/dma.h> /* isa_dma_bridge_buggy */
22 unsigned int pci_pm_d3_delay = 10;
25 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
26 * @bus: pointer to PCI bus structure to search
28 * Given a PCI bus, returns the highest PCI bus number present in the set
29 * including the given PCI bus and its list of child PCI buses.
31 unsigned char __devinit
32 pci_bus_max_busnr(struct pci_bus* bus)
34 struct list_head *tmp;
37 max = bus->subordinate;
38 list_for_each(tmp, &bus->children) {
39 n = pci_bus_max_busnr(pci_bus_b(tmp));
45 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
49 * pci_max_busnr - returns maximum PCI bus number
51 * Returns the highest PCI bus number present in the system global list of
54 unsigned char __devinit
57 struct pci_bus *bus = NULL;
61 while ((bus = pci_find_next_bus(bus)) != NULL) {
62 n = pci_bus_max_busnr(bus);
71 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, u8 pos, int cap)
77 pci_bus_read_config_byte(bus, devfn, pos, &pos);
81 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
87 pos += PCI_CAP_LIST_NEXT;
92 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
94 return __pci_find_next_cap(dev->bus, dev->devfn,
95 pos + PCI_CAP_LIST_NEXT, cap);
97 EXPORT_SYMBOL_GPL(pci_find_next_capability);
99 static int __pci_bus_find_cap(struct pci_bus *bus, unsigned int devfn, u8 hdr_type, int cap)
104 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
105 if (!(status & PCI_STATUS_CAP_LIST))
109 case PCI_HEADER_TYPE_NORMAL:
110 case PCI_HEADER_TYPE_BRIDGE:
111 pos = PCI_CAPABILITY_LIST;
113 case PCI_HEADER_TYPE_CARDBUS:
114 pos = PCI_CB_CAPABILITY_LIST;
119 return __pci_find_next_cap(bus, devfn, pos, cap);
123 * pci_find_capability - query for devices' capabilities
124 * @dev: PCI device to query
125 * @cap: capability code
127 * Tell if a device supports a given PCI capability.
128 * Returns the address of the requested capability structure within the
129 * device's PCI configuration space or 0 in case the device does not
130 * support it. Possible values for @cap:
132 * %PCI_CAP_ID_PM Power Management
133 * %PCI_CAP_ID_AGP Accelerated Graphics Port
134 * %PCI_CAP_ID_VPD Vital Product Data
135 * %PCI_CAP_ID_SLOTID Slot Identification
136 * %PCI_CAP_ID_MSI Message Signalled Interrupts
137 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
138 * %PCI_CAP_ID_PCIX PCI-X
139 * %PCI_CAP_ID_EXP PCI Express
141 int pci_find_capability(struct pci_dev *dev, int cap)
143 return __pci_bus_find_cap(dev->bus, dev->devfn, dev->hdr_type, cap);
147 * pci_bus_find_capability - query for devices' capabilities
148 * @bus: the PCI bus to query
149 * @devfn: PCI device to query
150 * @cap: capability code
152 * Like pci_find_capability() but works for pci devices that do not have a
153 * pci_dev structure set up yet.
155 * Returns the address of the requested capability structure within the
156 * device's PCI configuration space or 0 in case the device does not
159 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
163 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
165 return __pci_bus_find_cap(bus, devfn, hdr_type & 0x7f, cap);
169 * pci_find_ext_capability - Find an extended capability
170 * @dev: PCI device to query
171 * @cap: capability code
173 * Returns the address of the requested extended capability structure
174 * within the device's PCI configuration space or 0 if the device does
175 * not support it. Possible values for @cap:
177 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
178 * %PCI_EXT_CAP_ID_VC Virtual Channel
179 * %PCI_EXT_CAP_ID_DSN Device Serial Number
180 * %PCI_EXT_CAP_ID_PWR Power Budgeting
182 int pci_find_ext_capability(struct pci_dev *dev, int cap)
185 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
188 if (dev->cfg_size <= 256)
191 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
195 * If we have no capabilities, this is indicated by cap ID,
196 * cap version and next pointer all being 0.
202 if (PCI_EXT_CAP_ID(header) == cap)
205 pos = PCI_EXT_CAP_NEXT(header);
209 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
215 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
218 * pci_find_parent_resource - return resource region of parent bus of given region
219 * @dev: PCI device structure contains resources to be searched
220 * @res: child resource record for which parent is sought
222 * For given resource region of given device, return the resource
223 * region of parent bus the given region is contained in or where
224 * it should be allocated from.
227 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
229 const struct pci_bus *bus = dev->bus;
231 struct resource *best = NULL;
233 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
234 struct resource *r = bus->resource[i];
237 if (res->start && !(res->start >= r->start && res->end <= r->end))
238 continue; /* Not contained */
239 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
240 continue; /* Wrong type */
241 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
242 return r; /* Exact match */
243 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
244 best = r; /* Approximating prefetchable by non-prefetchable */
250 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
251 * @dev: PCI device to have its BARs restored
253 * Restore the BAR values for a given device, so as to make it
254 * accessible by its driver.
257 pci_restore_bars(struct pci_dev *dev)
261 switch (dev->hdr_type) {
262 case PCI_HEADER_TYPE_NORMAL:
265 case PCI_HEADER_TYPE_BRIDGE:
268 case PCI_HEADER_TYPE_CARDBUS:
272 /* Should never get here, but just in case... */
276 for (i = 0; i < numres; i ++)
277 pci_update_resource(dev, &dev->resource[i], i);
280 int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t);
283 * pci_set_power_state - Set the power state of a PCI device
284 * @dev: PCI device to be suspended
285 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
287 * Transition a device to a new power state, using the Power Management
288 * Capabilities in the device's config space.
291 * -EINVAL if trying to enter a lower state than we're already in.
292 * 0 if we're already in the requested state.
293 * -EIO if device does not support PCI PM.
294 * 0 if we can successfully change the power state.
297 pci_set_power_state(struct pci_dev *dev, pci_power_t state)
299 int pm, need_restore = 0;
302 /* bound the state we're entering */
303 if (state > PCI_D3hot)
306 /* Validate current state:
307 * Can enter D0 from any state, but if we can only go deeper
308 * to sleep if we're already in a low power state
310 if (state != PCI_D0 && dev->current_state > state) {
311 printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n",
312 __FUNCTION__, pci_name(dev), state, dev->current_state);
314 } else if (dev->current_state == state)
315 return 0; /* we're already there */
318 * If the device or the parent bridge can't support PCI PM, ignore
319 * the request if we're doing anything besides putting it into D0
320 * (which would only happen on boot).
322 if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
325 /* find PCI PM capability in list */
326 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
328 /* abort if the device doesn't support PM capabilities */
332 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
333 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
335 "PCI: %s has unsupported PM cap regs version (%u)\n",
336 pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
340 /* check if this device supports the desired state */
341 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
343 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
346 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
348 /* If we're (effectively) in D3, force entire word to 0.
349 * This doesn't affect PME_Status, disables PME_En, and
350 * sets PowerState to 0.
352 switch (dev->current_state) {
356 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
359 case PCI_UNKNOWN: /* Boot-up */
360 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
361 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
363 /* Fall-through: force to D0 */
369 /* enter specified state */
370 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
372 /* Mandatory power management transition delays */
373 /* see PCI PM 1.1 5.6.1 table 18 */
374 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
375 msleep(pci_pm_d3_delay);
376 else if (state == PCI_D2 || dev->current_state == PCI_D2)
380 * Give firmware a chance to be called, such as ACPI _PRx, _PSx
381 * Firmware method after native method ?
383 if (platform_pci_set_power_state)
384 platform_pci_set_power_state(dev, state);
386 dev->current_state = state;
388 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
389 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
390 * from D3hot to D0 _may_ perform an internal reset, thereby
391 * going to "D0 Uninitialized" rather than "D0 Initialized".
392 * For example, at least some versions of the 3c905B and the
393 * 3c556B exhibit this behaviour.
395 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
396 * devices in a D3hot state at boot. Consequently, we need to
397 * restore at least the BARs so that the device will be
398 * accessible to its driver.
401 pci_restore_bars(dev);
406 int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state);
409 * pci_choose_state - Choose the power state of a PCI device
410 * @dev: PCI device to be suspended
411 * @state: target sleep state for the whole system. This is the value
412 * that is passed to suspend() function.
414 * Returns PCI power state suitable for given device and given system
418 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
422 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
425 if (platform_pci_choose_state) {
426 ret = platform_pci_choose_state(dev, state);
431 switch (state.event) {
434 case PM_EVENT_FREEZE:
435 case PM_EVENT_PRETHAW:
436 /* REVISIT both freeze and pre-thaw "should" use D0 */
437 case PM_EVENT_SUSPEND:
440 printk("Unrecognized suspend event %d\n", state.event);
446 EXPORT_SYMBOL(pci_choose_state);
448 static int pci_save_pcie_state(struct pci_dev *dev)
451 struct pci_cap_saved_state *save_state;
454 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
458 save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL);
460 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
463 cap = (u16 *)&save_state->data[0];
465 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
466 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
467 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
468 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
469 pci_add_saved_cap(dev, save_state);
473 static void pci_restore_pcie_state(struct pci_dev *dev)
476 struct pci_cap_saved_state *save_state;
479 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
480 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
481 if (!save_state || pos <= 0)
483 cap = (u16 *)&save_state->data[0];
485 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
486 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
487 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
488 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
489 pci_remove_saved_cap(save_state);
494 static int pci_save_pcix_state(struct pci_dev *dev)
497 struct pci_cap_saved_state *save_state;
500 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
504 save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL);
506 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
509 cap = (u16 *)&save_state->data[0];
511 pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]);
512 pci_add_saved_cap(dev, save_state);
516 static void pci_restore_pcix_state(struct pci_dev *dev)
519 struct pci_cap_saved_state *save_state;
522 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
523 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
524 if (!save_state || pos <= 0)
526 cap = (u16 *)&save_state->data[0];
528 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
529 pci_remove_saved_cap(save_state);
535 * pci_save_state - save the PCI configuration space of a device before suspending
536 * @dev: - PCI device that we're dealing with
539 pci_save_state(struct pci_dev *dev)
542 /* XXX: 100% dword access ok here? */
543 for (i = 0; i < 16; i++)
544 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
545 if ((i = pci_save_msi_state(dev)) != 0)
547 if ((i = pci_save_msix_state(dev)) != 0)
549 if ((i = pci_save_pcie_state(dev)) != 0)
551 if ((i = pci_save_pcix_state(dev)) != 0)
557 * pci_restore_state - Restore the saved state of a PCI device
558 * @dev: - PCI device that we're dealing with
561 pci_restore_state(struct pci_dev *dev)
566 /* PCI Express register must be restored first */
567 pci_restore_pcie_state(dev);
570 * The Base Address register should be programmed before the command
573 for (i = 15; i >= 0; i--) {
574 pci_read_config_dword(dev, i * 4, &val);
575 if (val != dev->saved_config_space[i]) {
576 printk(KERN_DEBUG "PM: Writing back config space on "
577 "device %s at offset %x (was %x, writing %x)\n",
579 val, (int)dev->saved_config_space[i]);
580 pci_write_config_dword(dev,i * 4,
581 dev->saved_config_space[i]);
584 pci_restore_pcix_state(dev);
585 pci_restore_msi_state(dev);
586 pci_restore_msix_state(dev);
591 * pci_enable_device_bars - Initialize some of a device for use
592 * @dev: PCI device to be initialized
593 * @bars: bitmask of BAR's that must be configured
595 * Initialize device before it's used by a driver. Ask low-level code
596 * to enable selected I/O and memory resources. Wake up the device if it
597 * was suspended. Beware, this function can fail.
601 pci_enable_device_bars(struct pci_dev *dev, int bars)
605 err = pci_set_power_state(dev, PCI_D0);
606 if (err < 0 && err != -EIO)
608 err = pcibios_enable_device(dev, bars);
615 * pci_enable_device - Initialize device before it's used by a driver.
616 * @dev: PCI device to be initialized
618 * Initialize device before it's used by a driver. Ask low-level code
619 * to enable I/O and memory. Wake up the device if it was suspended.
620 * Beware, this function can fail.
623 pci_enable_device(struct pci_dev *dev)
630 err = pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1);
633 pci_fixup_device(pci_fixup_enable, dev);
639 * pcibios_disable_device - disable arch specific PCI resources for device dev
640 * @dev: the PCI device to disable
642 * Disables architecture specific PCI resources for the device. This
643 * is the default implementation. Architecture implementations can
646 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
649 * pci_disable_device - Disable PCI device after use
650 * @dev: PCI device to be disabled
652 * Signal to the system that the PCI device is not in use by the system
653 * anymore. This only involves disabling PCI bus-mastering, if active.
656 pci_disable_device(struct pci_dev *dev)
660 if (dev->msi_enabled)
661 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
663 if (dev->msix_enabled)
664 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
667 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
668 if (pci_command & PCI_COMMAND_MASTER) {
669 pci_command &= ~PCI_COMMAND_MASTER;
670 pci_write_config_word(dev, PCI_COMMAND, pci_command);
672 dev->is_busmaster = 0;
674 pcibios_disable_device(dev);
679 * pci_enable_wake - enable device to generate PME# when suspended
680 * @dev: - PCI device to operate on
681 * @state: - Current state of device.
682 * @enable: - Flag to enable or disable generation
684 * Set the bits in the device's PM Capabilities to generate PME# when
685 * the system is suspended.
687 * -EIO is returned if device doesn't have PM Capabilities.
688 * -EINVAL is returned if device supports it, but can't generate wake events.
689 * 0 if operation is successful.
692 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
697 /* find PCI PM capability in list */
698 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
700 /* If device doesn't support PM Capabilities, but request is to disable
701 * wake events, it's a nop; otherwise fail */
703 return enable ? -EIO : 0;
705 /* Check device's ability to generate PME# */
706 pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
708 value &= PCI_PM_CAP_PME_MASK;
709 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
711 /* Check if it can generate PME# from requested state. */
712 if (!value || !(value & (1 << state)))
713 return enable ? -EINVAL : 0;
715 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
717 /* Clear PME_Status by writing 1 to it and enable PME# */
718 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
721 value &= ~PCI_PM_CTRL_PME_ENABLE;
723 pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
729 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
737 while (dev->bus->self) {
738 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
739 dev = dev->bus->self;
746 * pci_release_region - Release a PCI bar
747 * @pdev: PCI device whose resources were previously reserved by pci_request_region
748 * @bar: BAR to release
750 * Releases the PCI I/O and memory resources previously reserved by a
751 * successful call to pci_request_region. Call this function only
752 * after all use of the PCI regions has ceased.
754 void pci_release_region(struct pci_dev *pdev, int bar)
756 if (pci_resource_len(pdev, bar) == 0)
758 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
759 release_region(pci_resource_start(pdev, bar),
760 pci_resource_len(pdev, bar));
761 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
762 release_mem_region(pci_resource_start(pdev, bar),
763 pci_resource_len(pdev, bar));
767 * pci_request_region - Reserved PCI I/O and memory resource
768 * @pdev: PCI device whose resources are to be reserved
769 * @bar: BAR to be reserved
770 * @res_name: Name to be associated with resource.
772 * Mark the PCI region associated with PCI device @pdev BR @bar as
773 * being reserved by owner @res_name. Do not access any
774 * address inside the PCI regions unless this call returns
777 * Returns 0 on success, or %EBUSY on error. A warning
778 * message is also printed on failure.
780 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
782 if (pci_resource_len(pdev, bar) == 0)
785 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
786 if (!request_region(pci_resource_start(pdev, bar),
787 pci_resource_len(pdev, bar), res_name))
790 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
791 if (!request_mem_region(pci_resource_start(pdev, bar),
792 pci_resource_len(pdev, bar), res_name))
799 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%llx@%llx "
801 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
802 bar + 1, /* PCI BAR # */
803 (unsigned long long)pci_resource_len(pdev, bar),
804 (unsigned long long)pci_resource_start(pdev, bar),
811 * pci_release_regions - Release reserved PCI I/O and memory resources
812 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
814 * Releases all PCI I/O and memory resources previously reserved by a
815 * successful call to pci_request_regions. Call this function only
816 * after all use of the PCI regions has ceased.
819 void pci_release_regions(struct pci_dev *pdev)
823 for (i = 0; i < 6; i++)
824 pci_release_region(pdev, i);
828 * pci_request_regions - Reserved PCI I/O and memory resources
829 * @pdev: PCI device whose resources are to be reserved
830 * @res_name: Name to be associated with resource.
832 * Mark all PCI regions associated with PCI device @pdev as
833 * being reserved by owner @res_name. Do not access any
834 * address inside the PCI regions unless this call returns
837 * Returns 0 on success, or %EBUSY on error. A warning
838 * message is also printed on failure.
840 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
844 for (i = 0; i < 6; i++)
845 if(pci_request_region(pdev, i, res_name))
851 pci_release_region(pdev, i);
857 * pci_set_master - enables bus-mastering for device dev
858 * @dev: the PCI device to enable
860 * Enables bus-mastering on the device and calls pcibios_set_master()
861 * to do the needed arch specific settings.
864 pci_set_master(struct pci_dev *dev)
868 pci_read_config_word(dev, PCI_COMMAND, &cmd);
869 if (! (cmd & PCI_COMMAND_MASTER)) {
870 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev));
871 cmd |= PCI_COMMAND_MASTER;
872 pci_write_config_word(dev, PCI_COMMAND, cmd);
874 dev->is_busmaster = 1;
875 pcibios_set_master(dev);
878 #ifdef PCI_DISABLE_MWI
879 int pci_set_mwi(struct pci_dev *dev)
884 void pci_clear_mwi(struct pci_dev *dev)
890 #ifndef PCI_CACHE_LINE_BYTES
891 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
894 /* This can be overridden by arch code. */
895 /* Don't forget this is measured in 32-bit words, not bytes */
896 u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
899 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
900 * @dev: the PCI device for which MWI is to be enabled
902 * Helper function for pci_set_mwi.
903 * Originally copied from drivers/net/acenic.c.
904 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
906 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
909 pci_set_cacheline_size(struct pci_dev *dev)
913 if (!pci_cache_line_size)
914 return -EINVAL; /* The system doesn't support MWI. */
916 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
917 equal to or multiple of the right value. */
918 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
919 if (cacheline_size >= pci_cache_line_size &&
920 (cacheline_size % pci_cache_line_size) == 0)
923 /* Write the correct value. */
924 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
926 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
927 if (cacheline_size == pci_cache_line_size)
930 printk(KERN_DEBUG "PCI: cache line size of %d is not supported "
931 "by device %s\n", pci_cache_line_size << 2, pci_name(dev));
937 * pci_set_mwi - enables memory-write-invalidate PCI transaction
938 * @dev: the PCI device for which MWI is enabled
940 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
941 * and then calls @pcibios_set_mwi to do the needed arch specific
942 * operations or a generic mwi-prep function.
944 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
947 pci_set_mwi(struct pci_dev *dev)
952 rc = pci_set_cacheline_size(dev);
956 pci_read_config_word(dev, PCI_COMMAND, &cmd);
957 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
958 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev));
959 cmd |= PCI_COMMAND_INVALIDATE;
960 pci_write_config_word(dev, PCI_COMMAND, cmd);
967 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
968 * @dev: the PCI device to disable
970 * Disables PCI Memory-Write-Invalidate transaction on the device
973 pci_clear_mwi(struct pci_dev *dev)
977 pci_read_config_word(dev, PCI_COMMAND, &cmd);
978 if (cmd & PCI_COMMAND_INVALIDATE) {
979 cmd &= ~PCI_COMMAND_INVALIDATE;
980 pci_write_config_word(dev, PCI_COMMAND, cmd);
983 #endif /* ! PCI_DISABLE_MWI */
986 * pci_intx - enables/disables PCI INTx for device dev
987 * @pdev: the PCI device to operate on
988 * @enable: boolean: whether to enable or disable PCI INTx
990 * Enables/disables PCI INTx for device dev
993 pci_intx(struct pci_dev *pdev, int enable)
995 u16 pci_command, new;
997 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1000 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
1002 new = pci_command | PCI_COMMAND_INTX_DISABLE;
1005 if (new != pci_command) {
1006 pci_write_config_word(pdev, PCI_COMMAND, new);
1010 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1012 * These can be overridden by arch-specific implementations
1015 pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1017 if (!pci_dma_supported(dev, mask))
1020 dev->dma_mask = mask;
1026 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1028 if (!pci_dma_supported(dev, mask))
1031 dev->dev.coherent_dma_mask = mask;
1037 static int __devinit pci_init(void)
1039 struct pci_dev *dev = NULL;
1041 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1042 pci_fixup_device(pci_fixup_final, dev);
1047 static int __devinit pci_setup(char *str)
1050 char *k = strchr(str, ',');
1053 if (*str && (str = pcibios_setup(str)) && *str) {
1054 if (!strcmp(str, "nomsi")) {
1057 printk(KERN_ERR "PCI: Unknown option `%s'\n",
1065 early_param("pci", pci_setup);
1067 device_initcall(pci_init);
1069 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
1070 /* FIXME: Some boxes have multiple ISA bridges! */
1071 struct pci_dev *isa_bridge;
1072 EXPORT_SYMBOL(isa_bridge);
1075 EXPORT_SYMBOL_GPL(pci_restore_bars);
1076 EXPORT_SYMBOL(pci_enable_device_bars);
1077 EXPORT_SYMBOL(pci_enable_device);
1078 EXPORT_SYMBOL(pci_disable_device);
1079 EXPORT_SYMBOL(pci_find_capability);
1080 EXPORT_SYMBOL(pci_bus_find_capability);
1081 EXPORT_SYMBOL(pci_release_regions);
1082 EXPORT_SYMBOL(pci_request_regions);
1083 EXPORT_SYMBOL(pci_release_region);
1084 EXPORT_SYMBOL(pci_request_region);
1085 EXPORT_SYMBOL(pci_set_master);
1086 EXPORT_SYMBOL(pci_set_mwi);
1087 EXPORT_SYMBOL(pci_clear_mwi);
1088 EXPORT_SYMBOL_GPL(pci_intx);
1089 EXPORT_SYMBOL(pci_set_dma_mask);
1090 EXPORT_SYMBOL(pci_set_consistent_dma_mask);
1091 EXPORT_SYMBOL(pci_assign_resource);
1092 EXPORT_SYMBOL(pci_find_parent_resource);
1094 EXPORT_SYMBOL(pci_set_power_state);
1095 EXPORT_SYMBOL(pci_save_state);
1096 EXPORT_SYMBOL(pci_restore_state);
1097 EXPORT_SYMBOL(pci_enable_wake);
1101 EXPORT_SYMBOL(isa_dma_bridge_buggy);
1102 EXPORT_SYMBOL(pci_pci_problems);