SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/pci/intr_remapping.c

   1 #include <linux/interrupt.h>
   2 #include <linux/dmar.h>
   3 #include <linux/spinlock.h>
   4 #include <linux/jiffies.h>
   5 #include <linux/pci.h>
   6 #include <linux/irq.h>
   7 #include <asm/io_apic.h>
   8 #include <asm/smp.h>
   9 #include <asm/cpu.h>
  10 #include <linux/intel-iommu.h>
  11 #include "intr_remapping.h"
  12 #include <acpi/acpi.h>
  13
  14 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
  15 static int ir_ioapic_num;
  16 int intr_remapping_enabled;
  17
  18 static int disable_intremap;
  19 static __init int setup_nointremap(char *str)
  20 {
  21         disable_intremap = 1;
  22         return 0;
  23 }
  24 early_param("nointremap", setup_nointremap);
  25
  26 struct irq_2_iommu {
  27         struct intel_iommu *iommu;
  28         u16 irte_index;
  29         u16 sub_handle;
  30         u8  irte_mask;
  31 };
  32
  33 #ifdef CONFIG_GENERIC_HARDIRQS
  34 static struct irq_2_iommu *get_one_free_irq_2_iommu(int cpu)
  35 {
  36         struct irq_2_iommu *iommu;
  37         int node;
  38
  39         node = cpu_to_node(cpu);
  40
  41         iommu = kzalloc_node(sizeof(*iommu), GFP_ATOMIC, node);
  42         printk(KERN_DEBUG "alloc irq_2_iommu on cpu %d node %d\n", cpu, node);
  43
  44         return iommu;
  45 }
  46
  47 static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
  48 {
  49         struct irq_desc *desc;
  50
  51         desc = irq_to_desc(irq);
  52
  53         if (WARN_ON_ONCE(!desc))
  54                 return NULL;
  55
  56         return desc->irq_2_iommu;
  57 }
  58
  59 static struct irq_2_iommu *irq_2_iommu_alloc_cpu(unsigned int irq, int cpu)
  60 {
  61         struct irq_desc *desc;
  62         struct irq_2_iommu *irq_iommu;
  63
  64         /*
  65          * alloc irq desc if not allocated already.
  66          */
  67         desc = irq_to_desc_alloc_cpu(irq, cpu);
  68         if (!desc) {
  69                 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
  70                 return NULL;
  71         }
  72
  73         irq_iommu = desc->irq_2_iommu;
  74
  75         if (!irq_iommu)
  76                 desc->irq_2_iommu = get_one_free_irq_2_iommu(cpu);
  77
  78         return desc->irq_2_iommu;
  79 }
  80
  81 static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
  82 {
  83         return irq_2_iommu_alloc_cpu(irq, boot_cpu_id);
  84 }
  85
  86 #else /* !CONFIG_SPARSE_IRQ */
  87
  88 static struct irq_2_iommu irq_2_iommuX[NR_IRQS];
  89
  90 static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
  91 {
  92         if (irq < nr_irqs)
  93                 return &irq_2_iommuX[irq];
  94
  95         return NULL;
  96 }
  97 static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
  98 {
  99         return irq_2_iommu(irq);
 100 }
 101 #endif
 102
 103 static DEFINE_SPINLOCK(irq_2_ir_lock);
 104
 105 static struct irq_2_iommu *valid_irq_2_iommu(unsigned int irq)
 106 {
 107         struct irq_2_iommu *irq_iommu;
 108
 109         irq_iommu = irq_2_iommu(irq);
 110
 111         if (!irq_iommu)
 112                 return NULL;
 113
 114         if (!irq_iommu->iommu)
 115                 return NULL;
 116
 117         return irq_iommu;
 118 }
 119
 120 int irq_remapped(int irq)
 121 {
 122         return valid_irq_2_iommu(irq) != NULL;
 123 }
 124
 125 int get_irte(int irq, struct irte *entry)
 126 {
 127         int index;
 128         struct irq_2_iommu *irq_iommu;
 129         unsigned long flags;
 130
 131         if (!entry)
 132                 return -1;
 133
 134         spin_lock_irqsave(&irq_2_ir_lock, flags);
 135         irq_iommu = valid_irq_2_iommu(irq);
 136         if (!irq_iommu) {
 137                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 138                 return -1;
 139         }
 140
 141         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 142         *entry = *(irq_iommu->iommu->ir_table->base + index);
 143
 144         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 145         return 0;
 146 }
 147
 148 int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
 149 {
 150         struct ir_table *table = iommu->ir_table;
 151         struct irq_2_iommu *irq_iommu;
 152         u16 index, start_index;
 153         unsigned int mask = 0;
 154         unsigned long flags;
 155         int i;
 156
 157         if (!count)
 158                 return -1;
 159
 160 #ifndef CONFIG_SPARSE_IRQ
 161         /* protect irq_2_iommu_alloc later */
 162         if (irq >= nr_irqs)
 163                 return -1;
 164 #endif
 165
 166         /*
 167          * start the IRTE search from index 0.
 168          */
 169         index = start_index = 0;
 170
 171         if (count > 1) {
 172                 count = __roundup_pow_of_two(count);
 173                 mask = ilog2(count);
 174         }
 175
 176         if (mask > ecap_max_handle_mask(iommu->ecap)) {
 177                 printk(KERN_ERR
 178                        "Requested mask %x exceeds the max invalidation handle"
 179                        " mask value %Lx\n", mask,
 180                        ecap_max_handle_mask(iommu->ecap));
 181                 return -1;
 182         }
 183
 184         spin_lock_irqsave(&irq_2_ir_lock, flags);
 185         do {
 186                 for (i = index; i < index + count; i++)
 187                         if  (table->base[i].present)
 188                                 break;
 189                 /* empty index found */
 190                 if (i == index + count)
 191                         break;
 192
 193                 index = (index + count) % INTR_REMAP_TABLE_ENTRIES;
 194
 195                 if (index == start_index) {
 196                         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 197                         printk(KERN_ERR "can't allocate an IRTE\n");
 198                         return -1;
 199                 }
 200         } while (1);
 201
 202         for (i = index; i < index + count; i++)
 203                 table->base[i].present = 1;
 204
 205         irq_iommu = irq_2_iommu_alloc(irq);
 206         if (!irq_iommu) {
 207                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 208                 printk(KERN_ERR "can't allocate irq_2_iommu\n");
 209                 return -1;
 210         }
 211
 212         irq_iommu->iommu = iommu;
 213         irq_iommu->irte_index =  index;
 214         irq_iommu->sub_handle = 0;
 215         irq_iommu->irte_mask = mask;
 216
 217         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 218
 219         return index;
 220 }
 221
 222 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
 223 {
 224         struct qi_desc desc;
 225
 226         desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
 227                    | QI_IEC_SELECTIVE;
 228         desc.high = 0;
 229
 230         return qi_submit_sync(&desc, iommu);
 231 }
 232
 233 int map_irq_to_irte_handle(int irq, u16 *sub_handle)
 234 {
 235         int index;
 236         struct irq_2_iommu *irq_iommu;
 237         unsigned long flags;
 238
 239         spin_lock_irqsave(&irq_2_ir_lock, flags);
 240         irq_iommu = valid_irq_2_iommu(irq);
 241         if (!irq_iommu) {
 242                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 243                 return -1;
 244         }
 245
 246         *sub_handle = irq_iommu->sub_handle;
 247         index = irq_iommu->irte_index;
 248         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 249         return index;
 250 }
 251
 252 int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle)
 253 {
 254         struct irq_2_iommu *irq_iommu;
 255         unsigned long flags;
 256
 257         spin_lock_irqsave(&irq_2_ir_lock, flags);
 258
 259         irq_iommu = irq_2_iommu_alloc(irq);
 260
 261         if (!irq_iommu) {
 262                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 263                 printk(KERN_ERR "can't allocate irq_2_iommu\n");
 264                 return -1;
 265         }
 266
 267         irq_iommu->iommu = iommu;
 268         irq_iommu->irte_index = index;
 269         irq_iommu->sub_handle = subhandle;
 270         irq_iommu->irte_mask = 0;
 271
 272         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 273
 274         return 0;
 275 }
 276
 277 int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index)
 278 {
 279         struct irq_2_iommu *irq_iommu;
 280         unsigned long flags;
 281
 282         spin_lock_irqsave(&irq_2_ir_lock, flags);
 283         irq_iommu = valid_irq_2_iommu(irq);
 284         if (!irq_iommu) {
 285                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 286                 return -1;
 287         }
 288
 289         irq_iommu->iommu = NULL;
 290         irq_iommu->irte_index = 0;
 291         irq_iommu->sub_handle = 0;
 292         irq_2_iommu(irq)->irte_mask = 0;
 293
 294         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 295
 296         return 0;
 297 }
 298
 299 int modify_irte(int irq, struct irte *irte_modified)
 300 {
 301         int rc;
 302         int index;
 303         struct irte *irte;
 304         struct intel_iommu *iommu;
 305         struct irq_2_iommu *irq_iommu;
 306         unsigned long flags;
 307
 308         spin_lock_irqsave(&irq_2_ir_lock, flags);
 309         irq_iommu = valid_irq_2_iommu(irq);
 310         if (!irq_iommu) {
 311                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 312                 return -1;
 313         }
 314
 315         iommu = irq_iommu->iommu;
 316
 317         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 318         irte = &iommu->ir_table->base[index];
 319
 320         set_64bit((unsigned long *)irte, irte_modified->low);
 321         __iommu_flush_cache(iommu, irte, sizeof(*irte));
 322
 323         rc = qi_flush_iec(iommu, index, 0);
 324         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 325
 326         return rc;
 327 }
 328
 329 int flush_irte(int irq)
 330 {
 331         int rc;
 332         int index;
 333         struct intel_iommu *iommu;
 334         struct irq_2_iommu *irq_iommu;
 335         unsigned long flags;
 336
 337         spin_lock_irqsave(&irq_2_ir_lock, flags);
 338         irq_iommu = valid_irq_2_iommu(irq);
 339         if (!irq_iommu) {
 340                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 341                 return -1;
 342         }
 343
 344         iommu = irq_iommu->iommu;
 345
 346         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 347
 348         rc = qi_flush_iec(iommu, index, irq_iommu->irte_mask);
 349         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 350
 351         return rc;
 352 }
 353
 354 struct intel_iommu *map_ioapic_to_ir(int apic)
 355 {
 356         int i;
 357
 358         for (i = 0; i < MAX_IO_APICS; i++)
 359                 if (ir_ioapic[i].id == apic)
 360                         return ir_ioapic[i].iommu;
 361         return NULL;
 362 }
 363
 364 struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
 365 {
 366         struct dmar_drhd_unit *drhd;
 367
 368         drhd = dmar_find_matched_drhd_unit(dev);
 369         if (!drhd)
 370                 return NULL;
 371
 372         return drhd->iommu;
 373 }
 374
 375 int free_irte(int irq)
 376 {
 377         int rc = 0;
 378         int index, i;
 379         struct irte *irte;
 380         struct intel_iommu *iommu;
 381         struct irq_2_iommu *irq_iommu;
 382         unsigned long flags;
 383
 384         spin_lock_irqsave(&irq_2_ir_lock, flags);
 385         irq_iommu = valid_irq_2_iommu(irq);
 386         if (!irq_iommu) {
 387                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 388                 return -1;
 389         }
 390
 391         iommu = irq_iommu->iommu;
 392
 393         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 394         irte = &iommu->ir_table->base[index];
 395
 396         if (!irq_iommu->sub_handle) {
 397                 for (i = 0; i < (1 << irq_iommu->irte_mask); i++)
 398                         set_64bit((unsigned long *)(irte + i), 0);
 399                 rc = qi_flush_iec(iommu, index, irq_iommu->irte_mask);
 400         }
 401
 402         irq_iommu->iommu = NULL;
 403         irq_iommu->irte_index = 0;
 404         irq_iommu->sub_handle = 0;
 405         irq_iommu->irte_mask = 0;
 406
 407         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 408
 409         return rc;
 410 }
 411
 412 static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
 413 {
 414         u64 addr;
 415         u32 cmd, sts;
 416         unsigned long flags;
 417
 418         addr = virt_to_phys((void *)iommu->ir_table->base);
 419
 420         spin_lock_irqsave(&iommu->register_lock, flags);
 421
 422         dmar_writeq(iommu->reg + DMAR_IRTA_REG,
 423                     (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
 424
 425         /* Set interrupt-remapping table pointer */
 426         cmd = iommu->gcmd | DMA_GCMD_SIRTP;
 427         iommu->gcmd |= DMA_GCMD_SIRTP;
 428         writel(cmd, iommu->reg + DMAR_GCMD_REG);
 429
 430         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 431                       readl, (sts & DMA_GSTS_IRTPS), sts);
 432         spin_unlock_irqrestore(&iommu->register_lock, flags);
 433
 434         /*
 435          * global invalidation of interrupt entry cache before enabling
 436          * interrupt-remapping.
 437          */
 438         qi_global_iec(iommu);
 439
 440         spin_lock_irqsave(&iommu->register_lock, flags);
 441
 442         /* Enable interrupt-remapping */
 443         cmd = iommu->gcmd | DMA_GCMD_IRE;
 444         iommu->gcmd |= DMA_GCMD_IRE;
 445         writel(cmd, iommu->reg + DMAR_GCMD_REG);
 446
 447         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 448                       readl, (sts & DMA_GSTS_IRES), sts);
 449
 450         spin_unlock_irqrestore(&iommu->register_lock, flags);
 451 }
 452
 453
 454 static int setup_intr_remapping(struct intel_iommu *iommu, int mode)
 455 {
 456         struct ir_table *ir_table;
 457         struct page *pages;
 458
 459         ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table),
 460                                              GFP_ATOMIC);
 461
 462         if (!iommu->ir_table)
 463                 return -ENOMEM;
 464
 465         pages = alloc_pages(GFP_ATOMIC | __GFP_ZERO, INTR_REMAP_PAGE_ORDER);
 466
 467         if (!pages) {
 468                 printk(KERN_ERR "failed to allocate pages of order %d\n",
 469                        INTR_REMAP_PAGE_ORDER);
 470                 kfree(iommu->ir_table);
 471                 return -ENOMEM;
 472         }
 473
 474         ir_table->base = page_address(pages);
 475
 476         iommu_set_intr_remapping(iommu, mode);
 477         return 0;
 478 }
 479
 480 /*
 481  * Disable Interrupt Remapping.
 482  */
 483 static void iommu_disable_intr_remapping(struct intel_iommu *iommu)
 484 {
 485         unsigned long flags;
 486         u32 sts;
 487
 488         if (!ecap_ir_support(iommu->ecap))
 489                 return;
 490
 491         /*
 492          * global invalidation of interrupt entry cache before disabling
 493          * interrupt-remapping.
 494          */
 495         qi_global_iec(iommu);
 496
 497         spin_lock_irqsave(&iommu->register_lock, flags);
 498
 499         sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
 500         if (!(sts & DMA_GSTS_IRES))
 501                 goto end;
 502
 503         iommu->gcmd &= ~DMA_GCMD_IRE;
 504         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
 505
 506         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 507                       readl, !(sts & DMA_GSTS_IRES), sts);
 508
 509 end:
 510         spin_unlock_irqrestore(&iommu->register_lock, flags);
 511 }
 512
 513 int __init intr_remapping_supported(void)
 514 {
 515         struct dmar_drhd_unit *drhd;
 516
 517         if (disable_intremap)
 518                 return 0;
 519
 520         for_each_drhd_unit(drhd) {
 521                 struct intel_iommu *iommu = drhd->iommu;
 522
 523                 if (!ecap_ir_support(iommu->ecap))
 524                         return 0;
 525         }
 526
 527         return 1;
 528 }
 529
 530 int __init enable_intr_remapping(int eim)
 531 {
 532         struct dmar_drhd_unit *drhd;
 533         int setup = 0;
 534
 535         for_each_drhd_unit(drhd) {
 536                 struct intel_iommu *iommu = drhd->iommu;
 537
 538                 /*
 539                  * If the queued invalidation is already initialized,
 540                  * shouldn't disable it.
 541                  */
 542                 if (iommu->qi)
 543                         continue;
 544
 545                 /*
 546                  * Clear previous faults.
 547                  */
 548                 dmar_fault(-1, iommu);
 549
 550                 /*
 551                  * Disable intr remapping and queued invalidation, if already
 552                  * enabled prior to OS handover.
 553                  */
 554                 iommu_disable_intr_remapping(iommu);
 555
 556                 dmar_disable_qi(iommu);
 557         }
 558
 559         /*
 560          * check for the Interrupt-remapping support
 561          */
 562         for_each_drhd_unit(drhd) {
 563                 struct intel_iommu *iommu = drhd->iommu;
 564
 565                 if (!ecap_ir_support(iommu->ecap))
 566                         continue;
 567
 568                 if (eim && !ecap_eim_support(iommu->ecap)) {
 569                         printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, "
 570                                " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
 571                         return -1;
 572                 }
 573         }
 574
 575         /*
 576          * Enable queued invalidation for all the DRHD's.
 577          */
 578         for_each_drhd_unit(drhd) {
 579                 int ret;
 580                 struct intel_iommu *iommu = drhd->iommu;
 581                 ret = dmar_enable_qi(iommu);
 582
 583                 if (ret) {
 584                         printk(KERN_ERR "DRHD %Lx: failed to enable queued, "
 585                                " invalidation, ecap %Lx, ret %d\n",
 586                                drhd->reg_base_addr, iommu->ecap, ret);
 587                         return -1;
 588                 }
 589         }
 590
 591         /*
 592          * Setup Interrupt-remapping for all the DRHD's now.
 593          */
 594         for_each_drhd_unit(drhd) {
 595                 struct intel_iommu *iommu = drhd->iommu;
 596
 597                 if (!ecap_ir_support(iommu->ecap))
 598                         continue;
 599
 600                 if (setup_intr_remapping(iommu, eim))
 601                         goto error;
 602
 603                 setup = 1;
 604         }
 605
 606         if (!setup)
 607                 goto error;
 608
 609         intr_remapping_enabled = 1;
 610
 611         return 0;
 612
 613 error:
 614         /*
 615          * handle error condition gracefully here!
 616          */
 617         return -1;
 618 }
 619
 620 static int ir_parse_ioapic_scope(struct acpi_dmar_header *header,
 621                                  struct intel_iommu *iommu)
 622 {
 623         struct acpi_dmar_hardware_unit *drhd;
 624         struct acpi_dmar_device_scope *scope;
 625         void *start, *end;
 626
 627         drhd = (struct acpi_dmar_hardware_unit *)header;
 628
 629         start = (void *)(drhd + 1);
 630         end = ((void *)drhd) + header->length;
 631
 632         while (start < end) {
 633                 scope = start;
 634                 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
 635                         if (ir_ioapic_num == MAX_IO_APICS) {
 636                                 printk(KERN_WARNING "Exceeded Max IO APICS\n");
 637                                 return -1;
 638                         }
 639
 640                         printk(KERN_INFO "IOAPIC id %d under DRHD base"
 641                                " 0x%Lx\n", scope->enumeration_id,
 642                                drhd->address);
 643
 644                         ir_ioapic[ir_ioapic_num].iommu = iommu;
 645                         ir_ioapic[ir_ioapic_num].id = scope->enumeration_id;
 646                         ir_ioapic_num++;
 647                 }
 648                 start += scope->length;
 649         }
 650
 651         return 0;
 652 }
 653
 654 /*
 655  * Finds the assocaition between IOAPIC's and its Interrupt-remapping
 656  * hardware unit.
 657  */
 658 int __init parse_ioapics_under_ir(void)
 659 {
 660         struct dmar_drhd_unit *drhd;
 661         int ir_supported = 0;
 662
 663         for_each_drhd_unit(drhd) {
 664                 struct intel_iommu *iommu = drhd->iommu;
 665
 666                 if (ecap_ir_support(iommu->ecap)) {
 667                         if (ir_parse_ioapic_scope(drhd->hdr, iommu))
 668                                 return -1;
 669
 670                         ir_supported = 1;
 671                 }
 672         }
 673
 674         if (ir_supported && ir_ioapic_num != nr_ioapics) {
 675                 printk(KERN_WARNING
 676                        "Not all IO-APIC's listed under remapping hardware\n");
 677                 return -1;
 678         }
 679
 680         return ir_supported;
 681 }
 682
 683 void disable_intr_remapping(void)
 684 {
 685         struct dmar_drhd_unit *drhd;
 686         struct intel_iommu *iommu = NULL;
 687
 688         /*
 689          * Disable Interrupt-remapping for all the DRHD's now.
 690          */
 691         for_each_iommu(iommu, drhd) {
 692                 if (!ecap_ir_support(iommu->ecap))
 693                         continue;
 694
 695                 iommu_disable_intr_remapping(iommu);
 696         }
 697 }
 698
 699 int reenable_intr_remapping(int eim)
 700 {
 701         struct dmar_drhd_unit *drhd;
 702         int setup = 0;
 703         struct intel_iommu *iommu = NULL;
 704
 705         for_each_iommu(iommu, drhd)
 706                 if (iommu->qi)
 707                         dmar_reenable_qi(iommu);
 708
 709         /*
 710          * Setup Interrupt-remapping for all the DRHD's now.
 711          */
 712         for_each_iommu(iommu, drhd) {
 713                 if (!ecap_ir_support(iommu->ecap))
 714                         continue;
 715
 716                 /* Set up interrupt remapping for iommu.*/
 717                 iommu_set_intr_remapping(iommu, eim);
 718                 setup = 1;
 719         }
 720
 721         if (!setup)
 722                 goto error;
 723
 724         return 0;
 725
 726 error:
 727         /*
 728          * handle error condition gracefully here!
 729          */
 730         return -1;
 731 }
 732