SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/pci/intr_remapping.c

   1 #include <linux/interrupt.h>
   2 #include <linux/dmar.h>
   3 #include <linux/spinlock.h>
   4 #include <linux/jiffies.h>
   5 #include <linux/pci.h>
   6 #include <linux/irq.h>
   7 #include <asm/io_apic.h>
   8 #include <asm/smp.h>
   9 #include <asm/cpu.h>
  10 #include <linux/intel-iommu.h>
  11 #include "intr_remapping.h"
  12 #include <acpi/acpi.h>
  13
  14 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
  15 static int ir_ioapic_num;
  16 int intr_remapping_enabled;
  17
  18 struct irq_2_iommu {
  19         struct intel_iommu *iommu;
  20         u16 irte_index;
  21         u16 sub_handle;
  22         u8  irte_mask;
  23 };
  24
  25 #ifdef CONFIG_GENERIC_HARDIRQS
  26 static struct irq_2_iommu *get_one_free_irq_2_iommu(int node)
  27 {
  28         struct irq_2_iommu *iommu;
  29
  30         iommu = kzalloc_node(sizeof(*iommu), GFP_ATOMIC, node);
  31         printk(KERN_DEBUG "alloc irq_2_iommu on node %d\n", node);
  32
  33         return iommu;
  34 }
  35
  36 static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
  37 {
  38         struct irq_desc *desc;
  39
  40         desc = irq_to_desc(irq);
  41
  42         if (WARN_ON_ONCE(!desc))
  43                 return NULL;
  44
  45         return desc->irq_2_iommu;
  46 }
  47
  48 static struct irq_2_iommu *irq_2_iommu_alloc_node(unsigned int irq, int node)
  49 {
  50         struct irq_desc *desc;
  51         struct irq_2_iommu *irq_iommu;
  52
  53         /*
  54          * alloc irq desc if not allocated already.
  55          */
  56         desc = irq_to_desc_alloc_node(irq, node);
  57         if (!desc) {
  58                 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
  59                 return NULL;
  60         }
  61
  62         irq_iommu = desc->irq_2_iommu;
  63
  64         if (!irq_iommu)
  65                 desc->irq_2_iommu = get_one_free_irq_2_iommu(node);
  66
  67         return desc->irq_2_iommu;
  68 }
  69
  70 static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
  71 {
  72         return irq_2_iommu_alloc_node(irq, cpu_to_node(boot_cpu_id));
  73 }
  74
  75 #else /* !CONFIG_SPARSE_IRQ */
  76
  77 static struct irq_2_iommu irq_2_iommuX[NR_IRQS];
  78
  79 static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
  80 {
  81         if (irq < nr_irqs)
  82                 return &irq_2_iommuX[irq];
  83
  84         return NULL;
  85 }
  86 static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
  87 {
  88         return irq_2_iommu(irq);
  89 }
  90 #endif
  91
  92 static DEFINE_SPINLOCK(irq_2_ir_lock);
  93
  94 static struct irq_2_iommu *valid_irq_2_iommu(unsigned int irq)
  95 {
  96         struct irq_2_iommu *irq_iommu;
  97
  98         irq_iommu = irq_2_iommu(irq);
  99
 100         if (!irq_iommu)
 101                 return NULL;
 102
 103         if (!irq_iommu->iommu)
 104                 return NULL;
 105
 106         return irq_iommu;
 107 }
 108
 109 int irq_remapped(int irq)
 110 {
 111         return valid_irq_2_iommu(irq) != NULL;
 112 }
 113
 114 int get_irte(int irq, struct irte *entry)
 115 {
 116         int index;
 117         struct irq_2_iommu *irq_iommu;
 118         unsigned long flags;
 119
 120         if (!entry)
 121                 return -1;
 122
 123         spin_lock_irqsave(&irq_2_ir_lock, flags);
 124         irq_iommu = valid_irq_2_iommu(irq);
 125         if (!irq_iommu) {
 126                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 127                 return -1;
 128         }
 129
 130         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 131         *entry = *(irq_iommu->iommu->ir_table->base + index);
 132
 133         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 134         return 0;
 135 }
 136
 137 int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
 138 {
 139         struct ir_table *table = iommu->ir_table;
 140         struct irq_2_iommu *irq_iommu;
 141         u16 index, start_index;
 142         unsigned int mask = 0;
 143         unsigned long flags;
 144         int i;
 145
 146         if (!count)
 147                 return -1;
 148
 149 #ifndef CONFIG_SPARSE_IRQ
 150         /* protect irq_2_iommu_alloc later */
 151         if (irq >= nr_irqs)
 152                 return -1;
 153 #endif
 154
 155         /*
 156          * start the IRTE search from index 0.
 157          */
 158         index = start_index = 0;
 159
 160         if (count > 1) {
 161                 count = __roundup_pow_of_two(count);
 162                 mask = ilog2(count);
 163         }
 164
 165         if (mask > ecap_max_handle_mask(iommu->ecap)) {
 166                 printk(KERN_ERR
 167                        "Requested mask %x exceeds the max invalidation handle"
 168                        " mask value %Lx\n", mask,
 169                        ecap_max_handle_mask(iommu->ecap));
 170                 return -1;
 171         }
 172
 173         spin_lock_irqsave(&irq_2_ir_lock, flags);
 174         do {
 175                 for (i = index; i < index + count; i++)
 176                         if  (table->base[i].present)
 177                                 break;
 178                 /* empty index found */
 179                 if (i == index + count)
 180                         break;
 181
 182                 index = (index + count) % INTR_REMAP_TABLE_ENTRIES;
 183
 184                 if (index == start_index) {
 185                         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 186                         printk(KERN_ERR "can't allocate an IRTE\n");
 187                         return -1;
 188                 }
 189         } while (1);
 190
 191         for (i = index; i < index + count; i++)
 192                 table->base[i].present = 1;
 193
 194         irq_iommu = irq_2_iommu_alloc(irq);
 195         if (!irq_iommu) {
 196                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 197                 printk(KERN_ERR "can't allocate irq_2_iommu\n");
 198                 return -1;
 199         }
 200
 201         irq_iommu->iommu = iommu;
 202         irq_iommu->irte_index =  index;
 203         irq_iommu->sub_handle = 0;
 204         irq_iommu->irte_mask = mask;
 205
 206         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 207
 208         return index;
 209 }
 210
 211 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
 212 {
 213         struct qi_desc desc;
 214
 215         desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
 216                    | QI_IEC_SELECTIVE;
 217         desc.high = 0;
 218
 219         return qi_submit_sync(&desc, iommu);
 220 }
 221
 222 int map_irq_to_irte_handle(int irq, u16 *sub_handle)
 223 {
 224         int index;
 225         struct irq_2_iommu *irq_iommu;
 226         unsigned long flags;
 227
 228         spin_lock_irqsave(&irq_2_ir_lock, flags);
 229         irq_iommu = valid_irq_2_iommu(irq);
 230         if (!irq_iommu) {
 231                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 232                 return -1;
 233         }
 234
 235         *sub_handle = irq_iommu->sub_handle;
 236         index = irq_iommu->irte_index;
 237         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 238         return index;
 239 }
 240
 241 int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle)
 242 {
 243         struct irq_2_iommu *irq_iommu;
 244         unsigned long flags;
 245
 246         spin_lock_irqsave(&irq_2_ir_lock, flags);
 247
 248         irq_iommu = irq_2_iommu_alloc(irq);
 249
 250         if (!irq_iommu) {
 251                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 252                 printk(KERN_ERR "can't allocate irq_2_iommu\n");
 253                 return -1;
 254         }
 255
 256         irq_iommu->iommu = iommu;
 257         irq_iommu->irte_index = index;
 258         irq_iommu->sub_handle = subhandle;
 259         irq_iommu->irte_mask = 0;
 260
 261         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 262
 263         return 0;
 264 }
 265
 266 int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index)
 267 {
 268         struct irq_2_iommu *irq_iommu;
 269         unsigned long flags;
 270
 271         spin_lock_irqsave(&irq_2_ir_lock, flags);
 272         irq_iommu = valid_irq_2_iommu(irq);
 273         if (!irq_iommu) {
 274                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 275                 return -1;
 276         }
 277
 278         irq_iommu->iommu = NULL;
 279         irq_iommu->irte_index = 0;
 280         irq_iommu->sub_handle = 0;
 281         irq_2_iommu(irq)->irte_mask = 0;
 282
 283         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 284
 285         return 0;
 286 }
 287
 288 int modify_irte(int irq, struct irte *irte_modified)
 289 {
 290         int rc;
 291         int index;
 292         struct irte *irte;
 293         struct intel_iommu *iommu;
 294         struct irq_2_iommu *irq_iommu;
 295         unsigned long flags;
 296
 297         spin_lock_irqsave(&irq_2_ir_lock, flags);
 298         irq_iommu = valid_irq_2_iommu(irq);
 299         if (!irq_iommu) {
 300                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 301                 return -1;
 302         }
 303
 304         iommu = irq_iommu->iommu;
 305
 306         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 307         irte = &iommu->ir_table->base[index];
 308
 309         set_64bit((unsigned long *)irte, irte_modified->low);
 310         __iommu_flush_cache(iommu, irte, sizeof(*irte));
 311
 312         rc = qi_flush_iec(iommu, index, 0);
 313         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 314
 315         return rc;
 316 }
 317
 318 int flush_irte(int irq)
 319 {
 320         int rc;
 321         int index;
 322         struct intel_iommu *iommu;
 323         struct irq_2_iommu *irq_iommu;
 324         unsigned long flags;
 325
 326         spin_lock_irqsave(&irq_2_ir_lock, flags);
 327         irq_iommu = valid_irq_2_iommu(irq);
 328         if (!irq_iommu) {
 329                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 330                 return -1;
 331         }
 332
 333         iommu = irq_iommu->iommu;
 334
 335         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 336
 337         rc = qi_flush_iec(iommu, index, irq_iommu->irte_mask);
 338         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 339
 340         return rc;
 341 }
 342
 343 struct intel_iommu *map_ioapic_to_ir(int apic)
 344 {
 345         int i;
 346
 347         for (i = 0; i < MAX_IO_APICS; i++)
 348                 if (ir_ioapic[i].id == apic)
 349                         return ir_ioapic[i].iommu;
 350         return NULL;
 351 }
 352
 353 struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
 354 {
 355         struct dmar_drhd_unit *drhd;
 356
 357         drhd = dmar_find_matched_drhd_unit(dev);
 358         if (!drhd)
 359                 return NULL;
 360
 361         return drhd->iommu;
 362 }
 363
 364 int free_irte(int irq)
 365 {
 366         int rc = 0;
 367         int index, i;
 368         struct irte *irte;
 369         struct intel_iommu *iommu;
 370         struct irq_2_iommu *irq_iommu;
 371         unsigned long flags;
 372
 373         spin_lock_irqsave(&irq_2_ir_lock, flags);
 374         irq_iommu = valid_irq_2_iommu(irq);
 375         if (!irq_iommu) {
 376                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 377                 return -1;
 378         }
 379
 380         iommu = irq_iommu->iommu;
 381
 382         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 383         irte = &iommu->ir_table->base[index];
 384
 385         if (!irq_iommu->sub_handle) {
 386                 for (i = 0; i < (1 << irq_iommu->irte_mask); i++)
 387                         set_64bit((unsigned long *)(irte + i), 0);
 388                 rc = qi_flush_iec(iommu, index, irq_iommu->irte_mask);
 389         }
 390
 391         irq_iommu->iommu = NULL;
 392         irq_iommu->irte_index = 0;
 393         irq_iommu->sub_handle = 0;
 394         irq_iommu->irte_mask = 0;
 395
 396         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 397
 398         return rc;
 399 }
 400
 401 static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
 402 {
 403         u64 addr;
 404         u32 cmd, sts;
 405         unsigned long flags;
 406
 407         addr = virt_to_phys((void *)iommu->ir_table->base);
 408
 409         spin_lock_irqsave(&iommu->register_lock, flags);
 410
 411         dmar_writeq(iommu->reg + DMAR_IRTA_REG,
 412                     (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
 413
 414         /* Set interrupt-remapping table pointer */
 415         cmd = iommu->gcmd | DMA_GCMD_SIRTP;
 416         iommu->gcmd |= DMA_GCMD_SIRTP;
 417         writel(cmd, iommu->reg + DMAR_GCMD_REG);
 418
 419         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 420                       readl, (sts & DMA_GSTS_IRTPS), sts);
 421         spin_unlock_irqrestore(&iommu->register_lock, flags);
 422
 423         if (mode == 0) {
 424                 spin_lock_irqsave(&iommu->register_lock, flags);
 425
 426                 /* enable comaptiblity format interrupt pass through */
 427                 cmd = iommu->gcmd | DMA_GCMD_CFI;
 428                 iommu->gcmd |= DMA_GCMD_CFI;
 429                 writel(cmd, iommu->reg + DMAR_GCMD_REG);
 430
 431                 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 432                               readl, (sts & DMA_GSTS_CFIS), sts);
 433
 434                 spin_unlock_irqrestore(&iommu->register_lock, flags);
 435         }
 436
 437         /*
 438          * global invalidation of interrupt entry cache before enabling
 439          * interrupt-remapping.
 440          */
 441         qi_global_iec(iommu);
 442
 443         spin_lock_irqsave(&iommu->register_lock, flags);
 444
 445         /* Enable interrupt-remapping */
 446         cmd = iommu->gcmd | DMA_GCMD_IRE;
 447         iommu->gcmd |= DMA_GCMD_IRE;
 448         writel(cmd, iommu->reg + DMAR_GCMD_REG);
 449
 450         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 451                       readl, (sts & DMA_GSTS_IRES), sts);
 452
 453         spin_unlock_irqrestore(&iommu->register_lock, flags);
 454 }
 455
 456
 457 static int setup_intr_remapping(struct intel_iommu *iommu, int mode)
 458 {
 459         struct ir_table *ir_table;
 460         struct page *pages;
 461
 462         ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table),
 463                                              GFP_ATOMIC);
 464
 465         if (!iommu->ir_table)
 466                 return -ENOMEM;
 467
 468         pages = alloc_pages(GFP_ATOMIC | __GFP_ZERO, INTR_REMAP_PAGE_ORDER);
 469
 470         if (!pages) {
 471                 printk(KERN_ERR "failed to allocate pages of order %d\n",
 472                        INTR_REMAP_PAGE_ORDER);
 473                 kfree(iommu->ir_table);
 474                 return -ENOMEM;
 475         }
 476
 477         ir_table->base = page_address(pages);
 478
 479         iommu_set_intr_remapping(iommu, mode);
 480         return 0;
 481 }
 482
 483 /*
 484  * Disable Interrupt Remapping.
 485  */
 486 static void iommu_disable_intr_remapping(struct intel_iommu *iommu)
 487 {
 488         unsigned long flags;
 489         u32 sts;
 490
 491         if (!ecap_ir_support(iommu->ecap))
 492                 return;
 493
 494         /*
 495          * global invalidation of interrupt entry cache before disabling
 496          * interrupt-remapping.
 497          */
 498         qi_global_iec(iommu);
 499
 500         spin_lock_irqsave(&iommu->register_lock, flags);
 501
 502         sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
 503         if (!(sts & DMA_GSTS_IRES))
 504                 goto end;
 505
 506         iommu->gcmd &= ~DMA_GCMD_IRE;
 507         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
 508
 509         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 510                       readl, !(sts & DMA_GSTS_IRES), sts);
 511
 512 end:
 513         spin_unlock_irqrestore(&iommu->register_lock, flags);
 514 }
 515
 516 int __init enable_intr_remapping(int eim)
 517 {
 518         struct dmar_drhd_unit *drhd;
 519         int setup = 0;
 520
 521         for_each_drhd_unit(drhd) {
 522                 struct intel_iommu *iommu = drhd->iommu;
 523
 524                 /*
 525                  * If the queued invalidation is already initialized,
 526                  * shouldn't disable it.
 527                  */
 528                 if (iommu->qi)
 529                         continue;
 530
 531                 /*
 532                  * Clear previous faults.
 533                  */
 534                 dmar_fault(-1, iommu);
 535
 536                 /*
 537                  * Disable intr remapping and queued invalidation, if already
 538                  * enabled prior to OS handover.
 539                  */
 540                 iommu_disable_intr_remapping(iommu);
 541
 542                 dmar_disable_qi(iommu);
 543         }
 544
 545         /*
 546          * check for the Interrupt-remapping support
 547          */
 548         for_each_drhd_unit(drhd) {
 549                 struct intel_iommu *iommu = drhd->iommu;
 550
 551                 if (!ecap_ir_support(iommu->ecap))
 552                         continue;
 553
 554                 if (eim && !ecap_eim_support(iommu->ecap)) {
 555                         printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, "
 556                                " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
 557                         return -1;
 558                 }
 559         }
 560
 561         /*
 562          * Enable queued invalidation for all the DRHD's.
 563          */
 564         for_each_drhd_unit(drhd) {
 565                 int ret;
 566                 struct intel_iommu *iommu = drhd->iommu;
 567                 ret = dmar_enable_qi(iommu);
 568
 569                 if (ret) {
 570                         printk(KERN_ERR "DRHD %Lx: failed to enable queued, "
 571                                " invalidation, ecap %Lx, ret %d\n",
 572                                drhd->reg_base_addr, iommu->ecap, ret);
 573                         return -1;
 574                 }
 575         }
 576
 577         /*
 578          * Setup Interrupt-remapping for all the DRHD's now.
 579          */
 580         for_each_drhd_unit(drhd) {
 581                 struct intel_iommu *iommu = drhd->iommu;
 582
 583                 if (!ecap_ir_support(iommu->ecap))
 584                         continue;
 585
 586                 if (setup_intr_remapping(iommu, eim))
 587                         goto error;
 588
 589                 setup = 1;
 590         }
 591
 592         if (!setup)
 593                 goto error;
 594
 595         intr_remapping_enabled = 1;
 596
 597         return 0;
 598
 599 error:
 600         /*
 601          * handle error condition gracefully here!
 602          */
 603         return -1;
 604 }
 605
 606 static int ir_parse_ioapic_scope(struct acpi_dmar_header *header,
 607                                  struct intel_iommu *iommu)
 608 {
 609         struct acpi_dmar_hardware_unit *drhd;
 610         struct acpi_dmar_device_scope *scope;
 611         void *start, *end;
 612
 613         drhd = (struct acpi_dmar_hardware_unit *)header;
 614
 615         start = (void *)(drhd + 1);
 616         end = ((void *)drhd) + header->length;
 617
 618         while (start < end) {
 619                 scope = start;
 620                 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
 621                         if (ir_ioapic_num == MAX_IO_APICS) {
 622                                 printk(KERN_WARNING "Exceeded Max IO APICS\n");
 623                                 return -1;
 624                         }
 625
 626                         printk(KERN_INFO "IOAPIC id %d under DRHD base"
 627                                " 0x%Lx\n", scope->enumeration_id,
 628                                drhd->address);
 629
 630                         ir_ioapic[ir_ioapic_num].iommu = iommu;
 631                         ir_ioapic[ir_ioapic_num].id = scope->enumeration_id;
 632                         ir_ioapic_num++;
 633                 }
 634                 start += scope->length;
 635         }
 636
 637         return 0;
 638 }
 639
 640 /*
 641  * Finds the assocaition between IOAPIC's and its Interrupt-remapping
 642  * hardware unit.
 643  */
 644 int __init parse_ioapics_under_ir(void)
 645 {
 646         struct dmar_drhd_unit *drhd;
 647         int ir_supported = 0;
 648
 649         for_each_drhd_unit(drhd) {
 650                 struct intel_iommu *iommu = drhd->iommu;
 651
 652                 if (ecap_ir_support(iommu->ecap)) {
 653                         if (ir_parse_ioapic_scope(drhd->hdr, iommu))
 654                                 return -1;
 655
 656                         ir_supported = 1;
 657                 }
 658         }
 659
 660         if (ir_supported && ir_ioapic_num != nr_ioapics) {
 661                 printk(KERN_WARNING
 662                        "Not all IO-APIC's listed under remapping hardware\n");
 663                 return -1;
 664         }
 665
 666         return ir_supported;
 667 }
 668
 669 void disable_intr_remapping(void)
 670 {
 671         struct dmar_drhd_unit *drhd;
 672         struct intel_iommu *iommu = NULL;
 673
 674         /*
 675          * Disable Interrupt-remapping for all the DRHD's now.
 676          */
 677         for_each_iommu(iommu, drhd) {
 678                 if (!ecap_ir_support(iommu->ecap))
 679                         continue;
 680
 681                 iommu_disable_intr_remapping(iommu);
 682         }
 683 }
 684
 685 int reenable_intr_remapping(int eim)
 686 {
 687         struct dmar_drhd_unit *drhd;
 688         int setup = 0;
 689         struct intel_iommu *iommu = NULL;
 690
 691         for_each_iommu(iommu, drhd)
 692                 if (iommu->qi)
 693                         dmar_reenable_qi(iommu);
 694
 695         /*
 696          * Setup Interrupt-remapping for all the DRHD's now.
 697          */
 698         for_each_iommu(iommu, drhd) {
 699                 if (!ecap_ir_support(iommu->ecap))
 700                         continue;
 701
 702                 /* Set up interrupt remapping for iommu.*/
 703                 iommu_set_intr_remapping(iommu, eim);
 704                 setup = 1;
 705         }
 706
 707         if (!setup)
 708                 goto error;
 709
 710         return 0;
 711
 712 error:
 713         /*
 714          * handle error condition gracefully here!
 715          */
 716         return -1;
 717 }
 718