2 * Copyright (c) 2006, Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Shaohua Li <shaohua.li@intel.com>
20 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
21 * Author: Fenghua Yu <fenghua.yu@intel.com>
24 #include <linux/init.h>
25 #include <linux/bitmap.h>
26 #include <linux/debugfs.h>
27 #include <linux/slab.h>
28 #include <linux/irq.h>
29 #include <linux/interrupt.h>
30 #include <linux/spinlock.h>
31 #include <linux/pci.h>
32 #include <linux/dmar.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/mempool.h>
35 #include <linux/timer.h>
36 #include <linux/iova.h>
37 #include <linux/iommu.h>
38 #include <linux/intel-iommu.h>
39 #include <linux/sysdev.h>
40 #include <asm/cacheflush.h>
41 #include <asm/iommu.h>
44 #define ROOT_SIZE VTD_PAGE_SIZE
45 #define CONTEXT_SIZE VTD_PAGE_SIZE
47 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
48 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
50 #define IOAPIC_RANGE_START (0xfee00000)
51 #define IOAPIC_RANGE_END (0xfeefffff)
52 #define IOVA_START_ADDR (0x1000)
54 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
56 #define MAX_AGAW_WIDTH 64
58 #define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1)
60 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
61 #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
62 #define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
64 #ifndef PHYSICAL_PAGE_MASK
65 #define PHYSICAL_PAGE_MASK PAGE_MASK
68 /* VT-d pages must always be _smaller_ than MM pages. Otherwise things
69 are never going to work. */
70 static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
72 return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
75 static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
77 return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
79 static inline unsigned long page_to_dma_pfn(struct page *pg)
81 return mm_to_dma_pfn(page_to_pfn(pg));
83 static inline unsigned long virt_to_dma_pfn(void *p)
85 return page_to_dma_pfn(virt_to_page(p));
88 /* global iommu list, set NULL for ignored DMAR units */
89 static struct intel_iommu **g_iommus;
91 static int rwbf_quirk;
96 * 12-63: Context Ptr (12 - (haw-1))
103 #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
104 static inline bool root_present(struct root_entry *root)
106 return (root->val & 1);
108 static inline void set_root_present(struct root_entry *root)
112 static inline void set_root_value(struct root_entry *root, unsigned long value)
114 root->val |= value & VTD_PAGE_MASK;
117 static inline struct context_entry *
118 get_context_addr_from_root(struct root_entry *root)
120 return (struct context_entry *)
121 (root_present(root)?phys_to_virt(
122 root->val & VTD_PAGE_MASK) :
129 * 1: fault processing disable
130 * 2-3: translation type
131 * 12-63: address space root
137 struct context_entry {
142 static inline bool context_present(struct context_entry *context)
144 return (context->lo & 1);
146 static inline void context_set_present(struct context_entry *context)
151 static inline void context_set_fault_enable(struct context_entry *context)
153 context->lo &= (((u64)-1) << 2) | 1;
156 static inline void context_set_translation_type(struct context_entry *context,
159 context->lo &= (((u64)-1) << 4) | 3;
160 context->lo |= (value & 3) << 2;
163 static inline void context_set_address_root(struct context_entry *context,
166 context->lo |= value & VTD_PAGE_MASK;
169 static inline void context_set_address_width(struct context_entry *context,
172 context->hi |= value & 7;
175 static inline void context_set_domain_id(struct context_entry *context,
178 context->hi |= (value & ((1 << 16) - 1)) << 8;
181 static inline void context_clear_entry(struct context_entry *context)
194 * 12-63: Host physcial address
200 static inline void dma_clear_pte(struct dma_pte *pte)
205 static inline void dma_set_pte_readable(struct dma_pte *pte)
207 pte->val |= DMA_PTE_READ;
210 static inline void dma_set_pte_writable(struct dma_pte *pte)
212 pte->val |= DMA_PTE_WRITE;
215 static inline void dma_set_pte_snp(struct dma_pte *pte)
217 pte->val |= DMA_PTE_SNP;
220 static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
222 pte->val = (pte->val & ~3) | (prot & 3);
225 static inline u64 dma_pte_addr(struct dma_pte *pte)
227 return (pte->val & VTD_PAGE_MASK);
230 static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn)
232 pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT;
235 static inline bool dma_pte_present(struct dma_pte *pte)
237 return (pte->val & 3) != 0;
241 * This domain is a statically identity mapping domain.
242 * 1. This domain creats a static 1:1 mapping to all usable memory.
243 * 2. It maps to each iommu if successful.
244 * 3. Each iommu mapps to this domain if successful.
246 struct dmar_domain *si_domain;
248 /* devices under the same p2p bridge are owned in one domain */
249 #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
251 /* domain represents a virtual machine, more than one devices
252 * across iommus may be owned in one domain, e.g. kvm guest.
254 #define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1)
256 /* si_domain contains mulitple devices */
257 #define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2)
260 int id; /* domain id */
261 unsigned long iommu_bmp; /* bitmap of iommus this domain uses*/
263 struct list_head devices; /* all devices' list */
264 struct iova_domain iovad; /* iova's that belong to this domain */
266 struct dma_pte *pgd; /* virtual address */
267 spinlock_t mapping_lock; /* page table lock */
268 int gaw; /* max guest address width */
270 /* adjusted guest address width, 0 is level 2 30-bit */
273 int flags; /* flags to find out type of domain */
275 int iommu_coherency;/* indicate coherency of iommu access */
276 int iommu_snooping; /* indicate snooping control feature*/
277 int iommu_count; /* reference count of iommu */
278 spinlock_t iommu_lock; /* protect iommu set in domain */
279 u64 max_addr; /* maximum mapped address */
282 /* PCI domain-device relationship */
283 struct device_domain_info {
284 struct list_head link; /* link to domain siblings */
285 struct list_head global; /* link to global list */
286 int segment; /* PCI domain */
287 u8 bus; /* PCI bus number */
288 u8 devfn; /* PCI devfn number */
289 struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
290 struct intel_iommu *iommu; /* IOMMU used by this device */
291 struct dmar_domain *domain; /* pointer to domain */
294 static void flush_unmaps_timeout(unsigned long data);
296 DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
298 #define HIGH_WATER_MARK 250
299 struct deferred_flush_tables {
301 struct iova *iova[HIGH_WATER_MARK];
302 struct dmar_domain *domain[HIGH_WATER_MARK];
305 static struct deferred_flush_tables *deferred_flush;
307 /* bitmap for indexing intel_iommus */
308 static int g_num_of_iommus;
310 static DEFINE_SPINLOCK(async_umap_flush_lock);
311 static LIST_HEAD(unmaps_to_do);
314 static long list_size;
316 static void domain_remove_dev_info(struct dmar_domain *domain);
318 #ifdef CONFIG_DMAR_DEFAULT_ON
319 int dmar_disabled = 0;
321 int dmar_disabled = 1;
322 #endif /*CONFIG_DMAR_DEFAULT_ON*/
324 static int __initdata dmar_map_gfx = 1;
325 static int dmar_forcedac;
326 static int intel_iommu_strict;
328 #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
329 static DEFINE_SPINLOCK(device_domain_lock);
330 static LIST_HEAD(device_domain_list);
332 static struct iommu_ops intel_iommu_ops;
334 static int __init intel_iommu_setup(char *str)
339 if (!strncmp(str, "on", 2)) {
341 printk(KERN_INFO "Intel-IOMMU: enabled\n");
342 } else if (!strncmp(str, "off", 3)) {
344 printk(KERN_INFO "Intel-IOMMU: disabled\n");
345 } else if (!strncmp(str, "igfx_off", 8)) {
348 "Intel-IOMMU: disable GFX device mapping\n");
349 } else if (!strncmp(str, "forcedac", 8)) {
351 "Intel-IOMMU: Forcing DAC for PCI devices\n");
353 } else if (!strncmp(str, "strict", 6)) {
355 "Intel-IOMMU: disable batched IOTLB flush\n");
356 intel_iommu_strict = 1;
359 str += strcspn(str, ",");
365 __setup("intel_iommu=", intel_iommu_setup);
367 static struct kmem_cache *iommu_domain_cache;
368 static struct kmem_cache *iommu_devinfo_cache;
369 static struct kmem_cache *iommu_iova_cache;
371 static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep)
376 /* trying to avoid low memory issues */
377 flags = current->flags & PF_MEMALLOC;
378 current->flags |= PF_MEMALLOC;
379 vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC);
380 current->flags &= (~PF_MEMALLOC | flags);
385 static inline void *alloc_pgtable_page(void)
390 /* trying to avoid low memory issues */
391 flags = current->flags & PF_MEMALLOC;
392 current->flags |= PF_MEMALLOC;
393 vaddr = (void *)get_zeroed_page(GFP_ATOMIC);
394 current->flags &= (~PF_MEMALLOC | flags);
398 static inline void free_pgtable_page(void *vaddr)
400 free_page((unsigned long)vaddr);
403 static inline void *alloc_domain_mem(void)
405 return iommu_kmem_cache_alloc(iommu_domain_cache);
408 static void free_domain_mem(void *vaddr)
410 kmem_cache_free(iommu_domain_cache, vaddr);
413 static inline void * alloc_devinfo_mem(void)
415 return iommu_kmem_cache_alloc(iommu_devinfo_cache);
418 static inline void free_devinfo_mem(void *vaddr)
420 kmem_cache_free(iommu_devinfo_cache, vaddr);
423 struct iova *alloc_iova_mem(void)
425 return iommu_kmem_cache_alloc(iommu_iova_cache);
428 void free_iova_mem(struct iova *iova)
430 kmem_cache_free(iommu_iova_cache, iova);
434 static inline int width_to_agaw(int width);
436 static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
441 sagaw = cap_sagaw(iommu->cap);
442 for (agaw = width_to_agaw(max_gaw);
444 if (test_bit(agaw, &sagaw))
452 * Calculate max SAGAW for each iommu.
454 int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
456 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
460 * calculate agaw for each iommu.
461 * "SAGAW" may be different across iommus, use a default agaw, and
462 * get a supported less agaw for iommus that don't support the default agaw.
464 int iommu_calculate_agaw(struct intel_iommu *iommu)
466 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
469 /* This functionin only returns single iommu in a domain */
470 static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
474 /* si_domain and vm domain should not get here. */
475 BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
476 BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
478 iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
479 if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
482 return g_iommus[iommu_id];
485 static void domain_update_iommu_coherency(struct dmar_domain *domain)
489 domain->iommu_coherency = 1;
491 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
492 for (; i < g_num_of_iommus; ) {
493 if (!ecap_coherent(g_iommus[i]->ecap)) {
494 domain->iommu_coherency = 0;
497 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
501 static void domain_update_iommu_snooping(struct dmar_domain *domain)
505 domain->iommu_snooping = 1;
507 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
508 for (; i < g_num_of_iommus; ) {
509 if (!ecap_sc_support(g_iommus[i]->ecap)) {
510 domain->iommu_snooping = 0;
513 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
517 /* Some capabilities may be different across iommus */
518 static void domain_update_iommu_cap(struct dmar_domain *domain)
520 domain_update_iommu_coherency(domain);
521 domain_update_iommu_snooping(domain);
524 static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
526 struct dmar_drhd_unit *drhd = NULL;
529 for_each_drhd_unit(drhd) {
532 if (segment != drhd->segment)
535 for (i = 0; i < drhd->devices_cnt; i++) {
536 if (drhd->devices[i] &&
537 drhd->devices[i]->bus->number == bus &&
538 drhd->devices[i]->devfn == devfn)
540 if (drhd->devices[i] &&
541 drhd->devices[i]->subordinate &&
542 drhd->devices[i]->subordinate->number <= bus &&
543 drhd->devices[i]->subordinate->subordinate >= bus)
547 if (drhd->include_all)
554 static void domain_flush_cache(struct dmar_domain *domain,
555 void *addr, int size)
557 if (!domain->iommu_coherency)
558 clflush_cache_range(addr, size);
561 /* Gets context entry for a given bus and devfn */
562 static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
565 struct root_entry *root;
566 struct context_entry *context;
567 unsigned long phy_addr;
570 spin_lock_irqsave(&iommu->lock, flags);
571 root = &iommu->root_entry[bus];
572 context = get_context_addr_from_root(root);
574 context = (struct context_entry *)alloc_pgtable_page();
576 spin_unlock_irqrestore(&iommu->lock, flags);
579 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
580 phy_addr = virt_to_phys((void *)context);
581 set_root_value(root, phy_addr);
582 set_root_present(root);
583 __iommu_flush_cache(iommu, root, sizeof(*root));
585 spin_unlock_irqrestore(&iommu->lock, flags);
586 return &context[devfn];
589 static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
591 struct root_entry *root;
592 struct context_entry *context;
596 spin_lock_irqsave(&iommu->lock, flags);
597 root = &iommu->root_entry[bus];
598 context = get_context_addr_from_root(root);
603 ret = context_present(&context[devfn]);
605 spin_unlock_irqrestore(&iommu->lock, flags);
609 static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
611 struct root_entry *root;
612 struct context_entry *context;
615 spin_lock_irqsave(&iommu->lock, flags);
616 root = &iommu->root_entry[bus];
617 context = get_context_addr_from_root(root);
619 context_clear_entry(&context[devfn]);
620 __iommu_flush_cache(iommu, &context[devfn], \
623 spin_unlock_irqrestore(&iommu->lock, flags);
626 static void free_context_table(struct intel_iommu *iommu)
628 struct root_entry *root;
631 struct context_entry *context;
633 spin_lock_irqsave(&iommu->lock, flags);
634 if (!iommu->root_entry) {
637 for (i = 0; i < ROOT_ENTRY_NR; i++) {
638 root = &iommu->root_entry[i];
639 context = get_context_addr_from_root(root);
641 free_pgtable_page(context);
643 free_pgtable_page(iommu->root_entry);
644 iommu->root_entry = NULL;
646 spin_unlock_irqrestore(&iommu->lock, flags);
649 /* page table handling */
650 #define LEVEL_STRIDE (9)
651 #define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
653 static inline int agaw_to_level(int agaw)
658 static inline int agaw_to_width(int agaw)
660 return 30 + agaw * LEVEL_STRIDE;
664 static inline int width_to_agaw(int width)
666 return (width - 30) / LEVEL_STRIDE;
669 static inline unsigned int level_to_offset_bits(int level)
671 return (12 + (level - 1) * LEVEL_STRIDE);
674 static inline int address_level_offset(u64 addr, int level)
676 return ((addr >> level_to_offset_bits(level)) & LEVEL_MASK);
679 static inline u64 level_mask(int level)
681 return ((u64)-1 << level_to_offset_bits(level));
684 static inline u64 level_size(int level)
686 return ((u64)1 << level_to_offset_bits(level));
689 static inline u64 align_to_level(u64 addr, int level)
691 return ((addr + level_size(level) - 1) & level_mask(level));
694 static struct dma_pte * addr_to_dma_pte(struct dmar_domain *domain, u64 addr)
696 int addr_width = agaw_to_width(domain->agaw);
697 struct dma_pte *parent, *pte = NULL;
698 int level = agaw_to_level(domain->agaw);
702 BUG_ON(!domain->pgd);
704 addr &= (((u64)1) << addr_width) - 1;
705 parent = domain->pgd;
707 spin_lock_irqsave(&domain->mapping_lock, flags);
711 offset = address_level_offset(addr, level);
712 pte = &parent[offset];
716 if (!dma_pte_present(pte)) {
717 tmp_page = alloc_pgtable_page();
720 spin_unlock_irqrestore(&domain->mapping_lock,
724 domain_flush_cache(domain, tmp_page, PAGE_SIZE);
725 dma_set_pte_pfn(pte, virt_to_dma_pfn(tmp_page));
727 * high level table always sets r/w, last level page
728 * table control read/write
730 dma_set_pte_readable(pte);
731 dma_set_pte_writable(pte);
732 domain_flush_cache(domain, pte, sizeof(*pte));
734 parent = phys_to_virt(dma_pte_addr(pte));
738 spin_unlock_irqrestore(&domain->mapping_lock, flags);
742 /* return address's pte at specific level */
743 static struct dma_pte *dma_addr_level_pte(struct dmar_domain *domain, u64 addr,
746 struct dma_pte *parent, *pte = NULL;
747 int total = agaw_to_level(domain->agaw);
750 parent = domain->pgd;
751 while (level <= total) {
752 offset = address_level_offset(addr, total);
753 pte = &parent[offset];
757 if (!dma_pte_present(pte))
759 parent = phys_to_virt(dma_pte_addr(pte));
765 /* clear one page's page table */
766 static void dma_pte_clear_one(struct dmar_domain *domain, u64 addr)
768 struct dma_pte *pte = NULL;
770 /* get last level pte */
771 pte = dma_addr_level_pte(domain, addr, 1);
775 domain_flush_cache(domain, pte, sizeof(*pte));
779 /* clear last level pte, a tlb flush should be followed */
780 static void dma_pte_clear_range(struct dmar_domain *domain, u64 start, u64 end)
782 int addr_width = agaw_to_width(domain->agaw);
785 start &= (((u64)1) << addr_width) - 1;
786 end &= (((u64)1) << addr_width) - 1;
787 /* in case it's partial page */
789 end = PAGE_ALIGN(end);
790 npages = (end - start) / VTD_PAGE_SIZE;
792 /* we don't need lock here, nobody else touches the iova range */
794 dma_pte_clear_one(domain, start);
795 start += VTD_PAGE_SIZE;
799 /* free page table pages. last level pte should already be cleared */
800 static void dma_pte_free_pagetable(struct dmar_domain *domain,
803 int addr_width = agaw_to_width(domain->agaw);
805 int total = agaw_to_level(domain->agaw);
809 start &= (((u64)1) << addr_width) - 1;
810 end &= (((u64)1) << addr_width) - 1;
812 /* we don't need lock here, nobody else touches the iova range */
814 while (level <= total) {
815 tmp = align_to_level(start, level);
816 if (tmp >= end || (tmp + level_size(level) > end))
820 pte = dma_addr_level_pte(domain, tmp, level);
823 phys_to_virt(dma_pte_addr(pte)));
825 domain_flush_cache(domain, pte, sizeof(*pte));
827 tmp += level_size(level);
832 if (start == 0 && end >= ((((u64)1) << addr_width) - 1)) {
833 free_pgtable_page(domain->pgd);
839 static int iommu_alloc_root_entry(struct intel_iommu *iommu)
841 struct root_entry *root;
844 root = (struct root_entry *)alloc_pgtable_page();
848 __iommu_flush_cache(iommu, root, ROOT_SIZE);
850 spin_lock_irqsave(&iommu->lock, flags);
851 iommu->root_entry = root;
852 spin_unlock_irqrestore(&iommu->lock, flags);
857 static void iommu_set_root_entry(struct intel_iommu *iommu)
863 addr = iommu->root_entry;
865 spin_lock_irqsave(&iommu->register_lock, flag);
866 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
868 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
870 /* Make sure hardware complete it */
871 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
872 readl, (sts & DMA_GSTS_RTPS), sts);
874 spin_unlock_irqrestore(&iommu->register_lock, flag);
877 static void iommu_flush_write_buffer(struct intel_iommu *iommu)
882 if (!rwbf_quirk && !cap_rwbf(iommu->cap))
885 spin_lock_irqsave(&iommu->register_lock, flag);
886 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
888 /* Make sure hardware complete it */
889 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
890 readl, (!(val & DMA_GSTS_WBFS)), val);
892 spin_unlock_irqrestore(&iommu->register_lock, flag);
895 /* return value determine if we need a write buffer flush */
896 static void __iommu_flush_context(struct intel_iommu *iommu,
897 u16 did, u16 source_id, u8 function_mask,
904 case DMA_CCMD_GLOBAL_INVL:
905 val = DMA_CCMD_GLOBAL_INVL;
907 case DMA_CCMD_DOMAIN_INVL:
908 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
910 case DMA_CCMD_DEVICE_INVL:
911 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
912 | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
919 spin_lock_irqsave(&iommu->register_lock, flag);
920 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
922 /* Make sure hardware complete it */
923 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
924 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
926 spin_unlock_irqrestore(&iommu->register_lock, flag);
929 /* return value determine if we need a write buffer flush */
930 static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
931 u64 addr, unsigned int size_order, u64 type)
933 int tlb_offset = ecap_iotlb_offset(iommu->ecap);
934 u64 val = 0, val_iva = 0;
938 case DMA_TLB_GLOBAL_FLUSH:
939 /* global flush doesn't need set IVA_REG */
940 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
942 case DMA_TLB_DSI_FLUSH:
943 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
945 case DMA_TLB_PSI_FLUSH:
946 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
947 /* Note: always flush non-leaf currently */
948 val_iva = size_order | addr;
953 /* Note: set drain read/write */
956 * This is probably to be super secure.. Looks like we can
957 * ignore it without any impact.
959 if (cap_read_drain(iommu->cap))
960 val |= DMA_TLB_READ_DRAIN;
962 if (cap_write_drain(iommu->cap))
963 val |= DMA_TLB_WRITE_DRAIN;
965 spin_lock_irqsave(&iommu->register_lock, flag);
966 /* Note: Only uses first TLB reg currently */
968 dmar_writeq(iommu->reg + tlb_offset, val_iva);
969 dmar_writeq(iommu->reg + tlb_offset + 8, val);
971 /* Make sure hardware complete it */
972 IOMMU_WAIT_OP(iommu, tlb_offset + 8,
973 dmar_readq, (!(val & DMA_TLB_IVT)), val);
975 spin_unlock_irqrestore(&iommu->register_lock, flag);
977 /* check IOTLB invalidation granularity */
978 if (DMA_TLB_IAIG(val) == 0)
979 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
980 if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
981 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
982 (unsigned long long)DMA_TLB_IIRG(type),
983 (unsigned long long)DMA_TLB_IAIG(val));
986 static struct device_domain_info *iommu_support_dev_iotlb(
987 struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
991 struct device_domain_info *info;
992 struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);
994 if (!ecap_dev_iotlb_support(iommu->ecap))
1000 spin_lock_irqsave(&device_domain_lock, flags);
1001 list_for_each_entry(info, &domain->devices, link)
1002 if (info->bus == bus && info->devfn == devfn) {
1006 spin_unlock_irqrestore(&device_domain_lock, flags);
1008 if (!found || !info->dev)
1011 if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
1014 if (!dmar_find_matched_atsr_unit(info->dev))
1017 info->iommu = iommu;
1022 static void iommu_enable_dev_iotlb(struct device_domain_info *info)
1027 pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
1030 static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1032 if (!info->dev || !pci_ats_enabled(info->dev))
1035 pci_disable_ats(info->dev);
1038 static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1039 u64 addr, unsigned mask)
1042 unsigned long flags;
1043 struct device_domain_info *info;
1045 spin_lock_irqsave(&device_domain_lock, flags);
1046 list_for_each_entry(info, &domain->devices, link) {
1047 if (!info->dev || !pci_ats_enabled(info->dev))
1050 sid = info->bus << 8 | info->devfn;
1051 qdep = pci_ats_queue_depth(info->dev);
1052 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1054 spin_unlock_irqrestore(&device_domain_lock, flags);
1057 static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
1058 u64 addr, unsigned int pages)
1060 unsigned int mask = ilog2(__roundup_pow_of_two(pages));
1062 BUG_ON(addr & (~VTD_PAGE_MASK));
1066 * Fallback to domain selective flush if no PSI support or the size is
1068 * PSI requires page size to be 2 ^ x, and the base address is naturally
1069 * aligned to the size
1071 if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1072 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1075 iommu->flush.flush_iotlb(iommu, did, addr, mask,
1079 * In caching mode, domain ID 0 is reserved for non-present to present
1080 * mapping flush. Device IOTLB doesn't need to be flushed in this case.
1082 if (!cap_caching_mode(iommu->cap) || did)
1083 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
1086 static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1089 unsigned long flags;
1091 spin_lock_irqsave(&iommu->register_lock, flags);
1092 pmen = readl(iommu->reg + DMAR_PMEN_REG);
1093 pmen &= ~DMA_PMEN_EPM;
1094 writel(pmen, iommu->reg + DMAR_PMEN_REG);
1096 /* wait for the protected region status bit to clear */
1097 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1098 readl, !(pmen & DMA_PMEN_PRS), pmen);
1100 spin_unlock_irqrestore(&iommu->register_lock, flags);
1103 static int iommu_enable_translation(struct intel_iommu *iommu)
1106 unsigned long flags;
1108 spin_lock_irqsave(&iommu->register_lock, flags);
1109 iommu->gcmd |= DMA_GCMD_TE;
1110 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1112 /* Make sure hardware complete it */
1113 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1114 readl, (sts & DMA_GSTS_TES), sts);
1116 spin_unlock_irqrestore(&iommu->register_lock, flags);
1120 static int iommu_disable_translation(struct intel_iommu *iommu)
1125 spin_lock_irqsave(&iommu->register_lock, flag);
1126 iommu->gcmd &= ~DMA_GCMD_TE;
1127 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1129 /* Make sure hardware complete it */
1130 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1131 readl, (!(sts & DMA_GSTS_TES)), sts);
1133 spin_unlock_irqrestore(&iommu->register_lock, flag);
1138 static int iommu_init_domains(struct intel_iommu *iommu)
1140 unsigned long ndomains;
1141 unsigned long nlongs;
1143 ndomains = cap_ndoms(iommu->cap);
1144 pr_debug("Number of Domains supportd <%ld>\n", ndomains);
1145 nlongs = BITS_TO_LONGS(ndomains);
1147 /* TBD: there might be 64K domains,
1148 * consider other allocation for future chip
1150 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1151 if (!iommu->domain_ids) {
1152 printk(KERN_ERR "Allocating domain id array failed\n");
1155 iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1157 if (!iommu->domains) {
1158 printk(KERN_ERR "Allocating domain array failed\n");
1159 kfree(iommu->domain_ids);
1163 spin_lock_init(&iommu->lock);
1166 * if Caching mode is set, then invalid translations are tagged
1167 * with domainid 0. Hence we need to pre-allocate it.
1169 if (cap_caching_mode(iommu->cap))
1170 set_bit(0, iommu->domain_ids);
1175 static void domain_exit(struct dmar_domain *domain);
1176 static void vm_domain_exit(struct dmar_domain *domain);
1178 void free_dmar_iommu(struct intel_iommu *iommu)
1180 struct dmar_domain *domain;
1182 unsigned long flags;
1184 i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap));
1185 for (; i < cap_ndoms(iommu->cap); ) {
1186 domain = iommu->domains[i];
1187 clear_bit(i, iommu->domain_ids);
1189 spin_lock_irqsave(&domain->iommu_lock, flags);
1190 if (--domain->iommu_count == 0) {
1191 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1192 vm_domain_exit(domain);
1194 domain_exit(domain);
1196 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1198 i = find_next_bit(iommu->domain_ids,
1199 cap_ndoms(iommu->cap), i+1);
1202 if (iommu->gcmd & DMA_GCMD_TE)
1203 iommu_disable_translation(iommu);
1206 set_irq_data(iommu->irq, NULL);
1207 /* This will mask the irq */
1208 free_irq(iommu->irq, iommu);
1209 destroy_irq(iommu->irq);
1212 kfree(iommu->domains);
1213 kfree(iommu->domain_ids);
1215 g_iommus[iommu->seq_id] = NULL;
1217 /* if all iommus are freed, free g_iommus */
1218 for (i = 0; i < g_num_of_iommus; i++) {
1223 if (i == g_num_of_iommus)
1226 /* free context mapping */
1227 free_context_table(iommu);
1230 static struct dmar_domain *alloc_domain(void)
1232 struct dmar_domain *domain;
1234 domain = alloc_domain_mem();
1238 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
1244 static int iommu_attach_domain(struct dmar_domain *domain,
1245 struct intel_iommu *iommu)
1248 unsigned long ndomains;
1249 unsigned long flags;
1251 ndomains = cap_ndoms(iommu->cap);
1253 spin_lock_irqsave(&iommu->lock, flags);
1255 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1256 if (num >= ndomains) {
1257 spin_unlock_irqrestore(&iommu->lock, flags);
1258 printk(KERN_ERR "IOMMU: no free domain ids\n");
1263 set_bit(num, iommu->domain_ids);
1264 set_bit(iommu->seq_id, &domain->iommu_bmp);
1265 iommu->domains[num] = domain;
1266 spin_unlock_irqrestore(&iommu->lock, flags);
1271 static void iommu_detach_domain(struct dmar_domain *domain,
1272 struct intel_iommu *iommu)
1274 unsigned long flags;
1278 spin_lock_irqsave(&iommu->lock, flags);
1279 ndomains = cap_ndoms(iommu->cap);
1280 num = find_first_bit(iommu->domain_ids, ndomains);
1281 for (; num < ndomains; ) {
1282 if (iommu->domains[num] == domain) {
1286 num = find_next_bit(iommu->domain_ids,
1287 cap_ndoms(iommu->cap), num+1);
1291 clear_bit(num, iommu->domain_ids);
1292 clear_bit(iommu->seq_id, &domain->iommu_bmp);
1293 iommu->domains[num] = NULL;
1295 spin_unlock_irqrestore(&iommu->lock, flags);
1298 static struct iova_domain reserved_iova_list;
1299 static struct lock_class_key reserved_alloc_key;
1300 static struct lock_class_key reserved_rbtree_key;
1302 static void dmar_init_reserved_ranges(void)
1304 struct pci_dev *pdev = NULL;
1309 init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
1311 lockdep_set_class(&reserved_iova_list.iova_alloc_lock,
1312 &reserved_alloc_key);
1313 lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1314 &reserved_rbtree_key);
1316 /* IOAPIC ranges shouldn't be accessed by DMA */
1317 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1318 IOVA_PFN(IOAPIC_RANGE_END));
1320 printk(KERN_ERR "Reserve IOAPIC range failed\n");
1322 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1323 for_each_pci_dev(pdev) {
1326 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1327 r = &pdev->resource[i];
1328 if (!r->flags || !(r->flags & IORESOURCE_MEM))
1331 addr &= PHYSICAL_PAGE_MASK;
1332 size = r->end - addr;
1333 size = PAGE_ALIGN(size);
1334 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(addr),
1335 IOVA_PFN(size + addr) - 1);
1337 printk(KERN_ERR "Reserve iova failed\n");
1343 static void domain_reserve_special_ranges(struct dmar_domain *domain)
1345 copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1348 static inline int guestwidth_to_adjustwidth(int gaw)
1351 int r = (gaw - 12) % 9;
1362 static int domain_init(struct dmar_domain *domain, int guest_width)
1364 struct intel_iommu *iommu;
1365 int adjust_width, agaw;
1366 unsigned long sagaw;
1368 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
1369 spin_lock_init(&domain->mapping_lock);
1370 spin_lock_init(&domain->iommu_lock);
1372 domain_reserve_special_ranges(domain);
1374 /* calculate AGAW */
1375 iommu = domain_get_iommu(domain);
1376 if (guest_width > cap_mgaw(iommu->cap))
1377 guest_width = cap_mgaw(iommu->cap);
1378 domain->gaw = guest_width;
1379 adjust_width = guestwidth_to_adjustwidth(guest_width);
1380 agaw = width_to_agaw(adjust_width);
1381 sagaw = cap_sagaw(iommu->cap);
1382 if (!test_bit(agaw, &sagaw)) {
1383 /* hardware doesn't support it, choose a bigger one */
1384 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1385 agaw = find_next_bit(&sagaw, 5, agaw);
1389 domain->agaw = agaw;
1390 INIT_LIST_HEAD(&domain->devices);
1392 if (ecap_coherent(iommu->ecap))
1393 domain->iommu_coherency = 1;
1395 domain->iommu_coherency = 0;
1397 if (ecap_sc_support(iommu->ecap))
1398 domain->iommu_snooping = 1;
1400 domain->iommu_snooping = 0;
1402 domain->iommu_count = 1;
1404 /* always allocate the top pgd */
1405 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
1408 __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
1412 static void domain_exit(struct dmar_domain *domain)
1414 struct dmar_drhd_unit *drhd;
1415 struct intel_iommu *iommu;
1418 /* Domain 0 is reserved, so dont process it */
1422 domain_remove_dev_info(domain);
1424 put_iova_domain(&domain->iovad);
1425 end = DOMAIN_MAX_ADDR(domain->gaw);
1426 end = end & (~PAGE_MASK);
1429 dma_pte_clear_range(domain, 0, end);
1431 /* free page tables */
1432 dma_pte_free_pagetable(domain, 0, end);
1434 for_each_active_iommu(iommu, drhd)
1435 if (test_bit(iommu->seq_id, &domain->iommu_bmp))
1436 iommu_detach_domain(domain, iommu);
1438 free_domain_mem(domain);
1441 static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1442 u8 bus, u8 devfn, int translation)
1444 struct context_entry *context;
1445 unsigned long flags;
1446 struct intel_iommu *iommu;
1447 struct dma_pte *pgd;
1449 unsigned long ndomains;
1452 struct device_domain_info *info = NULL;
1454 pr_debug("Set context mapping for %02x:%02x.%d\n",
1455 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1457 BUG_ON(!domain->pgd);
1458 BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1459 translation != CONTEXT_TT_MULTI_LEVEL);
1461 iommu = device_to_iommu(segment, bus, devfn);
1465 context = device_to_context_entry(iommu, bus, devfn);
1468 spin_lock_irqsave(&iommu->lock, flags);
1469 if (context_present(context)) {
1470 spin_unlock_irqrestore(&iommu->lock, flags);
1477 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1478 domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
1481 /* find an available domain id for this device in iommu */
1482 ndomains = cap_ndoms(iommu->cap);
1483 num = find_first_bit(iommu->domain_ids, ndomains);
1484 for (; num < ndomains; ) {
1485 if (iommu->domains[num] == domain) {
1490 num = find_next_bit(iommu->domain_ids,
1491 cap_ndoms(iommu->cap), num+1);
1495 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1496 if (num >= ndomains) {
1497 spin_unlock_irqrestore(&iommu->lock, flags);
1498 printk(KERN_ERR "IOMMU: no free domain ids\n");
1502 set_bit(num, iommu->domain_ids);
1503 set_bit(iommu->seq_id, &domain->iommu_bmp);
1504 iommu->domains[num] = domain;
1508 /* Skip top levels of page tables for
1509 * iommu which has less agaw than default.
1511 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1512 pgd = phys_to_virt(dma_pte_addr(pgd));
1513 if (!dma_pte_present(pgd)) {
1514 spin_unlock_irqrestore(&iommu->lock, flags);
1520 context_set_domain_id(context, id);
1522 if (translation != CONTEXT_TT_PASS_THROUGH) {
1523 info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
1524 translation = info ? CONTEXT_TT_DEV_IOTLB :
1525 CONTEXT_TT_MULTI_LEVEL;
1528 * In pass through mode, AW must be programmed to indicate the largest
1529 * AGAW value supported by hardware. And ASR is ignored by hardware.
1531 if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
1532 context_set_address_width(context, iommu->msagaw);
1534 context_set_address_root(context, virt_to_phys(pgd));
1535 context_set_address_width(context, iommu->agaw);
1538 context_set_translation_type(context, translation);
1539 context_set_fault_enable(context);
1540 context_set_present(context);
1541 domain_flush_cache(domain, context, sizeof(*context));
1544 * It's a non-present to present mapping. If hardware doesn't cache
1545 * non-present entry we only need to flush the write-buffer. If the
1546 * _does_ cache non-present entries, then it does so in the special
1547 * domain #0, which we have to flush:
1549 if (cap_caching_mode(iommu->cap)) {
1550 iommu->flush.flush_context(iommu, 0,
1551 (((u16)bus) << 8) | devfn,
1552 DMA_CCMD_MASK_NOBIT,
1553 DMA_CCMD_DEVICE_INVL);
1554 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH);
1556 iommu_flush_write_buffer(iommu);
1558 iommu_enable_dev_iotlb(info);
1559 spin_unlock_irqrestore(&iommu->lock, flags);
1561 spin_lock_irqsave(&domain->iommu_lock, flags);
1562 if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
1563 domain->iommu_count++;
1564 domain_update_iommu_cap(domain);
1566 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1571 domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1575 struct pci_dev *tmp, *parent;
1577 ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
1578 pdev->bus->number, pdev->devfn,
1583 /* dependent device mapping */
1584 tmp = pci_find_upstream_pcie_bridge(pdev);
1587 /* Secondary interface's bus number and devfn 0 */
1588 parent = pdev->bus->self;
1589 while (parent != tmp) {
1590 ret = domain_context_mapping_one(domain,
1591 pci_domain_nr(parent->bus),
1592 parent->bus->number,
1593 parent->devfn, translation);
1596 parent = parent->bus->self;
1598 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
1599 return domain_context_mapping_one(domain,
1600 pci_domain_nr(tmp->subordinate),
1601 tmp->subordinate->number, 0,
1603 else /* this is a legacy PCI bridge */
1604 return domain_context_mapping_one(domain,
1605 pci_domain_nr(tmp->bus),
1611 static int domain_context_mapped(struct pci_dev *pdev)
1614 struct pci_dev *tmp, *parent;
1615 struct intel_iommu *iommu;
1617 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1622 ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
1625 /* dependent device mapping */
1626 tmp = pci_find_upstream_pcie_bridge(pdev);
1629 /* Secondary interface's bus number and devfn 0 */
1630 parent = pdev->bus->self;
1631 while (parent != tmp) {
1632 ret = device_context_mapped(iommu, parent->bus->number,
1636 parent = parent->bus->self;
1639 return device_context_mapped(iommu, tmp->subordinate->number,
1642 return device_context_mapped(iommu, tmp->bus->number,
1647 domain_page_mapping(struct dmar_domain *domain, dma_addr_t iova,
1648 u64 hpa, size_t size, int prot)
1650 u64 start_pfn, end_pfn;
1651 struct dma_pte *pte;
1653 int addr_width = agaw_to_width(domain->agaw);
1655 hpa &= (((u64)1) << addr_width) - 1;
1657 if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1660 start_pfn = ((u64)hpa) >> VTD_PAGE_SHIFT;
1661 end_pfn = (VTD_PAGE_ALIGN(((u64)hpa) + size)) >> VTD_PAGE_SHIFT;
1663 while (start_pfn < end_pfn) {
1664 pte = addr_to_dma_pte(domain, iova + VTD_PAGE_SIZE * index);
1667 /* We don't need lock here, nobody else
1668 * touches the iova range
1670 BUG_ON(dma_pte_addr(pte));
1671 dma_set_pte_pfn(pte, start_pfn);
1672 dma_set_pte_prot(pte, prot);
1673 if (prot & DMA_PTE_SNP)
1674 dma_set_pte_snp(pte);
1675 domain_flush_cache(domain, pte, sizeof(*pte));
1682 static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
1687 clear_context_table(iommu, bus, devfn);
1688 iommu->flush.flush_context(iommu, 0, 0, 0,
1689 DMA_CCMD_GLOBAL_INVL);
1690 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
1693 static void domain_remove_dev_info(struct dmar_domain *domain)
1695 struct device_domain_info *info;
1696 unsigned long flags;
1697 struct intel_iommu *iommu;
1699 spin_lock_irqsave(&device_domain_lock, flags);
1700 while (!list_empty(&domain->devices)) {
1701 info = list_entry(domain->devices.next,
1702 struct device_domain_info, link);
1703 list_del(&info->link);
1704 list_del(&info->global);
1706 info->dev->dev.archdata.iommu = NULL;
1707 spin_unlock_irqrestore(&device_domain_lock, flags);
1709 iommu_disable_dev_iotlb(info);
1710 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
1711 iommu_detach_dev(iommu, info->bus, info->devfn);
1712 free_devinfo_mem(info);
1714 spin_lock_irqsave(&device_domain_lock, flags);
1716 spin_unlock_irqrestore(&device_domain_lock, flags);
1721 * Note: we use struct pci_dev->dev.archdata.iommu stores the info
1723 static struct dmar_domain *
1724 find_domain(struct pci_dev *pdev)
1726 struct device_domain_info *info;
1728 /* No lock here, assumes no domain exit in normal case */
1729 info = pdev->dev.archdata.iommu;
1731 return info->domain;
1735 /* domain is initialized */
1736 static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1738 struct dmar_domain *domain, *found = NULL;
1739 struct intel_iommu *iommu;
1740 struct dmar_drhd_unit *drhd;
1741 struct device_domain_info *info, *tmp;
1742 struct pci_dev *dev_tmp;
1743 unsigned long flags;
1744 int bus = 0, devfn = 0;
1748 domain = find_domain(pdev);
1752 segment = pci_domain_nr(pdev->bus);
1754 dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1756 if (dev_tmp->is_pcie) {
1757 bus = dev_tmp->subordinate->number;
1760 bus = dev_tmp->bus->number;
1761 devfn = dev_tmp->devfn;
1763 spin_lock_irqsave(&device_domain_lock, flags);
1764 list_for_each_entry(info, &device_domain_list, global) {
1765 if (info->segment == segment &&
1766 info->bus == bus && info->devfn == devfn) {
1767 found = info->domain;
1771 spin_unlock_irqrestore(&device_domain_lock, flags);
1772 /* pcie-pci bridge already has a domain, uses it */
1779 domain = alloc_domain();
1783 /* Allocate new domain for the device */
1784 drhd = dmar_find_matched_drhd_unit(pdev);
1786 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
1790 iommu = drhd->iommu;
1792 ret = iommu_attach_domain(domain, iommu);
1794 domain_exit(domain);
1798 if (domain_init(domain, gaw)) {
1799 domain_exit(domain);
1803 /* register pcie-to-pci device */
1805 info = alloc_devinfo_mem();
1807 domain_exit(domain);
1810 info->segment = segment;
1812 info->devfn = devfn;
1814 info->domain = domain;
1815 /* This domain is shared by devices under p2p bridge */
1816 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
1818 /* pcie-to-pci bridge already has a domain, uses it */
1820 spin_lock_irqsave(&device_domain_lock, flags);
1821 list_for_each_entry(tmp, &device_domain_list, global) {
1822 if (tmp->segment == segment &&
1823 tmp->bus == bus && tmp->devfn == devfn) {
1824 found = tmp->domain;
1829 free_devinfo_mem(info);
1830 domain_exit(domain);
1833 list_add(&info->link, &domain->devices);
1834 list_add(&info->global, &device_domain_list);
1836 spin_unlock_irqrestore(&device_domain_lock, flags);
1840 info = alloc_devinfo_mem();
1843 info->segment = segment;
1844 info->bus = pdev->bus->number;
1845 info->devfn = pdev->devfn;
1847 info->domain = domain;
1848 spin_lock_irqsave(&device_domain_lock, flags);
1849 /* somebody is fast */
1850 found = find_domain(pdev);
1851 if (found != NULL) {
1852 spin_unlock_irqrestore(&device_domain_lock, flags);
1853 if (found != domain) {
1854 domain_exit(domain);
1857 free_devinfo_mem(info);
1860 list_add(&info->link, &domain->devices);
1861 list_add(&info->global, &device_domain_list);
1862 pdev->dev.archdata.iommu = info;
1863 spin_unlock_irqrestore(&device_domain_lock, flags);
1866 /* recheck it here, maybe others set it */
1867 return find_domain(pdev);
1870 static int iommu_identity_mapping;
1872 static int iommu_domain_identity_map(struct dmar_domain *domain,
1873 unsigned long long start,
1874 unsigned long long end)
1877 unsigned long long base;
1879 /* The address might not be aligned */
1880 base = start & PAGE_MASK;
1882 size = PAGE_ALIGN(size);
1883 if (!reserve_iova(&domain->iovad, IOVA_PFN(base),
1884 IOVA_PFN(base + size) - 1)) {
1885 printk(KERN_ERR "IOMMU: reserve iova failed\n");
1889 pr_debug("Mapping reserved region %lx@%llx for domain %d\n",
1890 size, base, domain->id);
1892 * RMRR range might have overlap with physical memory range,
1895 dma_pte_clear_range(domain, base, base + size);
1897 return domain_page_mapping(domain, base, base, size,
1898 DMA_PTE_READ|DMA_PTE_WRITE);
1901 static int iommu_prepare_identity_map(struct pci_dev *pdev,
1902 unsigned long long start,
1903 unsigned long long end)
1905 struct dmar_domain *domain;
1909 "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
1910 pci_name(pdev), start, end);
1912 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1916 ret = iommu_domain_identity_map(domain, start, end);
1920 /* context entry init */
1921 ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
1928 domain_exit(domain);
1932 static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
1933 struct pci_dev *pdev)
1935 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
1937 return iommu_prepare_identity_map(pdev, rmrr->base_address,
1938 rmrr->end_address + 1);
1941 #ifdef CONFIG_DMAR_FLOPPY_WA
1942 static inline void iommu_prepare_isa(void)
1944 struct pci_dev *pdev;
1947 pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
1951 printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
1952 ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024);
1955 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
1956 "floppy might not work\n");
1960 static inline void iommu_prepare_isa(void)
1964 #endif /* !CONFIG_DMAR_FLPY_WA */
1966 /* Initialize each context entry as pass through.*/
1967 static int __init init_context_pass_through(void)
1969 struct pci_dev *pdev = NULL;
1970 struct dmar_domain *domain;
1973 for_each_pci_dev(pdev) {
1974 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1975 ret = domain_context_mapping(domain, pdev,
1976 CONTEXT_TT_PASS_THROUGH);
1983 static int md_domain_init(struct dmar_domain *domain, int guest_width);
1985 static int __init si_domain_work_fn(unsigned long start_pfn,
1986 unsigned long end_pfn, void *datax)
1990 *ret = iommu_domain_identity_map(si_domain,
1991 (uint64_t)start_pfn << PAGE_SHIFT,
1992 (uint64_t)end_pfn << PAGE_SHIFT);
1997 static int si_domain_init(void)
1999 struct dmar_drhd_unit *drhd;
2000 struct intel_iommu *iommu;
2003 si_domain = alloc_domain();
2007 pr_debug("Identity mapping domain is domain %d\n", si_domain->id);
2009 for_each_active_iommu(iommu, drhd) {
2010 ret = iommu_attach_domain(si_domain, iommu);
2012 domain_exit(si_domain);
2017 if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2018 domain_exit(si_domain);
2022 si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2024 for_each_online_node(nid) {
2025 work_with_active_regions(nid, si_domain_work_fn, &ret);
2033 static void domain_remove_one_dev_info(struct dmar_domain *domain,
2034 struct pci_dev *pdev);
2035 static int identity_mapping(struct pci_dev *pdev)
2037 struct device_domain_info *info;
2039 if (likely(!iommu_identity_mapping))
2043 list_for_each_entry(info, &si_domain->devices, link)
2044 if (info->dev == pdev)
2049 static int domain_add_dev_info(struct dmar_domain *domain,
2050 struct pci_dev *pdev)
2052 struct device_domain_info *info;
2053 unsigned long flags;
2055 info = alloc_devinfo_mem();
2059 info->segment = pci_domain_nr(pdev->bus);
2060 info->bus = pdev->bus->number;
2061 info->devfn = pdev->devfn;
2063 info->domain = domain;
2065 spin_lock_irqsave(&device_domain_lock, flags);
2066 list_add(&info->link, &domain->devices);
2067 list_add(&info->global, &device_domain_list);
2068 pdev->dev.archdata.iommu = info;
2069 spin_unlock_irqrestore(&device_domain_lock, flags);
2074 static int iommu_prepare_static_identity_mapping(void)
2076 struct pci_dev *pdev = NULL;
2079 ret = si_domain_init();
2083 for_each_pci_dev(pdev) {
2084 printk(KERN_INFO "IOMMU: identity mapping for device %s\n",
2087 ret = domain_context_mapping(si_domain, pdev,
2088 CONTEXT_TT_MULTI_LEVEL);
2091 ret = domain_add_dev_info(si_domain, pdev);
2099 int __init init_dmars(void)
2101 struct dmar_drhd_unit *drhd;
2102 struct dmar_rmrr_unit *rmrr;
2103 struct pci_dev *pdev;
2104 struct intel_iommu *iommu;
2106 int pass_through = 1;
2109 * In case pass through can not be enabled, iommu tries to use identity
2112 if (iommu_pass_through)
2113 iommu_identity_mapping = 1;
2118 * initialize and program root entry to not present
2121 for_each_drhd_unit(drhd) {
2124 * lock not needed as this is only incremented in the single
2125 * threaded kernel __init code path all other access are read
2130 g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2133 printk(KERN_ERR "Allocating global iommu array failed\n");
2138 deferred_flush = kzalloc(g_num_of_iommus *
2139 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2140 if (!deferred_flush) {
2146 for_each_drhd_unit(drhd) {
2150 iommu = drhd->iommu;
2151 g_iommus[iommu->seq_id] = iommu;
2153 ret = iommu_init_domains(iommu);
2159 * we could share the same root & context tables
2160 * amoung all IOMMU's. Need to Split it later.
2162 ret = iommu_alloc_root_entry(iommu);
2164 printk(KERN_ERR "IOMMU: allocate root entry failed\n");
2167 if (!ecap_pass_through(iommu->ecap))
2170 if (iommu_pass_through)
2171 if (!pass_through) {
2173 "Pass Through is not supported by hardware.\n");
2174 iommu_pass_through = 0;
2178 * Start from the sane iommu hardware state.
2180 for_each_drhd_unit(drhd) {
2184 iommu = drhd->iommu;
2187 * If the queued invalidation is already initialized by us
2188 * (for example, while enabling interrupt-remapping) then
2189 * we got the things already rolling from a sane state.
2195 * Clear any previous faults.
2197 dmar_fault(-1, iommu);
2199 * Disable queued invalidation if supported and already enabled
2200 * before OS handover.
2202 dmar_disable_qi(iommu);
2205 for_each_drhd_unit(drhd) {
2209 iommu = drhd->iommu;
2211 if (dmar_enable_qi(iommu)) {
2213 * Queued Invalidate not enabled, use Register Based
2216 iommu->flush.flush_context = __iommu_flush_context;
2217 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
2218 printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
2220 (unsigned long long)drhd->reg_base_addr);
2222 iommu->flush.flush_context = qi_flush_context;
2223 iommu->flush.flush_iotlb = qi_flush_iotlb;
2224 printk(KERN_INFO "IOMMU 0x%Lx: using Queued "
2226 (unsigned long long)drhd->reg_base_addr);
2231 * If pass through is set and enabled, context entries of all pci
2232 * devices are intialized by pass through translation type.
2234 if (iommu_pass_through) {
2235 ret = init_context_pass_through();
2237 printk(KERN_ERR "IOMMU: Pass through init failed.\n");
2238 iommu_pass_through = 0;
2243 * If pass through is not set or not enabled, setup context entries for
2244 * identity mappings for rmrr, gfx, and isa and may fall back to static
2245 * identity mapping if iommu_identity_mapping is set.
2247 if (!iommu_pass_through) {
2248 if (iommu_identity_mapping)
2249 iommu_prepare_static_identity_mapping();
2252 * for each dev attached to rmrr
2254 * locate drhd for dev, alloc domain for dev
2255 * allocate free domain
2256 * allocate page table entries for rmrr
2257 * if context not allocated for bus
2258 * allocate and init context
2259 * set present in root table for this bus
2260 * init context with domain, translation etc
2264 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
2265 for_each_rmrr_units(rmrr) {
2266 for (i = 0; i < rmrr->devices_cnt; i++) {
2267 pdev = rmrr->devices[i];
2269 * some BIOS lists non-exist devices in DMAR
2274 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2277 "IOMMU: mapping reserved region failed\n");
2281 iommu_prepare_isa();
2287 * global invalidate context cache
2288 * global invalidate iotlb
2289 * enable translation
2291 for_each_drhd_unit(drhd) {
2294 iommu = drhd->iommu;
2296 iommu_flush_write_buffer(iommu);
2298 ret = dmar_set_interrupt(iommu);
2302 iommu_set_root_entry(iommu);
2304 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
2305 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
2306 iommu_disable_protect_mem_regions(iommu);
2308 ret = iommu_enable_translation(iommu);
2315 for_each_drhd_unit(drhd) {
2318 iommu = drhd->iommu;
2325 static inline u64 aligned_size(u64 host_addr, size_t size)
2328 addr = (host_addr & (~PAGE_MASK)) + size;
2329 return PAGE_ALIGN(addr);
2333 iommu_alloc_iova(struct dmar_domain *domain, size_t size, u64 end)
2337 /* Make sure it's in range */
2338 end = min_t(u64, DOMAIN_MAX_ADDR(domain->gaw), end);
2339 if (!size || (IOVA_START_ADDR + size > end))
2342 piova = alloc_iova(&domain->iovad,
2343 size >> PAGE_SHIFT, IOVA_PFN(end), 1);
2347 static struct iova *
2348 __intel_alloc_iova(struct device *dev, struct dmar_domain *domain,
2349 size_t size, u64 dma_mask)
2351 struct pci_dev *pdev = to_pci_dev(dev);
2352 struct iova *iova = NULL;
2354 if (dma_mask <= DMA_BIT_MASK(32) || dmar_forcedac)
2355 iova = iommu_alloc_iova(domain, size, dma_mask);
2358 * First try to allocate an io virtual address in
2359 * DMA_BIT_MASK(32) and if that fails then try allocating
2362 iova = iommu_alloc_iova(domain, size, DMA_BIT_MASK(32));
2364 iova = iommu_alloc_iova(domain, size, dma_mask);
2368 printk(KERN_ERR"Allocating iova for %s failed", pci_name(pdev));
2375 static struct dmar_domain *
2376 get_valid_domain_for_dev(struct pci_dev *pdev)
2378 struct dmar_domain *domain;
2381 domain = get_domain_for_dev(pdev,
2382 DEFAULT_DOMAIN_ADDRESS_WIDTH);
2385 "Allocating domain for %s failed", pci_name(pdev));
2389 /* make sure context mapping is ok */
2390 if (unlikely(!domain_context_mapped(pdev))) {
2391 ret = domain_context_mapping(domain, pdev,
2392 CONTEXT_TT_MULTI_LEVEL);
2395 "Domain context map for %s failed",
2404 static int iommu_dummy(struct pci_dev *pdev)
2406 return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2409 /* Check if the pdev needs to go through non-identity map and unmap process.*/
2410 static int iommu_no_mapping(struct pci_dev *pdev)
2414 if (!iommu_identity_mapping)
2415 return iommu_dummy(pdev);
2417 found = identity_mapping(pdev);
2419 if (pdev->dma_mask > DMA_BIT_MASK(32))
2423 * 32 bit DMA is removed from si_domain and fall back
2424 * to non-identity mapping.
2426 domain_remove_one_dev_info(si_domain, pdev);
2427 printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2433 * In case of a detached 64 bit DMA device from vm, the device
2434 * is put into si_domain for identity mapping.
2436 if (pdev->dma_mask > DMA_BIT_MASK(32)) {
2438 ret = domain_add_dev_info(si_domain, pdev);
2440 printk(KERN_INFO "64bit %s uses identity mapping\n",
2447 return iommu_dummy(pdev);
2450 static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2451 size_t size, int dir, u64 dma_mask)
2453 struct pci_dev *pdev = to_pci_dev(hwdev);
2454 struct dmar_domain *domain;
2455 phys_addr_t start_paddr;
2459 struct intel_iommu *iommu;
2461 BUG_ON(dir == DMA_NONE);
2463 if (iommu_no_mapping(pdev))
2466 domain = get_valid_domain_for_dev(pdev);
2470 iommu = domain_get_iommu(domain);
2471 size = aligned_size((u64)paddr, size);
2473 iova = __intel_alloc_iova(hwdev, domain, size, pdev->dma_mask);
2477 start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2480 * Check if DMAR supports zero-length reads on write only
2483 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2484 !cap_zlr(iommu->cap))
2485 prot |= DMA_PTE_READ;
2486 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2487 prot |= DMA_PTE_WRITE;
2489 * paddr - (paddr + size) might be partial page, we should map the whole
2490 * page. Note: if two part of one page are separately mapped, we
2491 * might have two guest_addr mapping to the same host paddr, but this
2492 * is not a big problem
2494 ret = domain_page_mapping(domain, start_paddr,
2495 ((u64)paddr) & PHYSICAL_PAGE_MASK,
2500 /* it's a non-present to present mapping. Only flush if caching mode */
2501 if (cap_caching_mode(iommu->cap))
2502 iommu_flush_iotlb_psi(iommu, 0, start_paddr,
2503 size >> VTD_PAGE_SHIFT);
2505 iommu_flush_write_buffer(iommu);
2507 return start_paddr + ((u64)paddr & (~PAGE_MASK));
2511 __free_iova(&domain->iovad, iova);
2512 printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
2513 pci_name(pdev), size, (unsigned long long)paddr, dir);
2517 static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2518 unsigned long offset, size_t size,
2519 enum dma_data_direction dir,
2520 struct dma_attrs *attrs)
2522 return __intel_map_single(dev, page_to_phys(page) + offset, size,
2523 dir, to_pci_dev(dev)->dma_mask);
2526 static void flush_unmaps(void)
2532 /* just flush them all */
2533 for (i = 0; i < g_num_of_iommus; i++) {
2534 struct intel_iommu *iommu = g_iommus[i];
2538 if (!deferred_flush[i].next)
2541 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2542 DMA_TLB_GLOBAL_FLUSH);
2543 for (j = 0; j < deferred_flush[i].next; j++) {
2545 struct iova *iova = deferred_flush[i].iova[j];
2547 mask = (iova->pfn_hi - iova->pfn_lo + 1) << PAGE_SHIFT;
2548 mask = ilog2(mask >> VTD_PAGE_SHIFT);
2549 iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
2550 iova->pfn_lo << PAGE_SHIFT, mask);
2551 __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
2553 deferred_flush[i].next = 0;
2559 static void flush_unmaps_timeout(unsigned long data)
2561 unsigned long flags;
2563 spin_lock_irqsave(&async_umap_flush_lock, flags);
2565 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2568 static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2570 unsigned long flags;
2572 struct intel_iommu *iommu;
2574 spin_lock_irqsave(&async_umap_flush_lock, flags);
2575 if (list_size == HIGH_WATER_MARK)
2578 iommu = domain_get_iommu(dom);
2579 iommu_id = iommu->seq_id;
2581 next = deferred_flush[iommu_id].next;
2582 deferred_flush[iommu_id].domain[next] = dom;
2583 deferred_flush[iommu_id].iova[next] = iova;
2584 deferred_flush[iommu_id].next++;
2587 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2591 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2594 static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2595 size_t size, enum dma_data_direction dir,
2596 struct dma_attrs *attrs)
2598 struct pci_dev *pdev = to_pci_dev(dev);
2599 struct dmar_domain *domain;
2600 unsigned long start_addr;
2602 struct intel_iommu *iommu;
2604 if (iommu_no_mapping(pdev))
2607 domain = find_domain(pdev);
2610 iommu = domain_get_iommu(domain);
2612 iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
2616 start_addr = iova->pfn_lo << PAGE_SHIFT;
2617 size = aligned_size((u64)dev_addr, size);
2619 pr_debug("Device %s unmapping: %zx@%llx\n",
2620 pci_name(pdev), size, (unsigned long long)start_addr);
2622 /* clear the whole page */
2623 dma_pte_clear_range(domain, start_addr, start_addr + size);
2624 /* free page tables */
2625 dma_pte_free_pagetable(domain, start_addr, start_addr + size);
2626 if (intel_iommu_strict) {
2627 iommu_flush_iotlb_psi(iommu, domain->id, start_addr,
2628 size >> VTD_PAGE_SHIFT);
2630 __free_iova(&domain->iovad, iova);
2632 add_unmap(domain, iova);
2634 * queue up the release of the unmap to save the 1/6th of the
2635 * cpu used up by the iotlb flush operation...
2640 static void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size,
2643 intel_unmap_page(dev, dev_addr, size, dir, NULL);
2646 static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2647 dma_addr_t *dma_handle, gfp_t flags)
2652 size = PAGE_ALIGN(size);
2653 order = get_order(size);
2654 flags &= ~(GFP_DMA | GFP_DMA32);
2656 vaddr = (void *)__get_free_pages(flags, order);
2659 memset(vaddr, 0, size);
2661 *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
2663 hwdev->coherent_dma_mask);
2666 free_pages((unsigned long)vaddr, order);
2670 static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2671 dma_addr_t dma_handle)
2675 size = PAGE_ALIGN(size);
2676 order = get_order(size);
2678 intel_unmap_single(hwdev, dma_handle, size, DMA_BIDIRECTIONAL);
2679 free_pages((unsigned long)vaddr, order);
2682 static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
2683 int nelems, enum dma_data_direction dir,
2684 struct dma_attrs *attrs)
2687 struct pci_dev *pdev = to_pci_dev(hwdev);
2688 struct dmar_domain *domain;
2689 unsigned long start_addr;
2693 struct scatterlist *sg;
2694 struct intel_iommu *iommu;
2696 if (iommu_no_mapping(pdev))
2699 domain = find_domain(pdev);
2702 iommu = domain_get_iommu(domain);
2704 iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
2707 for_each_sg(sglist, sg, nelems, i) {
2708 addr = page_to_phys(sg_page(sg)) + sg->offset;
2709 size += aligned_size((u64)addr, sg->length);
2712 start_addr = iova->pfn_lo << PAGE_SHIFT;
2714 /* clear the whole page */
2715 dma_pte_clear_range(domain, start_addr, start_addr + size);
2716 /* free page tables */
2717 dma_pte_free_pagetable(domain, start_addr, start_addr + size);
2719 iommu_flush_iotlb_psi(iommu, domain->id, start_addr,
2720 size >> VTD_PAGE_SHIFT);
2723 __free_iova(&domain->iovad, iova);
2726 static int intel_nontranslate_map_sg(struct device *hddev,
2727 struct scatterlist *sglist, int nelems, int dir)
2730 struct scatterlist *sg;
2732 for_each_sg(sglist, sg, nelems, i) {
2733 BUG_ON(!sg_page(sg));
2734 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
2735 sg->dma_length = sg->length;
2740 static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
2741 enum dma_data_direction dir, struct dma_attrs *attrs)
2745 struct pci_dev *pdev = to_pci_dev(hwdev);
2746 struct dmar_domain *domain;
2750 struct iova *iova = NULL;
2752 struct scatterlist *sg;
2753 unsigned long start_addr;
2754 struct intel_iommu *iommu;
2756 BUG_ON(dir == DMA_NONE);
2757 if (iommu_no_mapping(pdev))
2758 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
2760 domain = get_valid_domain_for_dev(pdev);
2764 iommu = domain_get_iommu(domain);
2766 for_each_sg(sglist, sg, nelems, i) {
2767 addr = page_to_phys(sg_page(sg)) + sg->offset;
2768 size += aligned_size((u64)addr, sg->length);
2771 iova = __intel_alloc_iova(hwdev, domain, size, pdev->dma_mask);
2773 sglist->dma_length = 0;
2778 * Check if DMAR supports zero-length reads on write only
2781 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2782 !cap_zlr(iommu->cap))
2783 prot |= DMA_PTE_READ;
2784 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2785 prot |= DMA_PTE_WRITE;
2787 start_addr = iova->pfn_lo << PAGE_SHIFT;
2789 for_each_sg(sglist, sg, nelems, i) {
2790 addr = page_to_phys(sg_page(sg)) + sg->offset;
2791 size = aligned_size((u64)addr, sg->length);
2792 ret = domain_page_mapping(domain, start_addr + offset,
2793 ((u64)addr) & PHYSICAL_PAGE_MASK,
2796 /* clear the page */
2797 dma_pte_clear_range(domain, start_addr,
2798 start_addr + offset);
2799 /* free page tables */
2800 dma_pte_free_pagetable(domain, start_addr,
2801 start_addr + offset);
2803 __free_iova(&domain->iovad, iova);
2806 sg->dma_address = start_addr + offset +
2807 ((u64)addr & (~PAGE_MASK));
2808 sg->dma_length = sg->length;
2812 /* it's a non-present to present mapping. Only flush if caching mode */
2813 if (cap_caching_mode(iommu->cap))
2814 iommu_flush_iotlb_psi(iommu, 0, start_addr,
2815 offset >> VTD_PAGE_SHIFT);
2817 iommu_flush_write_buffer(iommu);
2822 static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
2827 struct dma_map_ops intel_dma_ops = {
2828 .alloc_coherent = intel_alloc_coherent,
2829 .free_coherent = intel_free_coherent,
2830 .map_sg = intel_map_sg,
2831 .unmap_sg = intel_unmap_sg,
2832 .map_page = intel_map_page,
2833 .unmap_page = intel_unmap_page,
2834 .mapping_error = intel_mapping_error,
2837 static inline int iommu_domain_cache_init(void)
2841 iommu_domain_cache = kmem_cache_create("iommu_domain",
2842 sizeof(struct dmar_domain),
2847 if (!iommu_domain_cache) {
2848 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
2855 static inline int iommu_devinfo_cache_init(void)
2859 iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
2860 sizeof(struct device_domain_info),
2864 if (!iommu_devinfo_cache) {
2865 printk(KERN_ERR "Couldn't create devinfo cache\n");
2872 static inline int iommu_iova_cache_init(void)
2876 iommu_iova_cache = kmem_cache_create("iommu_iova",
2877 sizeof(struct iova),
2881 if (!iommu_iova_cache) {
2882 printk(KERN_ERR "Couldn't create iova cache\n");
2889 static int __init iommu_init_mempool(void)
2892 ret = iommu_iova_cache_init();
2896 ret = iommu_domain_cache_init();
2900 ret = iommu_devinfo_cache_init();
2904 kmem_cache_destroy(iommu_domain_cache);
2906 kmem_cache_destroy(iommu_iova_cache);
2911 static void __init iommu_exit_mempool(void)
2913 kmem_cache_destroy(iommu_devinfo_cache);
2914 kmem_cache_destroy(iommu_domain_cache);
2915 kmem_cache_destroy(iommu_iova_cache);
2919 static void __init init_no_remapping_devices(void)
2921 struct dmar_drhd_unit *drhd;
2923 for_each_drhd_unit(drhd) {
2924 if (!drhd->include_all) {
2926 for (i = 0; i < drhd->devices_cnt; i++)
2927 if (drhd->devices[i] != NULL)
2929 /* ignore DMAR unit if no pci devices exist */
2930 if (i == drhd->devices_cnt)
2938 for_each_drhd_unit(drhd) {
2940 if (drhd->ignored || drhd->include_all)
2943 for (i = 0; i < drhd->devices_cnt; i++)
2944 if (drhd->devices[i] &&
2945 !IS_GFX_DEVICE(drhd->devices[i]))
2948 if (i < drhd->devices_cnt)
2951 /* bypass IOMMU if it is just for gfx devices */
2953 for (i = 0; i < drhd->devices_cnt; i++) {
2954 if (!drhd->devices[i])
2956 drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
2961 #ifdef CONFIG_SUSPEND
2962 static int init_iommu_hw(void)
2964 struct dmar_drhd_unit *drhd;
2965 struct intel_iommu *iommu = NULL;
2967 for_each_active_iommu(iommu, drhd)
2969 dmar_reenable_qi(iommu);
2971 for_each_active_iommu(iommu, drhd) {
2972 iommu_flush_write_buffer(iommu);
2974 iommu_set_root_entry(iommu);
2976 iommu->flush.flush_context(iommu, 0, 0, 0,
2977 DMA_CCMD_GLOBAL_INVL);
2978 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2979 DMA_TLB_GLOBAL_FLUSH);
2980 iommu_disable_protect_mem_regions(iommu);
2981 iommu_enable_translation(iommu);
2987 static void iommu_flush_all(void)
2989 struct dmar_drhd_unit *drhd;
2990 struct intel_iommu *iommu;
2992 for_each_active_iommu(iommu, drhd) {
2993 iommu->flush.flush_context(iommu, 0, 0, 0,
2994 DMA_CCMD_GLOBAL_INVL);
2995 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2996 DMA_TLB_GLOBAL_FLUSH);
3000 static int iommu_suspend(struct sys_device *dev, pm_message_t state)
3002 struct dmar_drhd_unit *drhd;
3003 struct intel_iommu *iommu = NULL;
3006 for_each_active_iommu(iommu, drhd) {
3007 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3009 if (!iommu->iommu_state)
3015 for_each_active_iommu(iommu, drhd) {
3016 iommu_disable_translation(iommu);
3018 spin_lock_irqsave(&iommu->register_lock, flag);
3020 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3021 readl(iommu->reg + DMAR_FECTL_REG);
3022 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3023 readl(iommu->reg + DMAR_FEDATA_REG);
3024 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3025 readl(iommu->reg + DMAR_FEADDR_REG);
3026 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3027 readl(iommu->reg + DMAR_FEUADDR_REG);
3029 spin_unlock_irqrestore(&iommu->register_lock, flag);
3034 for_each_active_iommu(iommu, drhd)
3035 kfree(iommu->iommu_state);
3040 static int iommu_resume(struct sys_device *dev)
3042 struct dmar_drhd_unit *drhd;
3043 struct intel_iommu *iommu = NULL;
3046 if (init_iommu_hw()) {
3047 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3051 for_each_active_iommu(iommu, drhd) {
3053 spin_lock_irqsave(&iommu->register_lock, flag);
3055 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3056 iommu->reg + DMAR_FECTL_REG);
3057 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3058 iommu->reg + DMAR_FEDATA_REG);
3059 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3060 iommu->reg + DMAR_FEADDR_REG);
3061 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3062 iommu->reg + DMAR_FEUADDR_REG);
3064 spin_unlock_irqrestore(&iommu->register_lock, flag);
3067 for_each_active_iommu(iommu, drhd)
3068 kfree(iommu->iommu_state);
3073 static struct sysdev_class iommu_sysclass = {
3075 .resume = iommu_resume,
3076 .suspend = iommu_suspend,
3079 static struct sys_device device_iommu = {
3080 .cls = &iommu_sysclass,
3083 static int __init init_iommu_sysfs(void)
3087 error = sysdev_class_register(&iommu_sysclass);
3091 error = sysdev_register(&device_iommu);
3093 sysdev_class_unregister(&iommu_sysclass);
3099 static int __init init_iommu_sysfs(void)
3103 #endif /* CONFIG_PM */
3105 int __init intel_iommu_init(void)
3109 if (dmar_table_init())
3112 if (dmar_dev_scope_init())
3116 * Check the need for DMA-remapping initialization now.
3117 * Above initialization will also be used by Interrupt-remapping.
3119 if (no_iommu || (swiotlb && !iommu_pass_through) || dmar_disabled)
3122 iommu_init_mempool();
3123 dmar_init_reserved_ranges();
3125 init_no_remapping_devices();
3129 printk(KERN_ERR "IOMMU: dmar init failed\n");
3130 put_iova_domain(&reserved_iova_list);
3131 iommu_exit_mempool();
3135 "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3137 init_timer(&unmap_timer);
3140 if (!iommu_pass_through) {
3142 "Multi-level page-table translation for DMAR.\n");
3143 dma_ops = &intel_dma_ops;
3146 "DMAR: Pass through translation for DMAR.\n");
3150 register_iommu(&intel_iommu_ops);
3155 static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
3156 struct pci_dev *pdev)
3158 struct pci_dev *tmp, *parent;
3160 if (!iommu || !pdev)
3163 /* dependent device detach */
3164 tmp = pci_find_upstream_pcie_bridge(pdev);
3165 /* Secondary interface's bus number and devfn 0 */
3167 parent = pdev->bus->self;
3168 while (parent != tmp) {
3169 iommu_detach_dev(iommu, parent->bus->number,
3171 parent = parent->bus->self;
3173 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
3174 iommu_detach_dev(iommu,
3175 tmp->subordinate->number, 0);
3176 else /* this is a legacy PCI bridge */
3177 iommu_detach_dev(iommu, tmp->bus->number,
3182 static void domain_remove_one_dev_info(struct dmar_domain *domain,
3183 struct pci_dev *pdev)
3185 struct device_domain_info *info;
3186 struct intel_iommu *iommu;
3187 unsigned long flags;
3189 struct list_head *entry, *tmp;
3191 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3196 spin_lock_irqsave(&device_domain_lock, flags);
3197 list_for_each_safe(entry, tmp, &domain->devices) {
3198 info = list_entry(entry, struct device_domain_info, link);
3199 /* No need to compare PCI domain; it has to be the same */
3200 if (info->bus == pdev->bus->number &&
3201 info->devfn == pdev->devfn) {
3202 list_del(&info->link);
3203 list_del(&info->global);
3205 info->dev->dev.archdata.iommu = NULL;
3206 spin_unlock_irqrestore(&device_domain_lock, flags);
3208 iommu_disable_dev_iotlb(info);
3209 iommu_detach_dev(iommu, info->bus, info->devfn);
3210 iommu_detach_dependent_devices(iommu, pdev);
3211 free_devinfo_mem(info);
3213 spin_lock_irqsave(&device_domain_lock, flags);
3221 /* if there is no other devices under the same iommu
3222 * owned by this domain, clear this iommu in iommu_bmp
3223 * update iommu count and coherency
3225 if (iommu == device_to_iommu(info->segment, info->bus,
3231 unsigned long tmp_flags;
3232 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
3233 clear_bit(iommu->seq_id, &domain->iommu_bmp);
3234 domain->iommu_count--;
3235 domain_update_iommu_cap(domain);
3236 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
3239 spin_unlock_irqrestore(&device_domain_lock, flags);
3242 static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
3244 struct device_domain_info *info;
3245 struct intel_iommu *iommu;
3246 unsigned long flags1, flags2;
3248 spin_lock_irqsave(&device_domain_lock, flags1);
3249 while (!list_empty(&domain->devices)) {
3250 info = list_entry(domain->devices.next,
3251 struct device_domain_info, link);
3252 list_del(&info->link);
3253 list_del(&info->global);
3255 info->dev->dev.archdata.iommu = NULL;
3257 spin_unlock_irqrestore(&device_domain_lock, flags1);
3259 iommu_disable_dev_iotlb(info);
3260 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
3261 iommu_detach_dev(iommu, info->bus, info->devfn);
3262 iommu_detach_dependent_devices(iommu, info->dev);
3264 /* clear this iommu in iommu_bmp, update iommu count
3267 spin_lock_irqsave(&domain->iommu_lock, flags2);
3268 if (test_and_clear_bit(iommu->seq_id,
3269 &domain->iommu_bmp)) {
3270 domain->iommu_count--;
3271 domain_update_iommu_cap(domain);
3273 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
3275 free_devinfo_mem(info);
3276 spin_lock_irqsave(&device_domain_lock, flags1);
3278 spin_unlock_irqrestore(&device_domain_lock, flags1);
3281 /* domain id for virtual machine, it won't be set in context */
3282 static unsigned long vm_domid;
3284 static int vm_domain_min_agaw(struct dmar_domain *domain)
3287 int min_agaw = domain->agaw;
3289 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
3290 for (; i < g_num_of_iommus; ) {
3291 if (min_agaw > g_iommus[i]->agaw)
3292 min_agaw = g_iommus[i]->agaw;
3294 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
3300 static struct dmar_domain *iommu_alloc_vm_domain(void)
3302 struct dmar_domain *domain;
3304 domain = alloc_domain_mem();
3308 domain->id = vm_domid++;
3309 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
3310 domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
3315 static int md_domain_init(struct dmar_domain *domain, int guest_width)
3319 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
3320 spin_lock_init(&domain->mapping_lock);
3321 spin_lock_init(&domain->iommu_lock);
3323 domain_reserve_special_ranges(domain);
3325 /* calculate AGAW */
3326 domain->gaw = guest_width;
3327 adjust_width = guestwidth_to_adjustwidth(guest_width);
3328 domain->agaw = width_to_agaw(adjust_width);
3330 INIT_LIST_HEAD(&domain->devices);
3332 domain->iommu_count = 0;
3333 domain->iommu_coherency = 0;
3334 domain->max_addr = 0;
3336 /* always allocate the top pgd */
3337 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
3340 domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
3344 static void iommu_free_vm_domain(struct dmar_domain *domain)
3346 unsigned long flags;
3347 struct dmar_drhd_unit *drhd;
3348 struct intel_iommu *iommu;
3350 unsigned long ndomains;
3352 for_each_drhd_unit(drhd) {
3355 iommu = drhd->iommu;
3357 ndomains = cap_ndoms(iommu->cap);
3358 i = find_first_bit(iommu->domain_ids, ndomains);
3359 for (; i < ndomains; ) {
3360 if (iommu->domains[i] == domain) {
3361 spin_lock_irqsave(&iommu->lock, flags);
3362 clear_bit(i, iommu->domain_ids);
3363 iommu->domains[i] = NULL;
3364 spin_unlock_irqrestore(&iommu->lock, flags);
3367 i = find_next_bit(iommu->domain_ids, ndomains, i+1);
3372 static void vm_domain_exit(struct dmar_domain *domain)
3376 /* Domain 0 is reserved, so dont process it */
3380 vm_domain_remove_all_dev_info(domain);
3382 put_iova_domain(&domain->iovad);
3383 end = DOMAIN_MAX_ADDR(domain->gaw);
3384 end = end & (~VTD_PAGE_MASK);
3387 dma_pte_clear_range(domain, 0, end);
3389 /* free page tables */
3390 dma_pte_free_pagetable(domain, 0, end);
3392 iommu_free_vm_domain(domain);
3393 free_domain_mem(domain);
3396 static int intel_iommu_domain_init(struct iommu_domain *domain)
3398 struct dmar_domain *dmar_domain;
3400 dmar_domain = iommu_alloc_vm_domain();
3403 "intel_iommu_domain_init: dmar_domain == NULL\n");
3406 if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
3408 "intel_iommu_domain_init() failed\n");
3409 vm_domain_exit(dmar_domain);
3412 domain->priv = dmar_domain;
3417 static void intel_iommu_domain_destroy(struct iommu_domain *domain)
3419 struct dmar_domain *dmar_domain = domain->priv;
3421 domain->priv = NULL;
3422 vm_domain_exit(dmar_domain);
3425 static int intel_iommu_attach_device(struct iommu_domain *domain,
3428 struct dmar_domain *dmar_domain = domain->priv;
3429 struct pci_dev *pdev = to_pci_dev(dev);
3430 struct intel_iommu *iommu;
3435 /* normally pdev is not mapped */
3436 if (unlikely(domain_context_mapped(pdev))) {
3437 struct dmar_domain *old_domain;
3439 old_domain = find_domain(pdev);
3441 if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
3442 dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
3443 domain_remove_one_dev_info(old_domain, pdev);
3445 domain_remove_dev_info(old_domain);
3449 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3454 /* check if this iommu agaw is sufficient for max mapped address */
3455 addr_width = agaw_to_width(iommu->agaw);
3456 end = DOMAIN_MAX_ADDR(addr_width);
3457 end = end & VTD_PAGE_MASK;
3458 if (end < dmar_domain->max_addr) {
3459 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3460 "sufficient for the mapped address (%llx)\n",
3461 __func__, iommu->agaw, dmar_domain->max_addr);
3465 ret = domain_add_dev_info(dmar_domain, pdev);
3469 ret = domain_context_mapping(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
3473 static void intel_iommu_detach_device(struct iommu_domain *domain,
3476 struct dmar_domain *dmar_domain = domain->priv;
3477 struct pci_dev *pdev = to_pci_dev(dev);
3479 domain_remove_one_dev_info(dmar_domain, pdev);
3482 static int intel_iommu_map_range(struct iommu_domain *domain,
3483 unsigned long iova, phys_addr_t hpa,
3484 size_t size, int iommu_prot)
3486 struct dmar_domain *dmar_domain = domain->priv;
3492 if (iommu_prot & IOMMU_READ)
3493 prot |= DMA_PTE_READ;
3494 if (iommu_prot & IOMMU_WRITE)
3495 prot |= DMA_PTE_WRITE;
3496 if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
3497 prot |= DMA_PTE_SNP;
3499 max_addr = (iova & VTD_PAGE_MASK) + VTD_PAGE_ALIGN(size);
3500 if (dmar_domain->max_addr < max_addr) {
3504 /* check if minimum agaw is sufficient for mapped address */
3505 min_agaw = vm_domain_min_agaw(dmar_domain);
3506 addr_width = agaw_to_width(min_agaw);
3507 end = DOMAIN_MAX_ADDR(addr_width);
3508 end = end & VTD_PAGE_MASK;
3509 if (end < max_addr) {
3510 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3511 "sufficient for the mapped address (%llx)\n",
3512 __func__, min_agaw, max_addr);
3515 dmar_domain->max_addr = max_addr;
3518 ret = domain_page_mapping(dmar_domain, iova, hpa, size, prot);
3522 static void intel_iommu_unmap_range(struct iommu_domain *domain,
3523 unsigned long iova, size_t size)
3525 struct dmar_domain *dmar_domain = domain->priv;
3528 /* The address might not be aligned */
3529 base = iova & VTD_PAGE_MASK;
3530 size = VTD_PAGE_ALIGN(size);
3531 dma_pte_clear_range(dmar_domain, base, base + size);
3533 if (dmar_domain->max_addr == base + size)
3534 dmar_domain->max_addr = base;
3537 static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
3540 struct dmar_domain *dmar_domain = domain->priv;
3541 struct dma_pte *pte;
3544 pte = addr_to_dma_pte(dmar_domain, iova);
3546 phys = dma_pte_addr(pte);
3551 static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
3554 struct dmar_domain *dmar_domain = domain->priv;
3556 if (cap == IOMMU_CAP_CACHE_COHERENCY)
3557 return dmar_domain->iommu_snooping;
3562 static struct iommu_ops intel_iommu_ops = {
3563 .domain_init = intel_iommu_domain_init,
3564 .domain_destroy = intel_iommu_domain_destroy,
3565 .attach_dev = intel_iommu_attach_device,
3566 .detach_dev = intel_iommu_detach_device,
3567 .map = intel_iommu_map_range,
3568 .unmap = intel_iommu_unmap_range,
3569 .iova_to_phys = intel_iommu_iova_to_phys,
3570 .domain_has_cap = intel_iommu_domain_has_cap,
3573 static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
3576 * Mobile 4 Series Chipset neglects to set RWBF capability,
3579 printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
3583 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);