2 * Copyright (c) 2006, Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Shaohua Li <shaohua.li@intel.com>
20 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
21 * Author: Fenghua Yu <fenghua.yu@intel.com>
24 #include <linux/init.h>
25 #include <linux/bitmap.h>
26 #include <linux/debugfs.h>
27 #include <linux/slab.h>
28 #include <linux/irq.h>
29 #include <linux/interrupt.h>
30 #include <linux/spinlock.h>
31 #include <linux/pci.h>
32 #include <linux/dmar.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/mempool.h>
35 #include <linux/timer.h>
36 #include <linux/iova.h>
37 #include <linux/iommu.h>
38 #include <linux/intel-iommu.h>
39 #include <linux/sysdev.h>
40 #include <asm/cacheflush.h>
41 #include <asm/iommu.h>
44 #define ROOT_SIZE VTD_PAGE_SIZE
45 #define CONTEXT_SIZE VTD_PAGE_SIZE
47 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
48 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
50 #define IOAPIC_RANGE_START (0xfee00000)
51 #define IOAPIC_RANGE_END (0xfeefffff)
52 #define IOVA_START_ADDR (0x1000)
54 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
56 #define MAX_AGAW_WIDTH 64
58 #define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1)
60 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
61 #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
62 #define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
64 /* global iommu list, set NULL for ignored DMAR units */
65 static struct intel_iommu **g_iommus;
67 static int rwbf_quirk;
72 * 12-63: Context Ptr (12 - (haw-1))
79 #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
80 static inline bool root_present(struct root_entry *root)
82 return (root->val & 1);
84 static inline void set_root_present(struct root_entry *root)
88 static inline void set_root_value(struct root_entry *root, unsigned long value)
90 root->val |= value & VTD_PAGE_MASK;
93 static inline struct context_entry *
94 get_context_addr_from_root(struct root_entry *root)
96 return (struct context_entry *)
97 (root_present(root)?phys_to_virt(
98 root->val & VTD_PAGE_MASK) :
105 * 1: fault processing disable
106 * 2-3: translation type
107 * 12-63: address space root
113 struct context_entry {
118 static inline bool context_present(struct context_entry *context)
120 return (context->lo & 1);
122 static inline void context_set_present(struct context_entry *context)
127 static inline void context_set_fault_enable(struct context_entry *context)
129 context->lo &= (((u64)-1) << 2) | 1;
132 static inline void context_set_translation_type(struct context_entry *context,
135 context->lo &= (((u64)-1) << 4) | 3;
136 context->lo |= (value & 3) << 2;
139 static inline void context_set_address_root(struct context_entry *context,
142 context->lo |= value & VTD_PAGE_MASK;
145 static inline void context_set_address_width(struct context_entry *context,
148 context->hi |= value & 7;
151 static inline void context_set_domain_id(struct context_entry *context,
154 context->hi |= (value & ((1 << 16) - 1)) << 8;
157 static inline void context_clear_entry(struct context_entry *context)
170 * 12-63: Host physcial address
176 static inline void dma_clear_pte(struct dma_pte *pte)
181 static inline void dma_set_pte_readable(struct dma_pte *pte)
183 pte->val |= DMA_PTE_READ;
186 static inline void dma_set_pte_writable(struct dma_pte *pte)
188 pte->val |= DMA_PTE_WRITE;
191 static inline void dma_set_pte_snp(struct dma_pte *pte)
193 pte->val |= DMA_PTE_SNP;
196 static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
198 pte->val = (pte->val & ~3) | (prot & 3);
201 static inline u64 dma_pte_addr(struct dma_pte *pte)
203 return (pte->val & VTD_PAGE_MASK);
206 static inline void dma_set_pte_addr(struct dma_pte *pte, u64 addr)
208 pte->val |= (addr & VTD_PAGE_MASK);
211 static inline bool dma_pte_present(struct dma_pte *pte)
213 return (pte->val & 3) != 0;
216 /* devices under the same p2p bridge are owned in one domain */
217 #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
219 /* domain represents a virtual machine, more than one devices
220 * across iommus may be owned in one domain, e.g. kvm guest.
222 #define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1)
225 int id; /* domain id */
226 unsigned long iommu_bmp; /* bitmap of iommus this domain uses*/
228 struct list_head devices; /* all devices' list */
229 struct iova_domain iovad; /* iova's that belong to this domain */
231 struct dma_pte *pgd; /* virtual address */
232 spinlock_t mapping_lock; /* page table lock */
233 int gaw; /* max guest address width */
235 /* adjusted guest address width, 0 is level 2 30-bit */
238 int flags; /* flags to find out type of domain */
240 int iommu_coherency;/* indicate coherency of iommu access */
241 int iommu_snooping; /* indicate snooping control feature*/
242 int iommu_count; /* reference count of iommu */
243 spinlock_t iommu_lock; /* protect iommu set in domain */
244 u64 max_addr; /* maximum mapped address */
247 /* PCI domain-device relationship */
248 struct device_domain_info {
249 struct list_head link; /* link to domain siblings */
250 struct list_head global; /* link to global list */
251 int segment; /* PCI domain */
252 u8 bus; /* PCI bus number */
253 u8 devfn; /* PCI devfn number */
254 struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
255 struct dmar_domain *domain; /* pointer to domain */
258 static void flush_unmaps_timeout(unsigned long data);
260 DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
262 #define HIGH_WATER_MARK 250
263 struct deferred_flush_tables {
265 struct iova *iova[HIGH_WATER_MARK];
266 struct dmar_domain *domain[HIGH_WATER_MARK];
269 static struct deferred_flush_tables *deferred_flush;
271 /* bitmap for indexing intel_iommus */
272 static int g_num_of_iommus;
274 static DEFINE_SPINLOCK(async_umap_flush_lock);
275 static LIST_HEAD(unmaps_to_do);
278 static long list_size;
280 static void domain_remove_dev_info(struct dmar_domain *domain);
282 #ifdef CONFIG_DMAR_DEFAULT_ON
283 int dmar_disabled = 0;
285 int dmar_disabled = 1;
286 #endif /*CONFIG_DMAR_DEFAULT_ON*/
288 static int __initdata dmar_map_gfx = 1;
289 static int dmar_forcedac;
290 static int intel_iommu_strict;
292 #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
293 static DEFINE_SPINLOCK(device_domain_lock);
294 static LIST_HEAD(device_domain_list);
296 static struct iommu_ops intel_iommu_ops;
298 static int __init intel_iommu_setup(char *str)
303 if (!strncmp(str, "on", 2)) {
305 printk(KERN_INFO "Intel-IOMMU: enabled\n");
306 } else if (!strncmp(str, "off", 3)) {
308 printk(KERN_INFO "Intel-IOMMU: disabled\n");
309 } else if (!strncmp(str, "igfx_off", 8)) {
312 "Intel-IOMMU: disable GFX device mapping\n");
313 } else if (!strncmp(str, "forcedac", 8)) {
315 "Intel-IOMMU: Forcing DAC for PCI devices\n");
317 } else if (!strncmp(str, "strict", 6)) {
319 "Intel-IOMMU: disable batched IOTLB flush\n");
320 intel_iommu_strict = 1;
323 str += strcspn(str, ",");
329 __setup("intel_iommu=", intel_iommu_setup);
331 static struct kmem_cache *iommu_domain_cache;
332 static struct kmem_cache *iommu_devinfo_cache;
333 static struct kmem_cache *iommu_iova_cache;
335 static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep)
340 /* trying to avoid low memory issues */
341 flags = current->flags & PF_MEMALLOC;
342 current->flags |= PF_MEMALLOC;
343 vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC);
344 current->flags &= (~PF_MEMALLOC | flags);
349 static inline void *alloc_pgtable_page(void)
354 /* trying to avoid low memory issues */
355 flags = current->flags & PF_MEMALLOC;
356 current->flags |= PF_MEMALLOC;
357 vaddr = (void *)get_zeroed_page(GFP_ATOMIC);
358 current->flags &= (~PF_MEMALLOC | flags);
362 static inline void free_pgtable_page(void *vaddr)
364 free_page((unsigned long)vaddr);
367 static inline void *alloc_domain_mem(void)
369 return iommu_kmem_cache_alloc(iommu_domain_cache);
372 static void free_domain_mem(void *vaddr)
374 kmem_cache_free(iommu_domain_cache, vaddr);
377 static inline void * alloc_devinfo_mem(void)
379 return iommu_kmem_cache_alloc(iommu_devinfo_cache);
382 static inline void free_devinfo_mem(void *vaddr)
384 kmem_cache_free(iommu_devinfo_cache, vaddr);
387 struct iova *alloc_iova_mem(void)
389 return iommu_kmem_cache_alloc(iommu_iova_cache);
392 void free_iova_mem(struct iova *iova)
394 kmem_cache_free(iommu_iova_cache, iova);
398 static inline int width_to_agaw(int width);
400 static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
405 sagaw = cap_sagaw(iommu->cap);
406 for (agaw = width_to_agaw(max_gaw);
408 if (test_bit(agaw, &sagaw))
416 * Calculate max SAGAW for each iommu.
418 int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
420 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
424 * calculate agaw for each iommu.
425 * "SAGAW" may be different across iommus, use a default agaw, and
426 * get a supported less agaw for iommus that don't support the default agaw.
428 int iommu_calculate_agaw(struct intel_iommu *iommu)
430 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
433 /* in native case, each domain is related to only one iommu */
434 static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
438 BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
440 iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
441 if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
444 return g_iommus[iommu_id];
447 static void domain_update_iommu_coherency(struct dmar_domain *domain)
451 domain->iommu_coherency = 1;
453 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
454 for (; i < g_num_of_iommus; ) {
455 if (!ecap_coherent(g_iommus[i]->ecap)) {
456 domain->iommu_coherency = 0;
459 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
463 static void domain_update_iommu_snooping(struct dmar_domain *domain)
467 domain->iommu_snooping = 1;
469 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
470 for (; i < g_num_of_iommus; ) {
471 if (!ecap_sc_support(g_iommus[i]->ecap)) {
472 domain->iommu_snooping = 0;
475 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
479 /* Some capabilities may be different across iommus */
480 static void domain_update_iommu_cap(struct dmar_domain *domain)
482 domain_update_iommu_coherency(domain);
483 domain_update_iommu_snooping(domain);
486 static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
488 struct dmar_drhd_unit *drhd = NULL;
491 for_each_drhd_unit(drhd) {
494 if (segment != drhd->segment)
497 for (i = 0; i < drhd->devices_cnt; i++) {
498 if (drhd->devices[i] &&
499 drhd->devices[i]->bus->number == bus &&
500 drhd->devices[i]->devfn == devfn)
502 if (drhd->devices[i] &&
503 drhd->devices[i]->subordinate &&
504 drhd->devices[i]->subordinate->number <= bus &&
505 drhd->devices[i]->subordinate->subordinate >= bus)
509 if (drhd->include_all)
516 static void domain_flush_cache(struct dmar_domain *domain,
517 void *addr, int size)
519 if (!domain->iommu_coherency)
520 clflush_cache_range(addr, size);
523 /* Gets context entry for a given bus and devfn */
524 static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
527 struct root_entry *root;
528 struct context_entry *context;
529 unsigned long phy_addr;
532 spin_lock_irqsave(&iommu->lock, flags);
533 root = &iommu->root_entry[bus];
534 context = get_context_addr_from_root(root);
536 context = (struct context_entry *)alloc_pgtable_page();
538 spin_unlock_irqrestore(&iommu->lock, flags);
541 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
542 phy_addr = virt_to_phys((void *)context);
543 set_root_value(root, phy_addr);
544 set_root_present(root);
545 __iommu_flush_cache(iommu, root, sizeof(*root));
547 spin_unlock_irqrestore(&iommu->lock, flags);
548 return &context[devfn];
551 static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
553 struct root_entry *root;
554 struct context_entry *context;
558 spin_lock_irqsave(&iommu->lock, flags);
559 root = &iommu->root_entry[bus];
560 context = get_context_addr_from_root(root);
565 ret = context_present(&context[devfn]);
567 spin_unlock_irqrestore(&iommu->lock, flags);
571 static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
573 struct root_entry *root;
574 struct context_entry *context;
577 spin_lock_irqsave(&iommu->lock, flags);
578 root = &iommu->root_entry[bus];
579 context = get_context_addr_from_root(root);
581 context_clear_entry(&context[devfn]);
582 __iommu_flush_cache(iommu, &context[devfn], \
585 spin_unlock_irqrestore(&iommu->lock, flags);
588 static void free_context_table(struct intel_iommu *iommu)
590 struct root_entry *root;
593 struct context_entry *context;
595 spin_lock_irqsave(&iommu->lock, flags);
596 if (!iommu->root_entry) {
599 for (i = 0; i < ROOT_ENTRY_NR; i++) {
600 root = &iommu->root_entry[i];
601 context = get_context_addr_from_root(root);
603 free_pgtable_page(context);
605 free_pgtable_page(iommu->root_entry);
606 iommu->root_entry = NULL;
608 spin_unlock_irqrestore(&iommu->lock, flags);
611 /* page table handling */
612 #define LEVEL_STRIDE (9)
613 #define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
615 static inline int agaw_to_level(int agaw)
620 static inline int agaw_to_width(int agaw)
622 return 30 + agaw * LEVEL_STRIDE;
626 static inline int width_to_agaw(int width)
628 return (width - 30) / LEVEL_STRIDE;
631 static inline unsigned int level_to_offset_bits(int level)
633 return (12 + (level - 1) * LEVEL_STRIDE);
636 static inline int address_level_offset(u64 addr, int level)
638 return ((addr >> level_to_offset_bits(level)) & LEVEL_MASK);
641 static inline u64 level_mask(int level)
643 return ((u64)-1 << level_to_offset_bits(level));
646 static inline u64 level_size(int level)
648 return ((u64)1 << level_to_offset_bits(level));
651 static inline u64 align_to_level(u64 addr, int level)
653 return ((addr + level_size(level) - 1) & level_mask(level));
656 static struct dma_pte * addr_to_dma_pte(struct dmar_domain *domain, u64 addr)
658 int addr_width = agaw_to_width(domain->agaw);
659 struct dma_pte *parent, *pte = NULL;
660 int level = agaw_to_level(domain->agaw);
664 BUG_ON(!domain->pgd);
666 addr &= (((u64)1) << addr_width) - 1;
667 parent = domain->pgd;
669 spin_lock_irqsave(&domain->mapping_lock, flags);
673 offset = address_level_offset(addr, level);
674 pte = &parent[offset];
678 if (!dma_pte_present(pte)) {
679 tmp_page = alloc_pgtable_page();
682 spin_unlock_irqrestore(&domain->mapping_lock,
686 domain_flush_cache(domain, tmp_page, PAGE_SIZE);
687 dma_set_pte_addr(pte, virt_to_phys(tmp_page));
689 * high level table always sets r/w, last level page
690 * table control read/write
692 dma_set_pte_readable(pte);
693 dma_set_pte_writable(pte);
694 domain_flush_cache(domain, pte, sizeof(*pte));
696 parent = phys_to_virt(dma_pte_addr(pte));
700 spin_unlock_irqrestore(&domain->mapping_lock, flags);
704 /* return address's pte at specific level */
705 static struct dma_pte *dma_addr_level_pte(struct dmar_domain *domain, u64 addr,
708 struct dma_pte *parent, *pte = NULL;
709 int total = agaw_to_level(domain->agaw);
712 parent = domain->pgd;
713 while (level <= total) {
714 offset = address_level_offset(addr, total);
715 pte = &parent[offset];
719 if (!dma_pte_present(pte))
721 parent = phys_to_virt(dma_pte_addr(pte));
727 /* clear one page's page table */
728 static void dma_pte_clear_one(struct dmar_domain *domain, u64 addr)
730 struct dma_pte *pte = NULL;
732 /* get last level pte */
733 pte = dma_addr_level_pte(domain, addr, 1);
737 domain_flush_cache(domain, pte, sizeof(*pte));
741 /* clear last level pte, a tlb flush should be followed */
742 static void dma_pte_clear_range(struct dmar_domain *domain, u64 start, u64 end)
744 int addr_width = agaw_to_width(domain->agaw);
747 start &= (((u64)1) << addr_width) - 1;
748 end &= (((u64)1) << addr_width) - 1;
749 /* in case it's partial page */
751 end = PAGE_ALIGN(end);
752 npages = (end - start) / VTD_PAGE_SIZE;
754 /* we don't need lock here, nobody else touches the iova range */
756 dma_pte_clear_one(domain, start);
757 start += VTD_PAGE_SIZE;
761 /* free page table pages. last level pte should already be cleared */
762 static void dma_pte_free_pagetable(struct dmar_domain *domain,
765 int addr_width = agaw_to_width(domain->agaw);
767 int total = agaw_to_level(domain->agaw);
771 start &= (((u64)1) << addr_width) - 1;
772 end &= (((u64)1) << addr_width) - 1;
774 /* we don't need lock here, nobody else touches the iova range */
776 while (level <= total) {
777 tmp = align_to_level(start, level);
778 if (tmp >= end || (tmp + level_size(level) > end))
782 pte = dma_addr_level_pte(domain, tmp, level);
785 phys_to_virt(dma_pte_addr(pte)));
787 domain_flush_cache(domain, pte, sizeof(*pte));
789 tmp += level_size(level);
794 if (start == 0 && end >= ((((u64)1) << addr_width) - 1)) {
795 free_pgtable_page(domain->pgd);
801 static int iommu_alloc_root_entry(struct intel_iommu *iommu)
803 struct root_entry *root;
806 root = (struct root_entry *)alloc_pgtable_page();
810 __iommu_flush_cache(iommu, root, ROOT_SIZE);
812 spin_lock_irqsave(&iommu->lock, flags);
813 iommu->root_entry = root;
814 spin_unlock_irqrestore(&iommu->lock, flags);
819 static void iommu_set_root_entry(struct intel_iommu *iommu)
825 addr = iommu->root_entry;
827 spin_lock_irqsave(&iommu->register_lock, flag);
828 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
830 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
832 /* Make sure hardware complete it */
833 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
834 readl, (sts & DMA_GSTS_RTPS), sts);
836 spin_unlock_irqrestore(&iommu->register_lock, flag);
839 static void iommu_flush_write_buffer(struct intel_iommu *iommu)
844 if (!rwbf_quirk && !cap_rwbf(iommu->cap))
847 spin_lock_irqsave(&iommu->register_lock, flag);
848 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
850 /* Make sure hardware complete it */
851 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
852 readl, (!(val & DMA_GSTS_WBFS)), val);
854 spin_unlock_irqrestore(&iommu->register_lock, flag);
857 /* return value determine if we need a write buffer flush */
858 static void __iommu_flush_context(struct intel_iommu *iommu,
859 u16 did, u16 source_id, u8 function_mask,
866 case DMA_CCMD_GLOBAL_INVL:
867 val = DMA_CCMD_GLOBAL_INVL;
869 case DMA_CCMD_DOMAIN_INVL:
870 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
872 case DMA_CCMD_DEVICE_INVL:
873 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
874 | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
881 spin_lock_irqsave(&iommu->register_lock, flag);
882 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
884 /* Make sure hardware complete it */
885 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
886 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
888 spin_unlock_irqrestore(&iommu->register_lock, flag);
891 /* return value determine if we need a write buffer flush */
892 static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
893 u64 addr, unsigned int size_order, u64 type)
895 int tlb_offset = ecap_iotlb_offset(iommu->ecap);
896 u64 val = 0, val_iva = 0;
900 case DMA_TLB_GLOBAL_FLUSH:
901 /* global flush doesn't need set IVA_REG */
902 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
904 case DMA_TLB_DSI_FLUSH:
905 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
907 case DMA_TLB_PSI_FLUSH:
908 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
909 /* Note: always flush non-leaf currently */
910 val_iva = size_order | addr;
915 /* Note: set drain read/write */
918 * This is probably to be super secure.. Looks like we can
919 * ignore it without any impact.
921 if (cap_read_drain(iommu->cap))
922 val |= DMA_TLB_READ_DRAIN;
924 if (cap_write_drain(iommu->cap))
925 val |= DMA_TLB_WRITE_DRAIN;
927 spin_lock_irqsave(&iommu->register_lock, flag);
928 /* Note: Only uses first TLB reg currently */
930 dmar_writeq(iommu->reg + tlb_offset, val_iva);
931 dmar_writeq(iommu->reg + tlb_offset + 8, val);
933 /* Make sure hardware complete it */
934 IOMMU_WAIT_OP(iommu, tlb_offset + 8,
935 dmar_readq, (!(val & DMA_TLB_IVT)), val);
937 spin_unlock_irqrestore(&iommu->register_lock, flag);
939 /* check IOTLB invalidation granularity */
940 if (DMA_TLB_IAIG(val) == 0)
941 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
942 if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
943 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
944 (unsigned long long)DMA_TLB_IIRG(type),
945 (unsigned long long)DMA_TLB_IAIG(val));
948 static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
949 u64 addr, unsigned int pages)
951 unsigned int mask = ilog2(__roundup_pow_of_two(pages));
953 BUG_ON(addr & (~VTD_PAGE_MASK));
957 * Fallback to domain selective flush if no PSI support or the size is
959 * PSI requires page size to be 2 ^ x, and the base address is naturally
960 * aligned to the size
962 if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
963 iommu->flush.flush_iotlb(iommu, did, 0, 0,
966 iommu->flush.flush_iotlb(iommu, did, addr, mask,
970 static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
975 spin_lock_irqsave(&iommu->register_lock, flags);
976 pmen = readl(iommu->reg + DMAR_PMEN_REG);
977 pmen &= ~DMA_PMEN_EPM;
978 writel(pmen, iommu->reg + DMAR_PMEN_REG);
980 /* wait for the protected region status bit to clear */
981 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
982 readl, !(pmen & DMA_PMEN_PRS), pmen);
984 spin_unlock_irqrestore(&iommu->register_lock, flags);
987 static int iommu_enable_translation(struct intel_iommu *iommu)
992 spin_lock_irqsave(&iommu->register_lock, flags);
993 iommu->gcmd |= DMA_GCMD_TE;
994 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
996 /* Make sure hardware complete it */
997 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
998 readl, (sts & DMA_GSTS_TES), sts);
1000 spin_unlock_irqrestore(&iommu->register_lock, flags);
1004 static int iommu_disable_translation(struct intel_iommu *iommu)
1009 spin_lock_irqsave(&iommu->register_lock, flag);
1010 iommu->gcmd &= ~DMA_GCMD_TE;
1011 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1013 /* Make sure hardware complete it */
1014 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1015 readl, (!(sts & DMA_GSTS_TES)), sts);
1017 spin_unlock_irqrestore(&iommu->register_lock, flag);
1022 static int iommu_init_domains(struct intel_iommu *iommu)
1024 unsigned long ndomains;
1025 unsigned long nlongs;
1027 ndomains = cap_ndoms(iommu->cap);
1028 pr_debug("Number of Domains supportd <%ld>\n", ndomains);
1029 nlongs = BITS_TO_LONGS(ndomains);
1031 /* TBD: there might be 64K domains,
1032 * consider other allocation for future chip
1034 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1035 if (!iommu->domain_ids) {
1036 printk(KERN_ERR "Allocating domain id array failed\n");
1039 iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1041 if (!iommu->domains) {
1042 printk(KERN_ERR "Allocating domain array failed\n");
1043 kfree(iommu->domain_ids);
1047 spin_lock_init(&iommu->lock);
1050 * if Caching mode is set, then invalid translations are tagged
1051 * with domainid 0. Hence we need to pre-allocate it.
1053 if (cap_caching_mode(iommu->cap))
1054 set_bit(0, iommu->domain_ids);
1059 static void domain_exit(struct dmar_domain *domain);
1060 static void vm_domain_exit(struct dmar_domain *domain);
1062 void free_dmar_iommu(struct intel_iommu *iommu)
1064 struct dmar_domain *domain;
1066 unsigned long flags;
1068 i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap));
1069 for (; i < cap_ndoms(iommu->cap); ) {
1070 domain = iommu->domains[i];
1071 clear_bit(i, iommu->domain_ids);
1073 spin_lock_irqsave(&domain->iommu_lock, flags);
1074 if (--domain->iommu_count == 0) {
1075 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1076 vm_domain_exit(domain);
1078 domain_exit(domain);
1080 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1082 i = find_next_bit(iommu->domain_ids,
1083 cap_ndoms(iommu->cap), i+1);
1086 if (iommu->gcmd & DMA_GCMD_TE)
1087 iommu_disable_translation(iommu);
1090 set_irq_data(iommu->irq, NULL);
1091 /* This will mask the irq */
1092 free_irq(iommu->irq, iommu);
1093 destroy_irq(iommu->irq);
1096 kfree(iommu->domains);
1097 kfree(iommu->domain_ids);
1099 g_iommus[iommu->seq_id] = NULL;
1101 /* if all iommus are freed, free g_iommus */
1102 for (i = 0; i < g_num_of_iommus; i++) {
1107 if (i == g_num_of_iommus)
1110 /* free context mapping */
1111 free_context_table(iommu);
1114 static struct dmar_domain * iommu_alloc_domain(struct intel_iommu *iommu)
1117 unsigned long ndomains;
1118 struct dmar_domain *domain;
1119 unsigned long flags;
1121 domain = alloc_domain_mem();
1125 ndomains = cap_ndoms(iommu->cap);
1127 spin_lock_irqsave(&iommu->lock, flags);
1128 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1129 if (num >= ndomains) {
1130 spin_unlock_irqrestore(&iommu->lock, flags);
1131 free_domain_mem(domain);
1132 printk(KERN_ERR "IOMMU: no free domain ids\n");
1136 set_bit(num, iommu->domain_ids);
1138 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
1139 set_bit(iommu->seq_id, &domain->iommu_bmp);
1141 iommu->domains[num] = domain;
1142 spin_unlock_irqrestore(&iommu->lock, flags);
1147 static void iommu_free_domain(struct dmar_domain *domain)
1149 unsigned long flags;
1150 struct intel_iommu *iommu;
1152 iommu = domain_get_iommu(domain);
1154 spin_lock_irqsave(&iommu->lock, flags);
1155 clear_bit(domain->id, iommu->domain_ids);
1156 spin_unlock_irqrestore(&iommu->lock, flags);
1159 static struct iova_domain reserved_iova_list;
1160 static struct lock_class_key reserved_alloc_key;
1161 static struct lock_class_key reserved_rbtree_key;
1163 static void dmar_init_reserved_ranges(void)
1165 struct pci_dev *pdev = NULL;
1170 init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
1172 lockdep_set_class(&reserved_iova_list.iova_alloc_lock,
1173 &reserved_alloc_key);
1174 lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1175 &reserved_rbtree_key);
1177 /* IOAPIC ranges shouldn't be accessed by DMA */
1178 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1179 IOVA_PFN(IOAPIC_RANGE_END));
1181 printk(KERN_ERR "Reserve IOAPIC range failed\n");
1183 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1184 for_each_pci_dev(pdev) {
1187 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1188 r = &pdev->resource[i];
1189 if (!r->flags || !(r->flags & IORESOURCE_MEM))
1193 size = r->end - addr;
1194 size = PAGE_ALIGN(size);
1195 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(addr),
1196 IOVA_PFN(size + addr) - 1);
1198 printk(KERN_ERR "Reserve iova failed\n");
1204 static void domain_reserve_special_ranges(struct dmar_domain *domain)
1206 copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1209 static inline int guestwidth_to_adjustwidth(int gaw)
1212 int r = (gaw - 12) % 9;
1223 static int domain_init(struct dmar_domain *domain, int guest_width)
1225 struct intel_iommu *iommu;
1226 int adjust_width, agaw;
1227 unsigned long sagaw;
1229 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
1230 spin_lock_init(&domain->mapping_lock);
1231 spin_lock_init(&domain->iommu_lock);
1233 domain_reserve_special_ranges(domain);
1235 /* calculate AGAW */
1236 iommu = domain_get_iommu(domain);
1237 if (guest_width > cap_mgaw(iommu->cap))
1238 guest_width = cap_mgaw(iommu->cap);
1239 domain->gaw = guest_width;
1240 adjust_width = guestwidth_to_adjustwidth(guest_width);
1241 agaw = width_to_agaw(adjust_width);
1242 sagaw = cap_sagaw(iommu->cap);
1243 if (!test_bit(agaw, &sagaw)) {
1244 /* hardware doesn't support it, choose a bigger one */
1245 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1246 agaw = find_next_bit(&sagaw, 5, agaw);
1250 domain->agaw = agaw;
1251 INIT_LIST_HEAD(&domain->devices);
1253 if (ecap_coherent(iommu->ecap))
1254 domain->iommu_coherency = 1;
1256 domain->iommu_coherency = 0;
1258 if (ecap_sc_support(iommu->ecap))
1259 domain->iommu_snooping = 1;
1261 domain->iommu_snooping = 0;
1263 domain->iommu_count = 1;
1265 /* always allocate the top pgd */
1266 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
1269 __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
1273 static void domain_exit(struct dmar_domain *domain)
1277 /* Domain 0 is reserved, so dont process it */
1281 domain_remove_dev_info(domain);
1283 put_iova_domain(&domain->iovad);
1284 end = DOMAIN_MAX_ADDR(domain->gaw);
1285 end = end & (~PAGE_MASK);
1288 dma_pte_clear_range(domain, 0, end);
1290 /* free page tables */
1291 dma_pte_free_pagetable(domain, 0, end);
1293 iommu_free_domain(domain);
1294 free_domain_mem(domain);
1297 static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1298 u8 bus, u8 devfn, int translation)
1300 struct context_entry *context;
1301 unsigned long flags;
1302 struct intel_iommu *iommu;
1303 struct dma_pte *pgd;
1305 unsigned long ndomains;
1309 pr_debug("Set context mapping for %02x:%02x.%d\n",
1310 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1312 BUG_ON(!domain->pgd);
1313 BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1314 translation != CONTEXT_TT_MULTI_LEVEL);
1316 iommu = device_to_iommu(segment, bus, devfn);
1320 context = device_to_context_entry(iommu, bus, devfn);
1323 spin_lock_irqsave(&iommu->lock, flags);
1324 if (context_present(context)) {
1325 spin_unlock_irqrestore(&iommu->lock, flags);
1332 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) {
1335 /* find an available domain id for this device in iommu */
1336 ndomains = cap_ndoms(iommu->cap);
1337 num = find_first_bit(iommu->domain_ids, ndomains);
1338 for (; num < ndomains; ) {
1339 if (iommu->domains[num] == domain) {
1344 num = find_next_bit(iommu->domain_ids,
1345 cap_ndoms(iommu->cap), num+1);
1349 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1350 if (num >= ndomains) {
1351 spin_unlock_irqrestore(&iommu->lock, flags);
1352 printk(KERN_ERR "IOMMU: no free domain ids\n");
1356 set_bit(num, iommu->domain_ids);
1357 iommu->domains[num] = domain;
1361 /* Skip top levels of page tables for
1362 * iommu which has less agaw than default.
1364 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1365 pgd = phys_to_virt(dma_pte_addr(pgd));
1366 if (!dma_pte_present(pgd)) {
1367 spin_unlock_irqrestore(&iommu->lock, flags);
1373 context_set_domain_id(context, id);
1376 * In pass through mode, AW must be programmed to indicate the largest
1377 * AGAW value supported by hardware. And ASR is ignored by hardware.
1379 if (likely(translation == CONTEXT_TT_MULTI_LEVEL)) {
1380 context_set_address_width(context, iommu->agaw);
1381 context_set_address_root(context, virt_to_phys(pgd));
1383 context_set_address_width(context, iommu->msagaw);
1385 context_set_translation_type(context, translation);
1386 context_set_fault_enable(context);
1387 context_set_present(context);
1388 domain_flush_cache(domain, context, sizeof(*context));
1391 * It's a non-present to present mapping. If hardware doesn't cache
1392 * non-present entry we only need to flush the write-buffer. If the
1393 * _does_ cache non-present entries, then it does so in the special
1394 * domain #0, which we have to flush:
1396 if (cap_caching_mode(iommu->cap)) {
1397 iommu->flush.flush_context(iommu, 0,
1398 (((u16)bus) << 8) | devfn,
1399 DMA_CCMD_MASK_NOBIT,
1400 DMA_CCMD_DEVICE_INVL);
1401 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH);
1403 iommu_flush_write_buffer(iommu);
1405 spin_unlock_irqrestore(&iommu->lock, flags);
1407 spin_lock_irqsave(&domain->iommu_lock, flags);
1408 if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
1409 domain->iommu_count++;
1410 domain_update_iommu_cap(domain);
1412 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1417 domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1421 struct pci_dev *tmp, *parent;
1423 ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
1424 pdev->bus->number, pdev->devfn,
1429 /* dependent device mapping */
1430 tmp = pci_find_upstream_pcie_bridge(pdev);
1433 /* Secondary interface's bus number and devfn 0 */
1434 parent = pdev->bus->self;
1435 while (parent != tmp) {
1436 ret = domain_context_mapping_one(domain,
1437 pci_domain_nr(parent->bus),
1438 parent->bus->number,
1439 parent->devfn, translation);
1442 parent = parent->bus->self;
1444 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
1445 return domain_context_mapping_one(domain,
1446 pci_domain_nr(tmp->subordinate),
1447 tmp->subordinate->number, 0,
1449 else /* this is a legacy PCI bridge */
1450 return domain_context_mapping_one(domain,
1451 pci_domain_nr(tmp->bus),
1457 static int domain_context_mapped(struct pci_dev *pdev)
1460 struct pci_dev *tmp, *parent;
1461 struct intel_iommu *iommu;
1463 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1468 ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
1471 /* dependent device mapping */
1472 tmp = pci_find_upstream_pcie_bridge(pdev);
1475 /* Secondary interface's bus number and devfn 0 */
1476 parent = pdev->bus->self;
1477 while (parent != tmp) {
1478 ret = device_context_mapped(iommu, parent->bus->number,
1482 parent = parent->bus->self;
1485 return device_context_mapped(iommu, tmp->subordinate->number,
1488 return device_context_mapped(iommu, tmp->bus->number,
1493 domain_page_mapping(struct dmar_domain *domain, dma_addr_t iova,
1494 u64 hpa, size_t size, int prot)
1496 u64 start_pfn, end_pfn;
1497 struct dma_pte *pte;
1499 int addr_width = agaw_to_width(domain->agaw);
1501 hpa &= (((u64)1) << addr_width) - 1;
1503 if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1506 start_pfn = ((u64)hpa) >> VTD_PAGE_SHIFT;
1507 end_pfn = (VTD_PAGE_ALIGN(((u64)hpa) + size)) >> VTD_PAGE_SHIFT;
1509 while (start_pfn < end_pfn) {
1510 pte = addr_to_dma_pte(domain, iova + VTD_PAGE_SIZE * index);
1513 /* We don't need lock here, nobody else
1514 * touches the iova range
1516 BUG_ON(dma_pte_addr(pte));
1517 dma_set_pte_addr(pte, start_pfn << VTD_PAGE_SHIFT);
1518 dma_set_pte_prot(pte, prot);
1519 if (prot & DMA_PTE_SNP)
1520 dma_set_pte_snp(pte);
1521 domain_flush_cache(domain, pte, sizeof(*pte));
1528 static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
1533 clear_context_table(iommu, bus, devfn);
1534 iommu->flush.flush_context(iommu, 0, 0, 0,
1535 DMA_CCMD_GLOBAL_INVL);
1536 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
1539 static void domain_remove_dev_info(struct dmar_domain *domain)
1541 struct device_domain_info *info;
1542 unsigned long flags;
1543 struct intel_iommu *iommu;
1545 spin_lock_irqsave(&device_domain_lock, flags);
1546 while (!list_empty(&domain->devices)) {
1547 info = list_entry(domain->devices.next,
1548 struct device_domain_info, link);
1549 list_del(&info->link);
1550 list_del(&info->global);
1552 info->dev->dev.archdata.iommu = NULL;
1553 spin_unlock_irqrestore(&device_domain_lock, flags);
1555 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
1556 iommu_detach_dev(iommu, info->bus, info->devfn);
1557 free_devinfo_mem(info);
1559 spin_lock_irqsave(&device_domain_lock, flags);
1561 spin_unlock_irqrestore(&device_domain_lock, flags);
1566 * Note: we use struct pci_dev->dev.archdata.iommu stores the info
1568 static struct dmar_domain *
1569 find_domain(struct pci_dev *pdev)
1571 struct device_domain_info *info;
1573 /* No lock here, assumes no domain exit in normal case */
1574 info = pdev->dev.archdata.iommu;
1576 return info->domain;
1580 /* domain is initialized */
1581 static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1583 struct dmar_domain *domain, *found = NULL;
1584 struct intel_iommu *iommu;
1585 struct dmar_drhd_unit *drhd;
1586 struct device_domain_info *info, *tmp;
1587 struct pci_dev *dev_tmp;
1588 unsigned long flags;
1589 int bus = 0, devfn = 0;
1592 domain = find_domain(pdev);
1596 segment = pci_domain_nr(pdev->bus);
1598 dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1600 if (dev_tmp->is_pcie) {
1601 bus = dev_tmp->subordinate->number;
1604 bus = dev_tmp->bus->number;
1605 devfn = dev_tmp->devfn;
1607 spin_lock_irqsave(&device_domain_lock, flags);
1608 list_for_each_entry(info, &device_domain_list, global) {
1609 if (info->segment == segment &&
1610 info->bus == bus && info->devfn == devfn) {
1611 found = info->domain;
1615 spin_unlock_irqrestore(&device_domain_lock, flags);
1616 /* pcie-pci bridge already has a domain, uses it */
1623 /* Allocate new domain for the device */
1624 drhd = dmar_find_matched_drhd_unit(pdev);
1626 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
1630 iommu = drhd->iommu;
1632 domain = iommu_alloc_domain(iommu);
1636 if (domain_init(domain, gaw)) {
1637 domain_exit(domain);
1641 /* register pcie-to-pci device */
1643 info = alloc_devinfo_mem();
1645 domain_exit(domain);
1648 info->segment = segment;
1650 info->devfn = devfn;
1652 info->domain = domain;
1653 /* This domain is shared by devices under p2p bridge */
1654 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
1656 /* pcie-to-pci bridge already has a domain, uses it */
1658 spin_lock_irqsave(&device_domain_lock, flags);
1659 list_for_each_entry(tmp, &device_domain_list, global) {
1660 if (tmp->segment == segment &&
1661 tmp->bus == bus && tmp->devfn == devfn) {
1662 found = tmp->domain;
1667 free_devinfo_mem(info);
1668 domain_exit(domain);
1671 list_add(&info->link, &domain->devices);
1672 list_add(&info->global, &device_domain_list);
1674 spin_unlock_irqrestore(&device_domain_lock, flags);
1678 info = alloc_devinfo_mem();
1681 info->segment = segment;
1682 info->bus = pdev->bus->number;
1683 info->devfn = pdev->devfn;
1685 info->domain = domain;
1686 spin_lock_irqsave(&device_domain_lock, flags);
1687 /* somebody is fast */
1688 found = find_domain(pdev);
1689 if (found != NULL) {
1690 spin_unlock_irqrestore(&device_domain_lock, flags);
1691 if (found != domain) {
1692 domain_exit(domain);
1695 free_devinfo_mem(info);
1698 list_add(&info->link, &domain->devices);
1699 list_add(&info->global, &device_domain_list);
1700 pdev->dev.archdata.iommu = info;
1701 spin_unlock_irqrestore(&device_domain_lock, flags);
1704 /* recheck it here, maybe others set it */
1705 return find_domain(pdev);
1708 static int iommu_prepare_identity_map(struct pci_dev *pdev,
1709 unsigned long long start,
1710 unsigned long long end)
1712 struct dmar_domain *domain;
1714 unsigned long long base;
1718 "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
1719 pci_name(pdev), start, end);
1720 /* page table init */
1721 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1725 /* The address might not be aligned */
1726 base = start & PAGE_MASK;
1728 size = PAGE_ALIGN(size);
1729 if (!reserve_iova(&domain->iovad, IOVA_PFN(base),
1730 IOVA_PFN(base + size) - 1)) {
1731 printk(KERN_ERR "IOMMU: reserve iova failed\n");
1736 pr_debug("Mapping reserved region %lx@%llx for %s\n",
1737 size, base, pci_name(pdev));
1739 * RMRR range might have overlap with physical memory range,
1742 dma_pte_clear_range(domain, base, base + size);
1744 ret = domain_page_mapping(domain, base, base, size,
1745 DMA_PTE_READ|DMA_PTE_WRITE);
1749 /* context entry init */
1750 ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
1754 domain_exit(domain);
1759 static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
1760 struct pci_dev *pdev)
1762 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
1764 return iommu_prepare_identity_map(pdev, rmrr->base_address,
1765 rmrr->end_address + 1);
1768 #ifdef CONFIG_DMAR_GFX_WA
1769 struct iommu_prepare_data {
1770 struct pci_dev *pdev;
1774 static int __init iommu_prepare_work_fn(unsigned long start_pfn,
1775 unsigned long end_pfn, void *datax)
1777 struct iommu_prepare_data *data;
1779 data = (struct iommu_prepare_data *)datax;
1781 data->ret = iommu_prepare_identity_map(data->pdev,
1782 start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT);
1787 static int __init iommu_prepare_with_active_regions(struct pci_dev *pdev)
1790 struct iommu_prepare_data data;
1795 for_each_online_node(nid) {
1796 work_with_active_regions(nid, iommu_prepare_work_fn, &data);
1803 static void __init iommu_prepare_gfx_mapping(void)
1805 struct pci_dev *pdev = NULL;
1808 for_each_pci_dev(pdev) {
1809 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO ||
1810 !IS_GFX_DEVICE(pdev))
1812 printk(KERN_INFO "IOMMU: gfx device %s 1-1 mapping\n",
1814 ret = iommu_prepare_with_active_regions(pdev);
1816 printk(KERN_ERR "IOMMU: mapping reserved region failed\n");
1819 #else /* !CONFIG_DMAR_GFX_WA */
1820 static inline void iommu_prepare_gfx_mapping(void)
1826 #ifdef CONFIG_DMAR_FLOPPY_WA
1827 static inline void iommu_prepare_isa(void)
1829 struct pci_dev *pdev;
1832 pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
1836 printk(KERN_INFO "IOMMU: Prepare 0-16M unity mapping for LPC\n");
1837 ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024);
1840 printk(KERN_ERR "IOMMU: Failed to create 0-64M identity map, "
1841 "floppy might not work\n");
1845 static inline void iommu_prepare_isa(void)
1849 #endif /* !CONFIG_DMAR_FLPY_WA */
1851 /* Initialize each context entry as pass through.*/
1852 static int __init init_context_pass_through(void)
1854 struct pci_dev *pdev = NULL;
1855 struct dmar_domain *domain;
1858 for_each_pci_dev(pdev) {
1859 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1860 ret = domain_context_mapping(domain, pdev,
1861 CONTEXT_TT_PASS_THROUGH);
1868 static int __init init_dmars(void)
1870 struct dmar_drhd_unit *drhd;
1871 struct dmar_rmrr_unit *rmrr;
1872 struct pci_dev *pdev;
1873 struct intel_iommu *iommu;
1875 int pass_through = 1;
1880 * initialize and program root entry to not present
1883 for_each_drhd_unit(drhd) {
1886 * lock not needed as this is only incremented in the single
1887 * threaded kernel __init code path all other access are read
1892 g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
1895 printk(KERN_ERR "Allocating global iommu array failed\n");
1900 deferred_flush = kzalloc(g_num_of_iommus *
1901 sizeof(struct deferred_flush_tables), GFP_KERNEL);
1902 if (!deferred_flush) {
1908 for_each_drhd_unit(drhd) {
1912 iommu = drhd->iommu;
1913 g_iommus[iommu->seq_id] = iommu;
1915 ret = iommu_init_domains(iommu);
1921 * we could share the same root & context tables
1922 * amoung all IOMMU's. Need to Split it later.
1924 ret = iommu_alloc_root_entry(iommu);
1926 printk(KERN_ERR "IOMMU: allocate root entry failed\n");
1929 if (!ecap_pass_through(iommu->ecap))
1932 if (iommu_pass_through)
1933 if (!pass_through) {
1935 "Pass Through is not supported by hardware.\n");
1936 iommu_pass_through = 0;
1940 * Start from the sane iommu hardware state.
1942 for_each_drhd_unit(drhd) {
1946 iommu = drhd->iommu;
1949 * If the queued invalidation is already initialized by us
1950 * (for example, while enabling interrupt-remapping) then
1951 * we got the things already rolling from a sane state.
1957 * Clear any previous faults.
1959 dmar_fault(-1, iommu);
1961 * Disable queued invalidation if supported and already enabled
1962 * before OS handover.
1964 dmar_disable_qi(iommu);
1967 for_each_drhd_unit(drhd) {
1971 iommu = drhd->iommu;
1973 if (dmar_enable_qi(iommu)) {
1975 * Queued Invalidate not enabled, use Register Based
1978 iommu->flush.flush_context = __iommu_flush_context;
1979 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
1980 printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
1982 (unsigned long long)drhd->reg_base_addr);
1984 iommu->flush.flush_context = qi_flush_context;
1985 iommu->flush.flush_iotlb = qi_flush_iotlb;
1986 printk(KERN_INFO "IOMMU 0x%Lx: using Queued "
1988 (unsigned long long)drhd->reg_base_addr);
1992 #ifdef CONFIG_INTR_REMAP
1993 if (!intr_remapping_enabled) {
1994 ret = enable_intr_remapping(0);
1997 "IOMMU: enable interrupt remapping failed\n");
2001 * If pass through is set and enabled, context entries of all pci
2002 * devices are intialized by pass through translation type.
2004 if (iommu_pass_through) {
2005 ret = init_context_pass_through();
2007 printk(KERN_ERR "IOMMU: Pass through init failed.\n");
2008 iommu_pass_through = 0;
2013 * If pass through is not set or not enabled, setup context entries for
2014 * identity mappings for rmrr, gfx, and isa.
2016 if (!iommu_pass_through) {
2019 * for each dev attached to rmrr
2021 * locate drhd for dev, alloc domain for dev
2022 * allocate free domain
2023 * allocate page table entries for rmrr
2024 * if context not allocated for bus
2025 * allocate and init context
2026 * set present in root table for this bus
2027 * init context with domain, translation etc
2031 for_each_rmrr_units(rmrr) {
2032 for (i = 0; i < rmrr->devices_cnt; i++) {
2033 pdev = rmrr->devices[i];
2035 * some BIOS lists non-exist devices in DMAR
2040 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2043 "IOMMU: mapping reserved region failed\n");
2047 iommu_prepare_gfx_mapping();
2049 iommu_prepare_isa();
2055 * global invalidate context cache
2056 * global invalidate iotlb
2057 * enable translation
2059 for_each_drhd_unit(drhd) {
2062 iommu = drhd->iommu;
2064 iommu_flush_write_buffer(iommu);
2066 ret = dmar_set_interrupt(iommu);
2070 iommu_set_root_entry(iommu);
2072 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
2073 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
2074 iommu_disable_protect_mem_regions(iommu);
2076 ret = iommu_enable_translation(iommu);
2083 for_each_drhd_unit(drhd) {
2086 iommu = drhd->iommu;
2093 static inline u64 aligned_size(u64 host_addr, size_t size)
2096 addr = (host_addr & (~PAGE_MASK)) + size;
2097 return PAGE_ALIGN(addr);
2101 iommu_alloc_iova(struct dmar_domain *domain, size_t size, u64 end)
2105 /* Make sure it's in range */
2106 end = min_t(u64, DOMAIN_MAX_ADDR(domain->gaw), end);
2107 if (!size || (IOVA_START_ADDR + size > end))
2110 piova = alloc_iova(&domain->iovad,
2111 size >> PAGE_SHIFT, IOVA_PFN(end), 1);
2115 static struct iova *
2116 __intel_alloc_iova(struct device *dev, struct dmar_domain *domain,
2117 size_t size, u64 dma_mask)
2119 struct pci_dev *pdev = to_pci_dev(dev);
2120 struct iova *iova = NULL;
2122 if (dma_mask <= DMA_BIT_MASK(32) || dmar_forcedac)
2123 iova = iommu_alloc_iova(domain, size, dma_mask);
2126 * First try to allocate an io virtual address in
2127 * DMA_BIT_MASK(32) and if that fails then try allocating
2130 iova = iommu_alloc_iova(domain, size, DMA_BIT_MASK(32));
2132 iova = iommu_alloc_iova(domain, size, dma_mask);
2136 printk(KERN_ERR"Allocating iova for %s failed", pci_name(pdev));
2143 static struct dmar_domain *
2144 get_valid_domain_for_dev(struct pci_dev *pdev)
2146 struct dmar_domain *domain;
2149 domain = get_domain_for_dev(pdev,
2150 DEFAULT_DOMAIN_ADDRESS_WIDTH);
2153 "Allocating domain for %s failed", pci_name(pdev));
2157 /* make sure context mapping is ok */
2158 if (unlikely(!domain_context_mapped(pdev))) {
2159 ret = domain_context_mapping(domain, pdev,
2160 CONTEXT_TT_MULTI_LEVEL);
2163 "Domain context map for %s failed",
2172 static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2173 size_t size, int dir, u64 dma_mask)
2175 struct pci_dev *pdev = to_pci_dev(hwdev);
2176 struct dmar_domain *domain;
2177 phys_addr_t start_paddr;
2181 struct intel_iommu *iommu;
2183 BUG_ON(dir == DMA_NONE);
2184 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
2187 domain = get_valid_domain_for_dev(pdev);
2191 iommu = domain_get_iommu(domain);
2192 size = aligned_size((u64)paddr, size);
2194 iova = __intel_alloc_iova(hwdev, domain, size, pdev->dma_mask);
2198 start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2201 * Check if DMAR supports zero-length reads on write only
2204 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2205 !cap_zlr(iommu->cap))
2206 prot |= DMA_PTE_READ;
2207 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2208 prot |= DMA_PTE_WRITE;
2210 * paddr - (paddr + size) might be partial page, we should map the whole
2211 * page. Note: if two part of one page are separately mapped, we
2212 * might have two guest_addr mapping to the same host paddr, but this
2213 * is not a big problem
2215 ret = domain_page_mapping(domain, start_paddr,
2216 ((u64)paddr) & PAGE_MASK, size, prot);
2220 /* it's a non-present to present mapping. Only flush if caching mode */
2221 if (cap_caching_mode(iommu->cap))
2222 iommu_flush_iotlb_psi(iommu, 0, start_paddr,
2223 size >> VTD_PAGE_SHIFT);
2225 iommu_flush_write_buffer(iommu);
2227 return start_paddr + ((u64)paddr & (~PAGE_MASK));
2231 __free_iova(&domain->iovad, iova);
2232 printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
2233 pci_name(pdev), size, (unsigned long long)paddr, dir);
2237 static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2238 unsigned long offset, size_t size,
2239 enum dma_data_direction dir,
2240 struct dma_attrs *attrs)
2242 return __intel_map_single(dev, page_to_phys(page) + offset, size,
2243 dir, to_pci_dev(dev)->dma_mask);
2246 static void flush_unmaps(void)
2252 /* just flush them all */
2253 for (i = 0; i < g_num_of_iommus; i++) {
2254 struct intel_iommu *iommu = g_iommus[i];
2258 if (!deferred_flush[i].next)
2261 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2262 DMA_TLB_GLOBAL_FLUSH, 0);
2263 for (j = 0; j < deferred_flush[i].next; j++) {
2264 __free_iova(&deferred_flush[i].domain[j]->iovad,
2265 deferred_flush[i].iova[j]);
2267 deferred_flush[i].next = 0;
2273 static void flush_unmaps_timeout(unsigned long data)
2275 unsigned long flags;
2277 spin_lock_irqsave(&async_umap_flush_lock, flags);
2279 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2282 static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2284 unsigned long flags;
2286 struct intel_iommu *iommu;
2288 spin_lock_irqsave(&async_umap_flush_lock, flags);
2289 if (list_size == HIGH_WATER_MARK)
2292 iommu = domain_get_iommu(dom);
2293 iommu_id = iommu->seq_id;
2295 next = deferred_flush[iommu_id].next;
2296 deferred_flush[iommu_id].domain[next] = dom;
2297 deferred_flush[iommu_id].iova[next] = iova;
2298 deferred_flush[iommu_id].next++;
2301 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2305 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2308 static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2309 size_t size, enum dma_data_direction dir,
2310 struct dma_attrs *attrs)
2312 struct pci_dev *pdev = to_pci_dev(dev);
2313 struct dmar_domain *domain;
2314 unsigned long start_addr;
2316 struct intel_iommu *iommu;
2318 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
2320 domain = find_domain(pdev);
2323 iommu = domain_get_iommu(domain);
2325 iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
2329 start_addr = iova->pfn_lo << PAGE_SHIFT;
2330 size = aligned_size((u64)dev_addr, size);
2332 pr_debug("Device %s unmapping: %zx@%llx\n",
2333 pci_name(pdev), size, (unsigned long long)start_addr);
2335 /* clear the whole page */
2336 dma_pte_clear_range(domain, start_addr, start_addr + size);
2337 /* free page tables */
2338 dma_pte_free_pagetable(domain, start_addr, start_addr + size);
2339 if (intel_iommu_strict) {
2340 iommu_flush_iotlb_psi(iommu, domain->id, start_addr,
2341 size >> VTD_PAGE_SHIFT);
2343 __free_iova(&domain->iovad, iova);
2345 add_unmap(domain, iova);
2347 * queue up the release of the unmap to save the 1/6th of the
2348 * cpu used up by the iotlb flush operation...
2353 static void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size,
2356 intel_unmap_page(dev, dev_addr, size, dir, NULL);
2359 static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2360 dma_addr_t *dma_handle, gfp_t flags)
2365 size = PAGE_ALIGN(size);
2366 order = get_order(size);
2367 flags &= ~(GFP_DMA | GFP_DMA32);
2369 vaddr = (void *)__get_free_pages(flags, order);
2372 memset(vaddr, 0, size);
2374 *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
2376 hwdev->coherent_dma_mask);
2379 free_pages((unsigned long)vaddr, order);
2383 static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2384 dma_addr_t dma_handle)
2388 size = PAGE_ALIGN(size);
2389 order = get_order(size);
2391 intel_unmap_single(hwdev, dma_handle, size, DMA_BIDIRECTIONAL);
2392 free_pages((unsigned long)vaddr, order);
2395 static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
2396 int nelems, enum dma_data_direction dir,
2397 struct dma_attrs *attrs)
2400 struct pci_dev *pdev = to_pci_dev(hwdev);
2401 struct dmar_domain *domain;
2402 unsigned long start_addr;
2406 struct scatterlist *sg;
2407 struct intel_iommu *iommu;
2409 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
2412 domain = find_domain(pdev);
2415 iommu = domain_get_iommu(domain);
2417 iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
2420 for_each_sg(sglist, sg, nelems, i) {
2421 addr = page_to_phys(sg_page(sg)) + sg->offset;
2422 size += aligned_size((u64)addr, sg->length);
2425 start_addr = iova->pfn_lo << PAGE_SHIFT;
2427 /* clear the whole page */
2428 dma_pte_clear_range(domain, start_addr, start_addr + size);
2429 /* free page tables */
2430 dma_pte_free_pagetable(domain, start_addr, start_addr + size);
2432 iommu_flush_iotlb_psi(iommu, domain->id, start_addr,
2433 size >> VTD_PAGE_SHIFT);
2436 __free_iova(&domain->iovad, iova);
2439 static int intel_nontranslate_map_sg(struct device *hddev,
2440 struct scatterlist *sglist, int nelems, int dir)
2443 struct scatterlist *sg;
2445 for_each_sg(sglist, sg, nelems, i) {
2446 BUG_ON(!sg_page(sg));
2447 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
2448 sg->dma_length = sg->length;
2453 static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
2454 enum dma_data_direction dir, struct dma_attrs *attrs)
2458 struct pci_dev *pdev = to_pci_dev(hwdev);
2459 struct dmar_domain *domain;
2463 struct iova *iova = NULL;
2465 struct scatterlist *sg;
2466 unsigned long start_addr;
2467 struct intel_iommu *iommu;
2469 BUG_ON(dir == DMA_NONE);
2470 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
2471 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
2473 domain = get_valid_domain_for_dev(pdev);
2477 iommu = domain_get_iommu(domain);
2479 for_each_sg(sglist, sg, nelems, i) {
2480 addr = page_to_phys(sg_page(sg)) + sg->offset;
2481 size += aligned_size((u64)addr, sg->length);
2484 iova = __intel_alloc_iova(hwdev, domain, size, pdev->dma_mask);
2486 sglist->dma_length = 0;
2491 * Check if DMAR supports zero-length reads on write only
2494 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2495 !cap_zlr(iommu->cap))
2496 prot |= DMA_PTE_READ;
2497 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2498 prot |= DMA_PTE_WRITE;
2500 start_addr = iova->pfn_lo << PAGE_SHIFT;
2502 for_each_sg(sglist, sg, nelems, i) {
2503 addr = page_to_phys(sg_page(sg)) + sg->offset;
2504 size = aligned_size((u64)addr, sg->length);
2505 ret = domain_page_mapping(domain, start_addr + offset,
2506 ((u64)addr) & PAGE_MASK,
2509 /* clear the page */
2510 dma_pte_clear_range(domain, start_addr,
2511 start_addr + offset);
2512 /* free page tables */
2513 dma_pte_free_pagetable(domain, start_addr,
2514 start_addr + offset);
2516 __free_iova(&domain->iovad, iova);
2519 sg->dma_address = start_addr + offset +
2520 ((u64)addr & (~PAGE_MASK));
2521 sg->dma_length = sg->length;
2525 /* it's a non-present to present mapping. Only flush if caching mode */
2526 if (cap_caching_mode(iommu->cap))
2527 iommu_flush_iotlb_psi(iommu, 0, start_addr,
2528 offset >> VTD_PAGE_SHIFT);
2530 iommu_flush_write_buffer(iommu);
2535 static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
2540 struct dma_map_ops intel_dma_ops = {
2541 .alloc_coherent = intel_alloc_coherent,
2542 .free_coherent = intel_free_coherent,
2543 .map_sg = intel_map_sg,
2544 .unmap_sg = intel_unmap_sg,
2545 .map_page = intel_map_page,
2546 .unmap_page = intel_unmap_page,
2547 .mapping_error = intel_mapping_error,
2550 static inline int iommu_domain_cache_init(void)
2554 iommu_domain_cache = kmem_cache_create("iommu_domain",
2555 sizeof(struct dmar_domain),
2560 if (!iommu_domain_cache) {
2561 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
2568 static inline int iommu_devinfo_cache_init(void)
2572 iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
2573 sizeof(struct device_domain_info),
2577 if (!iommu_devinfo_cache) {
2578 printk(KERN_ERR "Couldn't create devinfo cache\n");
2585 static inline int iommu_iova_cache_init(void)
2589 iommu_iova_cache = kmem_cache_create("iommu_iova",
2590 sizeof(struct iova),
2594 if (!iommu_iova_cache) {
2595 printk(KERN_ERR "Couldn't create iova cache\n");
2602 static int __init iommu_init_mempool(void)
2605 ret = iommu_iova_cache_init();
2609 ret = iommu_domain_cache_init();
2613 ret = iommu_devinfo_cache_init();
2617 kmem_cache_destroy(iommu_domain_cache);
2619 kmem_cache_destroy(iommu_iova_cache);
2624 static void __init iommu_exit_mempool(void)
2626 kmem_cache_destroy(iommu_devinfo_cache);
2627 kmem_cache_destroy(iommu_domain_cache);
2628 kmem_cache_destroy(iommu_iova_cache);
2632 static void __init init_no_remapping_devices(void)
2634 struct dmar_drhd_unit *drhd;
2636 for_each_drhd_unit(drhd) {
2637 if (!drhd->include_all) {
2639 for (i = 0; i < drhd->devices_cnt; i++)
2640 if (drhd->devices[i] != NULL)
2642 /* ignore DMAR unit if no pci devices exist */
2643 if (i == drhd->devices_cnt)
2651 for_each_drhd_unit(drhd) {
2653 if (drhd->ignored || drhd->include_all)
2656 for (i = 0; i < drhd->devices_cnt; i++)
2657 if (drhd->devices[i] &&
2658 !IS_GFX_DEVICE(drhd->devices[i]))
2661 if (i < drhd->devices_cnt)
2664 /* bypass IOMMU if it is just for gfx devices */
2666 for (i = 0; i < drhd->devices_cnt; i++) {
2667 if (!drhd->devices[i])
2669 drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
2674 #ifdef CONFIG_SUSPEND
2675 static int init_iommu_hw(void)
2677 struct dmar_drhd_unit *drhd;
2678 struct intel_iommu *iommu = NULL;
2680 for_each_active_iommu(iommu, drhd)
2682 dmar_reenable_qi(iommu);
2684 for_each_active_iommu(iommu, drhd) {
2685 iommu_flush_write_buffer(iommu);
2687 iommu_set_root_entry(iommu);
2689 iommu->flush.flush_context(iommu, 0, 0, 0,
2690 DMA_CCMD_GLOBAL_INVL);
2691 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2692 DMA_TLB_GLOBAL_FLUSH);
2693 iommu_disable_protect_mem_regions(iommu);
2694 iommu_enable_translation(iommu);
2700 static void iommu_flush_all(void)
2702 struct dmar_drhd_unit *drhd;
2703 struct intel_iommu *iommu;
2705 for_each_active_iommu(iommu, drhd) {
2706 iommu->flush.flush_context(iommu, 0, 0, 0,
2707 DMA_CCMD_GLOBAL_INVL);
2708 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2709 DMA_TLB_GLOBAL_FLUSH);
2713 static int iommu_suspend(struct sys_device *dev, pm_message_t state)
2715 struct dmar_drhd_unit *drhd;
2716 struct intel_iommu *iommu = NULL;
2719 for_each_active_iommu(iommu, drhd) {
2720 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
2722 if (!iommu->iommu_state)
2728 for_each_active_iommu(iommu, drhd) {
2729 iommu_disable_translation(iommu);
2731 spin_lock_irqsave(&iommu->register_lock, flag);
2733 iommu->iommu_state[SR_DMAR_FECTL_REG] =
2734 readl(iommu->reg + DMAR_FECTL_REG);
2735 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
2736 readl(iommu->reg + DMAR_FEDATA_REG);
2737 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
2738 readl(iommu->reg + DMAR_FEADDR_REG);
2739 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
2740 readl(iommu->reg + DMAR_FEUADDR_REG);
2742 spin_unlock_irqrestore(&iommu->register_lock, flag);
2747 for_each_active_iommu(iommu, drhd)
2748 kfree(iommu->iommu_state);
2753 static int iommu_resume(struct sys_device *dev)
2755 struct dmar_drhd_unit *drhd;
2756 struct intel_iommu *iommu = NULL;
2759 if (init_iommu_hw()) {
2760 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
2764 for_each_active_iommu(iommu, drhd) {
2766 spin_lock_irqsave(&iommu->register_lock, flag);
2768 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
2769 iommu->reg + DMAR_FECTL_REG);
2770 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
2771 iommu->reg + DMAR_FEDATA_REG);
2772 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
2773 iommu->reg + DMAR_FEADDR_REG);
2774 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
2775 iommu->reg + DMAR_FEUADDR_REG);
2777 spin_unlock_irqrestore(&iommu->register_lock, flag);
2780 for_each_active_iommu(iommu, drhd)
2781 kfree(iommu->iommu_state);
2786 static struct sysdev_class iommu_sysclass = {
2788 .resume = iommu_resume,
2789 .suspend = iommu_suspend,
2792 static struct sys_device device_iommu = {
2793 .cls = &iommu_sysclass,
2796 static int __init init_iommu_sysfs(void)
2800 error = sysdev_class_register(&iommu_sysclass);
2804 error = sysdev_register(&device_iommu);
2806 sysdev_class_unregister(&iommu_sysclass);
2812 static int __init init_iommu_sysfs(void)
2816 #endif /* CONFIG_PM */
2818 int __init intel_iommu_init(void)
2822 if (dmar_table_init())
2825 if (dmar_dev_scope_init())
2829 * Check the need for DMA-remapping initialization now.
2830 * Above initialization will also be used by Interrupt-remapping.
2832 if (no_iommu || (swiotlb && !iommu_pass_through) || dmar_disabled)
2835 iommu_init_mempool();
2836 dmar_init_reserved_ranges();
2838 init_no_remapping_devices();
2842 printk(KERN_ERR "IOMMU: dmar init failed\n");
2843 put_iova_domain(&reserved_iova_list);
2844 iommu_exit_mempool();
2848 "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
2850 init_timer(&unmap_timer);
2853 if (!iommu_pass_through) {
2855 "Multi-level page-table translation for DMAR.\n");
2856 dma_ops = &intel_dma_ops;
2859 "DMAR: Pass through translation for DMAR.\n");
2863 register_iommu(&intel_iommu_ops);
2868 static int vm_domain_add_dev_info(struct dmar_domain *domain,
2869 struct pci_dev *pdev)
2871 struct device_domain_info *info;
2872 unsigned long flags;
2874 info = alloc_devinfo_mem();
2878 info->segment = pci_domain_nr(pdev->bus);
2879 info->bus = pdev->bus->number;
2880 info->devfn = pdev->devfn;
2882 info->domain = domain;
2884 spin_lock_irqsave(&device_domain_lock, flags);
2885 list_add(&info->link, &domain->devices);
2886 list_add(&info->global, &device_domain_list);
2887 pdev->dev.archdata.iommu = info;
2888 spin_unlock_irqrestore(&device_domain_lock, flags);
2893 static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
2894 struct pci_dev *pdev)
2896 struct pci_dev *tmp, *parent;
2898 if (!iommu || !pdev)
2901 /* dependent device detach */
2902 tmp = pci_find_upstream_pcie_bridge(pdev);
2903 /* Secondary interface's bus number and devfn 0 */
2905 parent = pdev->bus->self;
2906 while (parent != tmp) {
2907 iommu_detach_dev(iommu, parent->bus->number,
2909 parent = parent->bus->self;
2911 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
2912 iommu_detach_dev(iommu,
2913 tmp->subordinate->number, 0);
2914 else /* this is a legacy PCI bridge */
2915 iommu_detach_dev(iommu, tmp->bus->number,
2920 static void vm_domain_remove_one_dev_info(struct dmar_domain *domain,
2921 struct pci_dev *pdev)
2923 struct device_domain_info *info;
2924 struct intel_iommu *iommu;
2925 unsigned long flags;
2927 struct list_head *entry, *tmp;
2929 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
2934 spin_lock_irqsave(&device_domain_lock, flags);
2935 list_for_each_safe(entry, tmp, &domain->devices) {
2936 info = list_entry(entry, struct device_domain_info, link);
2937 /* No need to compare PCI domain; it has to be the same */
2938 if (info->bus == pdev->bus->number &&
2939 info->devfn == pdev->devfn) {
2940 list_del(&info->link);
2941 list_del(&info->global);
2943 info->dev->dev.archdata.iommu = NULL;
2944 spin_unlock_irqrestore(&device_domain_lock, flags);
2946 iommu_detach_dev(iommu, info->bus, info->devfn);
2947 iommu_detach_dependent_devices(iommu, pdev);
2948 free_devinfo_mem(info);
2950 spin_lock_irqsave(&device_domain_lock, flags);
2958 /* if there is no other devices under the same iommu
2959 * owned by this domain, clear this iommu in iommu_bmp
2960 * update iommu count and coherency
2962 if (iommu == device_to_iommu(info->segment, info->bus,
2968 unsigned long tmp_flags;
2969 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
2970 clear_bit(iommu->seq_id, &domain->iommu_bmp);
2971 domain->iommu_count--;
2972 domain_update_iommu_cap(domain);
2973 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
2976 spin_unlock_irqrestore(&device_domain_lock, flags);
2979 static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
2981 struct device_domain_info *info;
2982 struct intel_iommu *iommu;
2983 unsigned long flags1, flags2;
2985 spin_lock_irqsave(&device_domain_lock, flags1);
2986 while (!list_empty(&domain->devices)) {
2987 info = list_entry(domain->devices.next,
2988 struct device_domain_info, link);
2989 list_del(&info->link);
2990 list_del(&info->global);
2992 info->dev->dev.archdata.iommu = NULL;
2994 spin_unlock_irqrestore(&device_domain_lock, flags1);
2996 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
2997 iommu_detach_dev(iommu, info->bus, info->devfn);
2998 iommu_detach_dependent_devices(iommu, info->dev);
3000 /* clear this iommu in iommu_bmp, update iommu count
3003 spin_lock_irqsave(&domain->iommu_lock, flags2);
3004 if (test_and_clear_bit(iommu->seq_id,
3005 &domain->iommu_bmp)) {
3006 domain->iommu_count--;
3007 domain_update_iommu_cap(domain);
3009 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
3011 free_devinfo_mem(info);
3012 spin_lock_irqsave(&device_domain_lock, flags1);
3014 spin_unlock_irqrestore(&device_domain_lock, flags1);
3017 /* domain id for virtual machine, it won't be set in context */
3018 static unsigned long vm_domid;
3020 static int vm_domain_min_agaw(struct dmar_domain *domain)
3023 int min_agaw = domain->agaw;
3025 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
3026 for (; i < g_num_of_iommus; ) {
3027 if (min_agaw > g_iommus[i]->agaw)
3028 min_agaw = g_iommus[i]->agaw;
3030 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
3036 static struct dmar_domain *iommu_alloc_vm_domain(void)
3038 struct dmar_domain *domain;
3040 domain = alloc_domain_mem();
3044 domain->id = vm_domid++;
3045 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
3046 domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
3051 static int vm_domain_init(struct dmar_domain *domain, int guest_width)
3055 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
3056 spin_lock_init(&domain->mapping_lock);
3057 spin_lock_init(&domain->iommu_lock);
3059 domain_reserve_special_ranges(domain);
3061 /* calculate AGAW */
3062 domain->gaw = guest_width;
3063 adjust_width = guestwidth_to_adjustwidth(guest_width);
3064 domain->agaw = width_to_agaw(adjust_width);
3066 INIT_LIST_HEAD(&domain->devices);
3068 domain->iommu_count = 0;
3069 domain->iommu_coherency = 0;
3070 domain->max_addr = 0;
3072 /* always allocate the top pgd */
3073 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
3076 domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
3080 static void iommu_free_vm_domain(struct dmar_domain *domain)
3082 unsigned long flags;
3083 struct dmar_drhd_unit *drhd;
3084 struct intel_iommu *iommu;
3086 unsigned long ndomains;
3088 for_each_drhd_unit(drhd) {
3091 iommu = drhd->iommu;
3093 ndomains = cap_ndoms(iommu->cap);
3094 i = find_first_bit(iommu->domain_ids, ndomains);
3095 for (; i < ndomains; ) {
3096 if (iommu->domains[i] == domain) {
3097 spin_lock_irqsave(&iommu->lock, flags);
3098 clear_bit(i, iommu->domain_ids);
3099 iommu->domains[i] = NULL;
3100 spin_unlock_irqrestore(&iommu->lock, flags);
3103 i = find_next_bit(iommu->domain_ids, ndomains, i+1);
3108 static void vm_domain_exit(struct dmar_domain *domain)
3112 /* Domain 0 is reserved, so dont process it */
3116 vm_domain_remove_all_dev_info(domain);
3118 put_iova_domain(&domain->iovad);
3119 end = DOMAIN_MAX_ADDR(domain->gaw);
3120 end = end & (~VTD_PAGE_MASK);
3123 dma_pte_clear_range(domain, 0, end);
3125 /* free page tables */
3126 dma_pte_free_pagetable(domain, 0, end);
3128 iommu_free_vm_domain(domain);
3129 free_domain_mem(domain);
3132 static int intel_iommu_domain_init(struct iommu_domain *domain)
3134 struct dmar_domain *dmar_domain;
3136 dmar_domain = iommu_alloc_vm_domain();
3139 "intel_iommu_domain_init: dmar_domain == NULL\n");
3142 if (vm_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
3144 "intel_iommu_domain_init() failed\n");
3145 vm_domain_exit(dmar_domain);
3148 domain->priv = dmar_domain;
3153 static void intel_iommu_domain_destroy(struct iommu_domain *domain)
3155 struct dmar_domain *dmar_domain = domain->priv;
3157 domain->priv = NULL;
3158 vm_domain_exit(dmar_domain);
3161 static int intel_iommu_attach_device(struct iommu_domain *domain,
3164 struct dmar_domain *dmar_domain = domain->priv;
3165 struct pci_dev *pdev = to_pci_dev(dev);
3166 struct intel_iommu *iommu;
3171 /* normally pdev is not mapped */
3172 if (unlikely(domain_context_mapped(pdev))) {
3173 struct dmar_domain *old_domain;
3175 old_domain = find_domain(pdev);
3177 if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
3178 vm_domain_remove_one_dev_info(old_domain, pdev);
3180 domain_remove_dev_info(old_domain);
3184 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3189 /* check if this iommu agaw is sufficient for max mapped address */
3190 addr_width = agaw_to_width(iommu->agaw);
3191 end = DOMAIN_MAX_ADDR(addr_width);
3192 end = end & VTD_PAGE_MASK;
3193 if (end < dmar_domain->max_addr) {
3194 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3195 "sufficient for the mapped address (%llx)\n",
3196 __func__, iommu->agaw, dmar_domain->max_addr);
3200 ret = domain_context_mapping(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
3204 ret = vm_domain_add_dev_info(dmar_domain, pdev);
3208 static void intel_iommu_detach_device(struct iommu_domain *domain,
3211 struct dmar_domain *dmar_domain = domain->priv;
3212 struct pci_dev *pdev = to_pci_dev(dev);
3214 vm_domain_remove_one_dev_info(dmar_domain, pdev);
3217 static int intel_iommu_map_range(struct iommu_domain *domain,
3218 unsigned long iova, phys_addr_t hpa,
3219 size_t size, int iommu_prot)
3221 struct dmar_domain *dmar_domain = domain->priv;
3227 if (iommu_prot & IOMMU_READ)
3228 prot |= DMA_PTE_READ;
3229 if (iommu_prot & IOMMU_WRITE)
3230 prot |= DMA_PTE_WRITE;
3231 if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
3232 prot |= DMA_PTE_SNP;
3234 max_addr = (iova & VTD_PAGE_MASK) + VTD_PAGE_ALIGN(size);
3235 if (dmar_domain->max_addr < max_addr) {
3239 /* check if minimum agaw is sufficient for mapped address */
3240 min_agaw = vm_domain_min_agaw(dmar_domain);
3241 addr_width = agaw_to_width(min_agaw);
3242 end = DOMAIN_MAX_ADDR(addr_width);
3243 end = end & VTD_PAGE_MASK;
3244 if (end < max_addr) {
3245 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3246 "sufficient for the mapped address (%llx)\n",
3247 __func__, min_agaw, max_addr);
3250 dmar_domain->max_addr = max_addr;
3253 ret = domain_page_mapping(dmar_domain, iova, hpa, size, prot);
3257 static void intel_iommu_unmap_range(struct iommu_domain *domain,
3258 unsigned long iova, size_t size)
3260 struct dmar_domain *dmar_domain = domain->priv;
3263 /* The address might not be aligned */
3264 base = iova & VTD_PAGE_MASK;
3265 size = VTD_PAGE_ALIGN(size);
3266 dma_pte_clear_range(dmar_domain, base, base + size);
3268 if (dmar_domain->max_addr == base + size)
3269 dmar_domain->max_addr = base;
3272 static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
3275 struct dmar_domain *dmar_domain = domain->priv;
3276 struct dma_pte *pte;
3279 pte = addr_to_dma_pte(dmar_domain, iova);
3281 phys = dma_pte_addr(pte);
3286 static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
3289 struct dmar_domain *dmar_domain = domain->priv;
3291 if (cap == IOMMU_CAP_CACHE_COHERENCY)
3292 return dmar_domain->iommu_snooping;
3297 static struct iommu_ops intel_iommu_ops = {
3298 .domain_init = intel_iommu_domain_init,
3299 .domain_destroy = intel_iommu_domain_destroy,
3300 .attach_dev = intel_iommu_attach_device,
3301 .detach_dev = intel_iommu_detach_device,
3302 .map = intel_iommu_map_range,
3303 .unmap = intel_iommu_unmap_range,
3304 .iova_to_phys = intel_iommu_iova_to_phys,
3305 .domain_has_cap = intel_iommu_domain_has_cap,
3308 static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
3311 * Mobile 4 Series Chipset neglects to set RWBF capability,
3314 printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
3318 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);