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   1 /*
   2  * Copyright (c) 2006, Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  15  * Place - Suite 330, Boston, MA 02111-1307 USA.
  16  *
  17  * Copyright (C) 2006-2008 Intel Corporation
  18  * Author: Ashok Raj <ashok.raj@intel.com>
  19  * Author: Shaohua Li <shaohua.li@intel.com>
  20  * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
  21  *
  22  * This file implements early detection/parsing of Remapping Devices
  23  * reported to OS through BIOS via DMA remapping reporting (DMAR) ACPI
  24  * tables.
  25  *
  26  * These routines are used by both DMA-remapping and Interrupt-remapping
  27  */
  28
  29 #include <linux/pci.h>
  30 #include <linux/dmar.h>
  31 #include <linux/iova.h>
  32 #include <linux/intel-iommu.h>
  33 #include <linux/timer.h>
  34 #include <linux/irq.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/tboot.h>
  37 #include <linux/dmi.h>
  38
  39 #define PREFIX "DMAR: "
  40
  41 /* No locks are needed as DMA remapping hardware unit
  42  * list is constructed at boot time and hotplug of
  43  * these units are not supported by the architecture.
  44  */
  45 LIST_HEAD(dmar_drhd_units);
  46
  47 static struct acpi_table_header * __initdata dmar_tbl;
  48 static acpi_size dmar_tbl_size;
  49
  50 static void __init dmar_register_drhd_unit(struct dmar_drhd_unit *drhd)
  51 {
  52         /*
  53          * add INCLUDE_ALL at the tail, so scan the list will find it at
  54          * the very end.
  55          */
  56         if (drhd->include_all)
  57                 list_add_tail(&drhd->list, &dmar_drhd_units);
  58         else
  59                 list_add(&drhd->list, &dmar_drhd_units);
  60 }
  61
  62 static int __init dmar_parse_one_dev_scope(struct acpi_dmar_device_scope *scope,
  63                                            struct pci_dev **dev, u16 segment)
  64 {
  65         struct pci_bus *bus;
  66         struct pci_dev *pdev = NULL;
  67         struct acpi_dmar_pci_path *path;
  68         int count;
  69
  70         bus = pci_find_bus(segment, scope->bus);
  71         path = (struct acpi_dmar_pci_path *)(scope + 1);
  72         count = (scope->length - sizeof(struct acpi_dmar_device_scope))
  73                 / sizeof(struct acpi_dmar_pci_path);
  74
  75         while (count) {
  76                 if (pdev)
  77                         pci_dev_put(pdev);
  78                 /*
  79                  * Some BIOSes list non-exist devices in DMAR table, just
  80                  * ignore it
  81                  */
  82                 if (!bus) {
  83                         printk(KERN_WARNING
  84                         PREFIX "Device scope bus [%d] not found\n",
  85                         scope->bus);
  86                         break;
  87                 }
  88                 pdev = pci_get_slot(bus, PCI_DEVFN(path->dev, path->fn));
  89                 if (!pdev) {
  90                         printk(KERN_WARNING PREFIX
  91                         "Device scope device [%04x:%02x:%02x.%02x] not found\n",
  92                                 segment, bus->number, path->dev, path->fn);
  93                         break;
  94                 }
  95                 path ++;
  96                 count --;
  97                 bus = pdev->subordinate;
  98         }
  99         if (!pdev) {
 100                 printk(KERN_WARNING PREFIX
 101                 "Device scope device [%04x:%02x:%02x.%02x] not found\n",
 102                 segment, scope->bus, path->dev, path->fn);
 103                 *dev = NULL;
 104                 return 0;
 105         }
 106         if ((scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && \
 107                         pdev->subordinate) || (scope->entry_type == \
 108                         ACPI_DMAR_SCOPE_TYPE_BRIDGE && !pdev->subordinate)) {
 109                 pci_dev_put(pdev);
 110                 printk(KERN_WARNING PREFIX
 111                         "Device scope type does not match for %s\n",
 112                          pci_name(pdev));
 113                 return -EINVAL;
 114         }
 115         *dev = pdev;
 116         return 0;
 117 }
 118
 119 static int __init dmar_parse_dev_scope(void *start, void *end, int *cnt,
 120                                        struct pci_dev ***devices, u16 segment)
 121 {
 122         struct acpi_dmar_device_scope *scope;
 123         void * tmp = start;
 124         int index;
 125         int ret;
 126
 127         *cnt = 0;
 128         while (start < end) {
 129                 scope = start;
 130                 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT ||
 131                     scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE)
 132                         (*cnt)++;
 133                 else
 134                         printk(KERN_WARNING PREFIX
 135                                 "Unsupported device scope\n");
 136                 start += scope->length;
 137         }
 138         if (*cnt == 0)
 139                 return 0;
 140
 141         *devices = kcalloc(*cnt, sizeof(struct pci_dev *), GFP_KERNEL);
 142         if (!*devices)
 143                 return -ENOMEM;
 144
 145         start = tmp;
 146         index = 0;
 147         while (start < end) {
 148                 scope = start;
 149                 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT ||
 150                     scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE) {
 151                         ret = dmar_parse_one_dev_scope(scope,
 152                                 &(*devices)[index], segment);
 153                         if (ret) {
 154                                 kfree(*devices);
 155                                 return ret;
 156                         }
 157                         index ++;
 158                 }
 159                 start += scope->length;
 160         }
 161
 162         return 0;
 163 }
 164
 165 /**
 166  * dmar_parse_one_drhd - parses exactly one DMA remapping hardware definition
 167  * structure which uniquely represent one DMA remapping hardware unit
 168  * present in the platform
 169  */
 170 static int __init
 171 dmar_parse_one_drhd(struct acpi_dmar_header *header)
 172 {
 173         struct acpi_dmar_hardware_unit *drhd;
 174         struct dmar_drhd_unit *dmaru;
 175         int ret = 0;
 176
 177         drhd = (struct acpi_dmar_hardware_unit *)header;
 178         dmaru = kzalloc(sizeof(*dmaru), GFP_KERNEL);
 179         if (!dmaru)
 180                 return -ENOMEM;
 181
 182         dmaru->hdr = header;
 183         dmaru->reg_base_addr = drhd->address;
 184         dmaru->segment = drhd->segment;
 185         dmaru->include_all = drhd->flags & 0x1; /* BIT0: INCLUDE_ALL */
 186
 187         ret = alloc_iommu(dmaru);
 188         if (ret) {
 189                 kfree(dmaru);
 190                 return ret;
 191         }
 192         dmar_register_drhd_unit(dmaru);
 193         return 0;
 194 }
 195
 196 static int __init dmar_parse_dev(struct dmar_drhd_unit *dmaru)
 197 {
 198         struct acpi_dmar_hardware_unit *drhd;
 199         int ret = 0;
 200
 201         drhd = (struct acpi_dmar_hardware_unit *) dmaru->hdr;
 202
 203         if (dmaru->include_all)
 204                 return 0;
 205
 206         ret = dmar_parse_dev_scope((void *)(drhd + 1),
 207                                 ((void *)drhd) + drhd->header.length,
 208                                 &dmaru->devices_cnt, &dmaru->devices,
 209                                 drhd->segment);
 210         if (ret) {
 211                 list_del(&dmaru->list);
 212                 kfree(dmaru);
 213         }
 214         return ret;
 215 }
 216
 217 #ifdef CONFIG_DMAR
 218 LIST_HEAD(dmar_rmrr_units);
 219
 220 static void __init dmar_register_rmrr_unit(struct dmar_rmrr_unit *rmrr)
 221 {
 222         list_add(&rmrr->list, &dmar_rmrr_units);
 223 }
 224
 225
 226 static int __init
 227 dmar_parse_one_rmrr(struct acpi_dmar_header *header)
 228 {
 229         struct acpi_dmar_reserved_memory *rmrr;
 230         struct dmar_rmrr_unit *rmrru;
 231
 232         rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL);
 233         if (!rmrru)
 234                 return -ENOMEM;
 235
 236         rmrru->hdr = header;
 237         rmrr = (struct acpi_dmar_reserved_memory *)header;
 238         rmrru->base_address = rmrr->base_address;
 239         rmrru->end_address = rmrr->end_address;
 240
 241         dmar_register_rmrr_unit(rmrru);
 242         return 0;
 243 }
 244
 245 static int __init
 246 rmrr_parse_dev(struct dmar_rmrr_unit *rmrru)
 247 {
 248         struct acpi_dmar_reserved_memory *rmrr;
 249         int ret;
 250
 251         rmrr = (struct acpi_dmar_reserved_memory *) rmrru->hdr;
 252         ret = dmar_parse_dev_scope((void *)(rmrr + 1),
 253                 ((void *)rmrr) + rmrr->header.length,
 254                 &rmrru->devices_cnt, &rmrru->devices, rmrr->segment);
 255
 256         if (ret || (rmrru->devices_cnt == 0)) {
 257                 list_del(&rmrru->list);
 258                 kfree(rmrru);
 259         }
 260         return ret;
 261 }
 262
 263 static LIST_HEAD(dmar_atsr_units);
 264
 265 static int __init dmar_parse_one_atsr(struct acpi_dmar_header *hdr)
 266 {
 267         struct acpi_dmar_atsr *atsr;
 268         struct dmar_atsr_unit *atsru;
 269
 270         atsr = container_of(hdr, struct acpi_dmar_atsr, header);
 271         atsru = kzalloc(sizeof(*atsru), GFP_KERNEL);
 272         if (!atsru)
 273                 return -ENOMEM;
 274
 275         atsru->hdr = hdr;
 276         atsru->include_all = atsr->flags & 0x1;
 277
 278         list_add(&atsru->list, &dmar_atsr_units);
 279
 280         return 0;
 281 }
 282
 283 static int __init atsr_parse_dev(struct dmar_atsr_unit *atsru)
 284 {
 285         int rc;
 286         struct acpi_dmar_atsr *atsr;
 287
 288         if (atsru->include_all)
 289                 return 0;
 290
 291         atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
 292         rc = dmar_parse_dev_scope((void *)(atsr + 1),
 293                                 (void *)atsr + atsr->header.length,
 294                                 &atsru->devices_cnt, &atsru->devices,
 295                                 atsr->segment);
 296         if (rc || !atsru->devices_cnt) {
 297                 list_del(&atsru->list);
 298                 kfree(atsru);
 299         }
 300
 301         return rc;
 302 }
 303
 304 int dmar_find_matched_atsr_unit(struct pci_dev *dev)
 305 {
 306         int i;
 307         struct pci_bus *bus;
 308         struct acpi_dmar_atsr *atsr;
 309         struct dmar_atsr_unit *atsru;
 310
 311         list_for_each_entry(atsru, &dmar_atsr_units, list) {
 312                 atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
 313                 if (atsr->segment == pci_domain_nr(dev->bus))
 314                         goto found;
 315         }
 316
 317         return 0;
 318
 319 found:
 320         for (bus = dev->bus; bus; bus = bus->parent) {
 321                 struct pci_dev *bridge = bus->self;
 322
 323                 if (!bridge || !bridge->is_pcie ||
 324                     bridge->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
 325                         return 0;
 326
 327                 if (bridge->pcie_type == PCI_EXP_TYPE_ROOT_PORT) {
 328                         for (i = 0; i < atsru->devices_cnt; i++)
 329                                 if (atsru->devices[i] == bridge)
 330                                         return 1;
 331                         break;
 332                 }
 333         }
 334
 335         if (atsru->include_all)
 336                 return 1;
 337
 338         return 0;
 339 }
 340 #endif
 341
 342 #ifdef CONFIG_ACPI_NUMA
 343 static int __init
 344 dmar_parse_one_rhsa(struct acpi_dmar_header *header)
 345 {
 346         struct acpi_dmar_rhsa *rhsa;
 347         struct dmar_drhd_unit *drhd;
 348
 349         rhsa = (struct acpi_dmar_rhsa *)header;
 350         for_each_drhd_unit(drhd) {
 351                 if (drhd->reg_base_addr == rhsa->base_address) {
 352                         int node = acpi_map_pxm_to_node(rhsa->proximity_domain);
 353
 354                         if (!node_online(node))
 355                                 node = -1;
 356                         drhd->iommu->node = node;
 357                         return 0;
 358                 }
 359         }
 360         WARN(1, "Your BIOS is broken; RHSA refers to non-existent DMAR unit at %llx\n"
 361              "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
 362              drhd->reg_base_addr,
 363              dmi_get_system_info(DMI_BIOS_VENDOR),
 364              dmi_get_system_info(DMI_BIOS_VERSION),
 365              dmi_get_system_info(DMI_PRODUCT_VERSION));
 366
 367         return 0;
 368 }
 369 #endif
 370
 371 static void __init
 372 dmar_table_print_dmar_entry(struct acpi_dmar_header *header)
 373 {
 374         struct acpi_dmar_hardware_unit *drhd;
 375         struct acpi_dmar_reserved_memory *rmrr;
 376         struct acpi_dmar_atsr *atsr;
 377         struct acpi_dmar_rhsa *rhsa;
 378
 379         switch (header->type) {
 380         case ACPI_DMAR_TYPE_HARDWARE_UNIT:
 381                 drhd = container_of(header, struct acpi_dmar_hardware_unit,
 382                                     header);
 383                 printk (KERN_INFO PREFIX
 384                         "DRHD base: %#016Lx flags: %#x\n",
 385                         (unsigned long long)drhd->address, drhd->flags);
 386                 break;
 387         case ACPI_DMAR_TYPE_RESERVED_MEMORY:
 388                 rmrr = container_of(header, struct acpi_dmar_reserved_memory,
 389                                     header);
 390                 printk (KERN_INFO PREFIX
 391                         "RMRR base: %#016Lx end: %#016Lx\n",
 392                         (unsigned long long)rmrr->base_address,
 393                         (unsigned long long)rmrr->end_address);
 394                 break;
 395         case ACPI_DMAR_TYPE_ATSR:
 396                 atsr = container_of(header, struct acpi_dmar_atsr, header);
 397                 printk(KERN_INFO PREFIX "ATSR flags: %#x\n", atsr->flags);
 398                 break;
 399         case ACPI_DMAR_HARDWARE_AFFINITY:
 400                 rhsa = container_of(header, struct acpi_dmar_rhsa, header);
 401                 printk(KERN_INFO PREFIX "RHSA base: %#016Lx proximity domain: %#x\n",
 402                        (unsigned long long)rhsa->base_address,
 403                        rhsa->proximity_domain);
 404                 break;
 405         }
 406 }
 407
 408 /**
 409  * dmar_table_detect - checks to see if the platform supports DMAR devices
 410  */
 411 static int __init dmar_table_detect(void)
 412 {
 413         acpi_status status = AE_OK;
 414
 415         /* if we could find DMAR table, then there are DMAR devices */
 416         status = acpi_get_table_with_size(ACPI_SIG_DMAR, 0,
 417                                 (struct acpi_table_header **)&dmar_tbl,
 418                                 &dmar_tbl_size);
 419
 420         if (ACPI_SUCCESS(status) && !dmar_tbl) {
 421                 printk (KERN_WARNING PREFIX "Unable to map DMAR\n");
 422                 status = AE_NOT_FOUND;
 423         }
 424
 425         return (ACPI_SUCCESS(status) ? 1 : 0);
 426 }
 427
 428 /**
 429  * parse_dmar_table - parses the DMA reporting table
 430  */
 431 static int __init
 432 parse_dmar_table(void)
 433 {
 434         struct acpi_table_dmar *dmar;
 435         struct acpi_dmar_header *entry_header;
 436         int ret = 0;
 437
 438         /*
 439          * Do it again, earlier dmar_tbl mapping could be mapped with
 440          * fixed map.
 441          */
 442         dmar_table_detect();
 443
 444         /*
 445          * ACPI tables may not be DMA protected by tboot, so use DMAR copy
 446          * SINIT saved in SinitMleData in TXT heap (which is DMA protected)
 447          */
 448         dmar_tbl = tboot_get_dmar_table(dmar_tbl);
 449
 450         dmar = (struct acpi_table_dmar *)dmar_tbl;
 451         if (!dmar)
 452                 return -ENODEV;
 453
 454         if (dmar->width < PAGE_SHIFT - 1) {
 455                 printk(KERN_WARNING PREFIX "Invalid DMAR haw\n");
 456                 return -EINVAL;
 457         }
 458
 459         printk (KERN_INFO PREFIX "Host address width %d\n",
 460                 dmar->width + 1);
 461
 462         entry_header = (struct acpi_dmar_header *)(dmar + 1);
 463         while (((unsigned long)entry_header) <
 464                         (((unsigned long)dmar) + dmar_tbl->length)) {
 465                 /* Avoid looping forever on bad ACPI tables */
 466                 if (entry_header->length == 0) {
 467                         printk(KERN_WARNING PREFIX
 468                                 "Invalid 0-length structure\n");
 469                         ret = -EINVAL;
 470                         break;
 471                 }
 472
 473                 dmar_table_print_dmar_entry(entry_header);
 474
 475                 switch (entry_header->type) {
 476                 case ACPI_DMAR_TYPE_HARDWARE_UNIT:
 477                         ret = dmar_parse_one_drhd(entry_header);
 478                         break;
 479                 case ACPI_DMAR_TYPE_RESERVED_MEMORY:
 480 #ifdef CONFIG_DMAR
 481                         ret = dmar_parse_one_rmrr(entry_header);
 482 #endif
 483                         break;
 484                 case ACPI_DMAR_TYPE_ATSR:
 485 #ifdef CONFIG_DMAR
 486                         ret = dmar_parse_one_atsr(entry_header);
 487 #endif
 488                         break;
 489                 case ACPI_DMAR_HARDWARE_AFFINITY:
 490 #ifdef CONFIG_ACPI_NUMA
 491                         ret = dmar_parse_one_rhsa(entry_header);
 492 #endif
 493                         break;
 494                 default:
 495                         printk(KERN_WARNING PREFIX
 496                                 "Unknown DMAR structure type %d\n",
 497                                 entry_header->type);
 498                         ret = 0; /* for forward compatibility */
 499                         break;
 500                 }
 501                 if (ret)
 502                         break;
 503
 504                 entry_header = ((void *)entry_header + entry_header->length);
 505         }
 506         return ret;
 507 }
 508
 509 int dmar_pci_device_match(struct pci_dev *devices[], int cnt,
 510                           struct pci_dev *dev)
 511 {
 512         int index;
 513
 514         while (dev) {
 515                 for (index = 0; index < cnt; index++)
 516                         if (dev == devices[index])
 517                                 return 1;
 518
 519                 /* Check our parent */
 520                 dev = dev->bus->self;
 521         }
 522
 523         return 0;
 524 }
 525
 526 struct dmar_drhd_unit *
 527 dmar_find_matched_drhd_unit(struct pci_dev *dev)
 528 {
 529         struct dmar_drhd_unit *dmaru = NULL;
 530         struct acpi_dmar_hardware_unit *drhd;
 531
 532         list_for_each_entry(dmaru, &dmar_drhd_units, list) {
 533                 drhd = container_of(dmaru->hdr,
 534                                     struct acpi_dmar_hardware_unit,
 535                                     header);
 536
 537                 if (dmaru->include_all &&
 538                     drhd->segment == pci_domain_nr(dev->bus))
 539                         return dmaru;
 540
 541                 if (dmar_pci_device_match(dmaru->devices,
 542                                           dmaru->devices_cnt, dev))
 543                         return dmaru;
 544         }
 545
 546         return NULL;
 547 }
 548
 549 int __init dmar_dev_scope_init(void)
 550 {
 551         struct dmar_drhd_unit *drhd, *drhd_n;
 552         int ret = -ENODEV;
 553
 554         list_for_each_entry_safe(drhd, drhd_n, &dmar_drhd_units, list) {
 555                 ret = dmar_parse_dev(drhd);
 556                 if (ret)
 557                         return ret;
 558         }
 559
 560 #ifdef CONFIG_DMAR
 561         {
 562                 struct dmar_rmrr_unit *rmrr, *rmrr_n;
 563                 struct dmar_atsr_unit *atsr, *atsr_n;
 564
 565                 list_for_each_entry_safe(rmrr, rmrr_n, &dmar_rmrr_units, list) {
 566                         ret = rmrr_parse_dev(rmrr);
 567                         if (ret)
 568                                 return ret;
 569                 }
 570
 571                 list_for_each_entry_safe(atsr, atsr_n, &dmar_atsr_units, list) {
 572                         ret = atsr_parse_dev(atsr);
 573                         if (ret)
 574                                 return ret;
 575                 }
 576         }
 577 #endif
 578
 579         return ret;
 580 }
 581
 582
 583 int __init dmar_table_init(void)
 584 {
 585         static int dmar_table_initialized;
 586         int ret;
 587
 588         if (dmar_table_initialized)
 589                 return 0;
 590
 591         dmar_table_initialized = 1;
 592
 593         ret = parse_dmar_table();
 594         if (ret) {
 595                 if (ret != -ENODEV)
 596                         printk(KERN_INFO PREFIX "parse DMAR table failure.\n");
 597                 return ret;
 598         }
 599
 600         if (list_empty(&dmar_drhd_units)) {
 601                 printk(KERN_INFO PREFIX "No DMAR devices found\n");
 602                 return -ENODEV;
 603         }
 604
 605 #ifdef CONFIG_DMAR
 606         if (list_empty(&dmar_rmrr_units))
 607                 printk(KERN_INFO PREFIX "No RMRR found\n");
 608
 609         if (list_empty(&dmar_atsr_units))
 610                 printk(KERN_INFO PREFIX "No ATSR found\n");
 611 #endif
 612
 613         return 0;
 614 }
 615
 616 int __init check_zero_address(void)
 617 {
 618         struct acpi_table_dmar *dmar;
 619         struct acpi_dmar_header *entry_header;
 620         struct acpi_dmar_hardware_unit *drhd;
 621
 622         dmar = (struct acpi_table_dmar *)dmar_tbl;
 623         entry_header = (struct acpi_dmar_header *)(dmar + 1);
 624
 625         while (((unsigned long)entry_header) <
 626                         (((unsigned long)dmar) + dmar_tbl->length)) {
 627                 /* Avoid looping forever on bad ACPI tables */
 628                 if (entry_header->length == 0) {
 629                         printk(KERN_WARNING PREFIX
 630                                 "Invalid 0-length structure\n");
 631                         return 0;
 632                 }
 633
 634                 if (entry_header->type == ACPI_DMAR_TYPE_HARDWARE_UNIT) {
 635                         void __iomem *addr;
 636                         u64 cap, ecap;
 637
 638                         drhd = (void *)entry_header;
 639                         if (!drhd->address) {
 640                                 /* Promote an attitude of violence to a BIOS engineer today */
 641                                 WARN(1, "Your BIOS is broken; DMAR reported at address zero!\n"
 642                                      "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
 643                                      dmi_get_system_info(DMI_BIOS_VENDOR),
 644                                      dmi_get_system_info(DMI_BIOS_VERSION),
 645                                      dmi_get_system_info(DMI_PRODUCT_VERSION));
 646                                 goto failed;
 647                         }
 648
 649                         addr = early_ioremap(drhd->address, VTD_PAGE_SIZE);
 650                         if (!addr ) {
 651                                 printk("IOMMU: can't validate: %llx\n", drhd->address);
 652                                 goto failed;
 653                         }
 654                         cap = dmar_readq(addr + DMAR_CAP_REG);
 655                         ecap = dmar_readq(addr + DMAR_ECAP_REG);
 656                         early_iounmap(addr, VTD_PAGE_SIZE);
 657                         if (cap == (uint64_t)-1 && ecap == (uint64_t)-1) {
 658                                 /* Promote an attitude of violence to a BIOS engineer today */
 659                                 WARN(1, "Your BIOS is broken; DMAR reported at address %llx returns all ones!\n"
 660                                      "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
 661                                       drhd->address,
 662                                       dmi_get_system_info(DMI_BIOS_VENDOR),
 663                                       dmi_get_system_info(DMI_BIOS_VERSION),
 664                                       dmi_get_system_info(DMI_PRODUCT_VERSION));
 665                                 goto failed;
 666                         }
 667                 }
 668
 669                 entry_header = ((void *)entry_header + entry_header->length);
 670         }
 671         return 1;
 672
 673 failed:
 674 #ifdef CONFIG_DMAR
 675         dmar_disabled = 1;
 676 #endif
 677         return 0;
 678 }
 679
 680 void __init detect_intel_iommu(void)
 681 {
 682         int ret;
 683
 684         ret = dmar_table_detect();
 685         if (ret)
 686                 ret = check_zero_address();
 687         {
 688 #ifdef CONFIG_INTR_REMAP
 689                 struct acpi_table_dmar *dmar;
 690                 /*
 691                  * for now we will disable dma-remapping when interrupt
 692                  * remapping is enabled.
 693                  * When support for queued invalidation for IOTLB invalidation
 694                  * is added, we will not need this any more.
 695                  */
 696                 dmar = (struct acpi_table_dmar *) dmar_tbl;
 697                 if (ret && cpu_has_x2apic && dmar->flags & 0x1)
 698                         printk(KERN_INFO
 699                                "Queued invalidation will be enabled to support "
 700                                "x2apic and Intr-remapping.\n");
 701 #endif
 702 #ifdef CONFIG_DMAR
 703                 if (ret && !no_iommu && !iommu_detected && !dmar_disabled)
 704                         iommu_detected = 1;
 705 #endif
 706 #ifdef CONFIG_X86
 707                 if (ret)
 708                         x86_init.iommu.iommu_init = intel_iommu_init;
 709 #endif
 710         }
 711         early_acpi_os_unmap_memory(dmar_tbl, dmar_tbl_size);
 712         dmar_tbl = NULL;
 713 }
 714
 715
 716 int alloc_iommu(struct dmar_drhd_unit *drhd)
 717 {
 718         struct intel_iommu *iommu;
 719         int map_size;
 720         u32 ver;
 721         static int iommu_allocated = 0;
 722         int agaw = 0;
 723         int msagaw = 0;
 724
 725         iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
 726         if (!iommu)
 727                 return -ENOMEM;
 728
 729         iommu->seq_id = iommu_allocated++;
 730         sprintf (iommu->name, "dmar%d", iommu->seq_id);
 731
 732         iommu->reg = ioremap(drhd->reg_base_addr, VTD_PAGE_SIZE);
 733         if (!iommu->reg) {
 734                 printk(KERN_ERR "IOMMU: can't map the region\n");
 735                 goto error;
 736         }
 737         iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG);
 738         iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG);
 739
 740         if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) {
 741                 /* Promote an attitude of violence to a BIOS engineer today */
 742                 WARN(1, "Your BIOS is broken; DMAR reported at address %llx returns all ones!\n"
 743                      "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
 744                      drhd->reg_base_addr,
 745                      dmi_get_system_info(DMI_BIOS_VENDOR),
 746                      dmi_get_system_info(DMI_BIOS_VERSION),
 747                      dmi_get_system_info(DMI_PRODUCT_VERSION));
 748                 goto err_unmap;
 749         }
 750
 751 #ifdef CONFIG_DMAR
 752         agaw = iommu_calculate_agaw(iommu);
 753         if (agaw < 0) {
 754                 printk(KERN_ERR
 755                        "Cannot get a valid agaw for iommu (seq_id = %d)\n",
 756                        iommu->seq_id);
 757                 goto err_unmap;
 758         }
 759         msagaw = iommu_calculate_max_sagaw(iommu);
 760         if (msagaw < 0) {
 761                 printk(KERN_ERR
 762                         "Cannot get a valid max agaw for iommu (seq_id = %d)\n",
 763                         iommu->seq_id);
 764                 goto err_unmap;
 765         }
 766 #endif
 767         iommu->agaw = agaw;
 768         iommu->msagaw = msagaw;
 769
 770         iommu->node = -1;
 771
 772         /* the registers might be more than one page */
 773         map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap),
 774                 cap_max_fault_reg_offset(iommu->cap));
 775         map_size = VTD_PAGE_ALIGN(map_size);
 776         if (map_size > VTD_PAGE_SIZE) {
 777                 iounmap(iommu->reg);
 778                 iommu->reg = ioremap(drhd->reg_base_addr, map_size);
 779                 if (!iommu->reg) {
 780                         printk(KERN_ERR "IOMMU: can't map the region\n");
 781                         goto error;
 782                 }
 783         }
 784
 785         ver = readl(iommu->reg + DMAR_VER_REG);
 786         pr_info("IOMMU %llx: ver %d:%d cap %llx ecap %llx\n",
 787                 (unsigned long long)drhd->reg_base_addr,
 788                 DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver),
 789                 (unsigned long long)iommu->cap,
 790                 (unsigned long long)iommu->ecap);
 791
 792         spin_lock_init(&iommu->register_lock);
 793
 794         drhd->iommu = iommu;
 795         return 0;
 796
 797  err_unmap:
 798         iounmap(iommu->reg);
 799  error:
 800         kfree(iommu);
 801         return -1;
 802 }
 803
 804 void free_iommu(struct intel_iommu *iommu)
 805 {
 806         if (!iommu)
 807                 return;
 808
 809 #ifdef CONFIG_DMAR
 810         free_dmar_iommu(iommu);
 811 #endif
 812
 813         if (iommu->reg)
 814                 iounmap(iommu->reg);
 815         kfree(iommu);
 816 }
 817
 818 /*
 819  * Reclaim all the submitted descriptors which have completed its work.
 820  */
 821 static inline void reclaim_free_desc(struct q_inval *qi)
 822 {
 823         while (qi->desc_status[qi->free_tail] == QI_DONE ||
 824                qi->desc_status[qi->free_tail] == QI_ABORT) {
 825                 qi->desc_status[qi->free_tail] = QI_FREE;
 826                 qi->free_tail = (qi->free_tail + 1) % QI_LENGTH;
 827                 qi->free_cnt++;
 828         }
 829 }
 830
 831 static int qi_check_fault(struct intel_iommu *iommu, int index)
 832 {
 833         u32 fault;
 834         int head, tail;
 835         struct q_inval *qi = iommu->qi;
 836         int wait_index = (index + 1) % QI_LENGTH;
 837
 838         if (qi->desc_status[wait_index] == QI_ABORT)
 839                 return -EAGAIN;
 840
 841         fault = readl(iommu->reg + DMAR_FSTS_REG);
 842
 843         /*
 844          * If IQE happens, the head points to the descriptor associated
 845          * with the error. No new descriptors are fetched until the IQE
 846          * is cleared.
 847          */
 848         if (fault & DMA_FSTS_IQE) {
 849                 head = readl(iommu->reg + DMAR_IQH_REG);
 850                 if ((head >> DMAR_IQ_SHIFT) == index) {
 851                         printk(KERN_ERR "VT-d detected invalid descriptor: "
 852                                 "low=%llx, high=%llx\n",
 853                                 (unsigned long long)qi->desc[index].low,
 854                                 (unsigned long long)qi->desc[index].high);
 855                         memcpy(&qi->desc[index], &qi->desc[wait_index],
 856                                         sizeof(struct qi_desc));
 857                         __iommu_flush_cache(iommu, &qi->desc[index],
 858                                         sizeof(struct qi_desc));
 859                         writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG);
 860                         return -EINVAL;
 861                 }
 862         }
 863
 864         /*
 865          * If ITE happens, all pending wait_desc commands are aborted.
 866          * No new descriptors are fetched until the ITE is cleared.
 867          */
 868         if (fault & DMA_FSTS_ITE) {
 869                 head = readl(iommu->reg + DMAR_IQH_REG);
 870                 head = ((head >> DMAR_IQ_SHIFT) - 1 + QI_LENGTH) % QI_LENGTH;
 871                 head |= 1;
 872                 tail = readl(iommu->reg + DMAR_IQT_REG);
 873                 tail = ((tail >> DMAR_IQ_SHIFT) - 1 + QI_LENGTH) % QI_LENGTH;
 874
 875                 writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG);
 876
 877                 do {
 878                         if (qi->desc_status[head] == QI_IN_USE)
 879                                 qi->desc_status[head] = QI_ABORT;
 880                         head = (head - 2 + QI_LENGTH) % QI_LENGTH;
 881                 } while (head != tail);
 882
 883                 if (qi->desc_status[wait_index] == QI_ABORT)
 884                         return -EAGAIN;
 885         }
 886
 887         if (fault & DMA_FSTS_ICE)
 888                 writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG);
 889
 890         return 0;
 891 }
 892
 893 /*
 894  * Submit the queued invalidation descriptor to the remapping
 895  * hardware unit and wait for its completion.
 896  */
 897 int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu)
 898 {
 899         int rc;
 900         struct q_inval *qi = iommu->qi;
 901         struct qi_desc *hw, wait_desc;
 902         int wait_index, index;
 903         unsigned long flags;
 904
 905         if (!qi)
 906                 return 0;
 907
 908         hw = qi->desc;
 909
 910 restart:
 911         rc = 0;
 912
 913         spin_lock_irqsave(&qi->q_lock, flags);
 914         while (qi->free_cnt < 3) {
 915                 spin_unlock_irqrestore(&qi->q_lock, flags);
 916                 cpu_relax();
 917                 spin_lock_irqsave(&qi->q_lock, flags);
 918         }
 919
 920         index = qi->free_head;
 921         wait_index = (index + 1) % QI_LENGTH;
 922
 923         qi->desc_status[index] = qi->desc_status[wait_index] = QI_IN_USE;
 924
 925         hw[index] = *desc;
 926
 927         wait_desc.low = QI_IWD_STATUS_DATA(QI_DONE) |
 928                         QI_IWD_STATUS_WRITE | QI_IWD_TYPE;
 929         wait_desc.high = virt_to_phys(&qi->desc_status[wait_index]);
 930
 931         hw[wait_index] = wait_desc;
 932
 933         __iommu_flush_cache(iommu, &hw[index], sizeof(struct qi_desc));
 934         __iommu_flush_cache(iommu, &hw[wait_index], sizeof(struct qi_desc));
 935
 936         qi->free_head = (qi->free_head + 2) % QI_LENGTH;
 937         qi->free_cnt -= 2;
 938
 939         /*
 940          * update the HW tail register indicating the presence of
 941          * new descriptors.
 942          */
 943         writel(qi->free_head << DMAR_IQ_SHIFT, iommu->reg + DMAR_IQT_REG);
 944
 945         while (qi->desc_status[wait_index] != QI_DONE) {
 946                 /*
 947                  * We will leave the interrupts disabled, to prevent interrupt
 948                  * context to queue another cmd while a cmd is already submitted
 949                  * and waiting for completion on this cpu. This is to avoid
 950                  * a deadlock where the interrupt context can wait indefinitely
 951                  * for free slots in the queue.
 952                  */
 953                 rc = qi_check_fault(iommu, index);
 954                 if (rc)
 955                         break;
 956
 957                 spin_unlock(&qi->q_lock);
 958                 cpu_relax();
 959                 spin_lock(&qi->q_lock);
 960         }
 961
 962         qi->desc_status[index] = QI_DONE;
 963
 964         reclaim_free_desc(qi);
 965         spin_unlock_irqrestore(&qi->q_lock, flags);
 966
 967         if (rc == -EAGAIN)
 968                 goto restart;
 969
 970         return rc;
 971 }
 972
 973 /*
 974  * Flush the global interrupt entry cache.
 975  */
 976 void qi_global_iec(struct intel_iommu *iommu)
 977 {
 978         struct qi_desc desc;
 979
 980         desc.low = QI_IEC_TYPE;
 981         desc.high = 0;
 982
 983         /* should never fail */
 984         qi_submit_sync(&desc, iommu);
 985 }
 986
 987 void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm,
 988                       u64 type)
 989 {
 990         struct qi_desc desc;
 991
 992         desc.low = QI_CC_FM(fm) | QI_CC_SID(sid) | QI_CC_DID(did)
 993                         | QI_CC_GRAN(type) | QI_CC_TYPE;
 994         desc.high = 0;
 995
 996         qi_submit_sync(&desc, iommu);
 997 }
 998
 999 void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
1000                     unsigned int size_order, u64 type)
1001 {
1002         u8 dw = 0, dr = 0;
1003
1004         struct qi_desc desc;
1005         int ih = 0;
1006
1007         if (cap_write_drain(iommu->cap))
1008                 dw = 1;
1009
1010         if (cap_read_drain(iommu->cap))
1011                 dr = 1;
1012
1013         desc.low = QI_IOTLB_DID(did) | QI_IOTLB_DR(dr) | QI_IOTLB_DW(dw)
1014                 | QI_IOTLB_GRAN(type) | QI_IOTLB_TYPE;
1015         desc.high = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih)
1016                 | QI_IOTLB_AM(size_order);
1017
1018         qi_submit_sync(&desc, iommu);
1019 }
1020
1021 void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep,
1022                         u64 addr, unsigned mask)
1023 {
1024         struct qi_desc desc;
1025
1026         if (mask) {
1027                 BUG_ON(addr & ((1 << (VTD_PAGE_SHIFT + mask)) - 1));
1028                 addr |= (1 << (VTD_PAGE_SHIFT + mask - 1)) - 1;
1029                 desc.high = QI_DEV_IOTLB_ADDR(addr) | QI_DEV_IOTLB_SIZE;
1030         } else
1031                 desc.high = QI_DEV_IOTLB_ADDR(addr);
1032
1033         if (qdep >= QI_DEV_IOTLB_MAX_INVS)
1034                 qdep = 0;
1035
1036         desc.low = QI_DEV_IOTLB_SID(sid) | QI_DEV_IOTLB_QDEP(qdep) |
1037                    QI_DIOTLB_TYPE;
1038
1039         qi_submit_sync(&desc, iommu);
1040 }
1041
1042 /*
1043  * Disable Queued Invalidation interface.
1044  */
1045 void dmar_disable_qi(struct intel_iommu *iommu)
1046 {
1047         unsigned long flags;
1048         u32 sts;
1049         cycles_t start_time = get_cycles();
1050
1051         if (!ecap_qis(iommu->ecap))
1052                 return;
1053
1054         spin_lock_irqsave(&iommu->register_lock, flags);
1055
1056         sts =  dmar_readq(iommu->reg + DMAR_GSTS_REG);
1057         if (!(sts & DMA_GSTS_QIES))
1058                 goto end;
1059
1060         /*
1061          * Give a chance to HW to complete the pending invalidation requests.
1062          */
1063         while ((readl(iommu->reg + DMAR_IQT_REG) !=
1064                 readl(iommu->reg + DMAR_IQH_REG)) &&
1065                 (DMAR_OPERATION_TIMEOUT > (get_cycles() - start_time)))
1066                 cpu_relax();
1067
1068         iommu->gcmd &= ~DMA_GCMD_QIE;
1069         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1070
1071         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl,
1072                       !(sts & DMA_GSTS_QIES), sts);
1073 end:
1074         spin_unlock_irqrestore(&iommu->register_lock, flags);
1075 }
1076
1077 /*
1078  * Enable queued invalidation.
1079  */
1080 static void __dmar_enable_qi(struct intel_iommu *iommu)
1081 {
1082         u32 sts;
1083         unsigned long flags;
1084         struct q_inval *qi = iommu->qi;
1085
1086         qi->free_head = qi->free_tail = 0;
1087         qi->free_cnt = QI_LENGTH;
1088
1089         spin_lock_irqsave(&iommu->register_lock, flags);
1090
1091         /* write zero to the tail reg */
1092         writel(0, iommu->reg + DMAR_IQT_REG);
1093
1094         dmar_writeq(iommu->reg + DMAR_IQA_REG, virt_to_phys(qi->desc));
1095
1096         iommu->gcmd |= DMA_GCMD_QIE;
1097         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1098
1099         /* Make sure hardware complete it */
1100         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts);
1101
1102         spin_unlock_irqrestore(&iommu->register_lock, flags);
1103 }
1104
1105 /*
1106  * Enable Queued Invalidation interface. This is a must to support
1107  * interrupt-remapping. Also used by DMA-remapping, which replaces
1108  * register based IOTLB invalidation.
1109  */
1110 int dmar_enable_qi(struct intel_iommu *iommu)
1111 {
1112         struct q_inval *qi;
1113         struct page *desc_page;
1114
1115         if (!ecap_qis(iommu->ecap))
1116                 return -ENOENT;
1117
1118         /*
1119          * queued invalidation is already setup and enabled.
1120          */
1121         if (iommu->qi)
1122                 return 0;
1123
1124         iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC);
1125         if (!iommu->qi)
1126                 return -ENOMEM;
1127
1128         qi = iommu->qi;
1129
1130
1131         desc_page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, 0);
1132         if (!desc_page) {
1133                 kfree(qi);
1134                 iommu->qi = 0;
1135                 return -ENOMEM;
1136         }
1137
1138         qi->desc = page_address(desc_page);
1139
1140         qi->desc_status = kmalloc(QI_LENGTH * sizeof(int), GFP_ATOMIC);
1141         if (!qi->desc_status) {
1142                 free_page((unsigned long) qi->desc);
1143                 kfree(qi);
1144                 iommu->qi = 0;
1145                 return -ENOMEM;
1146         }
1147
1148         qi->free_head = qi->free_tail = 0;
1149         qi->free_cnt = QI_LENGTH;
1150
1151         spin_lock_init(&qi->q_lock);
1152
1153         __dmar_enable_qi(iommu);
1154
1155         return 0;
1156 }
1157
1158 /* iommu interrupt handling. Most stuff are MSI-like. */
1159
1160 enum faulttype {
1161         DMA_REMAP,
1162         INTR_REMAP,
1163         UNKNOWN,
1164 };
1165
1166 static const char *dma_remap_fault_reasons[] =
1167 {
1168         "Software",
1169         "Present bit in root entry is clear",
1170         "Present bit in context entry is clear",
1171         "Invalid context entry",
1172         "Access beyond MGAW",
1173         "PTE Write access is not set",
1174         "PTE Read access is not set",
1175         "Next page table ptr is invalid",
1176         "Root table address invalid",
1177         "Context table ptr is invalid",
1178         "non-zero reserved fields in RTP",
1179         "non-zero reserved fields in CTP",
1180         "non-zero reserved fields in PTE",
1181 };
1182
1183 static const char *intr_remap_fault_reasons[] =
1184 {
1185         "Detected reserved fields in the decoded interrupt-remapped request",
1186         "Interrupt index exceeded the interrupt-remapping table size",
1187         "Present field in the IRTE entry is clear",
1188         "Error accessing interrupt-remapping table pointed by IRTA_REG",
1189         "Detected reserved fields in the IRTE entry",
1190         "Blocked a compatibility format interrupt request",
1191         "Blocked an interrupt request due to source-id verification failure",
1192 };
1193
1194 #define MAX_FAULT_REASON_IDX    (ARRAY_SIZE(fault_reason_strings) - 1)
1195
1196 const char *dmar_get_fault_reason(u8 fault_reason, int *fault_type)
1197 {
1198         if (fault_reason >= 0x20 && (fault_reason <= 0x20 +
1199                                      ARRAY_SIZE(intr_remap_fault_reasons))) {
1200                 *fault_type = INTR_REMAP;
1201                 return intr_remap_fault_reasons[fault_reason - 0x20];
1202         } else if (fault_reason < ARRAY_SIZE(dma_remap_fault_reasons)) {
1203                 *fault_type = DMA_REMAP;
1204                 return dma_remap_fault_reasons[fault_reason];
1205         } else {
1206                 *fault_type = UNKNOWN;
1207                 return "Unknown";
1208         }
1209 }
1210
1211 void dmar_msi_unmask(unsigned int irq)
1212 {
1213         struct intel_iommu *iommu = get_irq_data(irq);
1214         unsigned long flag;
1215
1216         /* unmask it */
1217         spin_lock_irqsave(&iommu->register_lock, flag);
1218         writel(0, iommu->reg + DMAR_FECTL_REG);
1219         /* Read a reg to force flush the post write */
1220         readl(iommu->reg + DMAR_FECTL_REG);
1221         spin_unlock_irqrestore(&iommu->register_lock, flag);
1222 }
1223
1224 void dmar_msi_mask(unsigned int irq)
1225 {
1226         unsigned long flag;
1227         struct intel_iommu *iommu = get_irq_data(irq);
1228
1229         /* mask it */
1230         spin_lock_irqsave(&iommu->register_lock, flag);
1231         writel(DMA_FECTL_IM, iommu->reg + DMAR_FECTL_REG);
1232         /* Read a reg to force flush the post write */
1233         readl(iommu->reg + DMAR_FECTL_REG);
1234         spin_unlock_irqrestore(&iommu->register_lock, flag);
1235 }
1236
1237 void dmar_msi_write(int irq, struct msi_msg *msg)
1238 {
1239         struct intel_iommu *iommu = get_irq_data(irq);
1240         unsigned long flag;
1241
1242         spin_lock_irqsave(&iommu->register_lock, flag);
1243         writel(msg->data, iommu->reg + DMAR_FEDATA_REG);
1244         writel(msg->address_lo, iommu->reg + DMAR_FEADDR_REG);
1245         writel(msg->address_hi, iommu->reg + DMAR_FEUADDR_REG);
1246         spin_unlock_irqrestore(&iommu->register_lock, flag);
1247 }
1248
1249 void dmar_msi_read(int irq, struct msi_msg *msg)
1250 {
1251         struct intel_iommu *iommu = get_irq_data(irq);
1252         unsigned long flag;
1253
1254         spin_lock_irqsave(&iommu->register_lock, flag);
1255         msg->data = readl(iommu->reg + DMAR_FEDATA_REG);
1256         msg->address_lo = readl(iommu->reg + DMAR_FEADDR_REG);
1257         msg->address_hi = readl(iommu->reg + DMAR_FEUADDR_REG);
1258         spin_unlock_irqrestore(&iommu->register_lock, flag);
1259 }
1260
1261 static int dmar_fault_do_one(struct intel_iommu *iommu, int type,
1262                 u8 fault_reason, u16 source_id, unsigned long long addr)
1263 {
1264         const char *reason;
1265         int fault_type;
1266
1267         reason = dmar_get_fault_reason(fault_reason, &fault_type);
1268
1269         if (fault_type == INTR_REMAP)
1270                 printk(KERN_ERR "INTR-REMAP: Request device [[%02x:%02x.%d] "
1271                        "fault index %llx\n"
1272                         "INTR-REMAP:[fault reason %02d] %s\n",
1273                         (source_id >> 8), PCI_SLOT(source_id & 0xFF),
1274                         PCI_FUNC(source_id & 0xFF), addr >> 48,
1275                         fault_reason, reason);
1276         else
1277                 printk(KERN_ERR
1278                        "DMAR:[%s] Request device [%02x:%02x.%d] "
1279                        "fault addr %llx \n"
1280                        "DMAR:[fault reason %02d] %s\n",
1281                        (type ? "DMA Read" : "DMA Write"),
1282                        (source_id >> 8), PCI_SLOT(source_id & 0xFF),
1283                        PCI_FUNC(source_id & 0xFF), addr, fault_reason, reason);
1284         return 0;
1285 }
1286
1287 #define PRIMARY_FAULT_REG_LEN (16)
1288 irqreturn_t dmar_fault(int irq, void *dev_id)
1289 {
1290         struct intel_iommu *iommu = dev_id;
1291         int reg, fault_index;
1292         u32 fault_status;
1293         unsigned long flag;
1294
1295         spin_lock_irqsave(&iommu->register_lock, flag);
1296         fault_status = readl(iommu->reg + DMAR_FSTS_REG);
1297         if (fault_status)
1298                 printk(KERN_ERR "DRHD: handling fault status reg %x\n",
1299                        fault_status);
1300
1301         /* TBD: ignore advanced fault log currently */
1302         if (!(fault_status & DMA_FSTS_PPF))
1303                 goto clear_rest;
1304
1305         fault_index = dma_fsts_fault_record_index(fault_status);
1306         reg = cap_fault_reg_offset(iommu->cap);
1307         while (1) {
1308                 u8 fault_reason;
1309                 u16 source_id;
1310                 u64 guest_addr;
1311                 int type;
1312                 u32 data;
1313
1314                 /* highest 32 bits */
1315                 data = readl(iommu->reg + reg +
1316                                 fault_index * PRIMARY_FAULT_REG_LEN + 12);
1317                 if (!(data & DMA_FRCD_F))
1318                         break;
1319
1320                 fault_reason = dma_frcd_fault_reason(data);
1321                 type = dma_frcd_type(data);
1322
1323                 data = readl(iommu->reg + reg +
1324                                 fault_index * PRIMARY_FAULT_REG_LEN + 8);
1325                 source_id = dma_frcd_source_id(data);
1326
1327                 guest_addr = dmar_readq(iommu->reg + reg +
1328                                 fault_index * PRIMARY_FAULT_REG_LEN);
1329                 guest_addr = dma_frcd_page_addr(guest_addr);
1330                 /* clear the fault */
1331                 writel(DMA_FRCD_F, iommu->reg + reg +
1332                         fault_index * PRIMARY_FAULT_REG_LEN + 12);
1333
1334                 spin_unlock_irqrestore(&iommu->register_lock, flag);
1335
1336                 dmar_fault_do_one(iommu, type, fault_reason,
1337                                 source_id, guest_addr);
1338
1339                 fault_index++;
1340                 if (fault_index >= cap_num_fault_regs(iommu->cap))
1341                         fault_index = 0;
1342                 spin_lock_irqsave(&iommu->register_lock, flag);
1343         }
1344 clear_rest:
1345         /* clear all the other faults */
1346         fault_status = readl(iommu->reg + DMAR_FSTS_REG);
1347         writel(fault_status, iommu->reg + DMAR_FSTS_REG);
1348
1349         spin_unlock_irqrestore(&iommu->register_lock, flag);
1350         return IRQ_HANDLED;
1351 }
1352
1353 int dmar_set_interrupt(struct intel_iommu *iommu)
1354 {
1355         int irq, ret;
1356
1357         /*
1358          * Check if the fault interrupt is already initialized.
1359          */
1360         if (iommu->irq)
1361                 return 0;
1362
1363         irq = create_irq();
1364         if (!irq) {
1365                 printk(KERN_ERR "IOMMU: no free vectors\n");
1366                 return -EINVAL;
1367         }
1368
1369         set_irq_data(irq, iommu);
1370         iommu->irq = irq;
1371
1372         ret = arch_setup_dmar_msi(irq);
1373         if (ret) {
1374                 set_irq_data(irq, NULL);
1375                 iommu->irq = 0;
1376                 destroy_irq(irq);
1377                 return ret;
1378         }
1379
1380         ret = request_irq(irq, dmar_fault, 0, iommu->name, iommu);
1381         if (ret)
1382                 printk(KERN_ERR "IOMMU: can't request irq\n");
1383         return ret;
1384 }
1385
1386 int __init enable_drhd_fault_handling(void)
1387 {
1388         struct dmar_drhd_unit *drhd;
1389
1390         /*
1391          * Enable fault control interrupt.
1392          */
1393         for_each_drhd_unit(drhd) {
1394                 int ret;
1395                 struct intel_iommu *iommu = drhd->iommu;
1396                 ret = dmar_set_interrupt(iommu);
1397
1398                 if (ret) {
1399                         printk(KERN_ERR "DRHD %Lx: failed to enable fault, "
1400                                " interrupt, ret %d\n",
1401                                (unsigned long long)drhd->reg_base_addr, ret);
1402                         return -1;
1403                 }
1404         }
1405
1406         return 0;
1407 }
1408
1409 /*
1410  * Re-enable Queued Invalidation interface.
1411  */
1412 int dmar_reenable_qi(struct intel_iommu *iommu)
1413 {
1414         if (!ecap_qis(iommu->ecap))
1415                 return -ENOENT;
1416
1417         if (!iommu->qi)
1418                 return -ENOENT;
1419
1420         /*
1421          * First disable queued invalidation.
1422          */
1423         dmar_disable_qi(iommu);
1424         /*
1425          * Then enable queued invalidation again. Since there is no pending
1426          * invalidation requests now, it's safe to re-enable queued
1427          * invalidation.
1428          */
1429         __dmar_enable_qi(iommu);
1430
1431         return 0;
1432 }
1433
1434 /*
1435  * Check interrupt remapping support in DMAR table description.
1436  */
1437 int dmar_ir_support(void)
1438 {
1439         struct acpi_table_dmar *dmar;
1440         dmar = (struct acpi_table_dmar *)dmar_tbl;
1441         return dmar->flags & 0x1;
1442 }