SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/rt2x00/rt73usb.c

   1 /*
   2         Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt73usb
  23         Abstract: rt73usb device specific routines.
  24         Supported chipsets: rt2571W & rt2671.
  25  */
  26
  27 /*
  28  * Set enviroment defines for rt2x00.h
  29  */
  30 #define DRV_NAME "rt73usb"
  31
  32 #include <linux/delay.h>
  33 #include <linux/etherdevice.h>
  34 #include <linux/init.h>
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/usb.h>
  38
  39 #include "rt2x00.h"
  40 #include "rt2x00usb.h"
  41 #include "rt73usb.h"
  42
  43 /*
  44  * Register access.
  45  * All access to the CSR registers will go through the methods
  46  * rt73usb_register_read and rt73usb_register_write.
  47  * BBP and RF register require indirect register access,
  48  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  49  * These indirect registers work with busy bits,
  50  * and we will try maximal REGISTER_BUSY_COUNT times to access
  51  * the register while taking a REGISTER_BUSY_DELAY us delay
  52  * between each attampt. When the busy bit is still set at that time,
  53  * the access attempt is considered to have failed,
  54  * and we will print an error.
  55  */
  56 static inline void rt73usb_register_read(const struct rt2x00_dev *rt2x00dev,
  57                                          const unsigned int offset, u32 *value)
  58 {
  59         __le32 reg;
  60         rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
  61                                       USB_VENDOR_REQUEST_IN, offset,
  62                                       &reg, sizeof(u32), REGISTER_TIMEOUT);
  63         *value = le32_to_cpu(reg);
  64 }
  65
  66 static inline void rt73usb_register_multiread(const struct rt2x00_dev
  67                                               *rt2x00dev,
  68                                               const unsigned int offset,
  69                                               void *value, const u32 length)
  70 {
  71         int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
  72         rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
  73                                       USB_VENDOR_REQUEST_IN, offset,
  74                                       value, length, timeout);
  75 }
  76
  77 static inline void rt73usb_register_write(const struct rt2x00_dev *rt2x00dev,
  78                                           const unsigned int offset, u32 value)
  79 {
  80         __le32 reg = cpu_to_le32(value);
  81         rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
  82                                       USB_VENDOR_REQUEST_OUT, offset,
  83                                       &reg, sizeof(u32), REGISTER_TIMEOUT);
  84 }
  85
  86 static inline void rt73usb_register_multiwrite(const struct rt2x00_dev
  87                                                *rt2x00dev,
  88                                                const unsigned int offset,
  89                                                void *value, const u32 length)
  90 {
  91         int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
  92         rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
  93                                       USB_VENDOR_REQUEST_OUT, offset,
  94                                       value, length, timeout);
  95 }
  96
  97 static u32 rt73usb_bbp_check(const struct rt2x00_dev *rt2x00dev)
  98 {
  99         u32 reg;
 100         unsigned int i;
 101
 102         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 103                 rt73usb_register_read(rt2x00dev, PHY_CSR3, &reg);
 104                 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
 105                         break;
 106                 udelay(REGISTER_BUSY_DELAY);
 107         }
 108
 109         return reg;
 110 }
 111
 112 static void rt73usb_bbp_write(const struct rt2x00_dev *rt2x00dev,
 113                               const unsigned int word, const u8 value)
 114 {
 115         u32 reg;
 116
 117         /*
 118          * Wait until the BBP becomes ready.
 119          */
 120         reg = rt73usb_bbp_check(rt2x00dev);
 121         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
 122                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
 123                 return;
 124         }
 125
 126         /*
 127          * Write the data into the BBP.
 128          */
 129         reg = 0;
 130         rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
 131         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 132         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 133         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
 134
 135         rt73usb_register_write(rt2x00dev, PHY_CSR3, reg);
 136 }
 137
 138 static void rt73usb_bbp_read(const struct rt2x00_dev *rt2x00dev,
 139                              const unsigned int word, u8 *value)
 140 {
 141         u32 reg;
 142
 143         /*
 144          * Wait until the BBP becomes ready.
 145          */
 146         reg = rt73usb_bbp_check(rt2x00dev);
 147         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
 148                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
 149                 return;
 150         }
 151
 152         /*
 153          * Write the request into the BBP.
 154          */
 155         reg = 0;
 156         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 157         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 158         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
 159
 160         rt73usb_register_write(rt2x00dev, PHY_CSR3, reg);
 161
 162         /*
 163          * Wait until the BBP becomes ready.
 164          */
 165         reg = rt73usb_bbp_check(rt2x00dev);
 166         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
 167                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
 168                 *value = 0xff;
 169                 return;
 170         }
 171
 172         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
 173 }
 174
 175 static void rt73usb_rf_write(const struct rt2x00_dev *rt2x00dev,
 176                              const unsigned int word, const u32 value)
 177 {
 178         u32 reg;
 179         unsigned int i;
 180
 181         if (!word)
 182                 return;
 183
 184         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 185                 rt73usb_register_read(rt2x00dev, PHY_CSR4, &reg);
 186                 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
 187                         goto rf_write;
 188                 udelay(REGISTER_BUSY_DELAY);
 189         }
 190
 191         ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
 192         return;
 193
 194 rf_write:
 195         reg = 0;
 196         rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
 197
 198         /*
 199          * RF5225 and RF2527 contain 21 bits per RF register value,
 200          * all others contain 20 bits.
 201          */
 202         rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
 203                            20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 204                                  rt2x00_rf(&rt2x00dev->chip, RF2527)));
 205         rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
 206         rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
 207
 208         rt73usb_register_write(rt2x00dev, PHY_CSR4, reg);
 209         rt2x00_rf_write(rt2x00dev, word, value);
 210 }
 211
 212 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 213 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 214
 215 static void rt73usb_read_csr(const struct rt2x00_dev *rt2x00dev,
 216                              const unsigned int word, u32 *data)
 217 {
 218         rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data);
 219 }
 220
 221 static void rt73usb_write_csr(const struct rt2x00_dev *rt2x00dev,
 222                               const unsigned int word, u32 data)
 223 {
 224         rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
 225 }
 226
 227 static const struct rt2x00debug rt73usb_rt2x00debug = {
 228         .owner  = THIS_MODULE,
 229         .csr    = {
 230                 .read           = rt73usb_read_csr,
 231                 .write          = rt73usb_write_csr,
 232                 .word_size      = sizeof(u32),
 233                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 234         },
 235         .eeprom = {
 236                 .read           = rt2x00_eeprom_read,
 237                 .write          = rt2x00_eeprom_write,
 238                 .word_size      = sizeof(u16),
 239                 .word_count     = EEPROM_SIZE / sizeof(u16),
 240         },
 241         .bbp    = {
 242                 .read           = rt73usb_bbp_read,
 243                 .write          = rt73usb_bbp_write,
 244                 .word_size      = sizeof(u8),
 245                 .word_count     = BBP_SIZE / sizeof(u8),
 246         },
 247         .rf     = {
 248                 .read           = rt2x00_rf_read,
 249                 .write          = rt73usb_rf_write,
 250                 .word_size      = sizeof(u32),
 251                 .word_count     = RF_SIZE / sizeof(u32),
 252         },
 253 };
 254 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 255
 256 /*
 257  * Configuration handlers.
 258  */
 259 static void rt73usb_config_mac_addr(struct rt2x00_dev *rt2x00dev, __le32 *mac)
 260 {
 261         u32 tmp;
 262
 263         tmp = le32_to_cpu(mac[1]);
 264         rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
 265         mac[1] = cpu_to_le32(tmp);
 266
 267         rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2, mac,
 268                                     (2 * sizeof(__le32)));
 269 }
 270
 271 static void rt73usb_config_bssid(struct rt2x00_dev *rt2x00dev, __le32 *bssid)
 272 {
 273         u32 tmp;
 274
 275         tmp = le32_to_cpu(bssid[1]);
 276         rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3);
 277         bssid[1] = cpu_to_le32(tmp);
 278
 279         rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4, bssid,
 280                                     (2 * sizeof(__le32)));
 281 }
 282
 283 static void rt73usb_config_type(struct rt2x00_dev *rt2x00dev, const int type,
 284                                 const int tsf_sync)
 285 {
 286         u32 reg;
 287
 288         /*
 289          * Clear current synchronisation setup.
 290          * For the Beacon base registers we only need to clear
 291          * the first byte since that byte contains the VALID and OWNER
 292          * bits which (when set to 0) will invalidate the entire beacon.
 293          */
 294         rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
 295         rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
 296         rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
 297         rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
 298         rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
 299
 300         /*
 301          * Enable synchronisation.
 302          */
 303         rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
 304         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
 305         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
 306         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
 307         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, tsf_sync);
 308         rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
 309 }
 310
 311 static void rt73usb_config_preamble(struct rt2x00_dev *rt2x00dev,
 312                                       const int short_preamble,
 313                                       const int ack_timeout,
 314                                       const int ack_consume_time)
 315 {
 316         u32 reg;
 317
 318         /*
 319          * When in atomic context, reschedule and let rt2x00lib
 320          * call this function again.
 321          */
 322         if (in_atomic()) {
 323                 queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->config_work);
 324                 return;
 325         }
 326
 327         rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
 328         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
 329         rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
 330
 331         rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
 332         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
 333                            !!short_preamble);
 334         rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
 335 }
 336
 337 static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev,
 338                                    const int basic_rate_mask)
 339 {
 340         rt73usb_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
 341 }
 342
 343 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
 344                                    struct rf_channel *rf, const int txpower)
 345 {
 346         u8 r3;
 347         u8 r94;
 348         u8 smart;
 349
 350         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 351         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 352
 353         smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 354                   rt2x00_rf(&rt2x00dev->chip, RF2527));
 355
 356         rt73usb_bbp_read(rt2x00dev, 3, &r3);
 357         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
 358         rt73usb_bbp_write(rt2x00dev, 3, r3);
 359
 360         r94 = 6;
 361         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
 362                 r94 += txpower - MAX_TXPOWER;
 363         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
 364                 r94 += txpower;
 365         rt73usb_bbp_write(rt2x00dev, 94, r94);
 366
 367         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 368         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 369         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 370         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 371
 372         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 373         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 374         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 375         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 376
 377         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 378         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 379         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 380         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 381
 382         udelay(10);
 383 }
 384
 385 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
 386                                    const int txpower)
 387 {
 388         struct rf_channel rf;
 389
 390         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
 391         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
 392         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
 393         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
 394
 395         rt73usb_config_channel(rt2x00dev, &rf, txpower);
 396 }
 397
 398 static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
 399                                       struct antenna_setup *ant)
 400 {
 401         u8 r3;
 402         u8 r4;
 403         u8 r77;
 404
 405         rt73usb_bbp_read(rt2x00dev, 3, &r3);
 406         rt73usb_bbp_read(rt2x00dev, 4, &r4);
 407         rt73usb_bbp_read(rt2x00dev, 77, &r77);
 408
 409         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
 410
 411         /*
 412          * Configure the TX antenna.
 413          */
 414         switch (ant->tx) {
 415         case ANTENNA_A:
 416                 rt2x00_set_field8(&r77, BBP_R77_TX_ANTENNA, 0);
 417                 break;
 418         case ANTENNA_SW_DIVERSITY:
 419         case ANTENNA_HW_DIVERSITY:
 420                 /*
 421                  * NOTE: We should never come here because rt2x00lib is
 422                  * supposed to catch this and send us the correct antenna
 423                  * explicitely. However we are nog going to bug about this.
 424                  * Instead, just default to antenna B.
 425                  */
 426         case ANTENNA_B:
 427                 rt2x00_set_field8(&r77, BBP_R77_TX_ANTENNA, 3);
 428                 break;
 429         }
 430
 431         /*
 432          * Configure the RX antenna.
 433          */
 434         switch (ant->rx) {
 435         case ANTENNA_HW_DIVERSITY:
 436                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
 437                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 438                                   (rt2x00dev->curr_hwmode != HWMODE_A));
 439                 break;
 440         case ANTENNA_A:
 441                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
 442                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 443                 break;
 444         case ANTENNA_SW_DIVERSITY:
 445                 /*
 446                  * NOTE: We should never come here because rt2x00lib is
 447                  * supposed to catch this and send us the correct antenna
 448                  * explicitely. However we are nog going to bug about this.
 449                  * Instead, just default to antenna B.
 450                  */
 451         case ANTENNA_B:
 452                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
 453                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 454                 break;
 455         }
 456
 457         rt73usb_bbp_write(rt2x00dev, 77, r77);
 458         rt73usb_bbp_write(rt2x00dev, 3, r3);
 459         rt73usb_bbp_write(rt2x00dev, 4, r4);
 460 }
 461
 462 static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
 463                                       struct antenna_setup *ant)
 464 {
 465         u8 r3;
 466         u8 r4;
 467         u8 r77;
 468
 469         rt73usb_bbp_read(rt2x00dev, 3, &r3);
 470         rt73usb_bbp_read(rt2x00dev, 4, &r4);
 471         rt73usb_bbp_read(rt2x00dev, 77, &r77);
 472
 473         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
 474         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 475                           !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
 476
 477         /*
 478          * Configure the TX antenna.
 479          */
 480         switch (ant->tx) {
 481         case ANTENNA_A:
 482                 rt2x00_set_field8(&r77, BBP_R77_TX_ANTENNA, 0);
 483                 break;
 484         case ANTENNA_SW_DIVERSITY:
 485         case ANTENNA_HW_DIVERSITY:
 486                 /*
 487                  * NOTE: We should never come here because rt2x00lib is
 488                  * supposed to catch this and send us the correct antenna
 489                  * explicitely. However we are nog going to bug about this.
 490                  * Instead, just default to antenna B.
 491                  */
 492         case ANTENNA_B:
 493                 rt2x00_set_field8(&r77, BBP_R77_TX_ANTENNA, 3);
 494                 break;
 495         }
 496
 497         /*
 498          * Configure the RX antenna.
 499          */
 500         switch (ant->rx) {
 501         case ANTENNA_HW_DIVERSITY:
 502                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
 503                 break;
 504         case ANTENNA_A:
 505                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
 506                 break;
 507         case ANTENNA_SW_DIVERSITY:
 508                 /*
 509                  * NOTE: We should never come here because rt2x00lib is
 510                  * supposed to catch this and send us the correct antenna
 511                  * explicitely. However we are nog going to bug about this.
 512                  * Instead, just default to antenna B.
 513                  */
 514         case ANTENNA_B:
 515                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
 516                 break;
 517         }
 518
 519         rt73usb_bbp_write(rt2x00dev, 77, r77);
 520         rt73usb_bbp_write(rt2x00dev, 3, r3);
 521         rt73usb_bbp_write(rt2x00dev, 4, r4);
 522 }
 523
 524 struct antenna_sel {
 525         u8 word;
 526         /*
 527          * value[0] -> non-LNA
 528          * value[1] -> LNA
 529          */
 530         u8 value[2];
 531 };
 532
 533 static const struct antenna_sel antenna_sel_a[] = {
 534         { 96,  { 0x58, 0x78 } },
 535         { 104, { 0x38, 0x48 } },
 536         { 75,  { 0xfe, 0x80 } },
 537         { 86,  { 0xfe, 0x80 } },
 538         { 88,  { 0xfe, 0x80 } },
 539         { 35,  { 0x60, 0x60 } },
 540         { 97,  { 0x58, 0x58 } },
 541         { 98,  { 0x58, 0x58 } },
 542 };
 543
 544 static const struct antenna_sel antenna_sel_bg[] = {
 545         { 96,  { 0x48, 0x68 } },
 546         { 104, { 0x2c, 0x3c } },
 547         { 75,  { 0xfe, 0x80 } },
 548         { 86,  { 0xfe, 0x80 } },
 549         { 88,  { 0xfe, 0x80 } },
 550         { 35,  { 0x50, 0x50 } },
 551         { 97,  { 0x48, 0x48 } },
 552         { 98,  { 0x48, 0x48 } },
 553 };
 554
 555 static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev,
 556                                    struct antenna_setup *ant)
 557 {
 558         const struct antenna_sel *sel;
 559         unsigned int lna;
 560         unsigned int i;
 561         u32 reg;
 562
 563         rt73usb_register_read(rt2x00dev, PHY_CSR0, &reg);
 564
 565         if (rt2x00dev->curr_hwmode == HWMODE_A) {
 566                 sel = antenna_sel_a;
 567                 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
 568         } else {
 569                 sel = antenna_sel_bg;
 570                 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
 571         }
 572
 573         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
 574                            (rt2x00dev->curr_hwmode == HWMODE_B ||
 575                             rt2x00dev->curr_hwmode == HWMODE_G));
 576         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
 577                            (rt2x00dev->curr_hwmode == HWMODE_A));
 578
 579         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
 580                 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
 581
 582         rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
 583
 584         if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
 585             rt2x00_rf(&rt2x00dev->chip, RF5225))
 586                 rt73usb_config_antenna_5x(rt2x00dev, ant);
 587         else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
 588                  rt2x00_rf(&rt2x00dev->chip, RF2527))
 589                 rt73usb_config_antenna_2x(rt2x00dev, ant);
 590 }
 591
 592 static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
 593                                     struct rt2x00lib_conf *libconf)
 594 {
 595         u32 reg;
 596
 597         rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
 598         rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
 599         rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
 600
 601         rt73usb_register_read(rt2x00dev, MAC_CSR8, &reg);
 602         rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
 603         rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
 604         rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
 605         rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
 606
 607         rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
 608         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
 609         rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
 610
 611         rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
 612         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
 613         rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
 614
 615         rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
 616         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
 617                            libconf->conf->beacon_int * 16);
 618         rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
 619 }
 620
 621 static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
 622                            const unsigned int flags,
 623                            struct rt2x00lib_conf *libconf)
 624 {
 625         if (flags & CONFIG_UPDATE_PHYMODE)
 626                 rt73usb_config_phymode(rt2x00dev, libconf->basic_rates);
 627         if (flags & CONFIG_UPDATE_CHANNEL)
 628                 rt73usb_config_channel(rt2x00dev, &libconf->rf,
 629                                        libconf->conf->power_level);
 630         if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
 631                 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
 632         if (flags & CONFIG_UPDATE_ANTENNA)
 633                 rt73usb_config_antenna(rt2x00dev, &libconf->ant);
 634         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 635                 rt73usb_config_duration(rt2x00dev, libconf);
 636 }
 637
 638 /*
 639  * LED functions.
 640  */
 641 static void rt73usb_enable_led(struct rt2x00_dev *rt2x00dev)
 642 {
 643         u32 reg;
 644
 645         rt73usb_register_read(rt2x00dev, MAC_CSR14, &reg);
 646         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
 647         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
 648         rt73usb_register_write(rt2x00dev, MAC_CSR14, reg);
 649
 650         rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 1);
 651         rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS,
 652                            (rt2x00dev->rx_status.phymode == MODE_IEEE80211A));
 653         rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS,
 654                            (rt2x00dev->rx_status.phymode != MODE_IEEE80211A));
 655
 656         rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, 0x0000,
 657                                     rt2x00dev->led_reg, REGISTER_TIMEOUT);
 658 }
 659
 660 static void rt73usb_disable_led(struct rt2x00_dev *rt2x00dev)
 661 {
 662         rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 0);
 663         rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
 664         rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
 665
 666         rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, 0x0000,
 667                                     rt2x00dev->led_reg, REGISTER_TIMEOUT);
 668 }
 669
 670 static void rt73usb_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
 671 {
 672         u32 led;
 673
 674         if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
 675                 return;
 676
 677         /*
 678          * Led handling requires a positive value for the rssi,
 679          * to do that correctly we need to add the correction.
 680          */
 681         rssi += rt2x00dev->rssi_offset;
 682
 683         if (rssi <= 30)
 684                 led = 0;
 685         else if (rssi <= 39)
 686                 led = 1;
 687         else if (rssi <= 49)
 688                 led = 2;
 689         else if (rssi <= 53)
 690                 led = 3;
 691         else if (rssi <= 63)
 692                 led = 4;
 693         else
 694                 led = 5;
 695
 696         rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, led,
 697                                     rt2x00dev->led_reg, REGISTER_TIMEOUT);
 698 }
 699
 700 /*
 701  * Link tuning
 702  */
 703 static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
 704                                struct link_qual *qual)
 705 {
 706         u32 reg;
 707
 708         /*
 709          * Update FCS error count from register.
 710          */
 711         rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
 712         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
 713
 714         /*
 715          * Update False CCA count from register.
 716          */
 717         rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
 718         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
 719 }
 720
 721 static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
 722 {
 723         rt73usb_bbp_write(rt2x00dev, 17, 0x20);
 724         rt2x00dev->link.vgc_level = 0x20;
 725 }
 726
 727 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
 728 {
 729         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
 730         u8 r17;
 731         u8 up_bound;
 732         u8 low_bound;
 733
 734         /*
 735          * Update Led strength
 736          */
 737         rt73usb_activity_led(rt2x00dev, rssi);
 738
 739         rt73usb_bbp_read(rt2x00dev, 17, &r17);
 740
 741         /*
 742          * Determine r17 bounds.
 743          */
 744         if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
 745                 low_bound = 0x28;
 746                 up_bound = 0x48;
 747
 748                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
 749                         low_bound += 0x10;
 750                         up_bound += 0x10;
 751                 }
 752         } else {
 753                 if (rssi > -82) {
 754                         low_bound = 0x1c;
 755                         up_bound = 0x40;
 756                 } else if (rssi > -84) {
 757                         low_bound = 0x1c;
 758                         up_bound = 0x20;
 759                 } else {
 760                         low_bound = 0x1c;
 761                         up_bound = 0x1c;
 762                 }
 763
 764                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 765                         low_bound += 0x14;
 766                         up_bound += 0x10;
 767                 }
 768         }
 769
 770         /*
 771          * Special big-R17 for very short distance
 772          */
 773         if (rssi > -35) {
 774                 if (r17 != 0x60)
 775                         rt73usb_bbp_write(rt2x00dev, 17, 0x60);
 776                 return;
 777         }
 778
 779         /*
 780          * Special big-R17 for short distance
 781          */
 782         if (rssi >= -58) {
 783                 if (r17 != up_bound)
 784                         rt73usb_bbp_write(rt2x00dev, 17, up_bound);
 785                 return;
 786         }
 787
 788         /*
 789          * Special big-R17 for middle-short distance
 790          */
 791         if (rssi >= -66) {
 792                 low_bound += 0x10;
 793                 if (r17 != low_bound)
 794                         rt73usb_bbp_write(rt2x00dev, 17, low_bound);
 795                 return;
 796         }
 797
 798         /*
 799          * Special mid-R17 for middle distance
 800          */
 801         if (rssi >= -74) {
 802                 if (r17 != (low_bound + 0x10))
 803                         rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
 804                 return;
 805         }
 806
 807         /*
 808          * Special case: Change up_bound based on the rssi.
 809          * Lower up_bound when rssi is weaker then -74 dBm.
 810          */
 811         up_bound -= 2 * (-74 - rssi);
 812         if (low_bound > up_bound)
 813                 up_bound = low_bound;
 814
 815         if (r17 > up_bound) {
 816                 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
 817                 return;
 818         }
 819
 820         /*
 821          * r17 does not yet exceed upper limit, continue and base
 822          * the r17 tuning on the false CCA count.
 823          */
 824         if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
 825                 r17 += 4;
 826                 if (r17 > up_bound)
 827                         r17 = up_bound;
 828                 rt73usb_bbp_write(rt2x00dev, 17, r17);
 829         } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
 830                 r17 -= 4;
 831                 if (r17 < low_bound)
 832                         r17 = low_bound;
 833                 rt73usb_bbp_write(rt2x00dev, 17, r17);
 834         }
 835 }
 836
 837 /*
 838  * Firmware name function.
 839  */
 840 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
 841 {
 842         return FIRMWARE_RT2571;
 843 }
 844
 845 /*
 846  * Initialization functions.
 847  */
 848 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
 849                                  const size_t len)
 850 {
 851         unsigned int i;
 852         int status;
 853         u32 reg;
 854         char *ptr = data;
 855         char *cache;
 856         int buflen;
 857         int timeout;
 858
 859         /*
 860          * Wait for stable hardware.
 861          */
 862         for (i = 0; i < 100; i++) {
 863                 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
 864                 if (reg)
 865                         break;
 866                 msleep(1);
 867         }
 868
 869         if (!reg) {
 870                 ERROR(rt2x00dev, "Unstable hardware.\n");
 871                 return -EBUSY;
 872         }
 873
 874         /*
 875          * Write firmware to device.
 876          * We setup a seperate cache for this action,
 877          * since we are going to write larger chunks of data
 878          * then normally used cache size.
 879          */
 880         cache = kmalloc(CSR_CACHE_SIZE_FIRMWARE, GFP_KERNEL);
 881         if (!cache) {
 882                 ERROR(rt2x00dev, "Failed to allocate firmware cache.\n");
 883                 return -ENOMEM;
 884         }
 885
 886         for (i = 0; i < len; i += CSR_CACHE_SIZE_FIRMWARE) {
 887                 buflen = min_t(int, len - i, CSR_CACHE_SIZE_FIRMWARE);
 888                 timeout = REGISTER_TIMEOUT * (buflen / sizeof(u32));
 889
 890                 memcpy(cache, ptr, buflen);
 891
 892                 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
 893                                          USB_VENDOR_REQUEST_OUT,
 894                                          FIRMWARE_IMAGE_BASE + i, 0x0000,
 895                                          cache, buflen, timeout);
 896
 897                 ptr += buflen;
 898         }
 899
 900         kfree(cache);
 901
 902         /*
 903          * Send firmware request to device to load firmware,
 904          * we need to specify a long timeout time.
 905          */
 906         status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
 907                                              0x0000, USB_MODE_FIRMWARE,
 908                                              REGISTER_TIMEOUT_FIRMWARE);
 909         if (status < 0) {
 910                 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
 911                 return status;
 912         }
 913
 914         rt73usb_disable_led(rt2x00dev);
 915
 916         return 0;
 917 }
 918
 919 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
 920 {
 921         u32 reg;
 922
 923         rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
 924         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
 925         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
 926         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
 927         rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
 928
 929         rt73usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
 930         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
 931         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
 932         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
 933         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
 934         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
 935         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
 936         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
 937         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
 938         rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
 939
 940         /*
 941          * CCK TXD BBP registers
 942          */
 943         rt73usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
 944         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
 945         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
 946         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
 947         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
 948         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
 949         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
 950         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
 951         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
 952         rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
 953
 954         /*
 955          * OFDM TXD BBP registers
 956          */
 957         rt73usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
 958         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
 959         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
 960         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
 961         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
 962         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
 963         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
 964         rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
 965
 966         rt73usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
 967         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
 968         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
 969         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
 970         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
 971         rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
 972
 973         rt73usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
 974         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
 975         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
 976         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
 977         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
 978         rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
 979
 980         rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
 981
 982         rt73usb_register_read(rt2x00dev, MAC_CSR6, &reg);
 983         rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
 984         rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
 985
 986         rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
 987
 988         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 989                 return -EBUSY;
 990
 991         rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
 992
 993         /*
 994          * Invalidate all Shared Keys (SEC_CSR0),
 995          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
 996          */
 997         rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
 998         rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
 999         rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1000
1001         reg = 0x000023b0;
1002         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1003             rt2x00_rf(&rt2x00dev->chip, RF2527))
1004                 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1005         rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
1006
1007         rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1008         rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1009         rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1010
1011         rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1012         rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1013         rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1014         rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1015
1016         rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1017         rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1018         rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1019         rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1020
1021         rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1022         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1023         rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
1024
1025         /*
1026          * We must clear the error counters.
1027          * These registers are cleared on read,
1028          * so we may pass a useless variable to store the value.
1029          */
1030         rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
1031         rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
1032         rt73usb_register_read(rt2x00dev, STA_CSR2, &reg);
1033
1034         /*
1035          * Reset MAC and BBP registers.
1036          */
1037         rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1038         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1039         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1040         rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1041
1042         rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1043         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1044         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1045         rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1046
1047         rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1048         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1049         rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1050
1051         return 0;
1052 }
1053
1054 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1055 {
1056         unsigned int i;
1057         u16 eeprom;
1058         u8 reg_id;
1059         u8 value;
1060
1061         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1062                 rt73usb_bbp_read(rt2x00dev, 0, &value);
1063                 if ((value != 0xff) && (value != 0x00))
1064                         goto continue_csr_init;
1065                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1066                 udelay(REGISTER_BUSY_DELAY);
1067         }
1068
1069         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1070         return -EACCES;
1071
1072 continue_csr_init:
1073         rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1074         rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1075         rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1076         rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1077         rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1078         rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1079         rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1080         rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1081         rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1082         rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1083         rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1084         rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1085         rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1086         rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1087         rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1088         rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1089         rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1090         rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1091         rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1092         rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1093         rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1094         rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1095         rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1096         rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1097         rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1098
1099         DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1100         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1101                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1102
1103                 if (eeprom != 0xffff && eeprom != 0x0000) {
1104                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1105                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1106                         DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1107                               reg_id, value);
1108                         rt73usb_bbp_write(rt2x00dev, reg_id, value);
1109                 }
1110         }
1111         DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1112
1113         return 0;
1114 }
1115
1116 /*
1117  * Device state switch handlers.
1118  */
1119 static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1120                               enum dev_state state)
1121 {
1122         u32 reg;
1123
1124         rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1125         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1126                            state == STATE_RADIO_RX_OFF);
1127         rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1128 }
1129
1130 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1131 {
1132         /*
1133          * Initialize all registers.
1134          */
1135         if (rt73usb_init_registers(rt2x00dev) ||
1136             rt73usb_init_bbp(rt2x00dev)) {
1137                 ERROR(rt2x00dev, "Register initialization failed.\n");
1138                 return -EIO;
1139         }
1140
1141         rt2x00usb_enable_radio(rt2x00dev);
1142
1143         /*
1144          * Enable LED
1145          */
1146         rt73usb_enable_led(rt2x00dev);
1147
1148         return 0;
1149 }
1150
1151 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1152 {
1153         /*
1154          * Disable LED
1155          */
1156         rt73usb_disable_led(rt2x00dev);
1157
1158         rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1159
1160         /*
1161          * Disable synchronisation.
1162          */
1163         rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1164
1165         rt2x00usb_disable_radio(rt2x00dev);
1166 }
1167
1168 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1169 {
1170         u32 reg;
1171         unsigned int i;
1172         char put_to_sleep;
1173         char current_state;
1174
1175         put_to_sleep = (state != STATE_AWAKE);
1176
1177         rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1178         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1179         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1180         rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
1181
1182         /*
1183          * Device is not guaranteed to be in the requested state yet.
1184          * We must wait until the register indicates that the
1185          * device has entered the correct state.
1186          */
1187         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1188                 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1189                 current_state =
1190                     rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1191                 if (current_state == !put_to_sleep)
1192                         return 0;
1193                 msleep(10);
1194         }
1195
1196         NOTICE(rt2x00dev, "Device failed to enter state %d, "
1197                "current device state %d.\n", !put_to_sleep, current_state);
1198
1199         return -EBUSY;
1200 }
1201
1202 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1203                                     enum dev_state state)
1204 {
1205         int retval = 0;
1206
1207         switch (state) {
1208         case STATE_RADIO_ON:
1209                 retval = rt73usb_enable_radio(rt2x00dev);
1210                 break;
1211         case STATE_RADIO_OFF:
1212                 rt73usb_disable_radio(rt2x00dev);
1213                 break;
1214         case STATE_RADIO_RX_ON:
1215         case STATE_RADIO_RX_OFF:
1216                 rt73usb_toggle_rx(rt2x00dev, state);
1217                 break;
1218         case STATE_DEEP_SLEEP:
1219         case STATE_SLEEP:
1220         case STATE_STANDBY:
1221         case STATE_AWAKE:
1222                 retval = rt73usb_set_state(rt2x00dev, state);
1223                 break;
1224         default:
1225                 retval = -ENOTSUPP;
1226                 break;
1227         }
1228
1229         return retval;
1230 }
1231
1232 /*
1233  * TX descriptor initialization
1234  */
1235 static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1236                                   struct data_desc *txd,
1237                                   struct txdata_entry_desc *desc,
1238                                   struct ieee80211_hdr *ieee80211hdr,
1239                                   unsigned int length,
1240                                   struct ieee80211_tx_control *control)
1241 {
1242         u32 word;
1243
1244         /*
1245          * Start writing the descriptor words.
1246          */
1247         rt2x00_desc_read(txd, 1, &word);
1248         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
1249         rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs);
1250         rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min);
1251         rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max);
1252         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1253         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1254         rt2x00_desc_write(txd, 1, word);
1255
1256         rt2x00_desc_read(txd, 2, &word);
1257         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
1258         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
1259         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
1260         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
1261         rt2x00_desc_write(txd, 2, word);
1262
1263         rt2x00_desc_read(txd, 5, &word);
1264         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1265                            TXPOWER_TO_DEV(control->power_level));
1266         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1267         rt2x00_desc_write(txd, 5, word);
1268
1269         rt2x00_desc_read(txd, 0, &word);
1270         rt2x00_set_field32(&word, TXD_W0_BURST,
1271                            test_bit(ENTRY_TXD_BURST, &desc->flags));
1272         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1273         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1274                            test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1275         rt2x00_set_field32(&word, TXD_W0_ACK,
1276                            !(control->flags & IEEE80211_TXCTL_NO_ACK));
1277         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1278                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1279         rt2x00_set_field32(&word, TXD_W0_OFDM,
1280                            test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1281         rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1282         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1283                            !!(control->flags &
1284                               IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1285         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1286         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1287         rt2x00_set_field32(&word, TXD_W0_BURST2,
1288                            test_bit(ENTRY_TXD_BURST, &desc->flags));
1289         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1290         rt2x00_desc_write(txd, 0, word);
1291 }
1292
1293 static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
1294                                    struct sk_buff *skb)
1295 {
1296         int length;
1297
1298         /*
1299          * The length _must_ be a multiple of 4,
1300          * but it must _not_ be a multiple of the USB packet size.
1301          */
1302         length = roundup(skb->len, 4);
1303         length += (4 * !(length % rt2x00dev->usb_maxpacket));
1304
1305         return length;
1306 }
1307
1308 /*
1309  * TX data initialization
1310  */
1311 static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1312                                   unsigned int queue)
1313 {
1314         u32 reg;
1315
1316         if (queue != IEEE80211_TX_QUEUE_BEACON)
1317                 return;
1318
1319         /*
1320          * For Wi-Fi faily generated beacons between participating stations.
1321          * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1322          */
1323         rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1324
1325         rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1326         if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1327                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1328                 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1329         }
1330 }
1331
1332 /*
1333  * RX control handlers
1334  */
1335 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1336 {
1337         u16 eeprom;
1338         u8 offset;
1339         u8 lna;
1340
1341         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1342         switch (lna) {
1343         case 3:
1344                 offset = 90;
1345                 break;
1346         case 2:
1347                 offset = 74;
1348                 break;
1349         case 1:
1350                 offset = 64;
1351                 break;
1352         default:
1353                 return 0;
1354         }
1355
1356         if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
1357                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1358                         if (lna == 3 || lna == 2)
1359                                 offset += 10;
1360                 } else {
1361                         if (lna == 3)
1362                                 offset += 6;
1363                         else if (lna == 2)
1364                                 offset += 8;
1365                 }
1366
1367                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1368                 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1369         } else {
1370                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1371                         offset += 14;
1372
1373                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1374                 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1375         }
1376
1377         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1378 }
1379
1380 static void rt73usb_fill_rxdone(struct data_entry *entry,
1381                                 struct rxdata_entry_desc *desc)
1382 {
1383         struct data_desc *rxd = (struct data_desc *)entry->skb->data;
1384         u32 word0;
1385         u32 word1;
1386
1387         rt2x00_desc_read(rxd, 0, &word0);
1388         rt2x00_desc_read(rxd, 1, &word1);
1389
1390         desc->flags = 0;
1391         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1392                 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1393
1394         /*
1395          * Obtain the status about this packet.
1396          */
1397         desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1398         desc->rssi = rt73usb_agc_to_rssi(entry->ring->rt2x00dev, word1);
1399         desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1400         desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1401
1402         /*
1403          * Pull the skb to clear the descriptor area.
1404          */
1405         skb_pull(entry->skb, entry->ring->desc_size);
1406
1407         return;
1408 }
1409
1410 /*
1411  * Device probe functions.
1412  */
1413 static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1414 {
1415         u16 word;
1416         u8 *mac;
1417         s8 value;
1418
1419         rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1420
1421         /*
1422          * Start validation of the data that has been read.
1423          */
1424         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1425         if (!is_valid_ether_addr(mac)) {
1426                 DECLARE_MAC_BUF(macbuf);
1427
1428                 random_ether_addr(mac);
1429                 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1430         }
1431
1432         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1433         if (word == 0xffff) {
1434                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1435                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1436                                    ANTENNA_B);
1437                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1438                                    ANTENNA_B);
1439                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1440                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1441                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1442                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1443                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1444                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1445         }
1446
1447         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1448         if (word == 0xffff) {
1449                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1450                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1451                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1452         }
1453
1454         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1455         if (word == 0xffff) {
1456                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1457                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1458                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1459                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1460                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1461                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1462                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1463                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1464                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1465                                    LED_MODE_DEFAULT);
1466                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1467                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1468         }
1469
1470         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1471         if (word == 0xffff) {
1472                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1473                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1474                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1475                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1476         }
1477
1478         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1479         if (word == 0xffff) {
1480                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1481                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1482                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1483                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1484         } else {
1485                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1486                 if (value < -10 || value > 10)
1487                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1488                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1489                 if (value < -10 || value > 10)
1490                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1491                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1492         }
1493
1494         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1495         if (word == 0xffff) {
1496                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1497                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1498                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1499                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1500         } else {
1501                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1502                 if (value < -10 || value > 10)
1503                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1504                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1505                 if (value < -10 || value > 10)
1506                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1507                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1508         }
1509
1510         return 0;
1511 }
1512
1513 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1514 {
1515         u32 reg;
1516         u16 value;
1517         u16 eeprom;
1518
1519         /*
1520          * Read EEPROM word for configuration.
1521          */
1522         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1523
1524         /*
1525          * Identify RF chipset.
1526          */
1527         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1528         rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1529         rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1530
1531         if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
1532                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1533                 return -ENODEV;
1534         }
1535
1536         if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1537             !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1538             !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1539             !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1540                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1541                 return -ENODEV;
1542         }
1543
1544         /*
1545          * Identify default antenna configuration.
1546          */
1547         rt2x00dev->default_ant.tx =
1548             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1549         rt2x00dev->default_ant.rx =
1550             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1551
1552         /*
1553          * Read the Frame type.
1554          */
1555         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1556                 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1557
1558         /*
1559          * Read frequency offset.
1560          */
1561         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1562         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1563
1564         /*
1565          * Read external LNA informations.
1566          */
1567         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1568
1569         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1570                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1571                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1572         }
1573
1574         /*
1575          * Store led settings, for correct led behaviour.
1576          */
1577         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1578
1579         rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
1580                            rt2x00dev->led_mode);
1581         rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
1582                            rt2x00_get_field16(eeprom,
1583                                               EEPROM_LED_POLARITY_GPIO_0));
1584         rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
1585                            rt2x00_get_field16(eeprom,
1586                                               EEPROM_LED_POLARITY_GPIO_1));
1587         rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
1588                            rt2x00_get_field16(eeprom,
1589                                               EEPROM_LED_POLARITY_GPIO_2));
1590         rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
1591                            rt2x00_get_field16(eeprom,
1592                                               EEPROM_LED_POLARITY_GPIO_3));
1593         rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
1594                            rt2x00_get_field16(eeprom,
1595                                               EEPROM_LED_POLARITY_GPIO_4));
1596         rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
1597                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1598         rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
1599                            rt2x00_get_field16(eeprom,
1600                                               EEPROM_LED_POLARITY_RDY_G));
1601         rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
1602                            rt2x00_get_field16(eeprom,
1603                                               EEPROM_LED_POLARITY_RDY_A));
1604
1605         return 0;
1606 }
1607
1608 /*
1609  * RF value list for RF2528
1610  * Supports: 2.4 GHz
1611  */
1612 static const struct rf_channel rf_vals_bg_2528[] = {
1613         { 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1614         { 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1615         { 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1616         { 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1617         { 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1618         { 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1619         { 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1620         { 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1621         { 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1622         { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1623         { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1624         { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1625         { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1626         { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1627 };
1628
1629 /*
1630  * RF value list for RF5226
1631  * Supports: 2.4 GHz & 5.2 GHz
1632  */
1633 static const struct rf_channel rf_vals_5226[] = {
1634         { 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1635         { 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1636         { 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1637         { 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1638         { 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1639         { 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1640         { 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1641         { 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1642         { 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1643         { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1644         { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1645         { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1646         { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1647         { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1648
1649         /* 802.11 UNI / HyperLan 2 */
1650         { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1651         { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1652         { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1653         { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1654         { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1655         { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1656         { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1657         { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1658
1659         /* 802.11 HyperLan 2 */
1660         { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1661         { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1662         { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1663         { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1664         { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1665         { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1666         { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1667         { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1668         { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1669         { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1670
1671         /* 802.11 UNII */
1672         { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1673         { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1674         { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1675         { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1676         { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1677         { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1678
1679         /* MMAC(Japan)J52 ch 34,38,42,46 */
1680         { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1681         { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1682         { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1683         { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1684 };
1685
1686 /*
1687  * RF value list for RF5225 & RF2527
1688  * Supports: 2.4 GHz & 5.2 GHz
1689  */
1690 static const struct rf_channel rf_vals_5225_2527[] = {
1691         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1692         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1693         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1694         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1695         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1696         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
1697         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
1698         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
1699         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
1700         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
1701         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
1702         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
1703         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
1704         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
1705
1706         /* 802.11 UNI / HyperLan 2 */
1707         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
1708         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
1709         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
1710         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
1711         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
1712         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
1713         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
1714         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
1715
1716         /* 802.11 HyperLan 2 */
1717         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
1718         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
1719         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
1720         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
1721         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
1722         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
1723         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
1724         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
1725         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
1726         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
1727
1728         /* 802.11 UNII */
1729         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
1730         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
1731         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
1732         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
1733         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
1734         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
1735
1736         /* MMAC(Japan)J52 ch 34,38,42,46 */
1737         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
1738         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
1739         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
1740         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
1741 };
1742
1743
1744 static void rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1745 {
1746         struct hw_mode_spec *spec = &rt2x00dev->spec;
1747         u8 *txpower;
1748         unsigned int i;
1749
1750         /*
1751          * Initialize all hw fields.
1752          */
1753         rt2x00dev->hw->flags =
1754             IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
1755             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1756         rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
1757         rt2x00dev->hw->max_signal = MAX_SIGNAL;
1758         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1759         rt2x00dev->hw->queues = 5;
1760
1761         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_usb(rt2x00dev)->dev);
1762         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1763                                 rt2x00_eeprom_addr(rt2x00dev,
1764                                                    EEPROM_MAC_ADDR_0));
1765
1766         /*
1767          * Convert tx_power array in eeprom.
1768          */
1769         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
1770         for (i = 0; i < 14; i++)
1771                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1772
1773         /*
1774          * Initialize hw_mode information.
1775          */
1776         spec->num_modes = 2;
1777         spec->num_rates = 12;
1778         spec->tx_power_a = NULL;
1779         spec->tx_power_bg = txpower;
1780         spec->tx_power_default = DEFAULT_TXPOWER;
1781
1782         if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
1783                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
1784                 spec->channels = rf_vals_bg_2528;
1785         } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1786                 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
1787                 spec->channels = rf_vals_5226;
1788         } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1789                 spec->num_channels = 14;
1790                 spec->channels = rf_vals_5225_2527;
1791         } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
1792                 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
1793                 spec->channels = rf_vals_5225_2527;
1794         }
1795
1796         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1797             rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1798                 spec->num_modes = 3;
1799
1800                 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
1801                 for (i = 0; i < 14; i++)
1802                         txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1803
1804                 spec->tx_power_a = txpower;
1805         }
1806 }
1807
1808 static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
1809 {
1810         int retval;
1811
1812         /*
1813          * Allocate eeprom data.
1814          */
1815         retval = rt73usb_validate_eeprom(rt2x00dev);
1816         if (retval)
1817                 return retval;
1818
1819         retval = rt73usb_init_eeprom(rt2x00dev);
1820         if (retval)
1821                 return retval;
1822
1823         /*
1824          * Initialize hw specifications.
1825          */
1826         rt73usb_probe_hw_mode(rt2x00dev);
1827
1828         /*
1829          * This device requires firmware
1830          */
1831         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1832
1833         /*
1834          * Set the rssi offset.
1835          */
1836         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1837
1838         return 0;
1839 }
1840
1841 /*
1842  * IEEE80211 stack callback functions.
1843  */
1844 static void rt73usb_configure_filter(struct ieee80211_hw *hw,
1845                                      unsigned int changed_flags,
1846                                      unsigned int *total_flags,
1847                                      int mc_count,
1848                                      struct dev_addr_list *mc_list)
1849 {
1850         struct rt2x00_dev *rt2x00dev = hw->priv;
1851         struct interface *intf = &rt2x00dev->interface;
1852         u32 reg;
1853
1854         /*
1855          * Mask off any flags we are going to ignore from
1856          * the total_flags field.
1857          */
1858         *total_flags &=
1859             FIF_ALLMULTI |
1860             FIF_FCSFAIL |
1861             FIF_PLCPFAIL |
1862             FIF_CONTROL |
1863             FIF_OTHER_BSS |
1864             FIF_PROMISC_IN_BSS;
1865
1866         /*
1867          * Apply some rules to the filters:
1868          * - Some filters imply different filters to be set.
1869          * - Some things we can't filter out at all.
1870          * - Some filters are set based on interface type.
1871          */
1872         if (mc_count)
1873                 *total_flags |= FIF_ALLMULTI;
1874         if (*total_flags & FIF_OTHER_BSS ||
1875             *total_flags & FIF_PROMISC_IN_BSS)
1876                 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1877         if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
1878                 *total_flags |= FIF_PROMISC_IN_BSS;
1879
1880         /*
1881          * Check if there is any work left for us.
1882          */
1883         if (intf->filter == *total_flags)
1884                 return;
1885         intf->filter = *total_flags;
1886
1887         /*
1888          * When in atomic context, reschedule and let rt2x00lib
1889          * call this function again.
1890          */
1891         if (in_atomic()) {
1892                 queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->filter_work);
1893                 return;
1894         }
1895
1896         /*
1897          * Start configuration steps.
1898          * Note that the version error will always be dropped
1899          * and broadcast frames will always be accepted since
1900          * there is no filter for it at this time.
1901          */
1902         rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1903         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
1904                            !(*total_flags & FIF_FCSFAIL));
1905         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
1906                            !(*total_flags & FIF_PLCPFAIL));
1907         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
1908                            !(*total_flags & FIF_CONTROL));
1909         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
1910                            !(*total_flags & FIF_PROMISC_IN_BSS));
1911         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
1912                            !(*total_flags & FIF_PROMISC_IN_BSS));
1913         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
1914         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
1915                            !(*total_flags & FIF_ALLMULTI));
1916         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
1917         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 1);
1918         rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1919 }
1920
1921 static int rt73usb_set_retry_limit(struct ieee80211_hw *hw,
1922                                    u32 short_retry, u32 long_retry)
1923 {
1924         struct rt2x00_dev *rt2x00dev = hw->priv;
1925         u32 reg;
1926
1927         rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
1928         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
1929         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
1930         rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
1931
1932         return 0;
1933 }
1934
1935 #if 0
1936 /*
1937  * Mac80211 demands get_tsf must be atomic.
1938  * This is not possible for rt73usb since all register access
1939  * functions require sleeping. Untill mac80211 no longer needs
1940  * get_tsf to be atomic, this function should be disabled.
1941  */
1942 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
1943 {
1944         struct rt2x00_dev *rt2x00dev = hw->priv;
1945         u64 tsf;
1946         u32 reg;
1947
1948         rt73usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
1949         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
1950         rt73usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
1951         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
1952
1953         return tsf;
1954 }
1955 #else
1956 #define rt73usb_get_tsf NULL
1957 #endif
1958
1959 static void rt73usb_reset_tsf(struct ieee80211_hw *hw)
1960 {
1961         struct rt2x00_dev *rt2x00dev = hw->priv;
1962
1963         rt73usb_register_write(rt2x00dev, TXRX_CSR12, 0);
1964         rt73usb_register_write(rt2x00dev, TXRX_CSR13, 0);
1965 }
1966
1967 static int rt73usb_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1968                           struct ieee80211_tx_control *control)
1969 {
1970         struct rt2x00_dev *rt2x00dev = hw->priv;
1971         int timeout;
1972
1973         /*
1974          * Just in case the ieee80211 doesn't set this,
1975          * but we need this queue set for the descriptor
1976          * initialization.
1977          */
1978         control->queue = IEEE80211_TX_QUEUE_BEACON;
1979
1980         /*
1981          * First we create the beacon.
1982          */
1983         skb_push(skb, TXD_DESC_SIZE);
1984         memset(skb->data, 0, TXD_DESC_SIZE);
1985
1986         rt2x00lib_write_tx_desc(rt2x00dev, (struct data_desc *)skb->data,
1987                                 (struct ieee80211_hdr *)(skb->data +
1988                                                          TXD_DESC_SIZE),
1989                                 skb->len - TXD_DESC_SIZE, control);
1990
1991         /*
1992          * Write entire beacon with descriptor to register,
1993          * and kick the beacon generator.
1994          */
1995         timeout = REGISTER_TIMEOUT * (skb->len / sizeof(u32));
1996         rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
1997                                  USB_VENDOR_REQUEST_OUT,
1998                                  HW_BEACON_BASE0, 0x0000,
1999                                  skb->data, skb->len, timeout);
2000         rt73usb_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
2001
2002         return 0;
2003 }
2004
2005 static const struct ieee80211_ops rt73usb_mac80211_ops = {
2006         .tx                     = rt2x00mac_tx,
2007         .start                  = rt2x00mac_start,
2008         .stop                   = rt2x00mac_stop,
2009         .add_interface          = rt2x00mac_add_interface,
2010         .remove_interface       = rt2x00mac_remove_interface,
2011         .config                 = rt2x00mac_config,
2012         .config_interface       = rt2x00mac_config_interface,
2013         .configure_filter       = rt73usb_configure_filter,
2014         .get_stats              = rt2x00mac_get_stats,
2015         .set_retry_limit        = rt73usb_set_retry_limit,
2016         .erp_ie_changed         = rt2x00mac_erp_ie_changed,
2017         .conf_tx                = rt2x00mac_conf_tx,
2018         .get_tx_stats           = rt2x00mac_get_tx_stats,
2019         .get_tsf                = rt73usb_get_tsf,
2020         .reset_tsf              = rt73usb_reset_tsf,
2021         .beacon_update          = rt73usb_beacon_update,
2022 };
2023
2024 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2025         .probe_hw               = rt73usb_probe_hw,
2026         .get_firmware_name      = rt73usb_get_firmware_name,
2027         .load_firmware          = rt73usb_load_firmware,
2028         .initialize             = rt2x00usb_initialize,
2029         .uninitialize           = rt2x00usb_uninitialize,
2030         .set_device_state       = rt73usb_set_device_state,
2031         .link_stats             = rt73usb_link_stats,
2032         .reset_tuner            = rt73usb_reset_tuner,
2033         .link_tuner             = rt73usb_link_tuner,
2034         .write_tx_desc          = rt73usb_write_tx_desc,
2035         .write_tx_data          = rt2x00usb_write_tx_data,
2036         .get_tx_data_len        = rt73usb_get_tx_data_len,
2037         .kick_tx_queue          = rt73usb_kick_tx_queue,
2038         .fill_rxdone            = rt73usb_fill_rxdone,
2039         .config_mac_addr        = rt73usb_config_mac_addr,
2040         .config_bssid           = rt73usb_config_bssid,
2041         .config_type            = rt73usb_config_type,
2042         .config_preamble        = rt73usb_config_preamble,
2043         .config                 = rt73usb_config,
2044 };
2045
2046 static const struct rt2x00_ops rt73usb_ops = {
2047         .name           = DRV_NAME,
2048         .rxd_size       = RXD_DESC_SIZE,
2049         .txd_size       = TXD_DESC_SIZE,
2050         .eeprom_size    = EEPROM_SIZE,
2051         .rf_size        = RF_SIZE,
2052         .lib            = &rt73usb_rt2x00_ops,
2053         .hw             = &rt73usb_mac80211_ops,
2054 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2055         .debugfs        = &rt73usb_rt2x00debug,
2056 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2057 };
2058
2059 /*
2060  * rt73usb module information.
2061  */
2062 static struct usb_device_id rt73usb_device_table[] = {
2063         /* AboCom */
2064         { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2065         /* Askey */
2066         { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2067         /* ASUS */
2068         { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2069         { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2070         /* Belkin */
2071         { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2072         { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2073         { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
2074         { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
2075         /* Billionton */
2076         { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2077         /* Buffalo */
2078         { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2079         /* CNet */
2080         { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2081         { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2082         /* Conceptronic */
2083         { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2084         /* D-Link */
2085         { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2086         { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2087         /* Gemtek */
2088         { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2089         /* Gigabyte */
2090         { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2091         { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2092         /* Huawei-3Com */
2093         { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2094         /* Hercules */
2095         { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2096         { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2097         /* Linksys */
2098         { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2099         { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2100         /* MSI */
2101         { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2102         { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2103         { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2104         { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2105         /* Ralink */
2106         { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2107         { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2108         /* Qcom */
2109         { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2110         { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2111         { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2112         /* Senao */
2113         { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2114         /* Sitecom */
2115         { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2116         { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2117         /* Surecom */
2118         { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2119         /* Planex */
2120         { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2121         { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2122         { 0, }
2123 };
2124
2125 MODULE_AUTHOR(DRV_PROJECT);
2126 MODULE_VERSION(DRV_VERSION);
2127 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2128 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2129 MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2130 MODULE_FIRMWARE(FIRMWARE_RT2571);
2131 MODULE_LICENSE("GPL");
2132
2133 static struct usb_driver rt73usb_driver = {
2134         .name           = DRV_NAME,
2135         .id_table       = rt73usb_device_table,
2136         .probe          = rt2x00usb_probe,
2137         .disconnect     = rt2x00usb_disconnect,
2138         .suspend        = rt2x00usb_suspend,
2139         .resume         = rt2x00usb_resume,
2140 };
2141
2142 static int __init rt73usb_init(void)
2143 {
2144         return usb_register(&rt73usb_driver);
2145 }
2146
2147 static void __exit rt73usb_exit(void)
2148 {
2149         usb_deregister(&rt73usb_driver);
2150 }
2151
2152 module_init(rt73usb_init);
2153 module_exit(rt73usb_exit);