2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
28 * Set enviroment defines for rt2x00.h
30 #define DRV_NAME "rt73usb"
32 #include <linux/delay.h>
33 #include <linux/etherdevice.h>
34 #include <linux/init.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/usb.h>
40 #include "rt2x00usb.h"
45 * All access to the CSR registers will go through the methods
46 * rt73usb_register_read and rt73usb_register_write.
47 * BBP and RF register require indirect register access,
48 * and use the CSR registers BBPCSR and RFCSR to achieve this.
49 * These indirect registers work with busy bits,
50 * and we will try maximal REGISTER_BUSY_COUNT times to access
51 * the register while taking a REGISTER_BUSY_DELAY us delay
52 * between each attampt. When the busy bit is still set at that time,
53 * the access attempt is considered to have failed,
54 * and we will print an error.
56 static inline void rt73usb_register_read(struct rt2x00_dev *rt2x00dev,
57 const unsigned int offset, u32 *value)
60 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
61 USB_VENDOR_REQUEST_IN, offset,
62 ®, sizeof(u32), REGISTER_TIMEOUT);
63 *value = le32_to_cpu(reg);
66 static inline void rt73usb_register_multiread(struct rt2x00_dev *rt2x00dev,
67 const unsigned int offset,
68 void *value, const u32 length)
70 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
71 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
72 USB_VENDOR_REQUEST_IN, offset,
73 value, length, timeout);
76 static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev,
77 const unsigned int offset, u32 value)
79 __le32 reg = cpu_to_le32(value);
80 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
81 USB_VENDOR_REQUEST_OUT, offset,
82 ®, sizeof(u32), REGISTER_TIMEOUT);
85 static inline void rt73usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
86 const unsigned int offset,
87 void *value, const u32 length)
89 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
90 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
91 USB_VENDOR_REQUEST_OUT, offset,
92 value, length, timeout);
95 static u32 rt73usb_bbp_check(struct rt2x00_dev *rt2x00dev)
100 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
101 rt73usb_register_read(rt2x00dev, PHY_CSR3, ®);
102 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
104 udelay(REGISTER_BUSY_DELAY);
110 static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
111 const unsigned int word, const u8 value)
116 * Wait until the BBP becomes ready.
118 reg = rt73usb_bbp_check(rt2x00dev);
119 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
120 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
125 * Write the data into the BBP.
128 rt2x00_set_field32(®, PHY_CSR3_VALUE, value);
129 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
130 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
131 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0);
133 rt73usb_register_write(rt2x00dev, PHY_CSR3, reg);
136 static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
137 const unsigned int word, u8 *value)
142 * Wait until the BBP becomes ready.
144 reg = rt73usb_bbp_check(rt2x00dev);
145 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
146 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
151 * Write the request into the BBP.
154 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
155 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
156 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1);
158 rt73usb_register_write(rt2x00dev, PHY_CSR3, reg);
161 * Wait until the BBP becomes ready.
163 reg = rt73usb_bbp_check(rt2x00dev);
164 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
165 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
170 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
173 static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
174 const unsigned int word, const u32 value)
182 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
183 rt73usb_register_read(rt2x00dev, PHY_CSR4, ®);
184 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
186 udelay(REGISTER_BUSY_DELAY);
189 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
194 rt2x00_set_field32(®, PHY_CSR4_VALUE, value);
197 * RF5225 and RF2527 contain 21 bits per RF register value,
198 * all others contain 20 bits.
200 rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS,
201 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
202 rt2x00_rf(&rt2x00dev->chip, RF2527)));
203 rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0);
204 rt2x00_set_field32(®, PHY_CSR4_BUSY, 1);
206 rt73usb_register_write(rt2x00dev, PHY_CSR4, reg);
207 rt2x00_rf_write(rt2x00dev, word, value);
210 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
211 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
213 static void rt73usb_read_csr(struct rt2x00_dev *rt2x00dev,
214 const unsigned int word, u32 *data)
216 rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data);
219 static void rt73usb_write_csr(struct rt2x00_dev *rt2x00dev,
220 const unsigned int word, u32 data)
222 rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
225 static const struct rt2x00debug rt73usb_rt2x00debug = {
226 .owner = THIS_MODULE,
228 .read = rt73usb_read_csr,
229 .write = rt73usb_write_csr,
230 .word_size = sizeof(u32),
231 .word_count = CSR_REG_SIZE / sizeof(u32),
234 .read = rt2x00_eeprom_read,
235 .write = rt2x00_eeprom_write,
236 .word_size = sizeof(u16),
237 .word_count = EEPROM_SIZE / sizeof(u16),
240 .read = rt73usb_bbp_read,
241 .write = rt73usb_bbp_write,
242 .word_size = sizeof(u8),
243 .word_count = BBP_SIZE / sizeof(u8),
246 .read = rt2x00_rf_read,
247 .write = rt73usb_rf_write,
248 .word_size = sizeof(u32),
249 .word_count = RF_SIZE / sizeof(u32),
252 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
255 * Configuration handlers.
257 static void rt73usb_config_mac_addr(struct rt2x00_dev *rt2x00dev, __le32 *mac)
261 tmp = le32_to_cpu(mac[1]);
262 rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
263 mac[1] = cpu_to_le32(tmp);
265 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2, mac,
266 (2 * sizeof(__le32)));
269 static void rt73usb_config_bssid(struct rt2x00_dev *rt2x00dev, __le32 *bssid)
273 tmp = le32_to_cpu(bssid[1]);
274 rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3);
275 bssid[1] = cpu_to_le32(tmp);
277 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4, bssid,
278 (2 * sizeof(__le32)));
281 static void rt73usb_config_type(struct rt2x00_dev *rt2x00dev, const int type,
287 * Clear current synchronisation setup.
288 * For the Beacon base registers we only need to clear
289 * the first byte since that byte contains the VALID and OWNER
290 * bits which (when set to 0) will invalidate the entire beacon.
292 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
293 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
294 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
295 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
296 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
299 * Enable synchronisation.
301 rt73usb_register_read(rt2x00dev, TXRX_CSR9, ®);
302 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
303 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1);
304 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
305 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, tsf_sync);
306 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
309 static void rt73usb_config_preamble(struct rt2x00_dev *rt2x00dev,
310 const int short_preamble,
311 const int ack_timeout,
312 const int ack_consume_time)
317 * When in atomic context, reschedule and let rt2x00lib
318 * call this function again.
321 queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->config_work);
325 rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
326 rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
327 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
329 rt73usb_register_read(rt2x00dev, TXRX_CSR4, ®);
330 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE,
332 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
335 static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev,
336 const int basic_rate_mask)
338 rt73usb_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
341 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
342 struct rf_channel *rf, const int txpower)
348 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
349 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
351 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
352 rt2x00_rf(&rt2x00dev->chip, RF2527));
354 rt73usb_bbp_read(rt2x00dev, 3, &r3);
355 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
356 rt73usb_bbp_write(rt2x00dev, 3, r3);
359 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
360 r94 += txpower - MAX_TXPOWER;
361 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
363 rt73usb_bbp_write(rt2x00dev, 94, r94);
365 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
366 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
367 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
368 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
370 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
371 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
372 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
373 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
375 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
376 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
377 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
378 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
383 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
386 struct rf_channel rf;
388 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
389 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
390 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
391 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
393 rt73usb_config_channel(rt2x00dev, &rf, txpower);
396 static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
397 struct antenna_setup *ant)
404 rt73usb_bbp_read(rt2x00dev, 3, &r3);
405 rt73usb_bbp_read(rt2x00dev, 4, &r4);
406 rt73usb_bbp_read(rt2x00dev, 77, &r77);
408 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
411 * Configure the RX antenna.
414 case ANTENNA_HW_DIVERSITY:
415 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
416 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
417 && (rt2x00dev->curr_hwmode != HWMODE_A);
418 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
421 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
422 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
423 if (rt2x00dev->curr_hwmode == HWMODE_A)
424 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
426 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
428 case ANTENNA_SW_DIVERSITY:
430 * NOTE: We should never come here because rt2x00lib is
431 * supposed to catch this and send us the correct antenna
432 * explicitely. However we are nog going to bug about this.
433 * Instead, just default to antenna B.
436 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
437 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
438 if (rt2x00dev->curr_hwmode == HWMODE_A)
439 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
441 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
445 rt73usb_bbp_write(rt2x00dev, 77, r77);
446 rt73usb_bbp_write(rt2x00dev, 3, r3);
447 rt73usb_bbp_write(rt2x00dev, 4, r4);
450 static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
451 struct antenna_setup *ant)
457 rt73usb_bbp_read(rt2x00dev, 3, &r3);
458 rt73usb_bbp_read(rt2x00dev, 4, &r4);
459 rt73usb_bbp_read(rt2x00dev, 77, &r77);
461 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
462 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
463 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
466 * Configure the RX antenna.
469 case ANTENNA_HW_DIVERSITY:
470 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
473 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
474 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
476 case ANTENNA_SW_DIVERSITY:
478 * NOTE: We should never come here because rt2x00lib is
479 * supposed to catch this and send us the correct antenna
480 * explicitely. However we are nog going to bug about this.
481 * Instead, just default to antenna B.
484 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
485 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
489 rt73usb_bbp_write(rt2x00dev, 77, r77);
490 rt73usb_bbp_write(rt2x00dev, 3, r3);
491 rt73usb_bbp_write(rt2x00dev, 4, r4);
497 * value[0] -> non-LNA
503 static const struct antenna_sel antenna_sel_a[] = {
504 { 96, { 0x58, 0x78 } },
505 { 104, { 0x38, 0x48 } },
506 { 75, { 0xfe, 0x80 } },
507 { 86, { 0xfe, 0x80 } },
508 { 88, { 0xfe, 0x80 } },
509 { 35, { 0x60, 0x60 } },
510 { 97, { 0x58, 0x58 } },
511 { 98, { 0x58, 0x58 } },
514 static const struct antenna_sel antenna_sel_bg[] = {
515 { 96, { 0x48, 0x68 } },
516 { 104, { 0x2c, 0x3c } },
517 { 75, { 0xfe, 0x80 } },
518 { 86, { 0xfe, 0x80 } },
519 { 88, { 0xfe, 0x80 } },
520 { 35, { 0x50, 0x50 } },
521 { 97, { 0x48, 0x48 } },
522 { 98, { 0x48, 0x48 } },
525 static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev,
526 struct antenna_setup *ant)
528 const struct antenna_sel *sel;
533 if (rt2x00dev->curr_hwmode == HWMODE_A) {
535 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
537 sel = antenna_sel_bg;
538 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
541 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
542 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
544 rt73usb_register_read(rt2x00dev, PHY_CSR0, ®);
546 rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG,
547 (rt2x00dev->curr_hwmode == HWMODE_B ||
548 rt2x00dev->curr_hwmode == HWMODE_G));
549 rt2x00_set_field32(®, PHY_CSR0_PA_PE_A,
550 (rt2x00dev->curr_hwmode == HWMODE_A));
552 rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
554 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
555 rt2x00_rf(&rt2x00dev->chip, RF5225))
556 rt73usb_config_antenna_5x(rt2x00dev, ant);
557 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
558 rt2x00_rf(&rt2x00dev->chip, RF2527))
559 rt73usb_config_antenna_2x(rt2x00dev, ant);
562 static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
563 struct rt2x00lib_conf *libconf)
567 rt73usb_register_read(rt2x00dev, MAC_CSR9, ®);
568 rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, libconf->slot_time);
569 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
571 rt73usb_register_read(rt2x00dev, MAC_CSR8, ®);
572 rt2x00_set_field32(®, MAC_CSR8_SIFS, libconf->sifs);
573 rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
574 rt2x00_set_field32(®, MAC_CSR8_EIFS, libconf->eifs);
575 rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
577 rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
578 rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
579 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
581 rt73usb_register_read(rt2x00dev, TXRX_CSR4, ®);
582 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
583 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
585 rt73usb_register_read(rt2x00dev, TXRX_CSR9, ®);
586 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL,
587 libconf->conf->beacon_int * 16);
588 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
591 static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
592 const unsigned int flags,
593 struct rt2x00lib_conf *libconf)
595 if (flags & CONFIG_UPDATE_PHYMODE)
596 rt73usb_config_phymode(rt2x00dev, libconf->basic_rates);
597 if (flags & CONFIG_UPDATE_CHANNEL)
598 rt73usb_config_channel(rt2x00dev, &libconf->rf,
599 libconf->conf->power_level);
600 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
601 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
602 if (flags & CONFIG_UPDATE_ANTENNA)
603 rt73usb_config_antenna(rt2x00dev, &libconf->ant);
604 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
605 rt73usb_config_duration(rt2x00dev, libconf);
611 static void rt73usb_enable_led(struct rt2x00_dev *rt2x00dev)
615 rt73usb_register_read(rt2x00dev, MAC_CSR14, ®);
616 rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, 70);
617 rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, 30);
618 rt73usb_register_write(rt2x00dev, MAC_CSR14, reg);
620 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 1);
621 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS,
622 (rt2x00dev->rx_status.phymode == MODE_IEEE80211A));
623 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS,
624 (rt2x00dev->rx_status.phymode != MODE_IEEE80211A));
626 rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, 0x0000,
627 rt2x00dev->led_reg, REGISTER_TIMEOUT);
630 static void rt73usb_disable_led(struct rt2x00_dev *rt2x00dev)
632 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 0);
633 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
634 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
636 rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, 0x0000,
637 rt2x00dev->led_reg, REGISTER_TIMEOUT);
640 static void rt73usb_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
644 if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
648 * Led handling requires a positive value for the rssi,
649 * to do that correctly we need to add the correction.
651 rssi += rt2x00dev->rssi_offset;
666 rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, led,
667 rt2x00dev->led_reg, REGISTER_TIMEOUT);
673 static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
674 struct link_qual *qual)
679 * Update FCS error count from register.
681 rt73usb_register_read(rt2x00dev, STA_CSR0, ®);
682 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
685 * Update False CCA count from register.
687 rt73usb_register_read(rt2x00dev, STA_CSR1, ®);
688 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
691 static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
693 rt73usb_bbp_write(rt2x00dev, 17, 0x20);
694 rt2x00dev->link.vgc_level = 0x20;
697 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
699 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
705 * Update Led strength
707 rt73usb_activity_led(rt2x00dev, rssi);
709 rt73usb_bbp_read(rt2x00dev, 17, &r17);
712 * Determine r17 bounds.
714 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
718 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
726 } else if (rssi > -84) {
734 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
741 * Special big-R17 for very short distance
745 rt73usb_bbp_write(rt2x00dev, 17, 0x60);
750 * Special big-R17 for short distance
754 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
759 * Special big-R17 for middle-short distance
763 if (r17 != low_bound)
764 rt73usb_bbp_write(rt2x00dev, 17, low_bound);
769 * Special mid-R17 for middle distance
772 if (r17 != (low_bound + 0x10))
773 rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
778 * Special case: Change up_bound based on the rssi.
779 * Lower up_bound when rssi is weaker then -74 dBm.
781 up_bound -= 2 * (-74 - rssi);
782 if (low_bound > up_bound)
783 up_bound = low_bound;
785 if (r17 > up_bound) {
786 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
791 * r17 does not yet exceed upper limit, continue and base
792 * the r17 tuning on the false CCA count.
794 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
798 rt73usb_bbp_write(rt2x00dev, 17, r17);
799 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
803 rt73usb_bbp_write(rt2x00dev, 17, r17);
808 * Firmware name function.
810 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
812 return FIRMWARE_RT2571;
816 * Initialization functions.
818 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
830 * Wait for stable hardware.
832 for (i = 0; i < 100; i++) {
833 rt73usb_register_read(rt2x00dev, MAC_CSR0, ®);
840 ERROR(rt2x00dev, "Unstable hardware.\n");
845 * Write firmware to device.
846 * We setup a seperate cache for this action,
847 * since we are going to write larger chunks of data
848 * then normally used cache size.
850 cache = kmalloc(CSR_CACHE_SIZE_FIRMWARE, GFP_KERNEL);
852 ERROR(rt2x00dev, "Failed to allocate firmware cache.\n");
856 for (i = 0; i < len; i += CSR_CACHE_SIZE_FIRMWARE) {
857 buflen = min_t(int, len - i, CSR_CACHE_SIZE_FIRMWARE);
858 timeout = REGISTER_TIMEOUT * (buflen / sizeof(u32));
860 memcpy(cache, ptr, buflen);
862 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
863 USB_VENDOR_REQUEST_OUT,
864 FIRMWARE_IMAGE_BASE + i, 0x0000,
865 cache, buflen, timeout);
873 * Send firmware request to device to load firmware,
874 * we need to specify a long timeout time.
876 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
877 0x0000, USB_MODE_FIRMWARE,
878 REGISTER_TIMEOUT_FIRMWARE);
880 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
884 rt73usb_disable_led(rt2x00dev);
889 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
893 rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
894 rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1);
895 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0);
896 rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
897 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
899 rt73usb_register_read(rt2x00dev, TXRX_CSR1, ®);
900 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
901 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1);
902 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
903 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1);
904 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
905 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1);
906 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
907 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1);
908 rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
911 * CCK TXD BBP registers
913 rt73usb_register_read(rt2x00dev, TXRX_CSR2, ®);
914 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13);
915 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1);
916 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12);
917 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1);
918 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11);
919 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1);
920 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10);
921 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1);
922 rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
925 * OFDM TXD BBP registers
927 rt73usb_register_read(rt2x00dev, TXRX_CSR3, ®);
928 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7);
929 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1);
930 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6);
931 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1);
932 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5);
933 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1);
934 rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
936 rt73usb_register_read(rt2x00dev, TXRX_CSR7, ®);
937 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59);
938 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53);
939 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49);
940 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46);
941 rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
943 rt73usb_register_read(rt2x00dev, TXRX_CSR8, ®);
944 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44);
945 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42);
946 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42);
947 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42);
948 rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
950 rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
952 rt73usb_register_read(rt2x00dev, MAC_CSR6, ®);
953 rt2x00_set_field32(®, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
954 rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
956 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
958 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
961 rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
964 * Invalidate all Shared Keys (SEC_CSR0),
965 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
967 rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
968 rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
969 rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
972 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
973 rt2x00_rf(&rt2x00dev->chip, RF2527))
974 rt2x00_set_field32(®, PHY_CSR1_RF_RPI, 1);
975 rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
977 rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
978 rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
979 rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
981 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, ®);
982 rt2x00_set_field32(®, AC_TXOP_CSR0_AC0_TX_OP, 0);
983 rt2x00_set_field32(®, AC_TXOP_CSR0_AC1_TX_OP, 0);
984 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
986 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, ®);
987 rt2x00_set_field32(®, AC_TXOP_CSR1_AC2_TX_OP, 192);
988 rt2x00_set_field32(®, AC_TXOP_CSR1_AC3_TX_OP, 48);
989 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
991 rt73usb_register_read(rt2x00dev, MAC_CSR9, ®);
992 rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0);
993 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
996 * We must clear the error counters.
997 * These registers are cleared on read,
998 * so we may pass a useless variable to store the value.
1000 rt73usb_register_read(rt2x00dev, STA_CSR0, ®);
1001 rt73usb_register_read(rt2x00dev, STA_CSR1, ®);
1002 rt73usb_register_read(rt2x00dev, STA_CSR2, ®);
1005 * Reset MAC and BBP registers.
1007 rt73usb_register_read(rt2x00dev, MAC_CSR1, ®);
1008 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
1009 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
1010 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1012 rt73usb_register_read(rt2x00dev, MAC_CSR1, ®);
1013 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
1014 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
1015 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1017 rt73usb_register_read(rt2x00dev, MAC_CSR1, ®);
1018 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
1019 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1024 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1031 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1032 rt73usb_bbp_read(rt2x00dev, 0, &value);
1033 if ((value != 0xff) && (value != 0x00))
1034 goto continue_csr_init;
1035 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1036 udelay(REGISTER_BUSY_DELAY);
1039 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1043 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1044 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1045 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1046 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1047 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1048 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1049 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1050 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1051 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1052 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1053 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1054 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1055 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1056 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1057 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1058 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1059 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1060 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1061 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1062 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1063 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1064 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1065 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1066 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1067 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1069 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1070 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1071 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1073 if (eeprom != 0xffff && eeprom != 0x0000) {
1074 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1075 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1076 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1078 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1081 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1087 * Device state switch handlers.
1089 static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1090 enum dev_state state)
1094 rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
1095 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX,
1096 state == STATE_RADIO_RX_OFF);
1097 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1100 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1103 * Initialize all registers.
1105 if (rt73usb_init_registers(rt2x00dev) ||
1106 rt73usb_init_bbp(rt2x00dev)) {
1107 ERROR(rt2x00dev, "Register initialization failed.\n");
1111 rt2x00usb_enable_radio(rt2x00dev);
1116 rt73usb_enable_led(rt2x00dev);
1121 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1126 rt73usb_disable_led(rt2x00dev);
1128 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1131 * Disable synchronisation.
1133 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1135 rt2x00usb_disable_radio(rt2x00dev);
1138 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1145 put_to_sleep = (state != STATE_AWAKE);
1147 rt73usb_register_read(rt2x00dev, MAC_CSR12, ®);
1148 rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1149 rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1150 rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
1153 * Device is not guaranteed to be in the requested state yet.
1154 * We must wait until the register indicates that the
1155 * device has entered the correct state.
1157 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1158 rt73usb_register_read(rt2x00dev, MAC_CSR12, ®);
1160 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1161 if (current_state == !put_to_sleep)
1166 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1167 "current device state %d.\n", !put_to_sleep, current_state);
1172 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1173 enum dev_state state)
1178 case STATE_RADIO_ON:
1179 retval = rt73usb_enable_radio(rt2x00dev);
1181 case STATE_RADIO_OFF:
1182 rt73usb_disable_radio(rt2x00dev);
1184 case STATE_RADIO_RX_ON:
1185 case STATE_RADIO_RX_OFF:
1186 rt73usb_toggle_rx(rt2x00dev, state);
1188 case STATE_DEEP_SLEEP:
1192 retval = rt73usb_set_state(rt2x00dev, state);
1203 * TX descriptor initialization
1205 static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1207 struct txdata_entry_desc *desc,
1208 struct ieee80211_hdr *ieee80211hdr,
1209 unsigned int length,
1210 struct ieee80211_tx_control *control)
1215 * Start writing the descriptor words.
1217 rt2x00_desc_read(txd, 1, &word);
1218 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
1219 rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs);
1220 rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min);
1221 rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max);
1222 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1223 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1224 rt2x00_desc_write(txd, 1, word);
1226 rt2x00_desc_read(txd, 2, &word);
1227 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
1228 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
1229 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
1230 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
1231 rt2x00_desc_write(txd, 2, word);
1233 rt2x00_desc_read(txd, 5, &word);
1234 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1235 TXPOWER_TO_DEV(control->power_level));
1236 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1237 rt2x00_desc_write(txd, 5, word);
1239 rt2x00_desc_read(txd, 0, &word);
1240 rt2x00_set_field32(&word, TXD_W0_BURST,
1241 test_bit(ENTRY_TXD_BURST, &desc->flags));
1242 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1243 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1244 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1245 rt2x00_set_field32(&word, TXD_W0_ACK,
1246 !(control->flags & IEEE80211_TXCTL_NO_ACK));
1247 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1248 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1249 rt2x00_set_field32(&word, TXD_W0_OFDM,
1250 test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1251 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1252 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1254 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1255 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1256 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1257 rt2x00_set_field32(&word, TXD_W0_BURST2,
1258 test_bit(ENTRY_TXD_BURST, &desc->flags));
1259 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1260 rt2x00_desc_write(txd, 0, word);
1263 static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
1264 struct sk_buff *skb)
1269 * The length _must_ be a multiple of 4,
1270 * but it must _not_ be a multiple of the USB packet size.
1272 length = roundup(skb->len, 4);
1273 length += (4 * !(length % rt2x00dev->usb_maxpacket));
1279 * TX data initialization
1281 static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1286 if (queue != IEEE80211_TX_QUEUE_BEACON)
1290 * For Wi-Fi faily generated beacons between participating stations.
1291 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1293 rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1295 rt73usb_register_read(rt2x00dev, TXRX_CSR9, ®);
1296 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1297 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1);
1298 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1303 * RX control handlers
1305 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1311 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1326 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
1327 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1328 if (lna == 3 || lna == 2)
1337 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1338 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1340 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1343 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1344 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1347 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1350 static void rt73usb_fill_rxdone(struct data_entry *entry,
1351 struct rxdata_entry_desc *desc)
1353 __le32 *rxd = (__le32 *)entry->skb->data;
1357 rt2x00_desc_read(rxd, 0, &word0);
1358 rt2x00_desc_read(rxd, 1, &word1);
1361 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1362 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1365 * Obtain the status about this packet.
1367 desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1368 desc->rssi = rt73usb_agc_to_rssi(entry->ring->rt2x00dev, word1);
1369 desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1370 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1373 * Pull the skb to clear the descriptor area.
1375 skb_pull(entry->skb, entry->ring->desc_size);
1381 * Device probe functions.
1383 static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1389 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1392 * Start validation of the data that has been read.
1394 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1395 if (!is_valid_ether_addr(mac)) {
1396 DECLARE_MAC_BUF(macbuf);
1398 random_ether_addr(mac);
1399 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1402 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1403 if (word == 0xffff) {
1404 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1405 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1407 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1409 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1410 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1411 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1412 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1413 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1414 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1417 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1418 if (word == 0xffff) {
1419 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1420 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1421 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1424 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1425 if (word == 0xffff) {
1426 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1427 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1428 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1429 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1430 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1431 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1432 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1433 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1434 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1436 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1437 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1440 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1441 if (word == 0xffff) {
1442 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1443 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1444 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1445 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1448 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1449 if (word == 0xffff) {
1450 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1451 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1452 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1453 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1455 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1456 if (value < -10 || value > 10)
1457 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1458 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1459 if (value < -10 || value > 10)
1460 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1461 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1464 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1465 if (word == 0xffff) {
1466 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1467 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1468 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1469 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1471 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1472 if (value < -10 || value > 10)
1473 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1474 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1475 if (value < -10 || value > 10)
1476 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1477 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1483 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1490 * Read EEPROM word for configuration.
1492 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1495 * Identify RF chipset.
1497 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1498 rt73usb_register_read(rt2x00dev, MAC_CSR0, ®);
1499 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1501 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
1502 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1506 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1507 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1508 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1509 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1510 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1515 * Identify default antenna configuration.
1517 rt2x00dev->default_ant.tx =
1518 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1519 rt2x00dev->default_ant.rx =
1520 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1523 * Read the Frame type.
1525 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1526 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1529 * Read frequency offset.
1531 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1532 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1535 * Read external LNA informations.
1537 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1539 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1540 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1541 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1545 * Store led settings, for correct led behaviour.
1547 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1549 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
1550 rt2x00dev->led_mode);
1551 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
1552 rt2x00_get_field16(eeprom,
1553 EEPROM_LED_POLARITY_GPIO_0));
1554 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
1555 rt2x00_get_field16(eeprom,
1556 EEPROM_LED_POLARITY_GPIO_1));
1557 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
1558 rt2x00_get_field16(eeprom,
1559 EEPROM_LED_POLARITY_GPIO_2));
1560 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
1561 rt2x00_get_field16(eeprom,
1562 EEPROM_LED_POLARITY_GPIO_3));
1563 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
1564 rt2x00_get_field16(eeprom,
1565 EEPROM_LED_POLARITY_GPIO_4));
1566 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
1567 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1568 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
1569 rt2x00_get_field16(eeprom,
1570 EEPROM_LED_POLARITY_RDY_G));
1571 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
1572 rt2x00_get_field16(eeprom,
1573 EEPROM_LED_POLARITY_RDY_A));
1579 * RF value list for RF2528
1582 static const struct rf_channel rf_vals_bg_2528[] = {
1583 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1584 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1585 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1586 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1587 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1588 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1589 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1590 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1591 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1592 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1593 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1594 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1595 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1596 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1600 * RF value list for RF5226
1601 * Supports: 2.4 GHz & 5.2 GHz
1603 static const struct rf_channel rf_vals_5226[] = {
1604 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1605 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1606 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1607 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1608 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1609 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1610 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1611 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1612 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1613 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1614 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1615 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1616 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1617 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1619 /* 802.11 UNI / HyperLan 2 */
1620 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1621 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1622 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1623 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1624 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1625 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1626 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1627 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1629 /* 802.11 HyperLan 2 */
1630 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1631 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1632 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1633 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1634 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1635 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1636 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1637 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1638 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1639 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1642 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1643 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1644 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1645 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1646 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1647 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1649 /* MMAC(Japan)J52 ch 34,38,42,46 */
1650 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1651 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1652 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1653 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1657 * RF value list for RF5225 & RF2527
1658 * Supports: 2.4 GHz & 5.2 GHz
1660 static const struct rf_channel rf_vals_5225_2527[] = {
1661 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1662 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1663 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1664 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1665 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1666 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
1667 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
1668 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
1669 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
1670 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
1671 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
1672 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
1673 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
1674 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
1676 /* 802.11 UNI / HyperLan 2 */
1677 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
1678 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
1679 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
1680 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
1681 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
1682 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
1683 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
1684 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
1686 /* 802.11 HyperLan 2 */
1687 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
1688 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
1689 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
1690 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
1691 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
1692 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
1693 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
1694 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
1695 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
1696 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
1699 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
1700 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
1701 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
1702 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
1703 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
1704 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
1706 /* MMAC(Japan)J52 ch 34,38,42,46 */
1707 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
1708 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
1709 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
1710 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
1714 static void rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1716 struct hw_mode_spec *spec = &rt2x00dev->spec;
1721 * Initialize all hw fields.
1723 rt2x00dev->hw->flags =
1724 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
1725 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1726 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
1727 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1728 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1729 rt2x00dev->hw->queues = 5;
1731 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_usb(rt2x00dev)->dev);
1732 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1733 rt2x00_eeprom_addr(rt2x00dev,
1734 EEPROM_MAC_ADDR_0));
1737 * Convert tx_power array in eeprom.
1739 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
1740 for (i = 0; i < 14; i++)
1741 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1744 * Initialize hw_mode information.
1746 spec->num_modes = 2;
1747 spec->num_rates = 12;
1748 spec->tx_power_a = NULL;
1749 spec->tx_power_bg = txpower;
1750 spec->tx_power_default = DEFAULT_TXPOWER;
1752 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
1753 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
1754 spec->channels = rf_vals_bg_2528;
1755 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1756 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
1757 spec->channels = rf_vals_5226;
1758 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1759 spec->num_channels = 14;
1760 spec->channels = rf_vals_5225_2527;
1761 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
1762 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
1763 spec->channels = rf_vals_5225_2527;
1766 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1767 rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1768 spec->num_modes = 3;
1770 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
1771 for (i = 0; i < 14; i++)
1772 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1774 spec->tx_power_a = txpower;
1778 static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
1783 * Allocate eeprom data.
1785 retval = rt73usb_validate_eeprom(rt2x00dev);
1789 retval = rt73usb_init_eeprom(rt2x00dev);
1794 * Initialize hw specifications.
1796 rt73usb_probe_hw_mode(rt2x00dev);
1799 * This device requires firmware
1801 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1804 * Set the rssi offset.
1806 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1812 * IEEE80211 stack callback functions.
1814 static void rt73usb_configure_filter(struct ieee80211_hw *hw,
1815 unsigned int changed_flags,
1816 unsigned int *total_flags,
1818 struct dev_addr_list *mc_list)
1820 struct rt2x00_dev *rt2x00dev = hw->priv;
1821 struct interface *intf = &rt2x00dev->interface;
1825 * Mask off any flags we are going to ignore from
1826 * the total_flags field.
1837 * Apply some rules to the filters:
1838 * - Some filters imply different filters to be set.
1839 * - Some things we can't filter out at all.
1840 * - Some filters are set based on interface type.
1843 *total_flags |= FIF_ALLMULTI;
1844 if (*total_flags & FIF_OTHER_BSS ||
1845 *total_flags & FIF_PROMISC_IN_BSS)
1846 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1847 if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
1848 *total_flags |= FIF_PROMISC_IN_BSS;
1851 * Check if there is any work left for us.
1853 if (intf->filter == *total_flags)
1855 intf->filter = *total_flags;
1858 * When in atomic context, reschedule and let rt2x00lib
1859 * call this function again.
1862 queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->filter_work);
1867 * Start configuration steps.
1868 * Note that the version error will always be dropped
1869 * and broadcast frames will always be accepted since
1870 * there is no filter for it at this time.
1872 rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
1873 rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC,
1874 !(*total_flags & FIF_FCSFAIL));
1875 rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL,
1876 !(*total_flags & FIF_PLCPFAIL));
1877 rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL,
1878 !(*total_flags & FIF_CONTROL));
1879 rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME,
1880 !(*total_flags & FIF_PROMISC_IN_BSS));
1881 rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS,
1882 !(*total_flags & FIF_PROMISC_IN_BSS));
1883 rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1);
1884 rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST,
1885 !(*total_flags & FIF_ALLMULTI));
1886 rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0);
1887 rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, 1);
1888 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1891 static int rt73usb_set_retry_limit(struct ieee80211_hw *hw,
1892 u32 short_retry, u32 long_retry)
1894 struct rt2x00_dev *rt2x00dev = hw->priv;
1897 rt73usb_register_read(rt2x00dev, TXRX_CSR4, ®);
1898 rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
1899 rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
1900 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
1907 * Mac80211 demands get_tsf must be atomic.
1908 * This is not possible for rt73usb since all register access
1909 * functions require sleeping. Untill mac80211 no longer needs
1910 * get_tsf to be atomic, this function should be disabled.
1912 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
1914 struct rt2x00_dev *rt2x00dev = hw->priv;
1918 rt73usb_register_read(rt2x00dev, TXRX_CSR13, ®);
1919 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
1920 rt73usb_register_read(rt2x00dev, TXRX_CSR12, ®);
1921 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
1926 #define rt73usb_get_tsf NULL
1929 static void rt73usb_reset_tsf(struct ieee80211_hw *hw)
1931 struct rt2x00_dev *rt2x00dev = hw->priv;
1933 rt73usb_register_write(rt2x00dev, TXRX_CSR12, 0);
1934 rt73usb_register_write(rt2x00dev, TXRX_CSR13, 0);
1937 static int rt73usb_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1938 struct ieee80211_tx_control *control)
1940 struct rt2x00_dev *rt2x00dev = hw->priv;
1944 * Just in case the ieee80211 doesn't set this,
1945 * but we need this queue set for the descriptor
1948 control->queue = IEEE80211_TX_QUEUE_BEACON;
1951 * First we create the beacon.
1953 skb_push(skb, TXD_DESC_SIZE);
1954 memset(skb->data, 0, TXD_DESC_SIZE);
1956 rt2x00lib_write_tx_desc(rt2x00dev, (__le32 *)skb->data,
1957 (struct ieee80211_hdr *)(skb->data +
1959 skb->len - TXD_DESC_SIZE, control);
1962 * Write entire beacon with descriptor to register,
1963 * and kick the beacon generator.
1965 timeout = REGISTER_TIMEOUT * (skb->len / sizeof(u32));
1966 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
1967 USB_VENDOR_REQUEST_OUT,
1968 HW_BEACON_BASE0, 0x0000,
1969 skb->data, skb->len, timeout);
1970 rt73usb_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
1975 static const struct ieee80211_ops rt73usb_mac80211_ops = {
1977 .start = rt2x00mac_start,
1978 .stop = rt2x00mac_stop,
1979 .add_interface = rt2x00mac_add_interface,
1980 .remove_interface = rt2x00mac_remove_interface,
1981 .config = rt2x00mac_config,
1982 .config_interface = rt2x00mac_config_interface,
1983 .configure_filter = rt73usb_configure_filter,
1984 .get_stats = rt2x00mac_get_stats,
1985 .set_retry_limit = rt73usb_set_retry_limit,
1986 .erp_ie_changed = rt2x00mac_erp_ie_changed,
1987 .conf_tx = rt2x00mac_conf_tx,
1988 .get_tx_stats = rt2x00mac_get_tx_stats,
1989 .get_tsf = rt73usb_get_tsf,
1990 .reset_tsf = rt73usb_reset_tsf,
1991 .beacon_update = rt73usb_beacon_update,
1994 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
1995 .probe_hw = rt73usb_probe_hw,
1996 .get_firmware_name = rt73usb_get_firmware_name,
1997 .load_firmware = rt73usb_load_firmware,
1998 .initialize = rt2x00usb_initialize,
1999 .uninitialize = rt2x00usb_uninitialize,
2000 .set_device_state = rt73usb_set_device_state,
2001 .link_stats = rt73usb_link_stats,
2002 .reset_tuner = rt73usb_reset_tuner,
2003 .link_tuner = rt73usb_link_tuner,
2004 .write_tx_desc = rt73usb_write_tx_desc,
2005 .write_tx_data = rt2x00usb_write_tx_data,
2006 .get_tx_data_len = rt73usb_get_tx_data_len,
2007 .kick_tx_queue = rt73usb_kick_tx_queue,
2008 .fill_rxdone = rt73usb_fill_rxdone,
2009 .config_mac_addr = rt73usb_config_mac_addr,
2010 .config_bssid = rt73usb_config_bssid,
2011 .config_type = rt73usb_config_type,
2012 .config_preamble = rt73usb_config_preamble,
2013 .config = rt73usb_config,
2016 static const struct rt2x00_ops rt73usb_ops = {
2018 .rxd_size = RXD_DESC_SIZE,
2019 .txd_size = TXD_DESC_SIZE,
2020 .eeprom_size = EEPROM_SIZE,
2022 .lib = &rt73usb_rt2x00_ops,
2023 .hw = &rt73usb_mac80211_ops,
2024 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2025 .debugfs = &rt73usb_rt2x00debug,
2026 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2030 * rt73usb module information.
2032 static struct usb_device_id rt73usb_device_table[] = {
2034 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2036 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2038 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2039 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2041 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2042 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2043 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
2044 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
2046 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2048 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2050 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2051 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2053 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2055 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2056 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2058 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2060 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2061 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2063 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2065 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2066 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2068 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2069 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2071 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2072 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2073 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2074 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2076 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2077 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2079 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2080 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2081 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2083 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2085 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2086 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2088 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2090 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2091 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2095 MODULE_AUTHOR(DRV_PROJECT);
2096 MODULE_VERSION(DRV_VERSION);
2097 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2098 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2099 MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2100 MODULE_FIRMWARE(FIRMWARE_RT2571);
2101 MODULE_LICENSE("GPL");
2103 static struct usb_driver rt73usb_driver = {
2105 .id_table = rt73usb_device_table,
2106 .probe = rt2x00usb_probe,
2107 .disconnect = rt2x00usb_disconnect,
2108 .suspend = rt2x00usb_suspend,
2109 .resume = rt2x00usb_resume,
2112 static int __init rt73usb_init(void)
2114 return usb_register(&rt73usb_driver);
2117 static void __exit rt73usb_exit(void)
2119 usb_deregister(&rt73usb_driver);
2122 module_init(rt73usb_init);
2123 module_exit(rt73usb_exit);