2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/usb.h>
36 #include "rt2x00usb.h"
41 * All access to the CSR registers will go through the methods
42 * rt73usb_register_read and rt73usb_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 * The _lock versions must be used if you already hold the usb_cache_mutex
53 static inline void rt73usb_register_read(struct rt2x00_dev *rt2x00dev,
54 const unsigned int offset, u32 *value)
57 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
58 USB_VENDOR_REQUEST_IN, offset,
59 ®, sizeof(u32), REGISTER_TIMEOUT);
60 *value = le32_to_cpu(reg);
63 static inline void rt73usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
64 const unsigned int offset, u32 *value)
67 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
68 USB_VENDOR_REQUEST_IN, offset,
69 ®, sizeof(u32), REGISTER_TIMEOUT);
70 *value = le32_to_cpu(reg);
73 static inline void rt73usb_register_multiread(struct rt2x00_dev *rt2x00dev,
74 const unsigned int offset,
75 void *value, const u32 length)
77 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
78 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
79 USB_VENDOR_REQUEST_IN, offset,
80 value, length, timeout);
83 static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev,
84 const unsigned int offset, u32 value)
86 __le32 reg = cpu_to_le32(value);
87 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
88 USB_VENDOR_REQUEST_OUT, offset,
89 ®, sizeof(u32), REGISTER_TIMEOUT);
92 static inline void rt73usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
93 const unsigned int offset, u32 value)
95 __le32 reg = cpu_to_le32(value);
96 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
97 USB_VENDOR_REQUEST_OUT, offset,
98 ®, sizeof(u32), REGISTER_TIMEOUT);
101 static inline void rt73usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
102 const unsigned int offset,
103 void *value, const u32 length)
105 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
106 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
107 USB_VENDOR_REQUEST_OUT, offset,
108 value, length, timeout);
111 static u32 rt73usb_bbp_check(struct rt2x00_dev *rt2x00dev)
116 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
117 rt73usb_register_read_lock(rt2x00dev, PHY_CSR3, ®);
118 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
120 udelay(REGISTER_BUSY_DELAY);
126 static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
127 const unsigned int word, const u8 value)
131 mutex_lock(&rt2x00dev->usb_cache_mutex);
134 * Wait until the BBP becomes ready.
136 reg = rt73usb_bbp_check(rt2x00dev);
137 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
138 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
139 mutex_unlock(&rt2x00dev->usb_cache_mutex);
144 * Write the data into the BBP.
147 rt2x00_set_field32(®, PHY_CSR3_VALUE, value);
148 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
149 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
150 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0);
152 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
153 mutex_unlock(&rt2x00dev->usb_cache_mutex);
156 static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
157 const unsigned int word, u8 *value)
161 mutex_lock(&rt2x00dev->usb_cache_mutex);
164 * Wait until the BBP becomes ready.
166 reg = rt73usb_bbp_check(rt2x00dev);
167 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
168 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
169 mutex_unlock(&rt2x00dev->usb_cache_mutex);
174 * Write the request into the BBP.
177 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
178 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
179 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1);
181 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
184 * Wait until the BBP becomes ready.
186 reg = rt73usb_bbp_check(rt2x00dev);
187 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
188 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
193 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
194 mutex_unlock(&rt2x00dev->usb_cache_mutex);
197 static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
198 const unsigned int word, const u32 value)
206 mutex_lock(&rt2x00dev->usb_cache_mutex);
208 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
209 rt73usb_register_read_lock(rt2x00dev, PHY_CSR4, ®);
210 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
212 udelay(REGISTER_BUSY_DELAY);
215 mutex_unlock(&rt2x00dev->usb_cache_mutex);
216 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
221 rt2x00_set_field32(®, PHY_CSR4_VALUE, value);
224 * RF5225 and RF2527 contain 21 bits per RF register value,
225 * all others contain 20 bits.
227 rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS,
228 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
229 rt2x00_rf(&rt2x00dev->chip, RF2527)));
230 rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0);
231 rt2x00_set_field32(®, PHY_CSR4_BUSY, 1);
233 rt73usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
234 rt2x00_rf_write(rt2x00dev, word, value);
235 mutex_unlock(&rt2x00dev->usb_cache_mutex);
238 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
239 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
241 static void rt73usb_read_csr(struct rt2x00_dev *rt2x00dev,
242 const unsigned int word, u32 *data)
244 rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data);
247 static void rt73usb_write_csr(struct rt2x00_dev *rt2x00dev,
248 const unsigned int word, u32 data)
250 rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
253 static const struct rt2x00debug rt73usb_rt2x00debug = {
254 .owner = THIS_MODULE,
256 .read = rt73usb_read_csr,
257 .write = rt73usb_write_csr,
258 .word_size = sizeof(u32),
259 .word_count = CSR_REG_SIZE / sizeof(u32),
262 .read = rt2x00_eeprom_read,
263 .write = rt2x00_eeprom_write,
264 .word_size = sizeof(u16),
265 .word_count = EEPROM_SIZE / sizeof(u16),
268 .read = rt73usb_bbp_read,
269 .write = rt73usb_bbp_write,
270 .word_size = sizeof(u8),
271 .word_count = BBP_SIZE / sizeof(u8),
274 .read = rt2x00_rf_read,
275 .write = rt73usb_rf_write,
276 .word_size = sizeof(u32),
277 .word_count = RF_SIZE / sizeof(u32),
280 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
282 #ifdef CONFIG_RT73USB_LEDS
283 static void rt73usb_led_brightness(struct led_classdev *led_cdev,
284 enum led_brightness brightness)
286 struct rt2x00_led *led =
287 container_of(led_cdev, struct rt2x00_led, led_dev);
288 unsigned int enabled = brightness != LED_OFF;
289 unsigned int a_mode =
290 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
291 unsigned int bg_mode =
292 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
295 NOTICE(led->rt2x00dev,
296 "Ignoring LED brightness command for led %d\n",
301 if (led->type == LED_TYPE_RADIO) {
302 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
303 MCU_LEDCS_RADIO_STATUS, enabled);
305 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
306 0, led->rt2x00dev->led_mcu_reg,
308 } else if (led->type == LED_TYPE_ASSOC) {
309 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
310 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
311 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
312 MCU_LEDCS_LINK_A_STATUS, a_mode);
314 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
315 0, led->rt2x00dev->led_mcu_reg,
317 } else if (led->type == LED_TYPE_QUALITY) {
319 * The brightness is divided into 6 levels (0 - 5),
320 * this means we need to convert the brightness
321 * argument into the matching level within that range.
323 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
324 brightness / (LED_FULL / 6),
325 led->rt2x00dev->led_mcu_reg,
330 #define rt73usb_led_brightness NULL
331 #endif /* CONFIG_RT73USB_LEDS */
334 * Configuration handlers.
336 static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
337 struct rt2x00_intf *intf,
338 struct rt2x00intf_conf *conf,
339 const unsigned int flags)
341 unsigned int beacon_base;
344 if (flags & CONFIG_UPDATE_TYPE) {
346 * Clear current synchronisation setup.
347 * For the Beacon base registers we only need to clear
348 * the first byte since that byte contains the VALID and OWNER
349 * bits which (when set to 0) will invalidate the entire beacon.
351 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
352 rt73usb_register_write(rt2x00dev, beacon_base, 0);
355 * Enable synchronisation.
357 rt73usb_register_read(rt2x00dev, TXRX_CSR9, ®);
358 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync);
359 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
362 if (flags & CONFIG_UPDATE_MAC) {
363 reg = le32_to_cpu(conf->mac[1]);
364 rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
365 conf->mac[1] = cpu_to_le32(reg);
367 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2,
368 conf->mac, sizeof(conf->mac));
371 if (flags & CONFIG_UPDATE_BSSID) {
372 reg = le32_to_cpu(conf->bssid[1]);
373 rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3);
374 conf->bssid[1] = cpu_to_le32(reg);
376 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4,
377 conf->bssid, sizeof(conf->bssid));
381 static int rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
382 struct rt2x00lib_erp *erp)
387 * When in atomic context, we should let rt2x00lib
388 * try this configuration again later.
393 rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
394 rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
395 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
397 rt73usb_register_read(rt2x00dev, TXRX_CSR4, ®);
398 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE,
399 !!erp->short_preamble);
400 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
405 static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev,
406 const int basic_rate_mask)
408 rt73usb_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
411 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
412 struct rf_channel *rf, const int txpower)
418 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
419 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
421 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
422 rt2x00_rf(&rt2x00dev->chip, RF2527));
424 rt73usb_bbp_read(rt2x00dev, 3, &r3);
425 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
426 rt73usb_bbp_write(rt2x00dev, 3, r3);
429 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
430 r94 += txpower - MAX_TXPOWER;
431 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
433 rt73usb_bbp_write(rt2x00dev, 94, r94);
435 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
436 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
437 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
438 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
440 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
441 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
442 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
443 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
445 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
446 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
447 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
448 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
453 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
456 struct rf_channel rf;
458 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
459 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
460 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
461 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
463 rt73usb_config_channel(rt2x00dev, &rf, txpower);
466 static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
467 struct antenna_setup *ant)
474 rt73usb_bbp_read(rt2x00dev, 3, &r3);
475 rt73usb_bbp_read(rt2x00dev, 4, &r4);
476 rt73usb_bbp_read(rt2x00dev, 77, &r77);
478 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
481 * Configure the RX antenna.
484 case ANTENNA_HW_DIVERSITY:
485 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
486 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
487 && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
488 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
491 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
492 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
493 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
494 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
496 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
500 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
501 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
502 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
503 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
505 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
509 rt73usb_bbp_write(rt2x00dev, 77, r77);
510 rt73usb_bbp_write(rt2x00dev, 3, r3);
511 rt73usb_bbp_write(rt2x00dev, 4, r4);
514 static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
515 struct antenna_setup *ant)
521 rt73usb_bbp_read(rt2x00dev, 3, &r3);
522 rt73usb_bbp_read(rt2x00dev, 4, &r4);
523 rt73usb_bbp_read(rt2x00dev, 77, &r77);
525 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
526 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
527 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
530 * Configure the RX antenna.
533 case ANTENNA_HW_DIVERSITY:
534 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
537 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
538 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
542 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
543 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
547 rt73usb_bbp_write(rt2x00dev, 77, r77);
548 rt73usb_bbp_write(rt2x00dev, 3, r3);
549 rt73usb_bbp_write(rt2x00dev, 4, r4);
555 * value[0] -> non-LNA
561 static const struct antenna_sel antenna_sel_a[] = {
562 { 96, { 0x58, 0x78 } },
563 { 104, { 0x38, 0x48 } },
564 { 75, { 0xfe, 0x80 } },
565 { 86, { 0xfe, 0x80 } },
566 { 88, { 0xfe, 0x80 } },
567 { 35, { 0x60, 0x60 } },
568 { 97, { 0x58, 0x58 } },
569 { 98, { 0x58, 0x58 } },
572 static const struct antenna_sel antenna_sel_bg[] = {
573 { 96, { 0x48, 0x68 } },
574 { 104, { 0x2c, 0x3c } },
575 { 75, { 0xfe, 0x80 } },
576 { 86, { 0xfe, 0x80 } },
577 { 88, { 0xfe, 0x80 } },
578 { 35, { 0x50, 0x50 } },
579 { 97, { 0x48, 0x48 } },
580 { 98, { 0x48, 0x48 } },
583 static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev,
584 struct antenna_setup *ant)
586 const struct antenna_sel *sel;
592 * We should never come here because rt2x00lib is supposed
593 * to catch this and send us the correct antenna explicitely.
595 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
596 ant->tx == ANTENNA_SW_DIVERSITY);
598 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
600 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
602 sel = antenna_sel_bg;
603 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
606 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
607 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
609 rt73usb_register_read(rt2x00dev, PHY_CSR0, ®);
611 rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG,
612 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
613 rt2x00_set_field32(®, PHY_CSR0_PA_PE_A,
614 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
616 rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
618 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
619 rt2x00_rf(&rt2x00dev->chip, RF5225))
620 rt73usb_config_antenna_5x(rt2x00dev, ant);
621 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
622 rt2x00_rf(&rt2x00dev->chip, RF2527))
623 rt73usb_config_antenna_2x(rt2x00dev, ant);
626 static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
627 struct rt2x00lib_conf *libconf)
631 rt73usb_register_read(rt2x00dev, MAC_CSR9, ®);
632 rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, libconf->slot_time);
633 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
635 rt73usb_register_read(rt2x00dev, MAC_CSR8, ®);
636 rt2x00_set_field32(®, MAC_CSR8_SIFS, libconf->sifs);
637 rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
638 rt2x00_set_field32(®, MAC_CSR8_EIFS, libconf->eifs);
639 rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
641 rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
642 rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
643 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
645 rt73usb_register_read(rt2x00dev, TXRX_CSR4, ®);
646 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
647 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
649 rt73usb_register_read(rt2x00dev, TXRX_CSR9, ®);
650 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL,
651 libconf->conf->beacon_int * 16);
652 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
655 static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
656 struct rt2x00lib_conf *libconf,
657 const unsigned int flags)
659 if (flags & CONFIG_UPDATE_PHYMODE)
660 rt73usb_config_phymode(rt2x00dev, libconf->basic_rates);
661 if (flags & CONFIG_UPDATE_CHANNEL)
662 rt73usb_config_channel(rt2x00dev, &libconf->rf,
663 libconf->conf->power_level);
664 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
665 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
666 if (flags & CONFIG_UPDATE_ANTENNA)
667 rt73usb_config_antenna(rt2x00dev, &libconf->ant);
668 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
669 rt73usb_config_duration(rt2x00dev, libconf);
675 static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
676 struct link_qual *qual)
681 * Update FCS error count from register.
683 rt73usb_register_read(rt2x00dev, STA_CSR0, ®);
684 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
687 * Update False CCA count from register.
689 rt73usb_register_read(rt2x00dev, STA_CSR1, ®);
690 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
693 static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
695 rt73usb_bbp_write(rt2x00dev, 17, 0x20);
696 rt2x00dev->link.vgc_level = 0x20;
699 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
701 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
706 rt73usb_bbp_read(rt2x00dev, 17, &r17);
709 * Determine r17 bounds.
711 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
715 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
723 } else if (rssi > -84) {
731 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
738 * If we are not associated, we should go straight to the
739 * dynamic CCA tuning.
741 if (!rt2x00dev->intf_associated)
742 goto dynamic_cca_tune;
745 * Special big-R17 for very short distance
749 rt73usb_bbp_write(rt2x00dev, 17, 0x60);
754 * Special big-R17 for short distance
758 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
763 * Special big-R17 for middle-short distance
767 if (r17 != low_bound)
768 rt73usb_bbp_write(rt2x00dev, 17, low_bound);
773 * Special mid-R17 for middle distance
776 if (r17 != (low_bound + 0x10))
777 rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
782 * Special case: Change up_bound based on the rssi.
783 * Lower up_bound when rssi is weaker then -74 dBm.
785 up_bound -= 2 * (-74 - rssi);
786 if (low_bound > up_bound)
787 up_bound = low_bound;
789 if (r17 > up_bound) {
790 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
797 * r17 does not yet exceed upper limit, continue and base
798 * the r17 tuning on the false CCA count.
800 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
804 rt73usb_bbp_write(rt2x00dev, 17, r17);
805 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
809 rt73usb_bbp_write(rt2x00dev, 17, r17);
816 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
818 return FIRMWARE_RT2571;
821 static u16 rt73usb_get_firmware_crc(void *data, const size_t len)
826 * Use the crc itu-t algorithm.
827 * The last 2 bytes in the firmware array are the crc checksum itself,
828 * this means that we should never pass those 2 bytes to the crc
831 crc = crc_itu_t(0, data, len - 2);
832 crc = crc_itu_t_byte(crc, 0);
833 crc = crc_itu_t_byte(crc, 0);
838 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
850 * Wait for stable hardware.
852 for (i = 0; i < 100; i++) {
853 rt73usb_register_read(rt2x00dev, MAC_CSR0, ®);
860 ERROR(rt2x00dev, "Unstable hardware.\n");
865 * Write firmware to device.
866 * We setup a seperate cache for this action,
867 * since we are going to write larger chunks of data
868 * then normally used cache size.
870 cache = kmalloc(CSR_CACHE_SIZE_FIRMWARE, GFP_KERNEL);
872 ERROR(rt2x00dev, "Failed to allocate firmware cache.\n");
876 for (i = 0; i < len; i += CSR_CACHE_SIZE_FIRMWARE) {
877 buflen = min_t(int, len - i, CSR_CACHE_SIZE_FIRMWARE);
878 timeout = REGISTER_TIMEOUT * (buflen / sizeof(u32));
880 memcpy(cache, ptr, buflen);
882 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
883 USB_VENDOR_REQUEST_OUT,
884 FIRMWARE_IMAGE_BASE + i, 0,
885 cache, buflen, timeout);
893 * Send firmware request to device to load firmware,
894 * we need to specify a long timeout time.
896 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
897 0, USB_MODE_FIRMWARE,
898 REGISTER_TIMEOUT_FIRMWARE);
900 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
908 * Initialization functions.
910 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
914 rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
915 rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1);
916 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0);
917 rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
918 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
920 rt73usb_register_read(rt2x00dev, TXRX_CSR1, ®);
921 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
922 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1);
923 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
924 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1);
925 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
926 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1);
927 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
928 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1);
929 rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
932 * CCK TXD BBP registers
934 rt73usb_register_read(rt2x00dev, TXRX_CSR2, ®);
935 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13);
936 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1);
937 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12);
938 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1);
939 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11);
940 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1);
941 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10);
942 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1);
943 rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
946 * OFDM TXD BBP registers
948 rt73usb_register_read(rt2x00dev, TXRX_CSR3, ®);
949 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7);
950 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1);
951 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6);
952 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1);
953 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5);
954 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1);
955 rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
957 rt73usb_register_read(rt2x00dev, TXRX_CSR7, ®);
958 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59);
959 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53);
960 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49);
961 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46);
962 rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
964 rt73usb_register_read(rt2x00dev, TXRX_CSR8, ®);
965 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44);
966 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42);
967 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42);
968 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42);
969 rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
971 rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
973 rt73usb_register_read(rt2x00dev, MAC_CSR6, ®);
974 rt2x00_set_field32(®, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
975 rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
977 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
979 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
982 rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
984 rt73usb_register_read(rt2x00dev, MAC_CSR14, ®);
985 rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, 70);
986 rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, 30);
987 rt73usb_register_write(rt2x00dev, MAC_CSR14, reg);
990 * Invalidate all Shared Keys (SEC_CSR0),
991 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
993 rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
994 rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
995 rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
998 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
999 rt2x00_rf(&rt2x00dev->chip, RF2527))
1000 rt2x00_set_field32(®, PHY_CSR1_RF_RPI, 1);
1001 rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
1003 rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1004 rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1005 rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1007 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, ®);
1008 rt2x00_set_field32(®, AC_TXOP_CSR0_AC0_TX_OP, 0);
1009 rt2x00_set_field32(®, AC_TXOP_CSR0_AC1_TX_OP, 0);
1010 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1012 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, ®);
1013 rt2x00_set_field32(®, AC_TXOP_CSR1_AC2_TX_OP, 192);
1014 rt2x00_set_field32(®, AC_TXOP_CSR1_AC3_TX_OP, 48);
1015 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1017 rt73usb_register_read(rt2x00dev, MAC_CSR9, ®);
1018 rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0);
1019 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
1023 * For the Beacon base registers we only need to clear
1024 * the first byte since that byte contains the VALID and OWNER
1025 * bits which (when set to 0) will invalidate the entire beacon.
1027 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1028 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1029 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1030 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1033 * We must clear the error counters.
1034 * These registers are cleared on read,
1035 * so we may pass a useless variable to store the value.
1037 rt73usb_register_read(rt2x00dev, STA_CSR0, ®);
1038 rt73usb_register_read(rt2x00dev, STA_CSR1, ®);
1039 rt73usb_register_read(rt2x00dev, STA_CSR2, ®);
1042 * Reset MAC and BBP registers.
1044 rt73usb_register_read(rt2x00dev, MAC_CSR1, ®);
1045 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
1046 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
1047 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1049 rt73usb_register_read(rt2x00dev, MAC_CSR1, ®);
1050 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
1051 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
1052 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1054 rt73usb_register_read(rt2x00dev, MAC_CSR1, ®);
1055 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
1056 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1061 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1068 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1069 rt73usb_bbp_read(rt2x00dev, 0, &value);
1070 if ((value != 0xff) && (value != 0x00))
1071 goto continue_csr_init;
1072 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1073 udelay(REGISTER_BUSY_DELAY);
1076 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1080 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1081 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1082 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1083 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1084 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1085 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1086 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1087 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1088 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1089 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1090 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1091 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1092 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1093 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1094 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1095 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1096 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1097 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1098 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1099 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1100 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1101 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1102 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1103 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1104 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1106 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1107 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1109 if (eeprom != 0xffff && eeprom != 0x0000) {
1110 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1111 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1112 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1120 * Device state switch handlers.
1122 static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1123 enum dev_state state)
1127 rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
1128 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX,
1129 state == STATE_RADIO_RX_OFF);
1130 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1133 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1136 * Initialize all registers.
1138 if (rt73usb_init_registers(rt2x00dev) ||
1139 rt73usb_init_bbp(rt2x00dev)) {
1140 ERROR(rt2x00dev, "Register initialization failed.\n");
1147 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1149 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1152 * Disable synchronisation.
1154 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1156 rt2x00usb_disable_radio(rt2x00dev);
1159 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1166 put_to_sleep = (state != STATE_AWAKE);
1168 rt73usb_register_read(rt2x00dev, MAC_CSR12, ®);
1169 rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1170 rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1171 rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
1174 * Device is not guaranteed to be in the requested state yet.
1175 * We must wait until the register indicates that the
1176 * device has entered the correct state.
1178 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1179 rt73usb_register_read(rt2x00dev, MAC_CSR12, ®);
1181 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1182 if (current_state == !put_to_sleep)
1187 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1188 "current device state %d.\n", !put_to_sleep, current_state);
1193 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1194 enum dev_state state)
1199 case STATE_RADIO_ON:
1200 retval = rt73usb_enable_radio(rt2x00dev);
1202 case STATE_RADIO_OFF:
1203 rt73usb_disable_radio(rt2x00dev);
1205 case STATE_RADIO_RX_ON:
1206 case STATE_RADIO_RX_ON_LINK:
1207 rt73usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1209 case STATE_RADIO_RX_OFF:
1210 case STATE_RADIO_RX_OFF_LINK:
1211 rt73usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
1213 case STATE_DEEP_SLEEP:
1217 retval = rt73usb_set_state(rt2x00dev, state);
1228 * TX descriptor initialization
1230 static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1231 struct sk_buff *skb,
1232 struct txentry_desc *txdesc,
1233 struct ieee80211_tx_control *control)
1235 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1236 __le32 *txd = skbdesc->desc;
1240 * Start writing the descriptor words.
1242 rt2x00_desc_read(txd, 1, &word);
1243 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1244 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1245 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1246 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1247 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1248 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1249 rt2x00_desc_write(txd, 1, word);
1251 rt2x00_desc_read(txd, 2, &word);
1252 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1253 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1254 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1255 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1256 rt2x00_desc_write(txd, 2, word);
1258 rt2x00_desc_read(txd, 5, &word);
1259 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1260 TXPOWER_TO_DEV(rt2x00dev->tx_power));
1261 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1262 rt2x00_desc_write(txd, 5, word);
1264 rt2x00_desc_read(txd, 0, &word);
1265 rt2x00_set_field32(&word, TXD_W0_BURST,
1266 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1267 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1268 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1269 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1270 rt2x00_set_field32(&word, TXD_W0_ACK,
1271 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1272 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1273 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1274 rt2x00_set_field32(&word, TXD_W0_OFDM,
1275 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1276 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1277 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1279 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1280 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1281 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1282 rt2x00_set_field32(&word, TXD_W0_BURST2,
1283 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1284 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1285 rt2x00_desc_write(txd, 0, word);
1288 static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
1289 struct sk_buff *skb)
1294 * The length _must_ be a multiple of 4,
1295 * but it must _not_ be a multiple of the USB packet size.
1297 length = roundup(skb->len, 4);
1298 length += (4 * !(length % rt2x00dev->usb_maxpacket));
1304 * TX data initialization
1306 static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1307 const unsigned int queue)
1311 if (queue != RT2X00_BCN_QUEUE_BEACON)
1315 * For Wi-Fi faily generated beacons between participating stations.
1316 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1318 rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1320 rt73usb_register_read(rt2x00dev, TXRX_CSR9, ®);
1321 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1322 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
1323 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1);
1324 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1);
1325 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1330 * RX control handlers
1332 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1338 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1353 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1354 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1355 if (lna == 3 || lna == 2)
1364 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1365 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1367 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1370 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1371 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1374 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1377 static void rt73usb_fill_rxdone(struct queue_entry *entry,
1378 struct rxdone_entry_desc *rxdesc)
1380 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1381 __le32 *rxd = (__le32 *)entry->skb->data;
1382 unsigned int offset = entry->queue->desc_size + 2;
1387 * Copy descriptor to the available headroom inside the skbuffer.
1389 skb_push(entry->skb, offset);
1390 memcpy(entry->skb->data, rxd, entry->queue->desc_size);
1391 rxd = (__le32 *)entry->skb->data;
1394 * The descriptor is now aligned to 4 bytes and thus it is
1395 * now safe to read it on all architectures.
1397 rt2x00_desc_read(rxd, 0, &word0);
1398 rt2x00_desc_read(rxd, 1, &word1);
1401 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1402 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1405 * Obtain the status about this packet.
1407 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1408 rxdesc->rssi = rt73usb_agc_to_rssi(entry->queue->rt2x00dev, word1);
1409 rxdesc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1410 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1411 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
1414 * Adjust the skb memory window to the frame boundaries.
1416 skb_pull(entry->skb, offset + entry->queue->desc_size);
1417 skb_trim(entry->skb, rxdesc->size);
1420 * Set descriptor and data pointer.
1422 skbdesc->data = entry->skb->data;
1423 skbdesc->data_len = rxdesc->size;
1424 skbdesc->desc = rxd;
1425 skbdesc->desc_len = entry->queue->desc_size;
1429 * Device probe functions.
1431 static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1437 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1440 * Start validation of the data that has been read.
1442 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1443 if (!is_valid_ether_addr(mac)) {
1444 DECLARE_MAC_BUF(macbuf);
1446 random_ether_addr(mac);
1447 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1450 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1451 if (word == 0xffff) {
1452 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1453 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1455 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1457 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1458 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1459 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1460 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1461 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1462 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1465 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1466 if (word == 0xffff) {
1467 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1468 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1469 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1472 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1473 if (word == 0xffff) {
1474 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1475 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1476 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1477 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1478 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1479 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1480 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1481 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1482 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1484 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1485 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1488 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1489 if (word == 0xffff) {
1490 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1491 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1492 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1493 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1496 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1497 if (word == 0xffff) {
1498 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1499 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1500 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1501 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1503 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1504 if (value < -10 || value > 10)
1505 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1506 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1507 if (value < -10 || value > 10)
1508 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1509 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1512 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1513 if (word == 0xffff) {
1514 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1515 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1516 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1517 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1519 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1520 if (value < -10 || value > 10)
1521 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1522 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1523 if (value < -10 || value > 10)
1524 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1525 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1531 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1538 * Read EEPROM word for configuration.
1540 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1543 * Identify RF chipset.
1545 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1546 rt73usb_register_read(rt2x00dev, MAC_CSR0, ®);
1547 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1549 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
1550 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1554 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1555 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1556 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1557 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1558 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1563 * Identify default antenna configuration.
1565 rt2x00dev->default_ant.tx =
1566 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1567 rt2x00dev->default_ant.rx =
1568 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1571 * Read the Frame type.
1573 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1574 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1577 * Read frequency offset.
1579 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1580 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1583 * Read external LNA informations.
1585 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1587 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1588 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1589 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1593 * Store led settings, for correct led behaviour.
1595 #ifdef CONFIG_RT73USB_LEDS
1596 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1599 case LED_MODE_TXRX_ACTIVITY:
1601 case LED_MODE_ALPHA:
1602 case LED_MODE_DEFAULT:
1603 rt2x00dev->led_flags =
1604 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC;
1606 case LED_MODE_SIGNAL_STRENGTH:
1607 rt2x00dev->led_flags =
1608 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC |
1609 LED_SUPPORT_QUALITY;
1613 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1614 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
1615 rt2x00_get_field16(eeprom,
1616 EEPROM_LED_POLARITY_GPIO_0));
1617 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
1618 rt2x00_get_field16(eeprom,
1619 EEPROM_LED_POLARITY_GPIO_1));
1620 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
1621 rt2x00_get_field16(eeprom,
1622 EEPROM_LED_POLARITY_GPIO_2));
1623 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
1624 rt2x00_get_field16(eeprom,
1625 EEPROM_LED_POLARITY_GPIO_3));
1626 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
1627 rt2x00_get_field16(eeprom,
1628 EEPROM_LED_POLARITY_GPIO_4));
1629 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
1630 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1631 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
1632 rt2x00_get_field16(eeprom,
1633 EEPROM_LED_POLARITY_RDY_G));
1634 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
1635 rt2x00_get_field16(eeprom,
1636 EEPROM_LED_POLARITY_RDY_A));
1637 #endif /* CONFIG_RT73USB_LEDS */
1643 * RF value list for RF2528
1646 static const struct rf_channel rf_vals_bg_2528[] = {
1647 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1648 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1649 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1650 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1651 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1652 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1653 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1654 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1655 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1656 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1657 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1658 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1659 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1660 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1664 * RF value list for RF5226
1665 * Supports: 2.4 GHz & 5.2 GHz
1667 static const struct rf_channel rf_vals_5226[] = {
1668 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1669 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1670 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1671 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1672 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1673 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1674 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1675 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1676 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1677 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1678 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1679 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1680 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1681 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1683 /* 802.11 UNI / HyperLan 2 */
1684 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1685 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1686 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1687 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1688 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1689 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1690 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1691 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1693 /* 802.11 HyperLan 2 */
1694 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1695 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1696 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1697 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1698 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1699 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1700 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1701 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1702 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1703 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1706 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1707 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1708 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1709 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1710 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1711 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1713 /* MMAC(Japan)J52 ch 34,38,42,46 */
1714 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1715 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1716 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1717 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1721 * RF value list for RF5225 & RF2527
1722 * Supports: 2.4 GHz & 5.2 GHz
1724 static const struct rf_channel rf_vals_5225_2527[] = {
1725 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1726 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1727 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1728 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1729 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1730 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
1731 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
1732 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
1733 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
1734 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
1735 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
1736 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
1737 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
1738 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
1740 /* 802.11 UNI / HyperLan 2 */
1741 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
1742 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
1743 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
1744 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
1745 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
1746 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
1747 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
1748 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
1750 /* 802.11 HyperLan 2 */
1751 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
1752 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
1753 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
1754 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
1755 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
1756 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
1757 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
1758 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
1759 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
1760 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
1763 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
1764 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
1765 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
1766 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
1767 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
1768 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
1770 /* MMAC(Japan)J52 ch 34,38,42,46 */
1771 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
1772 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
1773 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
1774 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
1778 static void rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1780 struct hw_mode_spec *spec = &rt2x00dev->spec;
1785 * Initialize all hw fields.
1787 rt2x00dev->hw->flags =
1788 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
1789 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1790 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
1791 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1792 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1793 rt2x00dev->hw->queues = 4;
1795 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_usb(rt2x00dev)->dev);
1796 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1797 rt2x00_eeprom_addr(rt2x00dev,
1798 EEPROM_MAC_ADDR_0));
1801 * Convert tx_power array in eeprom.
1803 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
1804 for (i = 0; i < 14; i++)
1805 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1808 * Initialize hw_mode information.
1810 spec->supported_bands = SUPPORT_BAND_2GHZ;
1811 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1812 spec->tx_power_a = NULL;
1813 spec->tx_power_bg = txpower;
1814 spec->tx_power_default = DEFAULT_TXPOWER;
1816 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
1817 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
1818 spec->channels = rf_vals_bg_2528;
1819 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1820 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1821 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
1822 spec->channels = rf_vals_5226;
1823 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1824 spec->num_channels = 14;
1825 spec->channels = rf_vals_5225_2527;
1826 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
1827 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1828 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
1829 spec->channels = rf_vals_5225_2527;
1832 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1833 rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1834 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
1835 for (i = 0; i < 14; i++)
1836 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1838 spec->tx_power_a = txpower;
1842 static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
1847 * Allocate eeprom data.
1849 retval = rt73usb_validate_eeprom(rt2x00dev);
1853 retval = rt73usb_init_eeprom(rt2x00dev);
1858 * Initialize hw specifications.
1860 rt73usb_probe_hw_mode(rt2x00dev);
1863 * This device requires firmware.
1865 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1868 * Set the rssi offset.
1870 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1876 * IEEE80211 stack callback functions.
1878 static void rt73usb_configure_filter(struct ieee80211_hw *hw,
1879 unsigned int changed_flags,
1880 unsigned int *total_flags,
1882 struct dev_addr_list *mc_list)
1884 struct rt2x00_dev *rt2x00dev = hw->priv;
1888 * Mask off any flags we are going to ignore from
1889 * the total_flags field.
1900 * Apply some rules to the filters:
1901 * - Some filters imply different filters to be set.
1902 * - Some things we can't filter out at all.
1905 *total_flags |= FIF_ALLMULTI;
1906 if (*total_flags & FIF_OTHER_BSS ||
1907 *total_flags & FIF_PROMISC_IN_BSS)
1908 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1911 * Check if there is any work left for us.
1913 if (rt2x00dev->packet_filter == *total_flags)
1915 rt2x00dev->packet_filter = *total_flags;
1918 * When in atomic context, reschedule and let rt2x00lib
1919 * call this function again.
1922 queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->filter_work);
1927 * Start configuration steps.
1928 * Note that the version error will always be dropped
1929 * and broadcast frames will always be accepted since
1930 * there is no filter for it at this time.
1932 rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
1933 rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC,
1934 !(*total_flags & FIF_FCSFAIL));
1935 rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL,
1936 !(*total_flags & FIF_PLCPFAIL));
1937 rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL,
1938 !(*total_flags & FIF_CONTROL));
1939 rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME,
1940 !(*total_flags & FIF_PROMISC_IN_BSS));
1941 rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS,
1942 !(*total_flags & FIF_PROMISC_IN_BSS));
1943 rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1);
1944 rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST,
1945 !(*total_flags & FIF_ALLMULTI));
1946 rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0);
1947 rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS,
1948 !(*total_flags & FIF_CONTROL));
1949 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1952 static int rt73usb_set_retry_limit(struct ieee80211_hw *hw,
1953 u32 short_retry, u32 long_retry)
1955 struct rt2x00_dev *rt2x00dev = hw->priv;
1958 rt73usb_register_read(rt2x00dev, TXRX_CSR4, ®);
1959 rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
1960 rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
1961 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
1968 * Mac80211 demands get_tsf must be atomic.
1969 * This is not possible for rt73usb since all register access
1970 * functions require sleeping. Untill mac80211 no longer needs
1971 * get_tsf to be atomic, this function should be disabled.
1973 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
1975 struct rt2x00_dev *rt2x00dev = hw->priv;
1979 rt73usb_register_read(rt2x00dev, TXRX_CSR13, ®);
1980 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
1981 rt73usb_register_read(rt2x00dev, TXRX_CSR12, ®);
1982 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
1987 #define rt73usb_get_tsf NULL
1990 static int rt73usb_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1991 struct ieee80211_tx_control *control)
1993 struct rt2x00_dev *rt2x00dev = hw->priv;
1994 struct rt2x00_intf *intf = vif_to_intf(control->vif);
1995 struct skb_frame_desc *skbdesc;
1996 unsigned int beacon_base;
1997 unsigned int timeout;
2000 if (unlikely(!intf->beacon))
2004 * Add the descriptor in front of the skb.
2006 skb_push(skb, intf->beacon->queue->desc_size);
2007 memset(skb->data, 0, intf->beacon->queue->desc_size);
2010 * Fill in skb descriptor
2012 skbdesc = get_skb_frame_desc(skb);
2013 memset(skbdesc, 0, sizeof(*skbdesc));
2014 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
2015 skbdesc->data = skb->data + intf->beacon->queue->desc_size;
2016 skbdesc->data_len = skb->len - intf->beacon->queue->desc_size;
2017 skbdesc->desc = skb->data;
2018 skbdesc->desc_len = intf->beacon->queue->desc_size;
2019 skbdesc->entry = intf->beacon;
2022 * Disable beaconing while we are reloading the beacon data,
2023 * otherwise we might be sending out invalid data.
2025 rt73usb_register_read(rt2x00dev, TXRX_CSR9, ®);
2026 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0);
2027 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0);
2028 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
2029 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
2032 * mac80211 doesn't provide the control->queue variable
2033 * for beacons. Set our own queue identification so
2034 * it can be used during descriptor initialization.
2036 control->queue = RT2X00_BCN_QUEUE_BEACON;
2037 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
2040 * Write entire beacon with descriptor to register,
2041 * and kick the beacon generator.
2043 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
2044 timeout = REGISTER_TIMEOUT * (skb->len / sizeof(u32));
2045 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
2046 USB_VENDOR_REQUEST_OUT, beacon_base, 0,
2047 skb->data, skb->len, timeout);
2048 rt73usb_kick_tx_queue(rt2x00dev, control->queue);
2053 static const struct ieee80211_ops rt73usb_mac80211_ops = {
2055 .start = rt2x00mac_start,
2056 .stop = rt2x00mac_stop,
2057 .add_interface = rt2x00mac_add_interface,
2058 .remove_interface = rt2x00mac_remove_interface,
2059 .config = rt2x00mac_config,
2060 .config_interface = rt2x00mac_config_interface,
2061 .configure_filter = rt73usb_configure_filter,
2062 .get_stats = rt2x00mac_get_stats,
2063 .set_retry_limit = rt73usb_set_retry_limit,
2064 .bss_info_changed = rt2x00mac_bss_info_changed,
2065 .conf_tx = rt2x00mac_conf_tx,
2066 .get_tx_stats = rt2x00mac_get_tx_stats,
2067 .get_tsf = rt73usb_get_tsf,
2068 .beacon_update = rt73usb_beacon_update,
2071 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2072 .probe_hw = rt73usb_probe_hw,
2073 .get_firmware_name = rt73usb_get_firmware_name,
2074 .get_firmware_crc = rt73usb_get_firmware_crc,
2075 .load_firmware = rt73usb_load_firmware,
2076 .initialize = rt2x00usb_initialize,
2077 .uninitialize = rt2x00usb_uninitialize,
2078 .init_rxentry = rt2x00usb_init_rxentry,
2079 .init_txentry = rt2x00usb_init_txentry,
2080 .set_device_state = rt73usb_set_device_state,
2081 .link_stats = rt73usb_link_stats,
2082 .reset_tuner = rt73usb_reset_tuner,
2083 .link_tuner = rt73usb_link_tuner,
2084 .led_brightness = rt73usb_led_brightness,
2085 .write_tx_desc = rt73usb_write_tx_desc,
2086 .write_tx_data = rt2x00usb_write_tx_data,
2087 .get_tx_data_len = rt73usb_get_tx_data_len,
2088 .kick_tx_queue = rt73usb_kick_tx_queue,
2089 .fill_rxdone = rt73usb_fill_rxdone,
2090 .config_intf = rt73usb_config_intf,
2091 .config_erp = rt73usb_config_erp,
2092 .config = rt73usb_config,
2095 static const struct data_queue_desc rt73usb_queue_rx = {
2096 .entry_num = RX_ENTRIES,
2097 .data_size = DATA_FRAME_SIZE,
2098 .desc_size = RXD_DESC_SIZE,
2099 .priv_size = sizeof(struct queue_entry_priv_usb_rx),
2102 static const struct data_queue_desc rt73usb_queue_tx = {
2103 .entry_num = TX_ENTRIES,
2104 .data_size = DATA_FRAME_SIZE,
2105 .desc_size = TXD_DESC_SIZE,
2106 .priv_size = sizeof(struct queue_entry_priv_usb_tx),
2109 static const struct data_queue_desc rt73usb_queue_bcn = {
2110 .entry_num = 4 * BEACON_ENTRIES,
2111 .data_size = MGMT_FRAME_SIZE,
2112 .desc_size = TXINFO_SIZE,
2113 .priv_size = sizeof(struct queue_entry_priv_usb_tx),
2116 static const struct rt2x00_ops rt73usb_ops = {
2117 .name = KBUILD_MODNAME,
2120 .eeprom_size = EEPROM_SIZE,
2122 .rx = &rt73usb_queue_rx,
2123 .tx = &rt73usb_queue_tx,
2124 .bcn = &rt73usb_queue_bcn,
2125 .lib = &rt73usb_rt2x00_ops,
2126 .hw = &rt73usb_mac80211_ops,
2127 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2128 .debugfs = &rt73usb_rt2x00debug,
2129 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2133 * rt73usb module information.
2135 static struct usb_device_id rt73usb_device_table[] = {
2137 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2139 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2141 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2142 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2144 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2145 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2146 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
2147 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
2149 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2151 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2153 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2154 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2156 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2158 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2159 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2161 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2163 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2164 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2166 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2168 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2169 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2171 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2172 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2174 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2175 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2176 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2177 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2179 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2180 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2182 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2183 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2184 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2186 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2188 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2189 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2191 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2193 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2194 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2198 MODULE_AUTHOR(DRV_PROJECT);
2199 MODULE_VERSION(DRV_VERSION);
2200 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2201 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2202 MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2203 MODULE_FIRMWARE(FIRMWARE_RT2571);
2204 MODULE_LICENSE("GPL");
2206 static struct usb_driver rt73usb_driver = {
2207 .name = KBUILD_MODNAME,
2208 .id_table = rt73usb_device_table,
2209 .probe = rt2x00usb_probe,
2210 .disconnect = rt2x00usb_disconnect,
2211 .suspend = rt2x00usb_suspend,
2212 .resume = rt2x00usb_resume,
2215 static int __init rt73usb_init(void)
2217 return usb_register(&rt73usb_driver);
2220 static void __exit rt73usb_exit(void)
2222 usb_deregister(&rt73usb_driver);
2225 module_init(rt73usb_init);
2226 module_exit(rt73usb_exit);