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   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt61pci
  23         Abstract: rt61pci device specific routines.
  24         Supported chipsets: RT2561, RT2561s, RT2661.
  25  */
  26
  27 #include <linux/crc-itu-t.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/pci.h>
  34 #include <linux/eeprom_93cx6.h>
  35
  36 #include "rt2x00.h"
  37 #include "rt2x00pci.h"
  38 #include "rt61pci.h"
  39
  40 /*
  41  * Register access.
  42  * BBP and RF register require indirect register access,
  43  * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
  44  * These indirect registers work with busy bits,
  45  * and we will try maximal REGISTER_BUSY_COUNT times to access
  46  * the register while taking a REGISTER_BUSY_DELAY us delay
  47  * between each attampt. When the busy bit is still set at that time,
  48  * the access attempt is considered to have failed,
  49  * and we will print an error.
  50  */
  51 static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
  52 {
  53         u32 reg;
  54         unsigned int i;
  55
  56         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  57                 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
  58                 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
  59                         break;
  60                 udelay(REGISTER_BUSY_DELAY);
  61         }
  62
  63         return reg;
  64 }
  65
  66 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  67                               const unsigned int word, const u8 value)
  68 {
  69         u32 reg;
  70
  71         /*
  72          * Wait until the BBP becomes ready.
  73          */
  74         reg = rt61pci_bbp_check(rt2x00dev);
  75         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
  76                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
  77                 return;
  78         }
  79
  80         /*
  81          * Write the data into the BBP.
  82          */
  83         reg = 0;
  84         rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
  85         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  86         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  87         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
  88
  89         rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
  90 }
  91
  92 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  93                              const unsigned int word, u8 *value)
  94 {
  95         u32 reg;
  96
  97         /*
  98          * Wait until the BBP becomes ready.
  99          */
 100         reg = rt61pci_bbp_check(rt2x00dev);
 101         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
 102                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
 103                 return;
 104         }
 105
 106         /*
 107          * Write the request into the BBP.
 108          */
 109         reg = 0;
 110         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 111         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 112         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
 113
 114         rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
 115
 116         /*
 117          * Wait until the BBP becomes ready.
 118          */
 119         reg = rt61pci_bbp_check(rt2x00dev);
 120         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
 121                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
 122                 *value = 0xff;
 123                 return;
 124         }
 125
 126         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
 127 }
 128
 129 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
 130                              const unsigned int word, const u32 value)
 131 {
 132         u32 reg;
 133         unsigned int i;
 134
 135         if (!word)
 136                 return;
 137
 138         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 139                 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
 140                 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
 141                         goto rf_write;
 142                 udelay(REGISTER_BUSY_DELAY);
 143         }
 144
 145         ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
 146         return;
 147
 148 rf_write:
 149         reg = 0;
 150         rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
 151         rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
 152         rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
 153         rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
 154
 155         rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
 156         rt2x00_rf_write(rt2x00dev, word, value);
 157 }
 158
 159 #ifdef CONFIG_RT61PCI_LEDS
 160 /*
 161  * This function is only called from rt61pci_led_brightness()
 162  * make gcc happy by placing this function inside the
 163  * same ifdef statement as the caller.
 164  */
 165 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
 166                                 const u8 command, const u8 token,
 167                                 const u8 arg0, const u8 arg1)
 168 {
 169         u32 reg;
 170
 171         rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
 172
 173         if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
 174                 ERROR(rt2x00dev, "mcu request error. "
 175                       "Request 0x%02x failed for token 0x%02x.\n",
 176                       command, token);
 177                 return;
 178         }
 179
 180         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 181         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 182         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 183         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 184         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
 185
 186         rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
 187         rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 188         rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
 189         rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
 190 }
 191 #endif /* CONFIG_RT61PCI_LEDS */
 192
 193 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 194 {
 195         struct rt2x00_dev *rt2x00dev = eeprom->data;
 196         u32 reg;
 197
 198         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
 199
 200         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 201         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 202         eeprom->reg_data_clock =
 203             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 204         eeprom->reg_chip_select =
 205             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 206 }
 207
 208 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 209 {
 210         struct rt2x00_dev *rt2x00dev = eeprom->data;
 211         u32 reg = 0;
 212
 213         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 214         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 215         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 216                            !!eeprom->reg_data_clock);
 217         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 218                            !!eeprom->reg_chip_select);
 219
 220         rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
 221 }
 222
 223 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 224 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 225
 226 static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev,
 227                              const unsigned int word, u32 *data)
 228 {
 229         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 230 }
 231
 232 static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev,
 233                               const unsigned int word, u32 data)
 234 {
 235         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 236 }
 237
 238 static const struct rt2x00debug rt61pci_rt2x00debug = {
 239         .owner  = THIS_MODULE,
 240         .csr    = {
 241                 .read           = rt61pci_read_csr,
 242                 .write          = rt61pci_write_csr,
 243                 .word_size      = sizeof(u32),
 244                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 245         },
 246         .eeprom = {
 247                 .read           = rt2x00_eeprom_read,
 248                 .write          = rt2x00_eeprom_write,
 249                 .word_size      = sizeof(u16),
 250                 .word_count     = EEPROM_SIZE / sizeof(u16),
 251         },
 252         .bbp    = {
 253                 .read           = rt61pci_bbp_read,
 254                 .write          = rt61pci_bbp_write,
 255                 .word_size      = sizeof(u8),
 256                 .word_count     = BBP_SIZE / sizeof(u8),
 257         },
 258         .rf     = {
 259                 .read           = rt2x00_rf_read,
 260                 .write          = rt61pci_rf_write,
 261                 .word_size      = sizeof(u32),
 262                 .word_count     = RF_SIZE / sizeof(u32),
 263         },
 264 };
 265 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 266
 267 #ifdef CONFIG_RT61PCI_RFKILL
 268 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 269 {
 270         u32 reg;
 271
 272         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 273         return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
 274 }
 275 #else
 276 #define rt61pci_rfkill_poll     NULL
 277 #endif /* CONFIG_RT61PCI_RFKILL */
 278
 279 #ifdef CONFIG_RT61PCI_LEDS
 280 static void rt61pci_brightness_set(struct led_classdev *led_cdev,
 281                                    enum led_brightness brightness)
 282 {
 283         struct rt2x00_led *led =
 284             container_of(led_cdev, struct rt2x00_led, led_dev);
 285         unsigned int enabled = brightness != LED_OFF;
 286         unsigned int a_mode =
 287             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 288         unsigned int bg_mode =
 289             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 290
 291         if (led->type == LED_TYPE_RADIO) {
 292                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 293                                    MCU_LEDCS_RADIO_STATUS, enabled);
 294
 295                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 296                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 297                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 298         } else if (led->type == LED_TYPE_ASSOC) {
 299                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 300                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
 301                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 302                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
 303
 304                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 305                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 306                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 307         } else if (led->type == LED_TYPE_QUALITY) {
 308                 /*
 309                  * The brightness is divided into 6 levels (0 - 5),
 310                  * this means we need to convert the brightness
 311                  * argument into the matching level within that range.
 312                  */
 313                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 314                                     brightness / (LED_FULL / 6), 0);
 315         }
 316 }
 317
 318 static int rt61pci_blink_set(struct led_classdev *led_cdev,
 319                              unsigned long *delay_on,
 320                              unsigned long *delay_off)
 321 {
 322         struct rt2x00_led *led =
 323             container_of(led_cdev, struct rt2x00_led, led_dev);
 324         u32 reg;
 325
 326         rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
 327         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
 328         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
 329         rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
 330
 331         return 0;
 332 }
 333
 334 static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
 335                              struct rt2x00_led *led,
 336                              enum led_type type)
 337 {
 338         led->rt2x00dev = rt2x00dev;
 339         led->type = type;
 340         led->led_dev.brightness_set = rt61pci_brightness_set;
 341         led->led_dev.blink_set = rt61pci_blink_set;
 342         led->flags = LED_INITIALIZED;
 343 }
 344 #endif /* CONFIG_RT61PCI_LEDS */
 345
 346 /*
 347  * Configuration handlers.
 348  */
 349 static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
 350                                      struct rt2x00lib_crypto *crypto,
 351                                      struct ieee80211_key_conf *key)
 352 {
 353         struct hw_key_entry key_entry;
 354         struct rt2x00_field32 field;
 355         u32 mask;
 356         u32 reg;
 357
 358         if (crypto->cmd == SET_KEY) {
 359                 /*
 360                  * rt2x00lib can't determine the correct free
 361                  * key_idx for shared keys. We have 1 register
 362                  * with key valid bits. The goal is simple, read
 363                  * the register, if that is full we have no slots
 364                  * left.
 365                  * Note that each BSS is allowed to have up to 4
 366                  * shared keys, so put a mask over the allowed
 367                  * entries.
 368                  */
 369                 mask = (0xf << crypto->bssidx);
 370
 371                 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
 372                 reg &= mask;
 373
 374                 if (reg && reg == mask)
 375                         return -ENOSPC;
 376
 377                 key->hw_key_idx += reg ? (ffz(reg) - 1) : 0;
 378
 379                 /*
 380                  * Upload key to hardware
 381                  */
 382                 memcpy(key_entry.key, crypto->key,
 383                        sizeof(key_entry.key));
 384                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 385                        sizeof(key_entry.tx_mic));
 386                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 387                        sizeof(key_entry.rx_mic));
 388
 389                 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
 390                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 391                                               &key_entry, sizeof(key_entry));
 392
 393                 /*
 394                  * The cipher types are stored over 2 registers.
 395                  * bssidx 0 and 1 keys are stored in SEC_CSR1 and
 396                  * bssidx 1 and 2 keys are stored in SEC_CSR5.
 397                  * Using the correct defines correctly will cause overhead,
 398                  * so just calculate the correct offset.
 399                  */
 400                 if (key->hw_key_idx < 8) {
 401                         field.bit_offset = (3 * key->hw_key_idx);
 402                         field.bit_mask = 0x7 << field.bit_offset;
 403
 404                         rt2x00pci_register_read(rt2x00dev, SEC_CSR1, &reg);
 405                         rt2x00_set_field32(&reg, field, crypto->cipher);
 406                         rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
 407                 } else {
 408                         field.bit_offset = (3 * (key->hw_key_idx - 8));
 409                         field.bit_mask = 0x7 << field.bit_offset;
 410
 411                         rt2x00pci_register_read(rt2x00dev, SEC_CSR5, &reg);
 412                         rt2x00_set_field32(&reg, field, crypto->cipher);
 413                         rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
 414                 }
 415
 416                 /*
 417                  * The driver does not support the IV/EIV generation
 418                  * in hardware. However it doesn't support the IV/EIV
 419                  * inside the ieee80211 frame either, but requires it
 420                  * to be provided seperately for the descriptor.
 421                  * rt2x00lib will cut the IV/EIV data out of all frames
 422                  * given to us by mac80211, but we must tell mac80211
 423                  * to generate the IV/EIV data.
 424                  */
 425                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 426         }
 427
 428         /*
 429          * SEC_CSR0 contains only single-bit fields to indicate
 430          * a particular key is valid. Because using the FIELD32()
 431          * defines directly will cause a lot of overhead we use
 432          * a calculation to determine the correct bit directly.
 433          */
 434         mask = 1 << key->hw_key_idx;
 435
 436         rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
 437         if (crypto->cmd == SET_KEY)
 438                 reg |= mask;
 439         else if (crypto->cmd == DISABLE_KEY)
 440                 reg &= ~mask;
 441         rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
 442
 443         return 0;
 444 }
 445
 446 static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 447                                        struct rt2x00lib_crypto *crypto,
 448                                        struct ieee80211_key_conf *key)
 449 {
 450         struct hw_pairwise_ta_entry addr_entry;
 451         struct hw_key_entry key_entry;
 452         u32 mask;
 453         u32 reg;
 454
 455         if (crypto->cmd == SET_KEY) {
 456                 /*
 457                  * rt2x00lib can't determine the correct free
 458                  * key_idx for pairwise keys. We have 2 registers
 459                  * with key valid bits. The goal is simple, read
 460                  * the first register, if that is full move to
 461                  * the next register.
 462                  * When both registers are full, we drop the key,
 463                  * otherwise we use the first invalid entry.
 464                  */
 465                 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
 466                 if (reg && reg == ~0) {
 467                         key->hw_key_idx = 32;
 468                         rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
 469                         if (reg && reg == ~0)
 470                                 return -ENOSPC;
 471                 }
 472
 473                 key->hw_key_idx += reg ? (ffz(reg) - 1) : 0;
 474
 475                 /*
 476                  * Upload key to hardware
 477                  */
 478                 memcpy(key_entry.key, crypto->key,
 479                        sizeof(key_entry.key));
 480                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 481                        sizeof(key_entry.tx_mic));
 482                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 483                        sizeof(key_entry.rx_mic));
 484
 485                 memset(&addr_entry, 0, sizeof(addr_entry));
 486                 memcpy(&addr_entry, crypto->address, ETH_ALEN);
 487                 addr_entry.cipher = crypto->cipher;
 488
 489                 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 490                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 491                                               &key_entry, sizeof(key_entry));
 492
 493                 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
 494                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 495                                               &addr_entry, sizeof(addr_entry));
 496
 497                 /*
 498                  * Enable pairwise lookup table for given BSS idx,
 499                  * without this received frames will not be decrypted
 500                  * by the hardware.
 501                  */
 502                 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, &reg);
 503                 reg |= (1 << crypto->bssidx);
 504                 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
 505
 506                 /*
 507                  * The driver does not support the IV/EIV generation
 508                  * in hardware. However it doesn't support the IV/EIV
 509                  * inside the ieee80211 frame either, but requires it
 510                  * to be provided seperately for the descriptor.
 511                  * rt2x00lib will cut the IV/EIV data out of all frames
 512                  * given to us by mac80211, but we must tell mac80211
 513                  * to generate the IV/EIV data.
 514                  */
 515                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 516         }
 517
 518         /*
 519          * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
 520          * a particular key is valid. Because using the FIELD32()
 521          * defines directly will cause a lot of overhead we use
 522          * a calculation to determine the correct bit directly.
 523          */
 524         if (key->hw_key_idx < 32) {
 525                 mask = 1 << key->hw_key_idx;
 526
 527                 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
 528                 if (crypto->cmd == SET_KEY)
 529                         reg |= mask;
 530                 else if (crypto->cmd == DISABLE_KEY)
 531                         reg &= ~mask;
 532                 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
 533         } else {
 534                 mask = 1 << (key->hw_key_idx - 32);
 535
 536                 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
 537                 if (crypto->cmd == SET_KEY)
 538                         reg |= mask;
 539                 else if (crypto->cmd == DISABLE_KEY)
 540                         reg &= ~mask;
 541                 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
 542         }
 543
 544         return 0;
 545 }
 546
 547 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
 548                                   const unsigned int filter_flags)
 549 {
 550         u32 reg;
 551
 552         /*
 553          * Start configuration steps.
 554          * Note that the version error will always be dropped
 555          * and broadcast frames will always be accepted since
 556          * there is no filter for it at this time.
 557          */
 558         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 559         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
 560                            !(filter_flags & FIF_FCSFAIL));
 561         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
 562                            !(filter_flags & FIF_PLCPFAIL));
 563         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
 564                            !(filter_flags & FIF_CONTROL));
 565         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
 566                            !(filter_flags & FIF_PROMISC_IN_BSS));
 567         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
 568                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 569                            !rt2x00dev->intf_ap_count);
 570         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
 571         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
 572                            !(filter_flags & FIF_ALLMULTI));
 573         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
 574         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
 575                            !(filter_flags & FIF_CONTROL));
 576         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 577 }
 578
 579 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
 580                                 struct rt2x00_intf *intf,
 581                                 struct rt2x00intf_conf *conf,
 582                                 const unsigned int flags)
 583 {
 584         unsigned int beacon_base;
 585         u32 reg;
 586
 587         if (flags & CONFIG_UPDATE_TYPE) {
 588                 /*
 589                  * Clear current synchronisation setup.
 590                  * For the Beacon base registers we only need to clear
 591                  * the first byte since that byte contains the VALID and OWNER
 592                  * bits which (when set to 0) will invalidate the entire beacon.
 593                  */
 594                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 595                 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
 596
 597                 /*
 598                  * Enable synchronisation.
 599                  */
 600                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
 601                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
 602                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
 603                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
 604                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
 605         }
 606
 607         if (flags & CONFIG_UPDATE_MAC) {
 608                 reg = le32_to_cpu(conf->mac[1]);
 609                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
 610                 conf->mac[1] = cpu_to_le32(reg);
 611
 612                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
 613                                               conf->mac, sizeof(conf->mac));
 614         }
 615
 616         if (flags & CONFIG_UPDATE_BSSID) {
 617                 reg = le32_to_cpu(conf->bssid[1]);
 618                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
 619                 conf->bssid[1] = cpu_to_le32(reg);
 620
 621                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
 622                                               conf->bssid, sizeof(conf->bssid));
 623         }
 624 }
 625
 626 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
 627                                struct rt2x00lib_erp *erp)
 628 {
 629         u32 reg;
 630
 631         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 632         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
 633         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 634
 635         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 636         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
 637                            !!erp->short_preamble);
 638         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 639 }
 640
 641 static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 642                                    const int basic_rate_mask)
 643 {
 644         rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
 645 }
 646
 647 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
 648                                    struct rf_channel *rf, const int txpower)
 649 {
 650         u8 r3;
 651         u8 r94;
 652         u8 smart;
 653
 654         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 655         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 656
 657         smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 658                   rt2x00_rf(&rt2x00dev->chip, RF2527));
 659
 660         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 661         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
 662         rt61pci_bbp_write(rt2x00dev, 3, r3);
 663
 664         r94 = 6;
 665         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
 666                 r94 += txpower - MAX_TXPOWER;
 667         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
 668                 r94 += txpower;
 669         rt61pci_bbp_write(rt2x00dev, 94, r94);
 670
 671         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 672         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 673         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 674         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 675
 676         udelay(200);
 677
 678         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 679         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 680         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 681         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 682
 683         udelay(200);
 684
 685         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 686         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 687         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 688         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 689
 690         msleep(1);
 691 }
 692
 693 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 694                                    const int txpower)
 695 {
 696         struct rf_channel rf;
 697
 698         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
 699         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
 700         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
 701         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
 702
 703         rt61pci_config_channel(rt2x00dev, &rf, txpower);
 704 }
 705
 706 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
 707                                       struct antenna_setup *ant)
 708 {
 709         u8 r3;
 710         u8 r4;
 711         u8 r77;
 712
 713         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 714         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 715         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 716
 717         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
 718                           rt2x00_rf(&rt2x00dev->chip, RF5325));
 719
 720         /*
 721          * Configure the RX antenna.
 722          */
 723         switch (ant->rx) {
 724         case ANTENNA_HW_DIVERSITY:
 725                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 726                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 727                                   (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
 728                 break;
 729         case ANTENNA_A:
 730                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 731                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 732                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 733                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 734                 else
 735                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 736                 break;
 737         case ANTENNA_B:
 738         default:
 739                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 740                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 741                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 742                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 743                 else
 744                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 745                 break;
 746         }
 747
 748         rt61pci_bbp_write(rt2x00dev, 77, r77);
 749         rt61pci_bbp_write(rt2x00dev, 3, r3);
 750         rt61pci_bbp_write(rt2x00dev, 4, r4);
 751 }
 752
 753 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
 754                                       struct antenna_setup *ant)
 755 {
 756         u8 r3;
 757         u8 r4;
 758         u8 r77;
 759
 760         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 761         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 762         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 763
 764         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
 765                           rt2x00_rf(&rt2x00dev->chip, RF2529));
 766         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 767                           !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
 768
 769         /*
 770          * Configure the RX antenna.
 771          */
 772         switch (ant->rx) {
 773         case ANTENNA_HW_DIVERSITY:
 774                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 775                 break;
 776         case ANTENNA_A:
 777                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 778                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 779                 break;
 780         case ANTENNA_B:
 781         default:
 782                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 783                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 784                 break;
 785         }
 786
 787         rt61pci_bbp_write(rt2x00dev, 77, r77);
 788         rt61pci_bbp_write(rt2x00dev, 3, r3);
 789         rt61pci_bbp_write(rt2x00dev, 4, r4);
 790 }
 791
 792 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
 793                                            const int p1, const int p2)
 794 {
 795         u32 reg;
 796
 797         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 798
 799         rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
 800         rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
 801
 802         rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
 803         rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
 804
 805         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
 806 }
 807
 808 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
 809                                         struct antenna_setup *ant)
 810 {
 811         u8 r3;
 812         u8 r4;
 813         u8 r77;
 814
 815         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 816         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 817         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 818
 819         /*
 820          * Configure the RX antenna.
 821          */
 822         switch (ant->rx) {
 823         case ANTENNA_A:
 824                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 825                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 826                 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
 827                 break;
 828         case ANTENNA_HW_DIVERSITY:
 829                 /*
 830                  * FIXME: Antenna selection for the rf 2529 is very confusing
 831                  * in the legacy driver. Just default to antenna B until the
 832                  * legacy code can be properly translated into rt2x00 code.
 833                  */
 834         case ANTENNA_B:
 835         default:
 836                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 837                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 838                 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
 839                 break;
 840         }
 841
 842         rt61pci_bbp_write(rt2x00dev, 77, r77);
 843         rt61pci_bbp_write(rt2x00dev, 3, r3);
 844         rt61pci_bbp_write(rt2x00dev, 4, r4);
 845 }
 846
 847 struct antenna_sel {
 848         u8 word;
 849         /*
 850          * value[0] -> non-LNA
 851          * value[1] -> LNA
 852          */
 853         u8 value[2];
 854 };
 855
 856 static const struct antenna_sel antenna_sel_a[] = {
 857         { 96,  { 0x58, 0x78 } },
 858         { 104, { 0x38, 0x48 } },
 859         { 75,  { 0xfe, 0x80 } },
 860         { 86,  { 0xfe, 0x80 } },
 861         { 88,  { 0xfe, 0x80 } },
 862         { 35,  { 0x60, 0x60 } },
 863         { 97,  { 0x58, 0x58 } },
 864         { 98,  { 0x58, 0x58 } },
 865 };
 866
 867 static const struct antenna_sel antenna_sel_bg[] = {
 868         { 96,  { 0x48, 0x68 } },
 869         { 104, { 0x2c, 0x3c } },
 870         { 75,  { 0xfe, 0x80 } },
 871         { 86,  { 0xfe, 0x80 } },
 872         { 88,  { 0xfe, 0x80 } },
 873         { 35,  { 0x50, 0x50 } },
 874         { 97,  { 0x48, 0x48 } },
 875         { 98,  { 0x48, 0x48 } },
 876 };
 877
 878 static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 879                                    struct antenna_setup *ant)
 880 {
 881         const struct antenna_sel *sel;
 882         unsigned int lna;
 883         unsigned int i;
 884         u32 reg;
 885
 886         /*
 887          * We should never come here because rt2x00lib is supposed
 888          * to catch this and send us the correct antenna explicitely.
 889          */
 890         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 891                ant->tx == ANTENNA_SW_DIVERSITY);
 892
 893         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
 894                 sel = antenna_sel_a;
 895                 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
 896         } else {
 897                 sel = antenna_sel_bg;
 898                 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
 899         }
 900
 901         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
 902                 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
 903
 904         rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
 905
 906         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
 907                            rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 908         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
 909                            rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 910
 911         rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
 912
 913         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 914             rt2x00_rf(&rt2x00dev->chip, RF5325))
 915                 rt61pci_config_antenna_5x(rt2x00dev, ant);
 916         else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
 917                 rt61pci_config_antenna_2x(rt2x00dev, ant);
 918         else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
 919                 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
 920                         rt61pci_config_antenna_2x(rt2x00dev, ant);
 921                 else
 922                         rt61pci_config_antenna_2529(rt2x00dev, ant);
 923         }
 924 }
 925
 926 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
 927                                     struct rt2x00lib_conf *libconf)
 928 {
 929         u32 reg;
 930
 931         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
 932         rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
 933         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
 934
 935         rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
 936         rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
 937         rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
 938         rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
 939         rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
 940
 941         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 942         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
 943         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 944
 945         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 946         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
 947         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 948
 949         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
 950         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
 951                            libconf->conf->beacon_int * 16);
 952         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
 953 }
 954
 955 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
 956                            struct rt2x00lib_conf *libconf,
 957                            const unsigned int flags)
 958 {
 959         if (flags & CONFIG_UPDATE_PHYMODE)
 960                 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
 961         if (flags & CONFIG_UPDATE_CHANNEL)
 962                 rt61pci_config_channel(rt2x00dev, &libconf->rf,
 963                                        libconf->conf->power_level);
 964         if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
 965                 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
 966         if (flags & CONFIG_UPDATE_ANTENNA)
 967                 rt61pci_config_antenna(rt2x00dev, &libconf->ant);
 968         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 969                 rt61pci_config_duration(rt2x00dev, libconf);
 970 }
 971
 972 /*
 973  * Link tuning
 974  */
 975 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
 976                                struct link_qual *qual)
 977 {
 978         u32 reg;
 979
 980         /*
 981          * Update FCS error count from register.
 982          */
 983         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
 984         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
 985
 986         /*
 987          * Update False CCA count from register.
 988          */
 989         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
 990         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
 991 }
 992
 993 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 994 {
 995         rt61pci_bbp_write(rt2x00dev, 17, 0x20);
 996         rt2x00dev->link.vgc_level = 0x20;
 997 }
 998
 999 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
1000 {
1001         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
1002         u8 r17;
1003         u8 up_bound;
1004         u8 low_bound;
1005
1006         rt61pci_bbp_read(rt2x00dev, 17, &r17);
1007
1008         /*
1009          * Determine r17 bounds.
1010          */
1011         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1012                 low_bound = 0x28;
1013                 up_bound = 0x48;
1014                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1015                         low_bound += 0x10;
1016                         up_bound += 0x10;
1017                 }
1018         } else {
1019                 low_bound = 0x20;
1020                 up_bound = 0x40;
1021                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1022                         low_bound += 0x10;
1023                         up_bound += 0x10;
1024                 }
1025         }
1026
1027         /*
1028          * If we are not associated, we should go straight to the
1029          * dynamic CCA tuning.
1030          */
1031         if (!rt2x00dev->intf_associated)
1032                 goto dynamic_cca_tune;
1033
1034         /*
1035          * Special big-R17 for very short distance
1036          */
1037         if (rssi >= -35) {
1038                 if (r17 != 0x60)
1039                         rt61pci_bbp_write(rt2x00dev, 17, 0x60);
1040                 return;
1041         }
1042
1043         /*
1044          * Special big-R17 for short distance
1045          */
1046         if (rssi >= -58) {
1047                 if (r17 != up_bound)
1048                         rt61pci_bbp_write(rt2x00dev, 17, up_bound);
1049                 return;
1050         }
1051
1052         /*
1053          * Special big-R17 for middle-short distance
1054          */
1055         if (rssi >= -66) {
1056                 low_bound += 0x10;
1057                 if (r17 != low_bound)
1058                         rt61pci_bbp_write(rt2x00dev, 17, low_bound);
1059                 return;
1060         }
1061
1062         /*
1063          * Special mid-R17 for middle distance
1064          */
1065         if (rssi >= -74) {
1066                 low_bound += 0x08;
1067                 if (r17 != low_bound)
1068                         rt61pci_bbp_write(rt2x00dev, 17, low_bound);
1069                 return;
1070         }
1071
1072         /*
1073          * Special case: Change up_bound based on the rssi.
1074          * Lower up_bound when rssi is weaker then -74 dBm.
1075          */
1076         up_bound -= 2 * (-74 - rssi);
1077         if (low_bound > up_bound)
1078                 up_bound = low_bound;
1079
1080         if (r17 > up_bound) {
1081                 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
1082                 return;
1083         }
1084
1085 dynamic_cca_tune:
1086
1087         /*
1088          * r17 does not yet exceed upper limit, continue and base
1089          * the r17 tuning on the false CCA count.
1090          */
1091         if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
1092                 if (++r17 > up_bound)
1093                         r17 = up_bound;
1094                 rt61pci_bbp_write(rt2x00dev, 17, r17);
1095         } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
1096                 if (--r17 < low_bound)
1097                         r17 = low_bound;
1098                 rt61pci_bbp_write(rt2x00dev, 17, r17);
1099         }
1100 }
1101
1102 /*
1103  * Firmware functions
1104  */
1105 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1106 {
1107         char *fw_name;
1108
1109         switch (rt2x00dev->chip.rt) {
1110         case RT2561:
1111                 fw_name = FIRMWARE_RT2561;
1112                 break;
1113         case RT2561s:
1114                 fw_name = FIRMWARE_RT2561s;
1115                 break;
1116         case RT2661:
1117                 fw_name = FIRMWARE_RT2661;
1118                 break;
1119         default:
1120                 fw_name = NULL;
1121                 break;
1122         }
1123
1124         return fw_name;
1125 }
1126
1127 static u16 rt61pci_get_firmware_crc(const void *data, const size_t len)
1128 {
1129         u16 crc;
1130
1131         /*
1132          * Use the crc itu-t algorithm.
1133          * The last 2 bytes in the firmware array are the crc checksum itself,
1134          * this means that we should never pass those 2 bytes to the crc
1135          * algorithm.
1136          */
1137         crc = crc_itu_t(0, data, len - 2);
1138         crc = crc_itu_t_byte(crc, 0);
1139         crc = crc_itu_t_byte(crc, 0);
1140
1141         return crc;
1142 }
1143
1144 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
1145                                  const size_t len)
1146 {
1147         int i;
1148         u32 reg;
1149
1150         /*
1151          * Wait for stable hardware.
1152          */
1153         for (i = 0; i < 100; i++) {
1154                 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1155                 if (reg)
1156                         break;
1157                 msleep(1);
1158         }
1159
1160         if (!reg) {
1161                 ERROR(rt2x00dev, "Unstable hardware.\n");
1162                 return -EBUSY;
1163         }
1164
1165         /*
1166          * Prepare MCU and mailbox for firmware loading.
1167          */
1168         reg = 0;
1169         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1170         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1171         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1172         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1173         rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1174
1175         /*
1176          * Write firmware to device.
1177          */
1178         reg = 0;
1179         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1180         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1181         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1182
1183         rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1184                                       data, len);
1185
1186         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1187         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1188
1189         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1190         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1191
1192         for (i = 0; i < 100; i++) {
1193                 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1194                 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1195                         break;
1196                 msleep(1);
1197         }
1198
1199         if (i == 100) {
1200                 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1201                 return -EBUSY;
1202         }
1203
1204         /*
1205          * Hardware needs another millisecond before it is ready.
1206          */
1207         msleep(1);
1208
1209         /*
1210          * Reset MAC and BBP registers.
1211          */
1212         reg = 0;
1213         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1214         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1215         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1216
1217         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1218         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1219         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1220         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1221
1222         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1223         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1224         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1225
1226         return 0;
1227 }
1228
1229 /*
1230  * Initialization functions.
1231  */
1232 static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
1233                                  struct queue_entry *entry)
1234 {
1235         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1236         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1237         u32 word;
1238
1239         rt2x00_desc_read(entry_priv->desc, 5, &word);
1240         rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1241                            skbdesc->skb_dma);
1242         rt2x00_desc_write(entry_priv->desc, 5, word);
1243
1244         rt2x00_desc_read(entry_priv->desc, 0, &word);
1245         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1246         rt2x00_desc_write(entry_priv->desc, 0, word);
1247 }
1248
1249 static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
1250                                  struct queue_entry *entry)
1251 {
1252         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1253         u32 word;
1254
1255         rt2x00_desc_read(entry_priv->desc, 0, &word);
1256         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1257         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1258         rt2x00_desc_write(entry_priv->desc, 0, word);
1259 }
1260
1261 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1262 {
1263         struct queue_entry_priv_pci *entry_priv;
1264         u32 reg;
1265
1266         /*
1267          * Initialize registers.
1268          */
1269         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1270         rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1271                            rt2x00dev->tx[0].limit);
1272         rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1273                            rt2x00dev->tx[1].limit);
1274         rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1275                            rt2x00dev->tx[2].limit);
1276         rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1277                            rt2x00dev->tx[3].limit);
1278         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1279
1280         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1281         rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1282                            rt2x00dev->tx[0].desc_size / 4);
1283         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1284
1285         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1286         rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1287         rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1288                            entry_priv->desc_dma);
1289         rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1290
1291         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1292         rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1293         rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1294                            entry_priv->desc_dma);
1295         rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1296
1297         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1298         rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1299         rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1300                            entry_priv->desc_dma);
1301         rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1302
1303         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1304         rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1305         rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1306                            entry_priv->desc_dma);
1307         rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1308
1309         rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1310         rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1311         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1312                            rt2x00dev->rx->desc_size / 4);
1313         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1314         rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1315
1316         entry_priv = rt2x00dev->rx->entries[0].priv_data;
1317         rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1318         rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1319                            entry_priv->desc_dma);
1320         rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1321
1322         rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1323         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1324         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1325         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1326         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1327         rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1328
1329         rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1330         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1331         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1332         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1333         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1334         rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1335
1336         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1337         rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1338         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1339
1340         return 0;
1341 }
1342
1343 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1344 {
1345         u32 reg;
1346
1347         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1348         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1349         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1350         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1351         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1352
1353         rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1354         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1355         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1356         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1357         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1358         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1359         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1360         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1361         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1362         rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1363
1364         /*
1365          * CCK TXD BBP registers
1366          */
1367         rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1368         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1369         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1370         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1371         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1372         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1373         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1374         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1375         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1376         rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1377
1378         /*
1379          * OFDM TXD BBP registers
1380          */
1381         rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1382         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1383         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1384         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1385         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1386         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1387         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1388         rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1389
1390         rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1391         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1392         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1393         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1394         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1395         rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1396
1397         rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1398         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1399         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1400         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1401         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1402         rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1403
1404         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1405         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1406         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1407         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1408         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1409         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1410         rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1411         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1412
1413         rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1414
1415         rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1416
1417         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1418         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1419         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1420
1421         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1422
1423         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1424                 return -EBUSY;
1425
1426         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1427
1428         /*
1429          * Invalidate all Shared Keys (SEC_CSR0),
1430          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1431          */
1432         rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1433         rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1434         rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1435
1436         rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1437         rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1438         rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1439         rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1440
1441         rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1442
1443         rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1444
1445         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1446
1447         rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1448         rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1449         rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1450         rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1451
1452         rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1453         rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1454         rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1455         rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1456
1457         /*
1458          * Clear all beacons
1459          * For the Beacon base registers we only need to clear
1460          * the first byte since that byte contains the VALID and OWNER
1461          * bits which (when set to 0) will invalidate the entire beacon.
1462          */
1463         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1464         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1465         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1466         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1467
1468         /*
1469          * We must clear the error counters.
1470          * These registers are cleared on read,
1471          * so we may pass a useless variable to store the value.
1472          */
1473         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1474         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1475         rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1476
1477         /*
1478          * Reset MAC and BBP registers.
1479          */
1480         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1481         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1482         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1483         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1484
1485         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1486         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1487         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1488         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1489
1490         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1491         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1492         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1493
1494         return 0;
1495 }
1496
1497 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1498 {
1499         unsigned int i;
1500         u8 value;
1501
1502         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1503                 rt61pci_bbp_read(rt2x00dev, 0, &value);
1504                 if ((value != 0xff) && (value != 0x00))
1505                         return 0;
1506                 udelay(REGISTER_BUSY_DELAY);
1507         }
1508
1509         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1510         return -EACCES;
1511 }
1512
1513 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1514 {
1515         unsigned int i;
1516         u16 eeprom;
1517         u8 reg_id;
1518         u8 value;
1519
1520         if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1521                 return -EACCES;
1522
1523         rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1524         rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1525         rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1526         rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1527         rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1528         rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1529         rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1530         rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1531         rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1532         rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1533         rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1534         rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1535         rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1536         rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1537         rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1538         rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1539         rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1540         rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1541         rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1542         rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1543         rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1544         rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1545         rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1546         rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1547
1548         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1549                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1550
1551                 if (eeprom != 0xffff && eeprom != 0x0000) {
1552                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1553                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1554                         rt61pci_bbp_write(rt2x00dev, reg_id, value);
1555                 }
1556         }
1557
1558         return 0;
1559 }
1560
1561 /*
1562  * Device state switch handlers.
1563  */
1564 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1565                               enum dev_state state)
1566 {
1567         u32 reg;
1568
1569         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1570         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1571                            (state == STATE_RADIO_RX_OFF) ||
1572                            (state == STATE_RADIO_RX_OFF_LINK));
1573         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1574 }
1575
1576 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1577                                enum dev_state state)
1578 {
1579         int mask = (state == STATE_RADIO_IRQ_OFF);
1580         u32 reg;
1581
1582         /*
1583          * When interrupts are being enabled, the interrupt registers
1584          * should clear the register to assure a clean state.
1585          */
1586         if (state == STATE_RADIO_IRQ_ON) {
1587                 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1588                 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1589
1590                 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1591                 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1592         }
1593
1594         /*
1595          * Only toggle the interrupts bits we are going to use.
1596          * Non-checked interrupt bits are disabled by default.
1597          */
1598         rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1599         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1600         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1601         rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1602         rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1603         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1604
1605         rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1606         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1607         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1608         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1609         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1610         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1611         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1612         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1613         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1614         rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1615 }
1616
1617 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1618 {
1619         u32 reg;
1620
1621         /*
1622          * Initialize all registers.
1623          */
1624         if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1625                      rt61pci_init_registers(rt2x00dev) ||
1626                      rt61pci_init_bbp(rt2x00dev)))
1627                 return -EIO;
1628
1629         /*
1630          * Enable RX.
1631          */
1632         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1633         rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1634         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1635
1636         return 0;
1637 }
1638
1639 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1640 {
1641         u32 reg;
1642
1643         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1644
1645         /*
1646          * Disable synchronisation.
1647          */
1648         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1649
1650         /*
1651          * Cancel RX and TX.
1652          */
1653         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1654         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1655         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1656         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1657         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1658         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1659 }
1660
1661 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1662 {
1663         u32 reg;
1664         unsigned int i;
1665         char put_to_sleep;
1666
1667         put_to_sleep = (state != STATE_AWAKE);
1668
1669         rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1670         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1671         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1672         rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1673
1674         /*
1675          * Device is not guaranteed to be in the requested state yet.
1676          * We must wait until the register indicates that the
1677          * device has entered the correct state.
1678          */
1679         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1680                 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1681                 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1682                 if (state == !put_to_sleep)
1683                         return 0;
1684                 msleep(10);
1685         }
1686
1687         return -EBUSY;
1688 }
1689
1690 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1691                                     enum dev_state state)
1692 {
1693         int retval = 0;
1694
1695         switch (state) {
1696         case STATE_RADIO_ON:
1697                 retval = rt61pci_enable_radio(rt2x00dev);
1698                 break;
1699         case STATE_RADIO_OFF:
1700                 rt61pci_disable_radio(rt2x00dev);
1701                 break;
1702         case STATE_RADIO_RX_ON:
1703         case STATE_RADIO_RX_ON_LINK:
1704         case STATE_RADIO_RX_OFF:
1705         case STATE_RADIO_RX_OFF_LINK:
1706                 rt61pci_toggle_rx(rt2x00dev, state);
1707                 break;
1708         case STATE_RADIO_IRQ_ON:
1709         case STATE_RADIO_IRQ_OFF:
1710                 rt61pci_toggle_irq(rt2x00dev, state);
1711                 break;
1712         case STATE_DEEP_SLEEP:
1713         case STATE_SLEEP:
1714         case STATE_STANDBY:
1715         case STATE_AWAKE:
1716                 retval = rt61pci_set_state(rt2x00dev, state);
1717                 break;
1718         default:
1719                 retval = -ENOTSUPP;
1720                 break;
1721         }
1722
1723         if (unlikely(retval))
1724                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1725                       state, retval);
1726
1727         return retval;
1728 }
1729
1730 /*
1731  * TX descriptor initialization
1732  */
1733 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1734                                   struct sk_buff *skb,
1735                                   struct txentry_desc *txdesc)
1736 {
1737         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1738         __le32 *txd = skbdesc->desc;
1739         u32 word;
1740
1741         /*
1742          * Start writing the descriptor words.
1743          */
1744         rt2x00_desc_read(txd, 1, &word);
1745         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1746         rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1747         rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1748         rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1749         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1750         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1751                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1752         rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1753         rt2x00_desc_write(txd, 1, word);
1754
1755         rt2x00_desc_read(txd, 2, &word);
1756         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1757         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1758         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1759         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1760         rt2x00_desc_write(txd, 2, word);
1761
1762         if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1763                 _rt2x00_desc_write(txd, 3, skbdesc->iv);
1764                 _rt2x00_desc_write(txd, 4, skbdesc->eiv);
1765         }
1766
1767         rt2x00_desc_read(txd, 5, &word);
1768         rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
1769         rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1770                            skbdesc->entry->entry_idx);
1771         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1772                            TXPOWER_TO_DEV(rt2x00dev->tx_power));
1773         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1774         rt2x00_desc_write(txd, 5, word);
1775
1776         rt2x00_desc_read(txd, 6, &word);
1777         rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1778                            skbdesc->skb_dma);
1779         rt2x00_desc_write(txd, 6, word);
1780
1781         if (skbdesc->desc_len > TXINFO_SIZE) {
1782                 rt2x00_desc_read(txd, 11, &word);
1783                 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skb->len);
1784                 rt2x00_desc_write(txd, 11, word);
1785         }
1786
1787         rt2x00_desc_read(txd, 0, &word);
1788         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1789         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1790         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1791                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1792         rt2x00_set_field32(&word, TXD_W0_ACK,
1793                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1794         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1795                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1796         rt2x00_set_field32(&word, TXD_W0_OFDM,
1797                            test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1798         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1799         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1800                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1801         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1802                            test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1803         rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1804                            test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1805         rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1806         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1807         rt2x00_set_field32(&word, TXD_W0_BURST,
1808                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1809         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1810         rt2x00_desc_write(txd, 0, word);
1811 }
1812
1813 /*
1814  * TX data initialization
1815  */
1816 static void rt61pci_write_beacon(struct queue_entry *entry)
1817 {
1818         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1819         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1820         unsigned int beacon_base;
1821         u32 reg;
1822
1823         /*
1824          * Disable beaconing while we are reloading the beacon data,
1825          * otherwise we might be sending out invalid data.
1826          */
1827         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1828         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1829         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1830         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1831         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1832
1833         /*
1834          * Write entire beacon with descriptor to register.
1835          */
1836         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1837         rt2x00pci_register_multiwrite(rt2x00dev,
1838                                       beacon_base,
1839                                       skbdesc->desc, skbdesc->desc_len);
1840         rt2x00pci_register_multiwrite(rt2x00dev,
1841                                       beacon_base + skbdesc->desc_len,
1842                                       entry->skb->data, entry->skb->len);
1843
1844         /*
1845          * Clean up beacon skb.
1846          */
1847         dev_kfree_skb_any(entry->skb);
1848         entry->skb = NULL;
1849 }
1850
1851 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1852                                   const enum data_queue_qid queue)
1853 {
1854         u32 reg;
1855
1856         if (queue == QID_BEACON) {
1857                 /*
1858                  * For Wi-Fi faily generated beacons between participating
1859                  * stations. Set TBTT phase adaptive adjustment step to 8us.
1860                  */
1861                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1862
1863                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1864                 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1865                         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1866                         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1867                         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1868                         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1869                 }
1870                 return;
1871         }
1872
1873         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1874         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
1875         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
1876         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
1877         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
1878         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1879 }
1880
1881 /*
1882  * RX control handlers
1883  */
1884 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1885 {
1886         u16 eeprom;
1887         u8 offset;
1888         u8 lna;
1889
1890         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1891         switch (lna) {
1892         case 3:
1893                 offset = 90;
1894                 break;
1895         case 2:
1896                 offset = 74;
1897                 break;
1898         case 1:
1899                 offset = 64;
1900                 break;
1901         default:
1902                 return 0;
1903         }
1904
1905         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1906                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1907                         offset += 14;
1908
1909                 if (lna == 3 || lna == 2)
1910                         offset += 10;
1911
1912                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1913                 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1914         } else {
1915                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1916                         offset += 14;
1917
1918                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1919                 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1920         }
1921
1922         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1923 }
1924
1925 static void rt61pci_fill_rxdone(struct queue_entry *entry,
1926                                 struct rxdone_entry_desc *rxdesc)
1927 {
1928         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1929         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1930         u32 word0;
1931         u32 word1;
1932
1933         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1934         rt2x00_desc_read(entry_priv->desc, 1, &word1);
1935
1936         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1937                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1938
1939         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1940                 rxdesc->cipher =
1941                     rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1942                 rxdesc->cipher_status =
1943                     rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1944         }
1945
1946         if (rxdesc->cipher != CIPHER_NONE) {
1947                 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv);
1948                 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->eiv);
1949                 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
1950
1951                 /*
1952                  * Hardware has stripped IV/EIV data from 802.11 frame during
1953                  * decryption. It has provided the data seperately but rt2x00lib
1954                  * should decide if it should be reinserted.
1955                  */
1956                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1957
1958                 /*
1959                  * FIXME: Legacy driver indicates that the frame does
1960                  * contain the Michael Mic. Unfortunately, in rt2x00
1961                  * the MIC seems to be missing completely...
1962                  */
1963                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1964
1965                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1966                         rxdesc->flags |= RX_FLAG_DECRYPTED;
1967                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1968                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1969         }
1970
1971         /*
1972          * Obtain the status about this packet.
1973          * When frame was received with an OFDM bitrate,
1974          * the signal is the PLCP value. If it was received with
1975          * a CCK bitrate the signal is the rate in 100kbit/s.
1976          */
1977         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1978         rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
1979         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1980
1981         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1982                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1983         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1984                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1985 }
1986
1987 /*
1988  * Interrupt functions.
1989  */
1990 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1991 {
1992         struct data_queue *queue;
1993         struct queue_entry *entry;
1994         struct queue_entry *entry_done;
1995         struct queue_entry_priv_pci *entry_priv;
1996         struct txdone_entry_desc txdesc;
1997         u32 word;
1998         u32 reg;
1999         u32 old_reg;
2000         int type;
2001         int index;
2002
2003         /*
2004          * During each loop we will compare the freshly read
2005          * STA_CSR4 register value with the value read from
2006          * the previous loop. If the 2 values are equal then
2007          * we should stop processing because the chance it
2008          * quite big that the device has been unplugged and
2009          * we risk going into an endless loop.
2010          */
2011         old_reg = 0;
2012
2013         while (1) {
2014                 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
2015                 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2016                         break;
2017
2018                 if (old_reg == reg)
2019                         break;
2020                 old_reg = reg;
2021
2022                 /*
2023                  * Skip this entry when it contains an invalid
2024                  * queue identication number.
2025                  */
2026                 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
2027                 queue = rt2x00queue_get_queue(rt2x00dev, type);
2028                 if (unlikely(!queue))
2029                         continue;
2030
2031                 /*
2032                  * Skip this entry when it contains an invalid
2033                  * index number.
2034                  */
2035                 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
2036                 if (unlikely(index >= queue->limit))
2037                         continue;
2038
2039                 entry = &queue->entries[index];
2040                 entry_priv = entry->priv_data;
2041                 rt2x00_desc_read(entry_priv->desc, 0, &word);
2042
2043                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2044                     !rt2x00_get_field32(word, TXD_W0_VALID))
2045                         return;
2046
2047                 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2048                 while (entry != entry_done) {
2049                         /* Catch up.
2050                          * Just report any entries we missed as failed.
2051                          */
2052                         WARNING(rt2x00dev,
2053                                 "TX status report missed for entry %d\n",
2054                                 entry_done->entry_idx);
2055
2056                         txdesc.flags = 0;
2057                         __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2058                         txdesc.retry = 0;
2059
2060                         rt2x00lib_txdone(entry_done, &txdesc);
2061                         entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2062                 }
2063
2064                 /*
2065                  * Obtain the status about this packet.
2066                  */
2067                 txdesc.flags = 0;
2068                 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2069                 case 0: /* Success, maybe with retry */
2070                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2071                         break;
2072                 case 6: /* Failure, excessive retries */
2073                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2074                         /* Don't break, this is a failed frame! */
2075                 default: /* Failure */
2076                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
2077                 }
2078                 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
2079
2080                 rt2x00lib_txdone(entry, &txdesc);
2081         }
2082 }
2083
2084 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2085 {
2086         struct rt2x00_dev *rt2x00dev = dev_instance;
2087         u32 reg_mcu;
2088         u32 reg;
2089
2090         /*
2091          * Get the interrupt sources & saved to local variable.
2092          * Write register value back to clear pending interrupts.
2093          */
2094         rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
2095         rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2096
2097         rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2098         rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2099
2100         if (!reg && !reg_mcu)
2101                 return IRQ_NONE;
2102
2103         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
2104                 return IRQ_HANDLED;
2105
2106         /*
2107          * Handle interrupts, walk through all bits
2108          * and run the tasks, the bits are checked in order of
2109          * priority.
2110          */
2111
2112         /*
2113          * 1 - Rx ring done interrupt.
2114          */
2115         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2116                 rt2x00pci_rxdone(rt2x00dev);
2117
2118         /*
2119          * 2 - Tx ring done interrupt.
2120          */
2121         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2122                 rt61pci_txdone(rt2x00dev);
2123
2124         /*
2125          * 3 - Handle MCU command done.
2126          */
2127         if (reg_mcu)
2128                 rt2x00pci_register_write(rt2x00dev,
2129                                          M2H_CMD_DONE_CSR, 0xffffffff);
2130
2131         return IRQ_HANDLED;
2132 }
2133
2134 /*
2135  * Device probe functions.
2136  */
2137 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2138 {
2139         struct eeprom_93cx6 eeprom;
2140         u32 reg;
2141         u16 word;
2142         u8 *mac;
2143         s8 value;
2144
2145         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2146
2147         eeprom.data = rt2x00dev;
2148         eeprom.register_read = rt61pci_eepromregister_read;
2149         eeprom.register_write = rt61pci_eepromregister_write;
2150         eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2151             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2152         eeprom.reg_data_in = 0;
2153         eeprom.reg_data_out = 0;
2154         eeprom.reg_data_clock = 0;
2155         eeprom.reg_chip_select = 0;
2156
2157         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2158                                EEPROM_SIZE / sizeof(u16));
2159
2160         /*
2161          * Start validation of the data that has been read.
2162          */
2163         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2164         if (!is_valid_ether_addr(mac)) {
2165                 DECLARE_MAC_BUF(macbuf);
2166
2167                 random_ether_addr(mac);
2168                 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2169         }
2170
2171         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2172         if (word == 0xffff) {
2173                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
2174                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2175                                    ANTENNA_B);
2176                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2177                                    ANTENNA_B);
2178                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2179                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2180                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2181                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2182                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2183                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2184         }
2185
2186         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2187         if (word == 0xffff) {
2188                 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2189                 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
2190                 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
2191                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2192                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2193                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2194                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2195                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2196         }
2197
2198         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2199         if (word == 0xffff) {
2200                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2201                                    LED_MODE_DEFAULT);
2202                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2203                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2204         }
2205
2206         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2207         if (word == 0xffff) {
2208                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2209                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2210                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2211                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2212         }
2213
2214         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2215         if (word == 0xffff) {
2216                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2217                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2218                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2219                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2220         } else {
2221                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2222                 if (value < -10 || value > 10)
2223                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2224                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2225                 if (value < -10 || value > 10)
2226                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2227                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2228         }
2229
2230         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2231         if (word == 0xffff) {
2232                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2233                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2234                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2235                 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
2236         } else {
2237                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2238                 if (value < -10 || value > 10)
2239                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2240                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2241                 if (value < -10 || value > 10)
2242                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2243                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2244         }
2245
2246         return 0;
2247 }
2248
2249 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2250 {
2251         u32 reg;
2252         u16 value;
2253         u16 eeprom;
2254         u16 device;
2255
2256         /*
2257          * Read EEPROM word for configuration.
2258          */
2259         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2260
2261         /*
2262          * Identify RF chipset.
2263          * To determine the RT chip we have to read the
2264          * PCI header of the device.
2265          */
2266         pci_read_config_word(to_pci_dev(rt2x00dev->dev),
2267                              PCI_CONFIG_HEADER_DEVICE, &device);
2268         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2269         rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2270         rt2x00_set_chip(rt2x00dev, device, value, reg);
2271
2272         if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
2273             !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
2274             !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
2275             !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
2276                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2277                 return -ENODEV;
2278         }
2279
2280         /*
2281          * Determine number of antenna's.
2282          */
2283         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2284                 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2285
2286         /*
2287          * Identify default antenna configuration.
2288          */
2289         rt2x00dev->default_ant.tx =
2290             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2291         rt2x00dev->default_ant.rx =
2292             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2293
2294         /*
2295          * Read the Frame type.
2296          */
2297         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2298                 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2299
2300         /*
2301          * Detect if this device has an hardware controlled radio.
2302          */
2303 #ifdef CONFIG_RT61PCI_RFKILL
2304         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2305                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2306 #endif /* CONFIG_RT61PCI_RFKILL */
2307
2308         /*
2309          * Read frequency offset and RF programming sequence.
2310          */
2311         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2312         if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2313                 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2314
2315         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2316
2317         /*
2318          * Read external LNA informations.
2319          */
2320         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2321
2322         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2323                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2324         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2325                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2326
2327         /*
2328          * When working with a RF2529 chip without double antenna
2329          * the antenna settings should be gathered from the NIC
2330          * eeprom word.
2331          */
2332         if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
2333             !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2334                 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
2335                 case 0:
2336                         rt2x00dev->default_ant.tx = ANTENNA_B;
2337                         rt2x00dev->default_ant.rx = ANTENNA_A;
2338                         break;
2339                 case 1:
2340                         rt2x00dev->default_ant.tx = ANTENNA_B;
2341                         rt2x00dev->default_ant.rx = ANTENNA_B;
2342                         break;
2343                 case 2:
2344                         rt2x00dev->default_ant.tx = ANTENNA_A;
2345                         rt2x00dev->default_ant.rx = ANTENNA_A;
2346                         break;
2347                 case 3:
2348                         rt2x00dev->default_ant.tx = ANTENNA_A;
2349                         rt2x00dev->default_ant.rx = ANTENNA_B;
2350                         break;
2351                 }
2352
2353                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2354                         rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2355                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2356                         rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2357         }
2358
2359         /*
2360          * Store led settings, for correct led behaviour.
2361          * If the eeprom value is invalid,
2362          * switch to default led mode.
2363          */
2364 #ifdef CONFIG_RT61PCI_LEDS
2365         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2366         value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2367
2368         rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2369         rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2370         if (value == LED_MODE_SIGNAL_STRENGTH)
2371                 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2372                                  LED_TYPE_QUALITY);
2373
2374         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2375         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2376                            rt2x00_get_field16(eeprom,
2377                                               EEPROM_LED_POLARITY_GPIO_0));
2378         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2379                            rt2x00_get_field16(eeprom,
2380                                               EEPROM_LED_POLARITY_GPIO_1));
2381         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2382                            rt2x00_get_field16(eeprom,
2383                                               EEPROM_LED_POLARITY_GPIO_2));
2384         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2385                            rt2x00_get_field16(eeprom,
2386                                               EEPROM_LED_POLARITY_GPIO_3));
2387         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2388                            rt2x00_get_field16(eeprom,
2389                                               EEPROM_LED_POLARITY_GPIO_4));
2390         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2391                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2392         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2393                            rt2x00_get_field16(eeprom,
2394                                               EEPROM_LED_POLARITY_RDY_G));
2395         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2396                            rt2x00_get_field16(eeprom,
2397                                               EEPROM_LED_POLARITY_RDY_A));
2398 #endif /* CONFIG_RT61PCI_LEDS */
2399
2400         return 0;
2401 }
2402
2403 /*
2404  * RF value list for RF5225 & RF5325
2405  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2406  */
2407 static const struct rf_channel rf_vals_noseq[] = {
2408         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2409         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2410         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2411         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2412         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2413         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2414         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2415         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2416         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2417         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2418         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2419         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2420         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2421         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2422
2423         /* 802.11 UNI / HyperLan 2 */
2424         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2425         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2426         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2427         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2428         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2429         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2430         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2431         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2432
2433         /* 802.11 HyperLan 2 */
2434         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2435         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2436         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2437         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2438         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2439         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2440         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2441         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2442         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2443         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2444
2445         /* 802.11 UNII */
2446         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2447         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2448         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2449         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2450         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2451         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2452
2453         /* MMAC(Japan)J52 ch 34,38,42,46 */
2454         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2455         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2456         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2457         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2458 };
2459
2460 /*
2461  * RF value list for RF5225 & RF5325
2462  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2463  */
2464 static const struct rf_channel rf_vals_seq[] = {
2465         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2466         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2467         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2468         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2469         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2470         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2471         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2472         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2473         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2474         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2475         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2476         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2477         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2478         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2479
2480         /* 802.11 UNI / HyperLan 2 */
2481         { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2482         { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2483         { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2484         { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2485         { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2486         { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2487         { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2488         { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2489
2490         /* 802.11 HyperLan 2 */
2491         { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2492         { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2493         { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2494         { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2495         { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2496         { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2497         { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2498         { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2499         { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2500         { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2501
2502         /* 802.11 UNII */
2503         { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2504         { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2505         { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2506         { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2507         { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2508         { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2509
2510         /* MMAC(Japan)J52 ch 34,38,42,46 */
2511         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2512         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2513         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2514         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2515 };
2516
2517 static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2518 {
2519         struct hw_mode_spec *spec = &rt2x00dev->spec;
2520         u8 *txpower;
2521         unsigned int i;
2522
2523         /*
2524          * Initialize all hw fields.
2525          */
2526         rt2x00dev->hw->flags =
2527             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2528             IEEE80211_HW_SIGNAL_DBM;
2529         rt2x00dev->hw->extra_tx_headroom = 0;
2530
2531         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2532         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2533                                 rt2x00_eeprom_addr(rt2x00dev,
2534                                                    EEPROM_MAC_ADDR_0));
2535
2536         /*
2537          * Convert tx_power array in eeprom.
2538          */
2539         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2540         for (i = 0; i < 14; i++)
2541                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2542
2543         /*
2544          * Initialize hw_mode information.
2545          */
2546         spec->supported_bands = SUPPORT_BAND_2GHZ;
2547         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2548         spec->tx_power_a = NULL;
2549         spec->tx_power_bg = txpower;
2550         spec->tx_power_default = DEFAULT_TXPOWER;
2551
2552         if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2553                 spec->num_channels = 14;
2554                 spec->channels = rf_vals_noseq;
2555         } else {
2556                 spec->num_channels = 14;
2557                 spec->channels = rf_vals_seq;
2558         }
2559
2560         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2561             rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2562                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2563                 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2564
2565                 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2566                 for (i = 0; i < 14; i++)
2567                         txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2568
2569                 spec->tx_power_a = txpower;
2570         }
2571 }
2572
2573 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2574 {
2575         int retval;
2576
2577         /*
2578          * Allocate eeprom data.
2579          */
2580         retval = rt61pci_validate_eeprom(rt2x00dev);
2581         if (retval)
2582                 return retval;
2583
2584         retval = rt61pci_init_eeprom(rt2x00dev);
2585         if (retval)
2586                 return retval;
2587
2588         /*
2589          * Initialize hw specifications.
2590          */
2591         rt61pci_probe_hw_mode(rt2x00dev);
2592
2593         /*
2594          * This device requires firmware and DMA mapped skbs.
2595          */
2596         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2597         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
2598         __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2599
2600         /*
2601          * Set the rssi offset.
2602          */
2603         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2604
2605         return 0;
2606 }
2607
2608 /*
2609  * IEEE80211 stack callback functions.
2610  */
2611 static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2612                                    u32 short_retry, u32 long_retry)
2613 {
2614         struct rt2x00_dev *rt2x00dev = hw->priv;
2615         u32 reg;
2616
2617         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
2618         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2619         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2620         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2621
2622         return 0;
2623 }
2624
2625 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2626 {
2627         struct rt2x00_dev *rt2x00dev = hw->priv;
2628         u64 tsf;
2629         u32 reg;
2630
2631         rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2632         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2633         rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2634         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2635
2636         return tsf;
2637 }
2638
2639 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2640         .tx                     = rt2x00mac_tx,
2641         .start                  = rt2x00mac_start,
2642         .stop                   = rt2x00mac_stop,
2643         .add_interface          = rt2x00mac_add_interface,
2644         .remove_interface       = rt2x00mac_remove_interface,
2645         .config                 = rt2x00mac_config,
2646         .config_interface       = rt2x00mac_config_interface,
2647         .configure_filter       = rt2x00mac_configure_filter,
2648         .set_key                = rt2x00mac_set_key,
2649         .get_stats              = rt2x00mac_get_stats,
2650         .set_retry_limit        = rt61pci_set_retry_limit,
2651         .bss_info_changed       = rt2x00mac_bss_info_changed,
2652         .conf_tx                = rt2x00mac_conf_tx,
2653         .get_tx_stats           = rt2x00mac_get_tx_stats,
2654         .get_tsf                = rt61pci_get_tsf,
2655 };
2656
2657 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2658         .irq_handler            = rt61pci_interrupt,
2659         .probe_hw               = rt61pci_probe_hw,
2660         .get_firmware_name      = rt61pci_get_firmware_name,
2661         .get_firmware_crc       = rt61pci_get_firmware_crc,
2662         .load_firmware          = rt61pci_load_firmware,
2663         .initialize             = rt2x00pci_initialize,
2664         .uninitialize           = rt2x00pci_uninitialize,
2665         .init_rxentry           = rt61pci_init_rxentry,
2666         .init_txentry           = rt61pci_init_txentry,
2667         .set_device_state       = rt61pci_set_device_state,
2668         .rfkill_poll            = rt61pci_rfkill_poll,
2669         .link_stats             = rt61pci_link_stats,
2670         .reset_tuner            = rt61pci_reset_tuner,
2671         .link_tuner             = rt61pci_link_tuner,
2672         .write_tx_desc          = rt61pci_write_tx_desc,
2673         .write_tx_data          = rt2x00pci_write_tx_data,
2674         .write_beacon           = rt61pci_write_beacon,
2675         .kick_tx_queue          = rt61pci_kick_tx_queue,
2676         .fill_rxdone            = rt61pci_fill_rxdone,
2677         .config_shared_key      = rt61pci_config_shared_key,
2678         .config_pairwise_key    = rt61pci_config_pairwise_key,
2679         .config_filter          = rt61pci_config_filter,
2680         .config_intf            = rt61pci_config_intf,
2681         .config_erp             = rt61pci_config_erp,
2682         .config                 = rt61pci_config,
2683 };
2684
2685 static const struct data_queue_desc rt61pci_queue_rx = {
2686         .entry_num              = RX_ENTRIES,
2687         .data_size              = DATA_FRAME_SIZE,
2688         .desc_size              = RXD_DESC_SIZE,
2689         .priv_size              = sizeof(struct queue_entry_priv_pci),
2690 };
2691
2692 static const struct data_queue_desc rt61pci_queue_tx = {
2693         .entry_num              = TX_ENTRIES,
2694         .data_size              = DATA_FRAME_SIZE,
2695         .desc_size              = TXD_DESC_SIZE,
2696         .priv_size              = sizeof(struct queue_entry_priv_pci),
2697 };
2698
2699 static const struct data_queue_desc rt61pci_queue_bcn = {
2700         .entry_num              = 4 * BEACON_ENTRIES,
2701         .data_size              = 0, /* No DMA required for beacons */
2702         .desc_size              = TXINFO_SIZE,
2703         .priv_size              = sizeof(struct queue_entry_priv_pci),
2704 };
2705
2706 static const struct rt2x00_ops rt61pci_ops = {
2707         .name           = KBUILD_MODNAME,
2708         .max_sta_intf   = 1,
2709         .max_ap_intf    = 4,
2710         .eeprom_size    = EEPROM_SIZE,
2711         .rf_size        = RF_SIZE,
2712         .tx_queues      = NUM_TX_QUEUES,
2713         .rx             = &rt61pci_queue_rx,
2714         .tx             = &rt61pci_queue_tx,
2715         .bcn            = &rt61pci_queue_bcn,
2716         .lib            = &rt61pci_rt2x00_ops,
2717         .hw             = &rt61pci_mac80211_ops,
2718 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2719         .debugfs        = &rt61pci_rt2x00debug,
2720 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2721 };
2722
2723 /*
2724  * RT61pci module information.
2725  */
2726 static struct pci_device_id rt61pci_device_table[] = {
2727         /* RT2561s */
2728         { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2729         /* RT2561 v2 */
2730         { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2731         /* RT2661 */
2732         { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2733         { 0, }
2734 };
2735
2736 MODULE_AUTHOR(DRV_PROJECT);
2737 MODULE_VERSION(DRV_VERSION);
2738 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2739 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2740                         "PCI & PCMCIA chipset based cards");
2741 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2742 MODULE_FIRMWARE(FIRMWARE_RT2561);
2743 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2744 MODULE_FIRMWARE(FIRMWARE_RT2661);
2745 MODULE_LICENSE("GPL");
2746
2747 static struct pci_driver rt61pci_driver = {
2748         .name           = KBUILD_MODNAME,
2749         .id_table       = rt61pci_device_table,
2750         .probe          = rt2x00pci_probe,
2751         .remove         = __devexit_p(rt2x00pci_remove),
2752         .suspend        = rt2x00pci_suspend,
2753         .resume         = rt2x00pci_resume,
2754 };
2755
2756 static int __init rt61pci_init(void)
2757 {
2758         return pci_register_driver(&rt61pci_driver);
2759 }
2760
2761 static void __exit rt61pci_exit(void)
2762 {
2763         pci_unregister_driver(&rt61pci_driver);
2764 }
2765
2766 module_init(rt61pci_init);
2767 module_exit(rt61pci_exit);