SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/rt2x00/rt2800usb.c

   1 /*
   2         Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2800usb
  23         Abstract: rt2800usb device specific routines.
  24         Supported chipsets: RT2800U.
  25  */
  26
  27 #include <linux/crc-ccitt.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/usb.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00usb.h"
  37 #include "rt2800lib.h"
  38 #include "rt2800usb.h"
  39
  40 /*
  41  * Allow hardware encryption to be disabled.
  42  */
  43 static int modparam_nohwcrypt = 1;
  44 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  45 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  46
  47 /*
  48  * Register access.
  49  * All access to the CSR registers will go through the methods
  50  * rt2800_register_read and rt2800_register_write.
  51  * BBP and RF register require indirect register access,
  52  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  53  * These indirect registers work with busy bits,
  54  * and we will try maximal REGISTER_BUSY_COUNT times to access
  55  * the register while taking a REGISTER_BUSY_DELAY us delay
  56  * between each attampt. When the busy bit is still set at that time,
  57  * the access attempt is considered to have failed,
  58  * and we will print an error.
  59  * The _lock versions must be used if you already hold the csr_mutex
  60  */
  61 #define WAIT_FOR_BBP(__dev, __reg) \
  62         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  63 #define WAIT_FOR_RFCSR(__dev, __reg) \
  64         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  65 #define WAIT_FOR_RF(__dev, __reg) \
  66         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  67 #define WAIT_FOR_MCU(__dev, __reg) \
  68         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  69                             H2M_MAILBOX_CSR_OWNER, (__reg))
  70
  71 static void rt2800usb_bbp_write(struct rt2x00_dev *rt2x00dev,
  72                                 const unsigned int word, const u8 value)
  73 {
  74         u32 reg;
  75
  76         mutex_lock(&rt2x00dev->csr_mutex);
  77
  78         /*
  79          * Wait until the BBP becomes available, afterwards we
  80          * can safely write the new data into the register.
  81          */
  82         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  83                 reg = 0;
  84                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
  85                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  86                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  87                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
  88
  89                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
  90         }
  91
  92         mutex_unlock(&rt2x00dev->csr_mutex);
  93 }
  94
  95 static void rt2800usb_bbp_read(struct rt2x00_dev *rt2x00dev,
  96                                const unsigned int word, u8 *value)
  97 {
  98         u32 reg;
  99
 100         mutex_lock(&rt2x00dev->csr_mutex);
 101
 102         /*
 103          * Wait until the BBP becomes available, afterwards we
 104          * can safely write the read request into the register.
 105          * After the data has been written, we wait until hardware
 106          * returns the correct value, if at any time the register
 107          * doesn't become available in time, reg will be 0xffffffff
 108          * which means we return 0xff to the caller.
 109          */
 110         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 111                 reg = 0;
 112                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 113                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 114                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 115
 116                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 117
 118                 WAIT_FOR_BBP(rt2x00dev, &reg);
 119         }
 120
 121         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 122
 123         mutex_unlock(&rt2x00dev->csr_mutex);
 124 }
 125
 126 static inline void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
 127                                     const unsigned int word, const u8 value)
 128 {
 129         rt2800usb_bbp_write(rt2x00dev, word, value);
 130 }
 131
 132 static inline void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 133                                    const unsigned int word, u8 *value)
 134 {
 135         rt2800usb_bbp_read(rt2x00dev, word, value);
 136 }
 137
 138 static void rt2800usb_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 139                                   const unsigned int word, const u8 value)
 140 {
 141         u32 reg;
 142
 143         mutex_lock(&rt2x00dev->csr_mutex);
 144
 145         /*
 146          * Wait until the RFCSR becomes available, afterwards we
 147          * can safely write the new data into the register.
 148          */
 149         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 150                 reg = 0;
 151                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 152                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 153                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 154                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 155
 156                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 157         }
 158
 159         mutex_unlock(&rt2x00dev->csr_mutex);
 160 }
 161
 162 static void rt2800usb_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 163                                  const unsigned int word, u8 *value)
 164 {
 165         u32 reg;
 166
 167         mutex_lock(&rt2x00dev->csr_mutex);
 168
 169         /*
 170          * Wait until the RFCSR becomes available, afterwards we
 171          * can safely write the read request into the register.
 172          * After the data has been written, we wait until hardware
 173          * returns the correct value, if at any time the register
 174          * doesn't become available in time, reg will be 0xffffffff
 175          * which means we return 0xff to the caller.
 176          */
 177         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 178                 reg = 0;
 179                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 180                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 181                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 182
 183                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 184
 185                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 186         }
 187
 188         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 189
 190         mutex_unlock(&rt2x00dev->csr_mutex);
 191 }
 192
 193 static inline void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 194                                       const unsigned int word, const u8 value)
 195 {
 196         rt2800usb_rfcsr_write(rt2x00dev, word, value);
 197 }
 198
 199 static inline void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 200                                      const unsigned int word, u8 *value)
 201 {
 202         rt2800usb_rfcsr_read(rt2x00dev, word, value);
 203 }
 204
 205 static void rt2800usb_rf_write(struct rt2x00_dev *rt2x00dev,
 206                                const unsigned int word, const u32 value)
 207 {
 208         u32 reg;
 209
 210         mutex_lock(&rt2x00dev->csr_mutex);
 211
 212         /*
 213          * Wait until the RF becomes available, afterwards we
 214          * can safely write the new data into the register.
 215          */
 216         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 217                 reg = 0;
 218                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 219                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 220                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 221                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 222
 223                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 224                 rt2x00_rf_write(rt2x00dev, word, value);
 225         }
 226
 227         mutex_unlock(&rt2x00dev->csr_mutex);
 228 }
 229
 230 static inline void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 231                                    const unsigned int word, const u32 value)
 232 {
 233         rt2800usb_rf_write(rt2x00dev, word, value);
 234 }
 235
 236 static void rt2800usb_mcu_request(struct rt2x00_dev *rt2x00dev,
 237                                   const u8 command, const u8 token,
 238                                   const u8 arg0, const u8 arg1)
 239 {
 240         u32 reg;
 241
 242         mutex_lock(&rt2x00dev->csr_mutex);
 243
 244         /*
 245          * Wait until the MCU becomes available, afterwards we
 246          * can safely write the new data into the register.
 247          */
 248         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 249                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 250                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 251                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 252                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 253                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 254
 255                 reg = 0;
 256                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 257                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 258         }
 259
 260         mutex_unlock(&rt2x00dev->csr_mutex);
 261 }
 262
 263 static inline void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 264                                       const u8 command, const u8 token,
 265                                       const u8 arg0, const u8 arg1)
 266 {
 267         rt2800usb_mcu_request(rt2x00dev, command, token, arg0, arg1);
 268 }
 269
 270 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 271 static const struct rt2x00debug rt2800usb_rt2x00debug = {
 272         .owner  = THIS_MODULE,
 273         .csr    = {
 274                 .read           = rt2800_register_read,
 275                 .write          = rt2800_register_write,
 276                 .flags          = RT2X00DEBUGFS_OFFSET,
 277                 .word_base      = CSR_REG_BASE,
 278                 .word_size      = sizeof(u32),
 279                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 280         },
 281         .eeprom = {
 282                 .read           = rt2x00_eeprom_read,
 283                 .write          = rt2x00_eeprom_write,
 284                 .word_base      = EEPROM_BASE,
 285                 .word_size      = sizeof(u16),
 286                 .word_count     = EEPROM_SIZE / sizeof(u16),
 287         },
 288         .bbp    = {
 289                 .read           = rt2800_bbp_read,
 290                 .write          = rt2800_bbp_write,
 291                 .word_base      = BBP_BASE,
 292                 .word_size      = sizeof(u8),
 293                 .word_count     = BBP_SIZE / sizeof(u8),
 294         },
 295         .rf     = {
 296                 .read           = rt2x00_rf_read,
 297                 .write          = rt2800_rf_write,
 298                 .word_base      = RF_BASE,
 299                 .word_size      = sizeof(u32),
 300                 .word_count     = RF_SIZE / sizeof(u32),
 301         },
 302 };
 303 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 304
 305 static int rt2800usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 306 {
 307         u32 reg;
 308
 309         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 310         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 311 }
 312
 313 #ifdef CONFIG_RT2X00_LIB_LEDS
 314 static void rt2800usb_brightness_set(struct led_classdev *led_cdev,
 315                                      enum led_brightness brightness)
 316 {
 317         struct rt2x00_led *led =
 318             container_of(led_cdev, struct rt2x00_led, led_dev);
 319         unsigned int enabled = brightness != LED_OFF;
 320         unsigned int bg_mode =
 321             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 322         unsigned int polarity =
 323                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 324                                    EEPROM_FREQ_LED_POLARITY);
 325         unsigned int ledmode =
 326                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 327                                    EEPROM_FREQ_LED_MODE);
 328
 329         if (led->type == LED_TYPE_RADIO) {
 330                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 331                                       enabled ? 0x20 : 0);
 332         } else if (led->type == LED_TYPE_ASSOC) {
 333                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 334                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 335         } else if (led->type == LED_TYPE_QUALITY) {
 336                 /*
 337                  * The brightness is divided into 6 levels (0 - 5),
 338                  * The specs tell us the following levels:
 339                  *      0, 1 ,3, 7, 15, 31
 340                  * to determine the level in a simple way we can simply
 341                  * work with bitshifting:
 342                  *      (1 << level) - 1
 343                  */
 344                 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 345                                       (1 << brightness / (LED_FULL / 6)) - 1,
 346                                       polarity);
 347         }
 348 }
 349
 350 static int rt2800usb_blink_set(struct led_classdev *led_cdev,
 351                                unsigned long *delay_on,
 352                                unsigned long *delay_off)
 353 {
 354         struct rt2x00_led *led =
 355             container_of(led_cdev, struct rt2x00_led, led_dev);
 356         u32 reg;
 357
 358         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 359         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 360         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 361         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
 362         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
 363         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
 364         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
 365         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
 366         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 367
 368         return 0;
 369 }
 370
 371 static void rt2800usb_init_led(struct rt2x00_dev *rt2x00dev,
 372                                struct rt2x00_led *led,
 373                                enum led_type type)
 374 {
 375         led->rt2x00dev = rt2x00dev;
 376         led->type = type;
 377         led->led_dev.brightness_set = rt2800usb_brightness_set;
 378         led->led_dev.blink_set = rt2800usb_blink_set;
 379         led->flags = LED_INITIALIZED;
 380 }
 381 #endif /* CONFIG_RT2X00_LIB_LEDS */
 382
 383 /*
 384  * Configuration handlers.
 385  */
 386 static void rt2800usb_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 387                                        struct rt2x00lib_crypto *crypto,
 388                                        struct ieee80211_key_conf *key)
 389 {
 390         struct mac_wcid_entry wcid_entry;
 391         struct mac_iveiv_entry iveiv_entry;
 392         u32 offset;
 393         u32 reg;
 394
 395         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 396
 397         rt2800_register_read(rt2x00dev, offset, &reg);
 398         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 399                            !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 400         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 401                            (crypto->cmd == SET_KEY) * crypto->cipher);
 402         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 403                            (crypto->cmd == SET_KEY) * crypto->bssidx);
 404         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 405         rt2800_register_write(rt2x00dev, offset, reg);
 406
 407         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 408
 409         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 410         if ((crypto->cipher == CIPHER_TKIP) ||
 411             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 412             (crypto->cipher == CIPHER_AES))
 413                 iveiv_entry.iv[3] |= 0x20;
 414         iveiv_entry.iv[3] |= key->keyidx << 6;
 415         rt2800_register_multiwrite(rt2x00dev, offset,
 416                                       &iveiv_entry, sizeof(iveiv_entry));
 417
 418         offset = MAC_WCID_ENTRY(key->hw_key_idx);
 419
 420         memset(&wcid_entry, 0, sizeof(wcid_entry));
 421         if (crypto->cmd == SET_KEY)
 422                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 423         rt2800_register_multiwrite(rt2x00dev, offset,
 424                                       &wcid_entry, sizeof(wcid_entry));
 425 }
 426
 427 static int rt2800usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
 428                                        struct rt2x00lib_crypto *crypto,
 429                                        struct ieee80211_key_conf *key)
 430 {
 431         struct hw_key_entry key_entry;
 432         struct rt2x00_field32 field;
 433         u32 offset;
 434         u32 reg;
 435
 436         if (crypto->cmd == SET_KEY) {
 437                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 438
 439                 memcpy(key_entry.key, crypto->key,
 440                        sizeof(key_entry.key));
 441                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 442                        sizeof(key_entry.tx_mic));
 443                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 444                        sizeof(key_entry.rx_mic));
 445
 446                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 447                 rt2800_register_multiwrite(rt2x00dev, offset,
 448                                               &key_entry, sizeof(key_entry));
 449         }
 450
 451         /*
 452          * The cipher types are stored over multiple registers
 453          * starting with SHARED_KEY_MODE_BASE each word will have
 454          * 32 bits and contains the cipher types for 2 bssidx each.
 455          * Using the correct defines correctly will cause overhead,
 456          * so just calculate the correct offset.
 457          */
 458         field.bit_offset = 4 * (key->hw_key_idx % 8);
 459         field.bit_mask = 0x7 << field.bit_offset;
 460
 461         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
 462
 463         rt2800_register_read(rt2x00dev, offset, &reg);
 464         rt2x00_set_field32(&reg, field,
 465                            (crypto->cmd == SET_KEY) * crypto->cipher);
 466         rt2800_register_write(rt2x00dev, offset, reg);
 467
 468         /*
 469          * Update WCID information
 470          */
 471         rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
 472
 473         return 0;
 474 }
 475
 476 static int rt2800usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 477                                          struct rt2x00lib_crypto *crypto,
 478                                          struct ieee80211_key_conf *key)
 479 {
 480         struct hw_key_entry key_entry;
 481         u32 offset;
 482
 483         if (crypto->cmd == SET_KEY) {
 484                 /*
 485                  * 1 pairwise key is possible per AID, this means that the AID
 486                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
 487                  * last possible shared key entry.
 488                  */
 489                 if (crypto->aid > (256 - 32))
 490                         return -ENOSPC;
 491
 492                 key->hw_key_idx = 32 + crypto->aid;
 493
 494                 memcpy(key_entry.key, crypto->key,
 495                        sizeof(key_entry.key));
 496                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 497                        sizeof(key_entry.tx_mic));
 498                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 499                        sizeof(key_entry.rx_mic));
 500
 501                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 502                 rt2800_register_multiwrite(rt2x00dev, offset,
 503                                               &key_entry, sizeof(key_entry));
 504         }
 505
 506         /*
 507          * Update WCID information
 508          */
 509         rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
 510
 511         return 0;
 512 }
 513
 514 static void rt2800usb_config_filter(struct rt2x00_dev *rt2x00dev,
 515                                     const unsigned int filter_flags)
 516 {
 517         u32 reg;
 518
 519         /*
 520          * Start configuration steps.
 521          * Note that the version error will always be dropped
 522          * and broadcast frames will always be accepted since
 523          * there is no filter for it at this time.
 524          */
 525         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
 526         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 527                            !(filter_flags & FIF_FCSFAIL));
 528         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 529                            !(filter_flags & FIF_PLCPFAIL));
 530         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 531                            !(filter_flags & FIF_PROMISC_IN_BSS));
 532         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
 533         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 534         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 535                            !(filter_flags & FIF_ALLMULTI));
 536         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 537         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 538         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 539                            !(filter_flags & FIF_CONTROL));
 540         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 541                            !(filter_flags & FIF_CONTROL));
 542         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 543                            !(filter_flags & FIF_CONTROL));
 544         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 545                            !(filter_flags & FIF_CONTROL));
 546         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 547                            !(filter_flags & FIF_CONTROL));
 548         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 549                            !(filter_flags & FIF_PSPOLL));
 550         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
 551         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
 552         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 553                            !(filter_flags & FIF_CONTROL));
 554         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 555 }
 556
 557 static void rt2800usb_config_intf(struct rt2x00_dev *rt2x00dev,
 558                                   struct rt2x00_intf *intf,
 559                                   struct rt2x00intf_conf *conf,
 560                                   const unsigned int flags)
 561 {
 562         unsigned int beacon_base;
 563         u32 reg;
 564
 565         if (flags & CONFIG_UPDATE_TYPE) {
 566                 /*
 567                  * Clear current synchronisation setup.
 568                  * For the Beacon base registers we only need to clear
 569                  * the first byte since that byte contains the VALID and OWNER
 570                  * bits which (when set to 0) will invalidate the entire beacon.
 571                  */
 572                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 573                 rt2800_register_write(rt2x00dev, beacon_base, 0);
 574
 575                 /*
 576                  * Enable synchronisation.
 577                  */
 578                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 579                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 580                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 581                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 582                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 583         }
 584
 585         if (flags & CONFIG_UPDATE_MAC) {
 586                 reg = le32_to_cpu(conf->mac[1]);
 587                 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 588                 conf->mac[1] = cpu_to_le32(reg);
 589
 590                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 591                                               conf->mac, sizeof(conf->mac));
 592         }
 593
 594         if (flags & CONFIG_UPDATE_BSSID) {
 595                 reg = le32_to_cpu(conf->bssid[1]);
 596                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
 597                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 598                 conf->bssid[1] = cpu_to_le32(reg);
 599
 600                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 601                                               conf->bssid, sizeof(conf->bssid));
 602         }
 603 }
 604
 605 static void rt2800usb_config_erp(struct rt2x00_dev *rt2x00dev,
 606                                  struct rt2x00lib_erp *erp)
 607 {
 608         u32 reg;
 609
 610         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
 611         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
 612         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
 613
 614         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
 615         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
 616                            !!erp->short_preamble);
 617         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 618                            !!erp->short_preamble);
 619         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 620
 621         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
 622         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 623                            erp->cts_protection ? 2 : 0);
 624         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 625
 626         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 627                                  erp->basic_rates);
 628         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
 629
 630         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
 631         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
 632         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
 633         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 634
 635         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
 636         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
 637         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
 638         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
 639         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 640         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
 641         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 642
 643         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 644         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 645                            erp->beacon_int * 16);
 646         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 647 }
 648
 649 static void rt2800usb_config_ant(struct rt2x00_dev *rt2x00dev,
 650                                  struct antenna_setup *ant)
 651 {
 652         u8 r1;
 653         u8 r3;
 654
 655         rt2800_bbp_read(rt2x00dev, 1, &r1);
 656         rt2800_bbp_read(rt2x00dev, 3, &r3);
 657
 658         /*
 659          * Configure the TX antenna.
 660          */
 661         switch ((int)ant->tx) {
 662         case 1:
 663                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
 664                 break;
 665         case 2:
 666                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
 667                 break;
 668         case 3:
 669                 /* Do nothing */
 670                 break;
 671         }
 672
 673         /*
 674          * Configure the RX antenna.
 675          */
 676         switch ((int)ant->rx) {
 677         case 1:
 678                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 679                 break;
 680         case 2:
 681                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 682                 break;
 683         case 3:
 684                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 685                 break;
 686         }
 687
 688         rt2800_bbp_write(rt2x00dev, 3, r3);
 689         rt2800_bbp_write(rt2x00dev, 1, r1);
 690 }
 691
 692 static void rt2800usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 693                                       struct rt2x00lib_conf *libconf)
 694 {
 695         u16 eeprom;
 696         short lna_gain;
 697
 698         if (libconf->rf.channel <= 14) {
 699                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 700                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 701         } else if (libconf->rf.channel <= 64) {
 702                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 703                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 704         } else if (libconf->rf.channel <= 128) {
 705                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 706                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
 707         } else {
 708                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 709                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
 710         }
 711
 712         rt2x00dev->lna_gain = lna_gain;
 713 }
 714
 715 static void rt2800usb_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
 716                                           struct ieee80211_conf *conf,
 717                                           struct rf_channel *rf,
 718                                           struct channel_info *info)
 719 {
 720         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 721
 722         if (rt2x00dev->default_ant.tx == 1)
 723                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 724
 725         if (rt2x00dev->default_ant.rx == 1) {
 726                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 727                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 728         } else if (rt2x00dev->default_ant.rx == 2)
 729                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 730
 731         if (rf->channel > 14) {
 732                 /*
 733                  * When TX power is below 0, we should increase it by 7 to
 734                  * make it a positive value (Minumum value is -7).
 735                  * However this means that values between 0 and 7 have
 736                  * double meaning, and we should set a 7DBm boost flag.
 737                  */
 738                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 739                                    (info->tx_power1 >= 0));
 740
 741                 if (info->tx_power1 < 0)
 742                         info->tx_power1 += 7;
 743
 744                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
 745                                    TXPOWER_A_TO_DEV(info->tx_power1));
 746
 747                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 748                                    (info->tx_power2 >= 0));
 749
 750                 if (info->tx_power2 < 0)
 751                         info->tx_power2 += 7;
 752
 753                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
 754                                    TXPOWER_A_TO_DEV(info->tx_power2));
 755         } else {
 756                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
 757                                    TXPOWER_G_TO_DEV(info->tx_power1));
 758                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
 759                                    TXPOWER_G_TO_DEV(info->tx_power2));
 760         }
 761
 762         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
 763
 764         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 765         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 766         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 767         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 768
 769         udelay(200);
 770
 771         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 772         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 773         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 774         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 775
 776         udelay(200);
 777
 778         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 779         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 780         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 781         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 782 }
 783
 784 static void rt2800usb_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
 785                                           struct ieee80211_conf *conf,
 786                                           struct rf_channel *rf,
 787                                           struct channel_info *info)
 788 {
 789         u8 rfcsr;
 790
 791         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
 792         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf3);
 793
 794         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
 795         rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
 796         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
 797
 798         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
 799         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
 800                           TXPOWER_G_TO_DEV(info->tx_power1));
 801         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
 802
 803         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
 804         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 805         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
 806
 807         rt2800_rfcsr_write(rt2x00dev, 24,
 808                               rt2x00dev->calibration[conf_is_ht40(conf)]);
 809
 810         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
 811         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 812         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
 813 }
 814
 815 static void rt2800usb_config_channel(struct rt2x00_dev *rt2x00dev,
 816                                      struct ieee80211_conf *conf,
 817                                      struct rf_channel *rf,
 818                                      struct channel_info *info)
 819 {
 820         u32 reg;
 821         unsigned int tx_pin;
 822         u8 bbp;
 823
 824         if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
 825                 rt2800usb_config_channel_rt2x(rt2x00dev, conf, rf, info);
 826         else
 827                 rt2800usb_config_channel_rt3x(rt2x00dev, conf, rf, info);
 828
 829         /*
 830          * Change BBP settings
 831          */
 832         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 833         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 834         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 835         rt2800_bbp_write(rt2x00dev, 86, 0);
 836
 837         if (rf->channel <= 14) {
 838                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 839                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
 840                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 841                 } else {
 842                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
 843                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 844                 }
 845         } else {
 846                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
 847
 848                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 849                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 850                 else
 851                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 852         }
 853
 854         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 855         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
 856         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
 857         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
 858         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
 859
 860         tx_pin = 0;
 861
 862         /* Turn on unused PA or LNA when not using 1T or 1R */
 863         if (rt2x00dev->default_ant.tx != 1) {
 864                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
 865                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 866         }
 867
 868         /* Turn on unused PA or LNA when not using 1T or 1R */
 869         if (rt2x00dev->default_ant.rx != 1) {
 870                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 871                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 872         }
 873
 874         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
 875         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
 876         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 877         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 878         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
 879         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
 880
 881         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 882
 883         rt2800_bbp_read(rt2x00dev, 4, &bbp);
 884         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
 885         rt2800_bbp_write(rt2x00dev, 4, bbp);
 886
 887         rt2800_bbp_read(rt2x00dev, 3, &bbp);
 888         rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
 889         rt2800_bbp_write(rt2x00dev, 3, bbp);
 890
 891         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
 892                 if (conf_is_ht40(conf)) {
 893                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
 894                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
 895                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
 896                 } else {
 897                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
 898                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
 899                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
 900                 }
 901         }
 902
 903         msleep(1);
 904 }
 905
 906 static void rt2800usb_config_txpower(struct rt2x00_dev *rt2x00dev,
 907                                      const int txpower)
 908 {
 909         u32 reg;
 910         u32 value = TXPOWER_G_TO_DEV(txpower);
 911         u8 r1;
 912
 913         rt2800_bbp_read(rt2x00dev, 1, &r1);
 914         rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
 915         rt2800_bbp_write(rt2x00dev, 1, r1);
 916
 917         rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
 918         rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
 919         rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
 920         rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
 921         rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
 922         rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
 923         rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
 924         rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
 925         rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
 926         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
 927
 928         rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
 929         rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
 930         rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
 931         rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
 932         rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
 933         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
 934         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
 935         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
 936         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
 937         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
 938
 939         rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
 940         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
 941         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
 942         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
 943         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
 944         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
 945         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
 946         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
 947         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
 948         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
 949
 950         rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
 951         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
 952         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
 953         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
 954         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
 955         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
 956         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
 957         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
 958         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
 959         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
 960
 961         rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
 962         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
 963         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
 964         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
 965         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
 966         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
 967 }
 968
 969 static void rt2800usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 970                                          struct rt2x00lib_conf *libconf)
 971 {
 972         u32 reg;
 973
 974         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
 975         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
 976                            libconf->conf->short_frame_max_tx_count);
 977         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
 978                            libconf->conf->long_frame_max_tx_count);
 979         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
 980         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
 981         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
 982         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
 983         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
 984 }
 985
 986 static void rt2800usb_config_ps(struct rt2x00_dev *rt2x00dev,
 987                                 struct rt2x00lib_conf *libconf)
 988 {
 989         enum dev_state state =
 990             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 991                 STATE_SLEEP : STATE_AWAKE;
 992         u32 reg;
 993
 994         if (state == STATE_SLEEP) {
 995                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
 996
 997                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
 998                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
 999                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1000                                    libconf->conf->listen_interval - 1);
1001                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1002                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1003
1004                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1005         } else {
1006                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1007
1008                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1009                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1010                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1011                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1012                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1013         }
1014 }
1015
1016 static void rt2800usb_config(struct rt2x00_dev *rt2x00dev,
1017                              struct rt2x00lib_conf *libconf,
1018                              const unsigned int flags)
1019 {
1020         /* Always recalculate LNA gain before changing configuration */
1021         rt2800usb_config_lna_gain(rt2x00dev, libconf);
1022
1023         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1024                 rt2800usb_config_channel(rt2x00dev, libconf->conf,
1025                                          &libconf->rf, &libconf->channel);
1026         if (flags & IEEE80211_CONF_CHANGE_POWER)
1027                 rt2800usb_config_txpower(rt2x00dev, libconf->conf->power_level);
1028         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1029                 rt2800usb_config_retry_limit(rt2x00dev, libconf);
1030         if (flags & IEEE80211_CONF_CHANGE_PS)
1031                 rt2800usb_config_ps(rt2x00dev, libconf);
1032 }
1033
1034 /*
1035  * Link tuning
1036  */
1037 static void rt2800usb_link_stats(struct rt2x00_dev *rt2x00dev,
1038                                  struct link_qual *qual)
1039 {
1040         u32 reg;
1041
1042         /*
1043          * Update FCS error count from register.
1044          */
1045         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1046         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1047 }
1048
1049 static u8 rt2800usb_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1050 {
1051         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1052                 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
1053                         return 0x1c + (2 * rt2x00dev->lna_gain);
1054                 else
1055                         return 0x2e + rt2x00dev->lna_gain;
1056         }
1057
1058         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1059                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1060         else
1061                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1062 }
1063
1064 static inline void rt2800usb_set_vgc(struct rt2x00_dev *rt2x00dev,
1065                                      struct link_qual *qual, u8 vgc_level)
1066 {
1067         if (qual->vgc_level != vgc_level) {
1068                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1069                 qual->vgc_level = vgc_level;
1070                 qual->vgc_level_reg = vgc_level;
1071         }
1072 }
1073
1074 static void rt2800usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
1075                                   struct link_qual *qual)
1076 {
1077         rt2800usb_set_vgc(rt2x00dev, qual,
1078                           rt2800usb_get_default_vgc(rt2x00dev));
1079 }
1080
1081 static void rt2800usb_link_tuner(struct rt2x00_dev *rt2x00dev,
1082                                  struct link_qual *qual, const u32 count)
1083 {
1084         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1085                 return;
1086
1087         /*
1088          * When RSSI is better then -80 increase VGC level with 0x10
1089          */
1090         rt2800usb_set_vgc(rt2x00dev, qual,
1091                           rt2800usb_get_default_vgc(rt2x00dev) +
1092                           ((qual->rssi > -80) * 0x10));
1093 }
1094
1095 /*
1096  * Firmware functions
1097  */
1098 static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1099 {
1100         return FIRMWARE_RT2870;
1101 }
1102
1103 static bool rt2800usb_check_crc(const u8 *data, const size_t len)
1104 {
1105         u16 fw_crc;
1106         u16 crc;
1107
1108         /*
1109          * The last 2 bytes in the firmware array are the crc checksum itself,
1110          * this means that we should never pass those 2 bytes to the crc
1111          * algorithm.
1112          */
1113         fw_crc = (data[len - 2] << 8 | data[len - 1]);
1114
1115         /*
1116          * Use the crc ccitt algorithm.
1117          * This will return the same value as the legacy driver which
1118          * used bit ordering reversion on the both the firmware bytes
1119          * before input input as well as on the final output.
1120          * Obviously using crc ccitt directly is much more efficient.
1121          */
1122         crc = crc_ccitt(~0, data, len - 2);
1123
1124         /*
1125          * There is a small difference between the crc-itu-t + bitrev and
1126          * the crc-ccitt crc calculation. In the latter method the 2 bytes
1127          * will be swapped, use swab16 to convert the crc to the correct
1128          * value.
1129          */
1130         crc = swab16(crc);
1131
1132         return fw_crc == crc;
1133 }
1134
1135 static int rt2800usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1136                                     const u8 *data, const size_t len)
1137 {
1138         u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1139         size_t offset = 0;
1140
1141         /*
1142          * Firmware files:
1143          * There are 2 variations of the rt2870 firmware.
1144          * a) size: 4kb
1145          * b) size: 8kb
1146          * Note that (b) contains 2 seperate firmware blobs of 4k
1147          * within the file. The first blob is the same firmware as (a),
1148          * but the second blob is for the additional chipsets.
1149          */
1150         if (len != 4096 && len != 8192)
1151                 return FW_BAD_LENGTH;
1152
1153         /*
1154          * Check if we need the upper 4kb firmware data or not.
1155          */
1156         if ((len == 4096) &&
1157             (chipset != 0x2860) &&
1158             (chipset != 0x2872) &&
1159             (chipset != 0x3070))
1160                 return FW_BAD_VERSION;
1161
1162         /*
1163          * 8kb firmware files must be checked as if it were
1164          * 2 seperate firmware files.
1165          */
1166         while (offset < len) {
1167                 if (!rt2800usb_check_crc(data + offset, 4096))
1168                         return FW_BAD_CRC;
1169
1170                 offset += 4096;
1171         }
1172
1173         return FW_OK;
1174 }
1175
1176 static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1177                                    const u8 *data, const size_t len)
1178 {
1179         unsigned int i;
1180         int status;
1181         u32 reg;
1182         u32 offset;
1183         u32 length;
1184         u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1185
1186         /*
1187          * Check which section of the firmware we need.
1188          */
1189         if ((chipset == 0x2860) ||
1190             (chipset == 0x2872) ||
1191             (chipset == 0x3070)) {
1192                 offset = 0;
1193                 length = 4096;
1194         } else {
1195                 offset = 4096;
1196                 length = 4096;
1197         }
1198
1199         /*
1200          * Wait for stable hardware.
1201          */
1202         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1203                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1204                 if (reg && reg != ~0)
1205                         break;
1206                 msleep(1);
1207         }
1208
1209         if (i == REGISTER_BUSY_COUNT) {
1210                 ERROR(rt2x00dev, "Unstable hardware.\n");
1211                 return -EBUSY;
1212         }
1213
1214         /*
1215          * Write firmware to device.
1216          */
1217         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1218                                             USB_VENDOR_REQUEST_OUT,
1219                                             FIRMWARE_IMAGE_BASE,
1220                                             data + offset, length,
1221                                             REGISTER_TIMEOUT32(length));
1222
1223         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
1224         rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
1225
1226         /*
1227          * Send firmware request to device to load firmware,
1228          * we need to specify a long timeout time.
1229          */
1230         status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1231                                              0, USB_MODE_FIRMWARE,
1232                                              REGISTER_TIMEOUT_FIRMWARE);
1233         if (status < 0) {
1234                 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1235                 return status;
1236         }
1237
1238         msleep(10);
1239         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1240
1241         /*
1242          * Send signal to firmware during boot time.
1243          */
1244         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1245
1246         if ((chipset == 0x3070) ||
1247             (chipset == 0x3071) ||
1248             (chipset == 0x3572)) {
1249                 udelay(200);
1250                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
1251                 udelay(10);
1252         }
1253
1254         /*
1255          * Wait for device to stabilize.
1256          */
1257         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1258                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1259                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1260                         break;
1261                 msleep(1);
1262         }
1263
1264         if (i == REGISTER_BUSY_COUNT) {
1265                 ERROR(rt2x00dev, "PBF system register not ready.\n");
1266                 return -EBUSY;
1267         }
1268
1269         /*
1270          * Initialize firmware.
1271          */
1272         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1273         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1274         msleep(1);
1275
1276         return 0;
1277 }
1278
1279 /*
1280  * Initialization functions.
1281  */
1282 static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
1283 {
1284         u32 reg;
1285         unsigned int i;
1286
1287         /*
1288          * Wait untill BBP and RF are ready.
1289          */
1290         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1291                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1292                 if (reg && reg != ~0)
1293                         break;
1294                 msleep(1);
1295         }
1296
1297         if (i == REGISTER_BUSY_COUNT) {
1298                 ERROR(rt2x00dev, "Unstable hardware.\n");
1299                 return -EBUSY;
1300         }
1301
1302         rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1303         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000);
1304
1305         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1306         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1307         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1308         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1309
1310         rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1311
1312         rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1313                                     USB_MODE_RESET, REGISTER_TIMEOUT);
1314
1315         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1316
1317         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1318         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1319         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1320         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1321         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1322         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1323
1324         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1325         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1326         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1327         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1328         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1329         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1330
1331         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1332         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1333
1334         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1335
1336         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1337         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1338         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1339         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1340         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1341         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1342         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1343         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1344
1345         if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1346                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1347                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1348                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1349         } else {
1350                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1351                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1352         }
1353
1354         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1355         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1356         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1357         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1358         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1359         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1360         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1361         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1362         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1363         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1364
1365         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1366         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1367         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1368         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1369
1370         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1371         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1372         if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1373             rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1374                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1375         else
1376                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1377         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1378         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1379         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1380
1381         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1382
1383         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1384         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1385         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1386         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1387         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1388         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1389         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1390
1391         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1392         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1393         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1394         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1395         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1396         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1397         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1398         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1399         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1400         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1401         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1402
1403         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1404         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1405         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1406         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1407         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1408         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1409         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1410         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1411         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1412         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1413         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1414
1415         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1416         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1417         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1418         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1419         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1420         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1421         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1422         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1423         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1424         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1425         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1426
1427         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1428         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1429         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1430         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1431         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1432         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1433         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1434         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1435         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1436         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1437         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1438
1439         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1440         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1441         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1442         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1443         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1444         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1445         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1446         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1447         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1448         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1449         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1450
1451         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1452         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1453         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1454         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1455         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1456         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1457         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1458         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1459         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1460         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1461         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1462
1463         rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1464
1465         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1466         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1467         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1468         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1469         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1470         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1471         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1472         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1473         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1474         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1475         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1476
1477         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1478         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1479
1480         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1481         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1482         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1483                            IEEE80211_MAX_RTS_THRESHOLD);
1484         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1485         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1486
1487         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1488         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1489
1490         /*
1491          * ASIC will keep garbage value after boot, clear encryption keys.
1492          */
1493         for (i = 0; i < 4; i++)
1494                 rt2800_register_write(rt2x00dev,
1495                                          SHARED_KEY_MODE_ENTRY(i), 0);
1496
1497         for (i = 0; i < 256; i++) {
1498                 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1499                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1500                                               wcid, sizeof(wcid));
1501
1502                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1503                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1504         }
1505
1506         /*
1507          * Clear all beacons
1508          * For the Beacon base registers we only need to clear
1509          * the first byte since that byte contains the VALID and OWNER
1510          * bits which (when set to 0) will invalidate the entire beacon.
1511          */
1512         rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1513         rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1514         rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1515         rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1516         rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1517         rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1518         rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1519         rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1520
1521         rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1522         rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1523         rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1524
1525         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1526         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1527         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1528         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1529         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1530         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1531         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1532         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1533         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1534         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1535
1536         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1537         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1538         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1539         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1540         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1541         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1542         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1543         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1544         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1545         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1546
1547         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1548         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1549         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1550         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1551         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1552         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1553         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1554         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1555         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1556         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1557
1558         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1559         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1560         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1561         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1562         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1563         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1564
1565         /*
1566          * We must clear the error counters.
1567          * These registers are cleared on read,
1568          * so we may pass a useless variable to store the value.
1569          */
1570         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1571         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1572         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1573         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1574         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1575         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1576
1577         return 0;
1578 }
1579
1580 static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1581 {
1582         unsigned int i;
1583         u32 reg;
1584
1585         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1586                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1587                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1588                         return 0;
1589
1590                 udelay(REGISTER_BUSY_DELAY);
1591         }
1592
1593         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1594         return -EACCES;
1595 }
1596
1597 static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1598 {
1599         unsigned int i;
1600         u8 value;
1601
1602         /*
1603          * BBP was enabled after firmware was loaded,
1604          * but we need to reactivate it now.
1605          */
1606         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1607         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1608         msleep(1);
1609
1610         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1611                 rt2800_bbp_read(rt2x00dev, 0, &value);
1612                 if ((value != 0xff) && (value != 0x00))
1613                         return 0;
1614                 udelay(REGISTER_BUSY_DELAY);
1615         }
1616
1617         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1618         return -EACCES;
1619 }
1620
1621 static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1622 {
1623         unsigned int i;
1624         u16 eeprom;
1625         u8 reg_id;
1626         u8 value;
1627
1628         if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
1629                      rt2800usb_wait_bbp_ready(rt2x00dev)))
1630                 return -EACCES;
1631
1632         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1633         rt2800_bbp_write(rt2x00dev, 66, 0x38);
1634         rt2800_bbp_write(rt2x00dev, 69, 0x12);
1635         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1636         rt2800_bbp_write(rt2x00dev, 73, 0x10);
1637         rt2800_bbp_write(rt2x00dev, 81, 0x37);
1638         rt2800_bbp_write(rt2x00dev, 82, 0x62);
1639         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1640         rt2800_bbp_write(rt2x00dev, 84, 0x99);
1641         rt2800_bbp_write(rt2x00dev, 86, 0x00);
1642         rt2800_bbp_write(rt2x00dev, 91, 0x04);
1643         rt2800_bbp_write(rt2x00dev, 92, 0x00);
1644         rt2800_bbp_write(rt2x00dev, 103, 0x00);
1645         rt2800_bbp_write(rt2x00dev, 105, 0x05);
1646
1647         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1648                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1649                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1650         }
1651
1652         if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION) {
1653                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1654         }
1655
1656         if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1657                 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1658                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1659                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1660         }
1661
1662         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1663                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1664
1665                 if (eeprom != 0xffff && eeprom != 0x0000) {
1666                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1667                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1668                         rt2800_bbp_write(rt2x00dev, reg_id, value);
1669                 }
1670         }
1671
1672         return 0;
1673 }
1674
1675 static u8 rt2800usb_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1676                                    bool bw40, u8 rfcsr24, u8 filter_target)
1677 {
1678         unsigned int i;
1679         u8 bbp;
1680         u8 rfcsr;
1681         u8 passband;
1682         u8 stopband;
1683         u8 overtuned = 0;
1684
1685         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1686
1687         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1688         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1689         rt2800_bbp_write(rt2x00dev, 4, bbp);
1690
1691         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1692         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1693         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1694
1695         /*
1696          * Set power & frequency of passband test tone
1697          */
1698         rt2800_bbp_write(rt2x00dev, 24, 0);
1699
1700         for (i = 0; i < 100; i++) {
1701                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1702                 msleep(1);
1703
1704                 rt2800_bbp_read(rt2x00dev, 55, &passband);
1705                 if (passband)
1706                         break;
1707         }
1708
1709         /*
1710          * Set power & frequency of stopband test tone
1711          */
1712         rt2800_bbp_write(rt2x00dev, 24, 0x06);
1713
1714         for (i = 0; i < 100; i++) {
1715                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1716                 msleep(1);
1717
1718                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1719
1720                 if ((passband - stopband) <= filter_target) {
1721                         rfcsr24++;
1722                         overtuned += ((passband - stopband) == filter_target);
1723                 } else
1724                         break;
1725
1726                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1727         }
1728
1729         rfcsr24 -= !!overtuned;
1730
1731         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1732         return rfcsr24;
1733 }
1734
1735 static int rt2800usb_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1736 {
1737         u8 rfcsr;
1738         u8 bbp;
1739
1740         if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1741                 return 0;
1742
1743         /*
1744          * Init RF calibration.
1745          */
1746         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1747         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1748         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1749         msleep(1);
1750         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1751         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1752
1753         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1754         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1755         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1756         rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1757         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1758         rt2800_rfcsr_write(rt2x00dev, 10, 0x71);
1759         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1760         rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1761         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1762         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1763         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1764         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1765         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1766         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1767         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1768         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1769         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1770         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1771         rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1772         rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1773
1774         /*
1775          * Set RX Filter calibration for 20MHz and 40MHz
1776          */
1777         rt2x00dev->calibration[0] =
1778             rt2800usb_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1779         rt2x00dev->calibration[1] =
1780             rt2800usb_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1781
1782         /*
1783          * Set back to initial state
1784          */
1785         rt2800_bbp_write(rt2x00dev, 24, 0);
1786
1787         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1788         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1789         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1790
1791         /*
1792          * set BBP back to BW20
1793          */
1794         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1795         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1796         rt2800_bbp_write(rt2x00dev, 4, bbp);
1797
1798         return 0;
1799 }
1800
1801 /*
1802  * Device state switch handlers.
1803  */
1804 static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1805                                 enum dev_state state)
1806 {
1807         u32 reg;
1808
1809         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1810         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1811                            (state == STATE_RADIO_RX_ON) ||
1812                            (state == STATE_RADIO_RX_ON_LINK));
1813         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1814 }
1815
1816 static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1817 {
1818         unsigned int i;
1819         u32 reg;
1820
1821         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1822                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1823                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1824                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1825                         return 0;
1826
1827                 msleep(1);
1828         }
1829
1830         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1831         return -EACCES;
1832 }
1833
1834 static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1835 {
1836         u32 reg;
1837         u16 word;
1838
1839         /*
1840          * Initialize all registers.
1841          */
1842         if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) ||
1843                      rt2800usb_init_registers(rt2x00dev) ||
1844                      rt2800usb_init_bbp(rt2x00dev) ||
1845                      rt2800usb_init_rfcsr(rt2x00dev)))
1846                 return -EIO;
1847
1848         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1849         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1850         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1851
1852         udelay(50);
1853
1854         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1855         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1856         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1857         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1858         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1859
1860
1861         rt2800_register_read(rt2x00dev, USB_DMA_CFG, &reg);
1862         rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0);
1863         /* Don't use bulk in aggregation when working with USB 1.1 */
1864         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN,
1865                            (rt2x00dev->rx->usb_maxpacket == 512));
1866         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128);
1867         /*
1868          * Total room for RX frames in kilobytes, PBF might still exceed
1869          * this limit so reduce the number to prevent errors.
1870          */
1871         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_LIMIT,
1872                            ((RX_ENTRIES * DATA_FRAME_SIZE) / 1024) - 3);
1873         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1);
1874         rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1);
1875         rt2800_register_write(rt2x00dev, USB_DMA_CFG, reg);
1876
1877         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1878         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1879         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1880         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1881
1882         /*
1883          * Initialize LED control
1884          */
1885         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1886         rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1887                               word & 0xff, (word >> 8) & 0xff);
1888
1889         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1890         rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1891                               word & 0xff, (word >> 8) & 0xff);
1892
1893         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1894         rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1895                               word & 0xff, (word >> 8) & 0xff);
1896
1897         return 0;
1898 }
1899
1900 static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1901 {
1902         u32 reg;
1903
1904         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1905         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1906         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1907         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1908
1909         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1910         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1911         rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
1912
1913         /* Wait for DMA, ignore error */
1914         rt2800usb_wait_wpdma_ready(rt2x00dev);
1915
1916         rt2x00usb_disable_radio(rt2x00dev);
1917 }
1918
1919 static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
1920                                enum dev_state state)
1921 {
1922         if (state == STATE_AWAKE)
1923                 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1924         else
1925                 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1926
1927         return 0;
1928 }
1929
1930 static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1931                                       enum dev_state state)
1932 {
1933         int retval = 0;
1934
1935         switch (state) {
1936         case STATE_RADIO_ON:
1937                 /*
1938                  * Before the radio can be enabled, the device first has
1939                  * to be woken up. After that it needs a bit of time
1940                  * to be fully awake and then the radio can be enabled.
1941                  */
1942                 rt2800usb_set_state(rt2x00dev, STATE_AWAKE);
1943                 msleep(1);
1944                 retval = rt2800usb_enable_radio(rt2x00dev);
1945                 break;
1946         case STATE_RADIO_OFF:
1947                 /*
1948                  * After the radio has been disabled, the device should
1949                  * be put to sleep for powersaving.
1950                  */
1951                 rt2800usb_disable_radio(rt2x00dev);
1952                 rt2800usb_set_state(rt2x00dev, STATE_SLEEP);
1953                 break;
1954         case STATE_RADIO_RX_ON:
1955         case STATE_RADIO_RX_ON_LINK:
1956         case STATE_RADIO_RX_OFF:
1957         case STATE_RADIO_RX_OFF_LINK:
1958                 rt2800usb_toggle_rx(rt2x00dev, state);
1959                 break;
1960         case STATE_RADIO_IRQ_ON:
1961         case STATE_RADIO_IRQ_OFF:
1962                 /* No support, but no error either */
1963                 break;
1964         case STATE_DEEP_SLEEP:
1965         case STATE_SLEEP:
1966         case STATE_STANDBY:
1967         case STATE_AWAKE:
1968                 retval = rt2800usb_set_state(rt2x00dev, state);
1969                 break;
1970         default:
1971                 retval = -ENOTSUPP;
1972                 break;
1973         }
1974
1975         if (unlikely(retval))
1976                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1977                       state, retval);
1978
1979         return retval;
1980 }
1981
1982 /*
1983  * TX descriptor initialization
1984  */
1985 static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1986                                     struct sk_buff *skb,
1987                                     struct txentry_desc *txdesc)
1988 {
1989         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1990         __le32 *txi = skbdesc->desc;
1991         __le32 *txwi = &txi[TXINFO_DESC_SIZE / sizeof(__le32)];
1992         u32 word;
1993
1994         /*
1995          * Initialize TX Info descriptor
1996          */
1997         rt2x00_desc_read(txwi, 0, &word);
1998         rt2x00_set_field32(&word, TXWI_W0_FRAG,
1999                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
2000         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
2001         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
2002         rt2x00_set_field32(&word, TXWI_W0_TS,
2003                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
2004         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
2005                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
2006         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
2007         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
2008         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
2009         rt2x00_set_field32(&word, TXWI_W0_BW,
2010                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
2011         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
2012                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
2013         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
2014         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
2015         rt2x00_desc_write(txwi, 0, word);
2016
2017         rt2x00_desc_read(txwi, 1, &word);
2018         rt2x00_set_field32(&word, TXWI_W1_ACK,
2019                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
2020         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
2021                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
2022         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
2023         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
2024                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
2025                            txdesc->key_idx : 0xff);
2026         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
2027                            skb->len - txdesc->l2pad);
2028         rt2x00_set_field32(&word, TXWI_W1_PACKETID,
2029                            skbdesc->entry->queue->qid + 1);
2030         rt2x00_desc_write(txwi, 1, word);
2031
2032         /*
2033          * Always write 0 to IV/EIV fields, hardware will insert the IV
2034          * from the IVEIV register when TXINFO_W0_WIV is set to 0.
2035          * When TXINFO_W0_WIV is set to 1 it will use the IV data
2036          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
2037          * crypto entry in the registers should be used to encrypt the frame.
2038          */
2039         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
2040         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
2041
2042         /*
2043          * Initialize TX descriptor
2044          */
2045         rt2x00_desc_read(txi, 0, &word);
2046         rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,
2047                            skb->len + TXWI_DESC_SIZE);
2048         rt2x00_set_field32(&word, TXINFO_W0_WIV,
2049                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
2050         rt2x00_set_field32(&word, TXINFO_W0_QSEL, 2);
2051         rt2x00_set_field32(&word, TXINFO_W0_SW_USE_LAST_ROUND, 0);
2052         rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_NEXT_VALID, 0);
2053         rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_BURST,
2054                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
2055         rt2x00_desc_write(txi, 0, word);
2056 }
2057
2058 /*
2059  * TX data initialization
2060  */
2061 static void rt2800usb_write_beacon(struct queue_entry *entry)
2062 {
2063         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2064         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2065         unsigned int beacon_base;
2066         u32 reg;
2067
2068         /*
2069          * Add the descriptor in front of the skb.
2070          */
2071         skb_push(entry->skb, entry->queue->desc_size);
2072         memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
2073         skbdesc->desc = entry->skb->data;
2074
2075         /*
2076          * Disable beaconing while we are reloading the beacon data,
2077          * otherwise we might be sending out invalid data.
2078          */
2079         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2080         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2081         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2082
2083         /*
2084          * Write entire beacon with descriptor to register.
2085          */
2086         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2087         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
2088                                             USB_VENDOR_REQUEST_OUT, beacon_base,
2089                                             entry->skb->data, entry->skb->len,
2090                                             REGISTER_TIMEOUT32(entry->skb->len));
2091
2092         /*
2093          * Clean up the beacon skb.
2094          */
2095         dev_kfree_skb(entry->skb);
2096         entry->skb = NULL;
2097 }
2098
2099 static int rt2800usb_get_tx_data_len(struct queue_entry *entry)
2100 {
2101         int length;
2102
2103         /*
2104          * The length _must_ include 4 bytes padding,
2105          * it should always be multiple of 4,
2106          * but it must _not_ be a multiple of the USB packet size.
2107          */
2108         length = roundup(entry->skb->len + 4, 4);
2109         length += (4 * !(length % entry->queue->usb_maxpacket));
2110
2111         return length;
2112 }
2113
2114 static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2115                                     const enum data_queue_qid queue)
2116 {
2117         u32 reg;
2118
2119         if (queue != QID_BEACON) {
2120                 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
2121                 return;
2122         }
2123
2124         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2125         if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2126                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2127                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2128                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2129                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2130         }
2131 }
2132
2133 /*
2134  * RX control handlers
2135  */
2136 static void rt2800usb_fill_rxdone(struct queue_entry *entry,
2137                                   struct rxdone_entry_desc *rxdesc)
2138 {
2139         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2140         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2141         __le32 *rxd = (__le32 *)entry->skb->data;
2142         __le32 *rxwi;
2143         u32 rxd0;
2144         u32 rxwi0;
2145         u32 rxwi1;
2146         u32 rxwi2;
2147         u32 rxwi3;
2148
2149         /*
2150          * Copy descriptor to the skbdesc->desc buffer, making it safe from
2151          * moving of frame data in rt2x00usb.
2152          */
2153         memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
2154         rxd = (__le32 *)skbdesc->desc;
2155         rxwi = &rxd[RXINFO_DESC_SIZE / sizeof(__le32)];
2156
2157         /*
2158          * It is now safe to read the descriptor on all architectures.
2159          */
2160         rt2x00_desc_read(rxd, 0, &rxd0);
2161         rt2x00_desc_read(rxwi, 0, &rxwi0);
2162         rt2x00_desc_read(rxwi, 1, &rxwi1);
2163         rt2x00_desc_read(rxwi, 2, &rxwi2);
2164         rt2x00_desc_read(rxwi, 3, &rxwi3);
2165
2166         if (rt2x00_get_field32(rxd0, RXD_W0_CRC_ERROR))
2167                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2168
2169         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2170                 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
2171                 rxdesc->cipher_status =
2172                     rt2x00_get_field32(rxd0, RXD_W0_CIPHER_ERROR);
2173         }
2174
2175         if (rt2x00_get_field32(rxd0, RXD_W0_DECRYPTED)) {
2176                 /*
2177                  * Hardware has stripped IV/EIV data from 802.11 frame during
2178                  * decryption. Unfortunately the descriptor doesn't contain
2179                  * any fields with the EIV/IV data either, so they can't
2180                  * be restored by rt2x00lib.
2181                  */
2182                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2183
2184                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2185                         rxdesc->flags |= RX_FLAG_DECRYPTED;
2186                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2187                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2188         }
2189
2190         if (rt2x00_get_field32(rxd0, RXD_W0_MY_BSS))
2191                 rxdesc->dev_flags |= RXDONE_MY_BSS;
2192
2193         if (rt2x00_get_field32(rxd0, RXD_W0_L2PAD)) {
2194                 rxdesc->dev_flags |= RXDONE_L2PAD;
2195                 skbdesc->flags |= SKBDESC_L2_PADDED;
2196         }
2197
2198         if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2199                 rxdesc->flags |= RX_FLAG_SHORT_GI;
2200
2201         if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2202                 rxdesc->flags |= RX_FLAG_40MHZ;
2203
2204         /*
2205          * Detect RX rate, always use MCS as signal type.
2206          */
2207         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2208         rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2209         rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2210
2211         /*
2212          * Mask of 0x8 bit to remove the short preamble flag.
2213          */
2214         if (rxdesc->rate_mode == RATE_MODE_CCK)
2215                 rxdesc->signal &= ~0x8;
2216
2217         rxdesc->rssi =
2218             (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2219              rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
2220
2221         rxdesc->noise =
2222             (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2223              rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2224
2225         rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2226
2227         /*
2228          * Remove RXWI descriptor from start of buffer.
2229          */
2230         skb_pull(entry->skb, skbdesc->desc_len);
2231         skb_trim(entry->skb, rxdesc->size);
2232 }
2233
2234 /*
2235  * Device probe functions.
2236  */
2237 static int rt2800usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2238 {
2239         u16 word;
2240         u8 *mac;
2241         u8 default_lna_gain;
2242
2243         rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
2244
2245         /*
2246          * Start validation of the data that has been read.
2247          */
2248         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2249         if (!is_valid_ether_addr(mac)) {
2250                 random_ether_addr(mac);
2251                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2252         }
2253
2254         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2255         if (word == 0xffff) {
2256                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2257                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2258                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2259                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2260                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2261         } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
2262                 /*
2263                  * There is a max of 2 RX streams for RT2870 series
2264                  */
2265                 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2266                         rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2267                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2268         }
2269
2270         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2271         if (word == 0xffff) {
2272                 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2273                 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2274                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2275                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2276                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2277                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2278                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2279                 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2280                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2281                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2282                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2283                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2284         }
2285
2286         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2287         if ((word & 0x00ff) == 0x00ff) {
2288                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2289                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2290                                    LED_MODE_TXRX_ACTIVITY);
2291                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2292                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2293                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2294                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2295                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2296                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2297         }
2298
2299         /*
2300          * During the LNA validation we are going to use
2301          * lna0 as correct value. Note that EEPROM_LNA
2302          * is never validated.
2303          */
2304         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2305         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2306
2307         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2308         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2309                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2310         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2311                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2312         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2313
2314         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2315         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2316                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2317         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2318             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2319                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2320                                    default_lna_gain);
2321         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2322
2323         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2324         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2325                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2326         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2327                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2328         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2329
2330         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2331         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2332                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2333         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2334             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2335                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2336                                    default_lna_gain);
2337         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2338
2339         return 0;
2340 }
2341
2342 static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
2343 {
2344         u32 reg;
2345         u16 value;
2346         u16 eeprom;
2347
2348         /*
2349          * Read EEPROM word for configuration.
2350          */
2351         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2352
2353         /*
2354          * Identify RF chipset.
2355          */
2356         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2357         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2358         rt2x00_set_chip(rt2x00dev, RT2870, value, reg);
2359
2360         /*
2361          * The check for rt2860 is not a typo, some rt2870 hardware
2362          * identifies itself as rt2860 in the CSR register.
2363          */
2364         if (!rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28600000) &&
2365             !rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28700000) &&
2366             !rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28800000) &&
2367             !rt2x00_check_rev(&rt2x00dev->chip, 0xffff0000, 0x30700000)) {
2368                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2369                 return -ENODEV;
2370         }
2371
2372         if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2373             !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2374             !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2375             !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2376             !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2377             !rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2378                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2379                 return -ENODEV;
2380         }
2381
2382         /*
2383          * Identify default antenna configuration.
2384          */
2385         rt2x00dev->default_ant.tx =
2386             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2387         rt2x00dev->default_ant.rx =
2388             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2389
2390         /*
2391          * Read frequency offset and RF programming sequence.
2392          */
2393         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2394         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2395
2396         /*
2397          * Read external LNA informations.
2398          */
2399         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2400
2401         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2402                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2403         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2404                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2405
2406         /*
2407          * Detect if this device has an hardware controlled radio.
2408          */
2409         if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2410                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2411
2412         /*
2413          * Store led settings, for correct led behaviour.
2414          */
2415 #ifdef CONFIG_RT2X00_LIB_LEDS
2416         rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2417         rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2418         rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2419
2420         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ,
2421                            &rt2x00dev->led_mcu_reg);
2422 #endif /* CONFIG_RT2X00_LIB_LEDS */
2423
2424         return 0;
2425 }
2426
2427 /*
2428  * RF value list for rt2870
2429  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2430  */
2431 static const struct rf_channel rf_vals[] = {
2432         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2433         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2434         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2435         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2436         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2437         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2438         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2439         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2440         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2441         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2442         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2443         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2444         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2445         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2446
2447         /* 802.11 UNI / HyperLan 2 */
2448         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2449         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2450         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2451         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2452         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2453         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2454         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2455         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2456         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2457         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2458         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2459         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2460
2461         /* 802.11 HyperLan 2 */
2462         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2463         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2464         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2465         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2466         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2467         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2468         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2469         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2470         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2471         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2472         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2473         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2474         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2475         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2476         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2477         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2478
2479         /* 802.11 UNII */
2480         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2481         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2482         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2483         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2484         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2485         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2486         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2487         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2488         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2489         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2490         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2491
2492         /* 802.11 Japan */
2493         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2494         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2495         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2496         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2497         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2498         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2499         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2500 };
2501
2502 /*
2503  * RF value list for rt3070
2504  * Supports: 2.4 GHz
2505  */
2506 static const struct rf_channel rf_vals_3070[] = {
2507         {1,  241, 2, 2 },
2508         {2,  241, 2, 7 },
2509         {3,  242, 2, 2 },
2510         {4,  242, 2, 7 },
2511         {5,  243, 2, 2 },
2512         {6,  243, 2, 7 },
2513         {7,  244, 2, 2 },
2514         {8,  244, 2, 7 },
2515         {9,  245, 2, 2 },
2516         {10, 245, 2, 7 },
2517         {11, 246, 2, 2 },
2518         {12, 246, 2, 7 },
2519         {13, 247, 2, 2 },
2520         {14, 248, 2, 4 },
2521 };
2522
2523 static int rt2800usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2524 {
2525         struct hw_mode_spec *spec = &rt2x00dev->spec;
2526         struct channel_info *info;
2527         char *tx_power1;
2528         char *tx_power2;
2529         unsigned int i;
2530         u16 eeprom;
2531
2532         /*
2533          * Initialize all hw fields.
2534          */
2535         rt2x00dev->hw->flags =
2536             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2537             IEEE80211_HW_SIGNAL_DBM |
2538             IEEE80211_HW_SUPPORTS_PS |
2539             IEEE80211_HW_PS_NULLFUNC_STACK;
2540         rt2x00dev->hw->extra_tx_headroom = TXINFO_DESC_SIZE + TXWI_DESC_SIZE;
2541
2542         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2543         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2544                                 rt2x00_eeprom_addr(rt2x00dev,
2545                                                    EEPROM_MAC_ADDR_0));
2546
2547         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2548
2549         /*
2550          * Initialize HT information.
2551          */
2552         spec->ht.ht_supported = true;
2553         spec->ht.cap =
2554             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2555             IEEE80211_HT_CAP_GRN_FLD |
2556             IEEE80211_HT_CAP_SGI_20 |
2557             IEEE80211_HT_CAP_SGI_40 |
2558             IEEE80211_HT_CAP_TX_STBC |
2559             IEEE80211_HT_CAP_RX_STBC |
2560             IEEE80211_HT_CAP_PSMP_SUPPORT;
2561         spec->ht.ampdu_factor = 3;
2562         spec->ht.ampdu_density = 4;
2563         spec->ht.mcs.tx_params =
2564             IEEE80211_HT_MCS_TX_DEFINED |
2565             IEEE80211_HT_MCS_TX_RX_DIFF |
2566             ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2567                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2568
2569         switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2570         case 3:
2571                 spec->ht.mcs.rx_mask[2] = 0xff;
2572         case 2:
2573                 spec->ht.mcs.rx_mask[1] = 0xff;
2574         case 1:
2575                 spec->ht.mcs.rx_mask[0] = 0xff;
2576                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2577                 break;
2578         }
2579
2580         /*
2581          * Initialize hw_mode information.
2582          */
2583         spec->supported_bands = SUPPORT_BAND_2GHZ;
2584         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2585
2586         if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2587             rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2588                 spec->num_channels = 14;
2589                 spec->channels = rf_vals;
2590         } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2591                    rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2592                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2593                 spec->num_channels = ARRAY_SIZE(rf_vals);
2594                 spec->channels = rf_vals;
2595         } else if (rt2x00_rf(&rt2x00dev->chip, RF3020) ||
2596                    rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2597                 spec->num_channels = ARRAY_SIZE(rf_vals_3070);
2598                 spec->channels = rf_vals_3070;
2599         }
2600
2601         /*
2602          * Create channel information array
2603          */
2604         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2605         if (!info)
2606                 return -ENOMEM;
2607
2608         spec->channels_info = info;
2609
2610         tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2611         tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2612
2613         for (i = 0; i < 14; i++) {
2614                 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2615                 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2616         }
2617
2618         if (spec->num_channels > 14) {
2619                 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2620                 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2621
2622                 for (i = 14; i < spec->num_channels; i++) {
2623                         info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2624                         info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2625                 }
2626         }
2627
2628         return 0;
2629 }
2630
2631 static const struct rt2800_ops rt2800usb_rt2800_ops = {
2632         .register_read          = rt2x00usb_register_read,
2633         .register_write         = rt2x00usb_register_write,
2634         .register_write_lock    = rt2x00usb_register_write_lock,
2635
2636         .register_multiread     = rt2x00usb_register_multiread,
2637         .register_multiwrite    = rt2x00usb_register_multiwrite,
2638
2639         .regbusy_read           = rt2x00usb_regbusy_read,
2640 };
2641
2642 static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2643 {
2644         int retval;
2645
2646         rt2x00dev->priv = (void *)&rt2800usb_rt2800_ops;
2647
2648         /*
2649          * Allocate eeprom data.
2650          */
2651         retval = rt2800usb_validate_eeprom(rt2x00dev);
2652         if (retval)
2653                 return retval;
2654
2655         retval = rt2800usb_init_eeprom(rt2x00dev);
2656         if (retval)
2657                 return retval;
2658
2659         /*
2660          * Initialize hw specifications.
2661          */
2662         retval = rt2800usb_probe_hw_mode(rt2x00dev);
2663         if (retval)
2664                 return retval;
2665
2666         /*
2667          * This device has multiple filters for control frames
2668          * and has a separate filter for PS Poll frames.
2669          */
2670         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2671         __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
2672
2673         /*
2674          * This device requires firmware.
2675          */
2676         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2677         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
2678         if (!modparam_nohwcrypt)
2679                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2680
2681         /*
2682          * Set the rssi offset.
2683          */
2684         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2685
2686         return 0;
2687 }
2688
2689 /*
2690  * IEEE80211 stack callback functions.
2691  */
2692 static void rt2800usb_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2693                                    u32 *iv32, u16 *iv16)
2694 {
2695         struct rt2x00_dev *rt2x00dev = hw->priv;
2696         struct mac_iveiv_entry iveiv_entry;
2697         u32 offset;
2698
2699         offset = MAC_IVEIV_ENTRY(hw_key_idx);
2700         rt2800_register_multiread(rt2x00dev, offset,
2701                                       &iveiv_entry, sizeof(iveiv_entry));
2702
2703         memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2704         memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2705 }
2706
2707 static int rt2800usb_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2708 {
2709         struct rt2x00_dev *rt2x00dev = hw->priv;
2710         u32 reg;
2711         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2712
2713         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2714         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2715         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2716
2717         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2718         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2719         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2720
2721         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2722         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2723         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2724
2725         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2726         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2727         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2728
2729         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2730         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2731         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2732
2733         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2734         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2735         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2736
2737         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2738         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2739         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2740
2741         return 0;
2742 }
2743
2744 static int rt2800usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2745                              const struct ieee80211_tx_queue_params *params)
2746 {
2747         struct rt2x00_dev *rt2x00dev = hw->priv;
2748         struct data_queue *queue;
2749         struct rt2x00_field32 field;
2750         int retval;
2751         u32 reg;
2752         u32 offset;
2753
2754         /*
2755          * First pass the configuration through rt2x00lib, that will
2756          * update the queue settings and validate the input. After that
2757          * we are free to update the registers based on the value
2758          * in the queue parameter.
2759          */
2760         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2761         if (retval)
2762                 return retval;
2763
2764         /*
2765          * We only need to perform additional register initialization
2766          * for WMM queues/
2767          */
2768         if (queue_idx >= 4)
2769                 return 0;
2770
2771         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2772
2773         /* Update WMM TXOP register */
2774         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2775         field.bit_offset = (queue_idx & 1) * 16;
2776         field.bit_mask = 0xffff << field.bit_offset;
2777
2778         rt2800_register_read(rt2x00dev, offset, &reg);
2779         rt2x00_set_field32(&reg, field, queue->txop);
2780         rt2800_register_write(rt2x00dev, offset, reg);
2781
2782         /* Update WMM registers */
2783         field.bit_offset = queue_idx * 4;
2784         field.bit_mask = 0xf << field.bit_offset;
2785
2786         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2787         rt2x00_set_field32(&reg, field, queue->aifs);
2788         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2789
2790         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2791         rt2x00_set_field32(&reg, field, queue->cw_min);
2792         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2793
2794         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2795         rt2x00_set_field32(&reg, field, queue->cw_max);
2796         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2797
2798         /* Update EDCA registers */
2799         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2800
2801         rt2800_register_read(rt2x00dev, offset, &reg);
2802         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2803         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2804         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2805         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2806         rt2800_register_write(rt2x00dev, offset, reg);
2807
2808         return 0;
2809 }
2810
2811 static u64 rt2800usb_get_tsf(struct ieee80211_hw *hw)
2812 {
2813         struct rt2x00_dev *rt2x00dev = hw->priv;
2814         u64 tsf;
2815         u32 reg;
2816
2817         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2818         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2819         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2820         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2821
2822         return tsf;
2823 }
2824
2825 static const struct ieee80211_ops rt2800usb_mac80211_ops = {
2826         .tx                     = rt2x00mac_tx,
2827         .start                  = rt2x00mac_start,
2828         .stop                   = rt2x00mac_stop,
2829         .add_interface          = rt2x00mac_add_interface,
2830         .remove_interface       = rt2x00mac_remove_interface,
2831         .config                 = rt2x00mac_config,
2832         .configure_filter       = rt2x00mac_configure_filter,
2833         .set_tim                = rt2x00mac_set_tim,
2834         .set_key                = rt2x00mac_set_key,
2835         .get_stats              = rt2x00mac_get_stats,
2836         .get_tkip_seq           = rt2800usb_get_tkip_seq,
2837         .set_rts_threshold      = rt2800usb_set_rts_threshold,
2838         .bss_info_changed       = rt2x00mac_bss_info_changed,
2839         .conf_tx                = rt2800usb_conf_tx,
2840         .get_tx_stats           = rt2x00mac_get_tx_stats,
2841         .get_tsf                = rt2800usb_get_tsf,
2842         .rfkill_poll            = rt2x00mac_rfkill_poll,
2843 };
2844
2845 static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2846         .probe_hw               = rt2800usb_probe_hw,
2847         .get_firmware_name      = rt2800usb_get_firmware_name,
2848         .check_firmware         = rt2800usb_check_firmware,
2849         .load_firmware          = rt2800usb_load_firmware,
2850         .initialize             = rt2x00usb_initialize,
2851         .uninitialize           = rt2x00usb_uninitialize,
2852         .clear_entry            = rt2x00usb_clear_entry,
2853         .set_device_state       = rt2800usb_set_device_state,
2854         .rfkill_poll            = rt2800usb_rfkill_poll,
2855         .link_stats             = rt2800usb_link_stats,
2856         .reset_tuner            = rt2800usb_reset_tuner,
2857         .link_tuner             = rt2800usb_link_tuner,
2858         .write_tx_desc          = rt2800usb_write_tx_desc,
2859         .write_tx_data          = rt2x00usb_write_tx_data,
2860         .write_beacon           = rt2800usb_write_beacon,
2861         .get_tx_data_len        = rt2800usb_get_tx_data_len,
2862         .kick_tx_queue          = rt2800usb_kick_tx_queue,
2863         .kill_tx_queue          = rt2x00usb_kill_tx_queue,
2864         .fill_rxdone            = rt2800usb_fill_rxdone,
2865         .config_shared_key      = rt2800usb_config_shared_key,
2866         .config_pairwise_key    = rt2800usb_config_pairwise_key,
2867         .config_filter          = rt2800usb_config_filter,
2868         .config_intf            = rt2800usb_config_intf,
2869         .config_erp             = rt2800usb_config_erp,
2870         .config_ant             = rt2800usb_config_ant,
2871         .config                 = rt2800usb_config,
2872 };
2873
2874 static const struct data_queue_desc rt2800usb_queue_rx = {
2875         .entry_num              = RX_ENTRIES,
2876         .data_size              = AGGREGATION_SIZE,
2877         .desc_size              = RXINFO_DESC_SIZE + RXWI_DESC_SIZE,
2878         .priv_size              = sizeof(struct queue_entry_priv_usb),
2879 };
2880
2881 static const struct data_queue_desc rt2800usb_queue_tx = {
2882         .entry_num              = TX_ENTRIES,
2883         .data_size              = AGGREGATION_SIZE,
2884         .desc_size              = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2885         .priv_size              = sizeof(struct queue_entry_priv_usb),
2886 };
2887
2888 static const struct data_queue_desc rt2800usb_queue_bcn = {
2889         .entry_num              = 8 * BEACON_ENTRIES,
2890         .data_size              = MGMT_FRAME_SIZE,
2891         .desc_size              = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2892         .priv_size              = sizeof(struct queue_entry_priv_usb),
2893 };
2894
2895 static const struct rt2x00_ops rt2800usb_ops = {
2896         .name           = KBUILD_MODNAME,
2897         .max_sta_intf   = 1,
2898         .max_ap_intf    = 8,
2899         .eeprom_size    = EEPROM_SIZE,
2900         .rf_size        = RF_SIZE,
2901         .tx_queues      = NUM_TX_QUEUES,
2902         .rx             = &rt2800usb_queue_rx,
2903         .tx             = &rt2800usb_queue_tx,
2904         .bcn            = &rt2800usb_queue_bcn,
2905         .lib            = &rt2800usb_rt2x00_ops,
2906         .hw             = &rt2800usb_mac80211_ops,
2907 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2908         .debugfs        = &rt2800usb_rt2x00debug,
2909 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2910 };
2911
2912 /*
2913  * rt2800usb module information.
2914  */
2915 static struct usb_device_id rt2800usb_device_table[] = {
2916         /* Abocom */
2917         { USB_DEVICE(0x07b8, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2918         { USB_DEVICE(0x07b8, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2919         { USB_DEVICE(0x07b8, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2920         { USB_DEVICE(0x07b8, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
2921         { USB_DEVICE(0x07b8, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2922         { USB_DEVICE(0x1482, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2923         /* AirTies */
2924         { USB_DEVICE(0x1eda, 0x2310), USB_DEVICE_DATA(&rt2800usb_ops) },
2925         /* Amigo */
2926         { USB_DEVICE(0x0e0b, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
2927         { USB_DEVICE(0x0e0b, 0x9041), USB_DEVICE_DATA(&rt2800usb_ops) },
2928         /* Amit */
2929         { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2930         /* ASUS */
2931         { USB_DEVICE(0x0b05, 0x1731), USB_DEVICE_DATA(&rt2800usb_ops) },
2932         { USB_DEVICE(0x0b05, 0x1732), USB_DEVICE_DATA(&rt2800usb_ops) },
2933         { USB_DEVICE(0x0b05, 0x1742), USB_DEVICE_DATA(&rt2800usb_ops) },
2934         { USB_DEVICE(0x0b05, 0x1760), USB_DEVICE_DATA(&rt2800usb_ops) },
2935         { USB_DEVICE(0x0b05, 0x1761), USB_DEVICE_DATA(&rt2800usb_ops) },
2936         /* AzureWave */
2937         { USB_DEVICE(0x13d3, 0x3247), USB_DEVICE_DATA(&rt2800usb_ops) },
2938         { USB_DEVICE(0x13d3, 0x3262), USB_DEVICE_DATA(&rt2800usb_ops) },
2939         { USB_DEVICE(0x13d3, 0x3273), USB_DEVICE_DATA(&rt2800usb_ops) },
2940         { USB_DEVICE(0x13d3, 0x3284), USB_DEVICE_DATA(&rt2800usb_ops) },
2941         /* Belkin */
2942         { USB_DEVICE(0x050d, 0x8053), USB_DEVICE_DATA(&rt2800usb_ops) },
2943         { USB_DEVICE(0x050d, 0x805c), USB_DEVICE_DATA(&rt2800usb_ops) },
2944         { USB_DEVICE(0x050d, 0x815c), USB_DEVICE_DATA(&rt2800usb_ops) },
2945         { USB_DEVICE(0x050d, 0x825a), USB_DEVICE_DATA(&rt2800usb_ops) },
2946         /* Buffalo */
2947         { USB_DEVICE(0x0411, 0x00e8), USB_DEVICE_DATA(&rt2800usb_ops) },
2948         { USB_DEVICE(0x0411, 0x012e), USB_DEVICE_DATA(&rt2800usb_ops) },
2949         /* Conceptronic */
2950         { USB_DEVICE(0x14b2, 0x3c06), USB_DEVICE_DATA(&rt2800usb_ops) },
2951         { USB_DEVICE(0x14b2, 0x3c07), USB_DEVICE_DATA(&rt2800usb_ops) },
2952         { USB_DEVICE(0x14b2, 0x3c08), USB_DEVICE_DATA(&rt2800usb_ops) },
2953         { USB_DEVICE(0x14b2, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2954         { USB_DEVICE(0x14b2, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2955         { USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) },
2956         { USB_DEVICE(0x14b2, 0x3c23), USB_DEVICE_DATA(&rt2800usb_ops) },
2957         { USB_DEVICE(0x14b2, 0x3c25), USB_DEVICE_DATA(&rt2800usb_ops) },
2958         { USB_DEVICE(0x14b2, 0x3c27), USB_DEVICE_DATA(&rt2800usb_ops) },
2959         { USB_DEVICE(0x14b2, 0x3c28), USB_DEVICE_DATA(&rt2800usb_ops) },
2960         /* Corega */
2961         { USB_DEVICE(0x07aa, 0x002f), USB_DEVICE_DATA(&rt2800usb_ops) },
2962         { USB_DEVICE(0x07aa, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
2963         { USB_DEVICE(0x07aa, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
2964         { USB_DEVICE(0x18c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2965         { USB_DEVICE(0x18c5, 0x0012), USB_DEVICE_DATA(&rt2800usb_ops) },
2966         /* D-Link */
2967         { USB_DEVICE(0x07d1, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2968         { USB_DEVICE(0x07d1, 0x3c0a), USB_DEVICE_DATA(&rt2800usb_ops) },
2969         { USB_DEVICE(0x07d1, 0x3c0b), USB_DEVICE_DATA(&rt2800usb_ops) },
2970         { USB_DEVICE(0x07d1, 0x3c0d), USB_DEVICE_DATA(&rt2800usb_ops) },
2971         { USB_DEVICE(0x07d1, 0x3c0e), USB_DEVICE_DATA(&rt2800usb_ops) },
2972         { USB_DEVICE(0x07d1, 0x3c0f), USB_DEVICE_DATA(&rt2800usb_ops) },
2973         { USB_DEVICE(0x07d1, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2974         { USB_DEVICE(0x07d1, 0x3c13), USB_DEVICE_DATA(&rt2800usb_ops) },
2975         /* Edimax */
2976         { USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) },
2977         { USB_DEVICE(0x7392, 0x7717), USB_DEVICE_DATA(&rt2800usb_ops) },
2978         { USB_DEVICE(0x7392, 0x7718), USB_DEVICE_DATA(&rt2800usb_ops) },
2979         /* Encore */
2980         { USB_DEVICE(0x203d, 0x1480), USB_DEVICE_DATA(&rt2800usb_ops) },
2981         /* EnGenius */
2982         { USB_DEVICE(0X1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) },
2983         { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) },
2984         { USB_DEVICE(0x1740, 0x9703), USB_DEVICE_DATA(&rt2800usb_ops) },
2985         { USB_DEVICE(0x1740, 0x9705), USB_DEVICE_DATA(&rt2800usb_ops) },
2986         { USB_DEVICE(0x1740, 0x9706), USB_DEVICE_DATA(&rt2800usb_ops) },
2987         { USB_DEVICE(0x1740, 0x9801), USB_DEVICE_DATA(&rt2800usb_ops) },
2988         /* Gemtek */
2989         { USB_DEVICE(0x15a9, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) },
2990         /* Gigabyte */
2991         { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) },
2992         { USB_DEVICE(0x1044, 0x800c), USB_DEVICE_DATA(&rt2800usb_ops) },
2993         { USB_DEVICE(0x1044, 0x800d), USB_DEVICE_DATA(&rt2800usb_ops) },
2994         /* Hawking */
2995         { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) },
2996         { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) },
2997         { USB_DEVICE(0x0e66, 0x0009), USB_DEVICE_DATA(&rt2800usb_ops) },
2998         { USB_DEVICE(0x0e66, 0x000b), USB_DEVICE_DATA(&rt2800usb_ops) },
2999         /* I-O DATA */
3000         { USB_DEVICE(0x04bb, 0x0945), USB_DEVICE_DATA(&rt2800usb_ops) },
3001         /* LevelOne */
3002         { USB_DEVICE(0x1740, 0x0605), USB_DEVICE_DATA(&rt2800usb_ops) },
3003         { USB_DEVICE(0x1740, 0x0615), USB_DEVICE_DATA(&rt2800usb_ops) },
3004         /* Linksys */
3005         { USB_DEVICE(0x1737, 0x0070), USB_DEVICE_DATA(&rt2800usb_ops) },
3006         { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) },
3007         { USB_DEVICE(0x1737, 0x0077), USB_DEVICE_DATA(&rt2800usb_ops) },
3008         /* Logitec */
3009         { USB_DEVICE(0x0789, 0x0162), USB_DEVICE_DATA(&rt2800usb_ops) },
3010         { USB_DEVICE(0x0789, 0x0163), USB_DEVICE_DATA(&rt2800usb_ops) },
3011         { USB_DEVICE(0x0789, 0x0164), USB_DEVICE_DATA(&rt2800usb_ops) },
3012         /* Motorola */
3013         { USB_DEVICE(0x100d, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
3014         { USB_DEVICE(0x100d, 0x9032), USB_DEVICE_DATA(&rt2800usb_ops) },
3015         /* Ovislink */
3016         { USB_DEVICE(0x1b75, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
3017         /* Pegatron */
3018         { USB_DEVICE(0x1d4d, 0x0002), USB_DEVICE_DATA(&rt2800usb_ops) },
3019         { USB_DEVICE(0x1d4d, 0x000c), USB_DEVICE_DATA(&rt2800usb_ops) },
3020         { USB_DEVICE(0x1d4d, 0x000e), USB_DEVICE_DATA(&rt2800usb_ops) },
3021         /* Philips */
3022         { USB_DEVICE(0x0471, 0x200f), USB_DEVICE_DATA(&rt2800usb_ops) },
3023         /* Planex */
3024         { USB_DEVICE(0x2019, 0xed06), USB_DEVICE_DATA(&rt2800usb_ops) },
3025         { USB_DEVICE(0x2019, 0xab24), USB_DEVICE_DATA(&rt2800usb_ops) },
3026         { USB_DEVICE(0x2019, 0xab25), USB_DEVICE_DATA(&rt2800usb_ops) },
3027         /* Qcom */
3028         { USB_DEVICE(0x18e8, 0x6259), USB_DEVICE_DATA(&rt2800usb_ops) },
3029         /* Quanta */
3030         { USB_DEVICE(0x1a32, 0x0304), USB_DEVICE_DATA(&rt2800usb_ops) },
3031         /* Ralink */
3032         { USB_DEVICE(0x0db0, 0x3820), USB_DEVICE_DATA(&rt2800usb_ops) },
3033         { USB_DEVICE(0x0db0, 0x6899), USB_DEVICE_DATA(&rt2800usb_ops) },
3034         { USB_DEVICE(0x148f, 0x2070), USB_DEVICE_DATA(&rt2800usb_ops) },
3035         { USB_DEVICE(0x148f, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
3036         { USB_DEVICE(0x148f, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
3037         { USB_DEVICE(0x148f, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
3038         { USB_DEVICE(0x148f, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
3039         { USB_DEVICE(0x148f, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
3040         { USB_DEVICE(0x148f, 0x3572), USB_DEVICE_DATA(&rt2800usb_ops) },
3041         /* Samsung */
3042         { USB_DEVICE(0x04e8, 0x2018), USB_DEVICE_DATA(&rt2800usb_ops) },
3043         /* Siemens */
3044         { USB_DEVICE(0x129b, 0x1828), USB_DEVICE_DATA(&rt2800usb_ops) },
3045         /* Sitecom */
3046         { USB_DEVICE(0x0df6, 0x0017), USB_DEVICE_DATA(&rt2800usb_ops) },
3047         { USB_DEVICE(0x0df6, 0x002b), USB_DEVICE_DATA(&rt2800usb_ops) },
3048         { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) },
3049         { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) },
3050         { USB_DEVICE(0x0df6, 0x0039), USB_DEVICE_DATA(&rt2800usb_ops) },
3051         { USB_DEVICE(0x0df6, 0x003b), USB_DEVICE_DATA(&rt2800usb_ops) },
3052         { USB_DEVICE(0x0df6, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
3053         { USB_DEVICE(0x0df6, 0x003d), USB_DEVICE_DATA(&rt2800usb_ops) },
3054         { USB_DEVICE(0x0df6, 0x003e), USB_DEVICE_DATA(&rt2800usb_ops) },
3055         { USB_DEVICE(0x0df6, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
3056         { USB_DEVICE(0x0df6, 0x0040), USB_DEVICE_DATA(&rt2800usb_ops) },
3057         { USB_DEVICE(0x0df6, 0x0042), USB_DEVICE_DATA(&rt2800usb_ops) },
3058         /* SMC */
3059         { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) },
3060         { USB_DEVICE(0x083a, 0x7511), USB_DEVICE_DATA(&rt2800usb_ops) },
3061         { USB_DEVICE(0x083a, 0x7512), USB_DEVICE_DATA(&rt2800usb_ops) },
3062         { USB_DEVICE(0x083a, 0x7522), USB_DEVICE_DATA(&rt2800usb_ops) },
3063         { USB_DEVICE(0x083a, 0x8522), USB_DEVICE_DATA(&rt2800usb_ops) },
3064         { USB_DEVICE(0x083a, 0xa512), USB_DEVICE_DATA(&rt2800usb_ops) },
3065         { USB_DEVICE(0x083a, 0xa618), USB_DEVICE_DATA(&rt2800usb_ops) },
3066         { USB_DEVICE(0x083a, 0xb522), USB_DEVICE_DATA(&rt2800usb_ops) },
3067         { USB_DEVICE(0x083a, 0xc522), USB_DEVICE_DATA(&rt2800usb_ops) },
3068         /* Sparklan */
3069         { USB_DEVICE(0x15a9, 0x0006), USB_DEVICE_DATA(&rt2800usb_ops) },
3070         /* Sweex */
3071         { USB_DEVICE(0x177f, 0x0153), USB_DEVICE_DATA(&rt2800usb_ops) },
3072         { USB_DEVICE(0x177f, 0x0302), USB_DEVICE_DATA(&rt2800usb_ops) },
3073         { USB_DEVICE(0x177f, 0x0313), USB_DEVICE_DATA(&rt2800usb_ops) },
3074         /* U-Media*/
3075         { USB_DEVICE(0x157e, 0x300e), USB_DEVICE_DATA(&rt2800usb_ops) },
3076         /* ZCOM */
3077         { USB_DEVICE(0x0cde, 0x0022), USB_DEVICE_DATA(&rt2800usb_ops) },
3078         { USB_DEVICE(0x0cde, 0x0025), USB_DEVICE_DATA(&rt2800usb_ops) },
3079         /* Zinwell */
3080         { USB_DEVICE(0x5a57, 0x0280), USB_DEVICE_DATA(&rt2800usb_ops) },
3081         { USB_DEVICE(0x5a57, 0x0282), USB_DEVICE_DATA(&rt2800usb_ops) },
3082         { USB_DEVICE(0x5a57, 0x0283), USB_DEVICE_DATA(&rt2800usb_ops) },
3083         { USB_DEVICE(0x5a57, 0x5257), USB_DEVICE_DATA(&rt2800usb_ops) },
3084         /* Zyxel */
3085         { USB_DEVICE(0x0586, 0x3416), USB_DEVICE_DATA(&rt2800usb_ops) },
3086         { USB_DEVICE(0x0586, 0x341a), USB_DEVICE_DATA(&rt2800usb_ops) },
3087         { 0, }
3088 };
3089
3090 MODULE_AUTHOR(DRV_PROJECT);
3091 MODULE_VERSION(DRV_VERSION);
3092 MODULE_DESCRIPTION("Ralink RT2800 USB Wireless LAN driver.");
3093 MODULE_SUPPORTED_DEVICE("Ralink RT2870 USB chipset based cards");
3094 MODULE_DEVICE_TABLE(usb, rt2800usb_device_table);
3095 MODULE_FIRMWARE(FIRMWARE_RT2870);
3096 MODULE_LICENSE("GPL");
3097
3098 static struct usb_driver rt2800usb_driver = {
3099         .name           = KBUILD_MODNAME,
3100         .id_table       = rt2800usb_device_table,
3101         .probe          = rt2x00usb_probe,
3102         .disconnect     = rt2x00usb_disconnect,
3103         .suspend        = rt2x00usb_suspend,
3104         .resume         = rt2x00usb_resume,
3105 };
3106
3107 static int __init rt2800usb_init(void)
3108 {
3109         return usb_register(&rt2800usb_driver);
3110 }
3111
3112 static void __exit rt2800usb_exit(void)
3113 {
3114         usb_deregister(&rt2800usb_driver);
3115 }
3116
3117 module_init(rt2800usb_init);
3118 module_exit(rt2800usb_exit);