SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/rt2x00/rt2800pci.c

   1 /*
   2         Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
   3         Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   4         Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5         Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
   6         Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
   7         Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
   8         Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
   9         Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
  10         <http://rt2x00.serialmonkey.com>
  11
  12         This program is free software; you can redistribute it and/or modify
  13         it under the terms of the GNU General Public License as published by
  14         the Free Software Foundation; either version 2 of the License, or
  15         (at your option) any later version.
  16
  17         This program is distributed in the hope that it will be useful,
  18         but WITHOUT ANY WARRANTY; without even the implied warranty of
  19         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20         GNU General Public License for more details.
  21
  22         You should have received a copy of the GNU General Public License
  23         along with this program; if not, write to the
  24         Free Software Foundation, Inc.,
  25         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  26  */
  27
  28 /*
  29         Module: rt2800pci
  30         Abstract: rt2800pci device specific routines.
  31         Supported chipsets: RT2800E & RT2800ED.
  32  */
  33
  34 #include <linux/crc-ccitt.h>
  35 #include <linux/delay.h>
  36 #include <linux/etherdevice.h>
  37 #include <linux/init.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/pci.h>
  41 #include <linux/platform_device.h>
  42 #include <linux/eeprom_93cx6.h>
  43
  44 #include "rt2x00.h"
  45 #include "rt2x00pci.h"
  46 #include "rt2x00soc.h"
  47 #include "rt2800lib.h"
  48 #include "rt2800.h"
  49 #include "rt2800pci.h"
  50
  51 /*
  52  * Allow hardware encryption to be disabled.
  53  */
  54 static int modparam_nohwcrypt = 1;
  55 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  56 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  57
  58 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
  59 {
  60         unsigned int i;
  61         u32 reg;
  62
  63         /*
  64          * SOC devices don't support MCU requests.
  65          */
  66         if (rt2x00_is_soc(rt2x00dev))
  67                 return;
  68
  69         for (i = 0; i < 200; i++) {
  70                 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
  71
  72                 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
  73                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
  74                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
  75                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
  76                         break;
  77
  78                 udelay(REGISTER_BUSY_DELAY);
  79         }
  80
  81         if (i == 200)
  82                 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
  83
  84         rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
  85         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
  86 }
  87
  88 #ifdef CONFIG_RT2800PCI_SOC
  89 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  90 {
  91         u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
  92
  93         memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
  94 }
  95 #else
  96 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  97 {
  98 }
  99 #endif /* CONFIG_RT2800PCI_SOC */
 100
 101 #ifdef CONFIG_RT2800PCI_PCI
 102 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 103 {
 104         struct rt2x00_dev *rt2x00dev = eeprom->data;
 105         u32 reg;
 106
 107         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
 108
 109         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 110         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 111         eeprom->reg_data_clock =
 112             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 113         eeprom->reg_chip_select =
 114             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 115 }
 116
 117 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 118 {
 119         struct rt2x00_dev *rt2x00dev = eeprom->data;
 120         u32 reg = 0;
 121
 122         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 123         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 124         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 125                            !!eeprom->reg_data_clock);
 126         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 127                            !!eeprom->reg_chip_select);
 128
 129         rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
 130 }
 131
 132 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 133 {
 134         struct eeprom_93cx6 eeprom;
 135         u32 reg;
 136
 137         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
 138
 139         eeprom.data = rt2x00dev;
 140         eeprom.register_read = rt2800pci_eepromregister_read;
 141         eeprom.register_write = rt2800pci_eepromregister_write;
 142         eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
 143             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
 144         eeprom.reg_data_in = 0;
 145         eeprom.reg_data_out = 0;
 146         eeprom.reg_data_clock = 0;
 147         eeprom.reg_chip_select = 0;
 148
 149         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
 150                                EEPROM_SIZE / sizeof(u16));
 151 }
 152
 153 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 154 {
 155         return rt2800_efuse_detect(rt2x00dev);
 156 }
 157
 158 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 159 {
 160         rt2800_read_eeprom_efuse(rt2x00dev);
 161 }
 162 #else
 163 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 164 {
 165 }
 166
 167 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 168 {
 169         return 0;
 170 }
 171
 172 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 173 {
 174 }
 175 #endif /* CONFIG_RT2800PCI_PCI */
 176
 177 /*
 178  * Firmware functions
 179  */
 180 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
 181 {
 182         return FIRMWARE_RT2860;
 183 }
 184
 185 static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
 186                                     const u8 *data, const size_t len)
 187 {
 188         u16 fw_crc;
 189         u16 crc;
 190
 191         /*
 192          * Only support 8kb firmware files.
 193          */
 194         if (len != 8192)
 195                 return FW_BAD_LENGTH;
 196
 197         /*
 198          * The last 2 bytes in the firmware array are the crc checksum itself,
 199          * this means that we should never pass those 2 bytes to the crc
 200          * algorithm.
 201          */
 202         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 203
 204         /*
 205          * Use the crc ccitt algorithm.
 206          * This will return the same value as the legacy driver which
 207          * used bit ordering reversion on the both the firmware bytes
 208          * before input input as well as on the final output.
 209          * Obviously using crc ccitt directly is much more efficient.
 210          */
 211         crc = crc_ccitt(~0, data, len - 2);
 212
 213         /*
 214          * There is a small difference between the crc-itu-t + bitrev and
 215          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 216          * will be swapped, use swab16 to convert the crc to the correct
 217          * value.
 218          */
 219         crc = swab16(crc);
 220
 221         return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
 222 }
 223
 224 static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
 225                                    const u8 *data, const size_t len)
 226 {
 227         unsigned int i;
 228         u32 reg;
 229
 230         /*
 231          * Wait for stable hardware.
 232          */
 233         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 234                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 235                 if (reg && reg != ~0)
 236                         break;
 237                 msleep(1);
 238         }
 239
 240         if (i == REGISTER_BUSY_COUNT) {
 241                 ERROR(rt2x00dev, "Unstable hardware.\n");
 242                 return -EBUSY;
 243         }
 244
 245         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 246         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 247
 248         /*
 249          * Disable DMA, will be reenabled later when enabling
 250          * the radio.
 251          */
 252         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 253         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 254         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 255         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 256         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 257         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 258         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 259
 260         /*
 261          * enable Host program ram write selection
 262          */
 263         reg = 0;
 264         rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
 265         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
 266
 267         /*
 268          * Write firmware to device.
 269          */
 270         rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
 271                                       data, len);
 272
 273         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
 274         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
 275
 276         /*
 277          * Wait for device to stabilize.
 278          */
 279         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 280                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 281                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 282                         break;
 283                 msleep(1);
 284         }
 285
 286         if (i == REGISTER_BUSY_COUNT) {
 287                 ERROR(rt2x00dev, "PBF system register not ready.\n");
 288                 return -EBUSY;
 289         }
 290
 291         /*
 292          * Disable interrupts
 293          */
 294         rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
 295
 296         /*
 297          * Initialize BBP R/W access agent
 298          */
 299         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 300         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 301
 302         return 0;
 303 }
 304
 305 /*
 306  * Initialization functions.
 307  */
 308 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
 309 {
 310         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 311         u32 word;
 312
 313         if (entry->queue->qid == QID_RX) {
 314                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 315
 316                 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
 317         } else {
 318                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 319
 320                 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
 321         }
 322 }
 323
 324 static void rt2800pci_clear_entry(struct queue_entry *entry)
 325 {
 326         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 327         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 328         u32 word;
 329
 330         if (entry->queue->qid == QID_RX) {
 331                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 332                 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
 333                 rt2x00_desc_write(entry_priv->desc, 0, word);
 334
 335                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 336                 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
 337                 rt2x00_desc_write(entry_priv->desc, 1, word);
 338         } else {
 339                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 340                 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
 341                 rt2x00_desc_write(entry_priv->desc, 1, word);
 342         }
 343 }
 344
 345 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
 346 {
 347         struct queue_entry_priv_pci *entry_priv;
 348         u32 reg;
 349
 350         /*
 351          * Initialize registers.
 352          */
 353         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 354         rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
 355         rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
 356         rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
 357         rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
 358
 359         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 360         rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
 361         rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
 362         rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
 363         rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
 364
 365         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
 366         rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
 367         rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
 368         rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
 369         rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
 370
 371         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
 372         rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
 373         rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
 374         rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
 375         rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
 376
 377         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 378         rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
 379         rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
 380         rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
 381         rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
 382
 383         /*
 384          * Enable global DMA configuration
 385          */
 386         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 387         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 388         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 389         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 390         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 391
 392         rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
 393
 394         return 0;
 395 }
 396
 397 /*
 398  * Device state switch handlers.
 399  */
 400 static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 401                                 enum dev_state state)
 402 {
 403         u32 reg;
 404
 405         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 406         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
 407                            (state == STATE_RADIO_RX_ON) ||
 408                            (state == STATE_RADIO_RX_ON_LINK));
 409         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 410 }
 411
 412 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 413                                  enum dev_state state)
 414 {
 415         int mask = (state == STATE_RADIO_IRQ_ON);
 416         u32 reg;
 417
 418         /*
 419          * When interrupts are being enabled, the interrupt registers
 420          * should clear the register to assure a clean state.
 421          */
 422         if (state == STATE_RADIO_IRQ_ON) {
 423                 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
 424                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
 425         }
 426
 427         rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
 428         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
 429         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
 430         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
 431         rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
 432         rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
 433         rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
 434         rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
 435         rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
 436         rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
 437         rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
 438         rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
 439         rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
 440         rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
 441         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
 442         rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
 443         rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
 444         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
 445         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
 446         rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
 447 }
 448
 449 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 450 {
 451         u32 reg;
 452         u16 word;
 453
 454         /*
 455          * Initialize all registers.
 456          */
 457         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
 458                      rt2800pci_init_queues(rt2x00dev) ||
 459                      rt2800_init_registers(rt2x00dev) ||
 460                      rt2800_wait_wpdma_ready(rt2x00dev) ||
 461                      rt2800_init_bbp(rt2x00dev) ||
 462                      rt2800_init_rfcsr(rt2x00dev)))
 463                 return -EIO;
 464
 465         /*
 466          * Send signal to firmware during boot time.
 467          */
 468         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
 469
 470         /*
 471          * Enable RX.
 472          */
 473         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 474         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
 475         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
 476         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 477
 478         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 479         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
 480         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
 481         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
 482         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 483         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 484
 485         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 486         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
 487         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
 488         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 489
 490         /*
 491          * Initialize LED control
 492          */
 493         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
 494         rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
 495                               word & 0xff, (word >> 8) & 0xff);
 496
 497         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
 498         rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
 499                               word & 0xff, (word >> 8) & 0xff);
 500
 501         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
 502         rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
 503                               word & 0xff, (word >> 8) & 0xff);
 504
 505         return 0;
 506 }
 507
 508 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 509 {
 510         u32 reg;
 511
 512         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 513         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 514         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 515         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 516         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 517         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 518         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 519
 520         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
 521         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
 522         rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
 523
 524         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
 525
 526         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 527         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
 528         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
 529         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
 530         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
 531         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
 532         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
 533         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
 534         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 535
 536         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
 537         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
 538
 539         /* Wait for DMA, ignore error */
 540         rt2800_wait_wpdma_ready(rt2x00dev);
 541 }
 542
 543 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
 544                                enum dev_state state)
 545 {
 546         /*
 547          * Always put the device to sleep (even when we intend to wakeup!)
 548          * if the device is booting and wasn't asleep it will return
 549          * failure when attempting to wakeup.
 550          */
 551         rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
 552
 553         if (state == STATE_AWAKE) {
 554                 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
 555                 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
 556         }
 557
 558         return 0;
 559 }
 560
 561 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
 562                                       enum dev_state state)
 563 {
 564         int retval = 0;
 565
 566         switch (state) {
 567         case STATE_RADIO_ON:
 568                 /*
 569                  * Before the radio can be enabled, the device first has
 570                  * to be woken up. After that it needs a bit of time
 571                  * to be fully awake and then the radio can be enabled.
 572                  */
 573                 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
 574                 msleep(1);
 575                 retval = rt2800pci_enable_radio(rt2x00dev);
 576                 break;
 577         case STATE_RADIO_OFF:
 578                 /*
 579                  * After the radio has been disabled, the device should
 580                  * be put to sleep for powersaving.
 581                  */
 582                 rt2800pci_disable_radio(rt2x00dev);
 583                 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
 584                 break;
 585         case STATE_RADIO_RX_ON:
 586         case STATE_RADIO_RX_ON_LINK:
 587         case STATE_RADIO_RX_OFF:
 588         case STATE_RADIO_RX_OFF_LINK:
 589                 rt2800pci_toggle_rx(rt2x00dev, state);
 590                 break;
 591         case STATE_RADIO_IRQ_ON:
 592         case STATE_RADIO_IRQ_OFF:
 593                 rt2800pci_toggle_irq(rt2x00dev, state);
 594                 break;
 595         case STATE_DEEP_SLEEP:
 596         case STATE_SLEEP:
 597         case STATE_STANDBY:
 598         case STATE_AWAKE:
 599                 retval = rt2800pci_set_state(rt2x00dev, state);
 600                 break;
 601         default:
 602                 retval = -ENOTSUPP;
 603                 break;
 604         }
 605
 606         if (unlikely(retval))
 607                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
 608                       state, retval);
 609
 610         return retval;
 611 }
 612
 613 /*
 614  * TX descriptor initialization
 615  */
 616 static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
 617                                     struct sk_buff *skb,
 618                                     struct txentry_desc *txdesc)
 619 {
 620         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
 621         __le32 *txd = skbdesc->desc;
 622         __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->ops->extra_tx_headroom);
 623         u32 word;
 624
 625         /*
 626          * Initialize TX Info descriptor
 627          */
 628         rt2x00_desc_read(txwi, 0, &word);
 629         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 630                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 631         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
 632         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 633         rt2x00_set_field32(&word, TXWI_W0_TS,
 634                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 635         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 636                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 637         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
 638         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
 639         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
 640         rt2x00_set_field32(&word, TXWI_W0_BW,
 641                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 642         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 643                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 644         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
 645         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 646         rt2x00_desc_write(txwi, 0, word);
 647
 648         rt2x00_desc_read(txwi, 1, &word);
 649         rt2x00_set_field32(&word, TXWI_W1_ACK,
 650                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 651         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 652                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 653         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
 654         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 655                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 656                            txdesc->key_idx : 0xff);
 657         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 658                            skb->len - txdesc->l2pad);
 659         rt2x00_set_field32(&word, TXWI_W1_PACKETID,
 660                            skbdesc->entry->queue->qid + 1);
 661         rt2x00_desc_write(txwi, 1, word);
 662
 663         /*
 664          * Always write 0 to IV/EIV fields, hardware will insert the IV
 665          * from the IVEIV register when TXD_W3_WIV is set to 0.
 666          * When TXD_W3_WIV is set to 1 it will use the IV data
 667          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 668          * crypto entry in the registers should be used to encrypt the frame.
 669          */
 670         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
 671         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
 672
 673         /*
 674          * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
 675          * must contains a TXWI structure + 802.11 header + padding + 802.11
 676          * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
 677          * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
 678          * data. It means that LAST_SEC0 is always 0.
 679          */
 680
 681         /*
 682          * Initialize TX descriptor
 683          */
 684         rt2x00_desc_read(txd, 0, &word);
 685         rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
 686         rt2x00_desc_write(txd, 0, word);
 687
 688         rt2x00_desc_read(txd, 1, &word);
 689         rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
 690         rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
 691                            !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 692         rt2x00_set_field32(&word, TXD_W1_BURST,
 693                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
 694         rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
 695                            rt2x00dev->ops->extra_tx_headroom);
 696         rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
 697         rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
 698         rt2x00_desc_write(txd, 1, word);
 699
 700         rt2x00_desc_read(txd, 2, &word);
 701         rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
 702                            skbdesc->skb_dma + rt2x00dev->ops->extra_tx_headroom);
 703         rt2x00_desc_write(txd, 2, word);
 704
 705         rt2x00_desc_read(txd, 3, &word);
 706         rt2x00_set_field32(&word, TXD_W3_WIV,
 707                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
 708         rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
 709         rt2x00_desc_write(txd, 3, word);
 710 }
 711
 712 /*
 713  * TX data initialization
 714  */
 715 static void rt2800pci_write_beacon(struct queue_entry *entry)
 716 {
 717         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 718         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 719         unsigned int beacon_base;
 720         u32 reg;
 721
 722         /*
 723          * Disable beaconing while we are reloading the beacon data,
 724          * otherwise we might be sending out invalid data.
 725          */
 726         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 727         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 728         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 729
 730         /*
 731          * Write entire beacon with descriptor to register.
 732          */
 733         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
 734         rt2800_register_multiwrite(rt2x00dev,
 735                                       beacon_base,
 736                                       skbdesc->desc, skbdesc->desc_len);
 737         rt2800_register_multiwrite(rt2x00dev,
 738                                       beacon_base + skbdesc->desc_len,
 739                                       entry->skb->data, entry->skb->len);
 740
 741         /*
 742          * Clean up beacon skb.
 743          */
 744         dev_kfree_skb_any(entry->skb);
 745         entry->skb = NULL;
 746 }
 747
 748 static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
 749                                     const enum data_queue_qid queue_idx)
 750 {
 751         struct data_queue *queue;
 752         unsigned int idx, qidx = 0;
 753         u32 reg;
 754
 755         if (queue_idx == QID_BEACON) {
 756                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 757                 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
 758                         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 759                         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 760                         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 761                         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 762                 }
 763                 return;
 764         }
 765
 766         if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
 767                 return;
 768
 769         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
 770         idx = queue->index[Q_INDEX];
 771
 772         if (queue_idx == QID_MGMT)
 773                 qidx = 5;
 774         else
 775                 qidx = queue_idx;
 776
 777         rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
 778 }
 779
 780 static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
 781                                     const enum data_queue_qid qid)
 782 {
 783         u32 reg;
 784
 785         if (qid == QID_BEACON) {
 786                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
 787                 return;
 788         }
 789
 790         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 791         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
 792         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
 793         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
 794         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
 795         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 796 }
 797
 798 /*
 799  * RX control handlers
 800  */
 801 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
 802                                   struct rxdone_entry_desc *rxdesc)
 803 {
 804         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 805         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 806         __le32 *rxd = entry_priv->desc;
 807         __le32 *rxwi = (__le32 *)entry->skb->data;
 808         u32 rxd3;
 809         u32 rxwi0;
 810         u32 rxwi1;
 811         u32 rxwi2;
 812         u32 rxwi3;
 813
 814         rt2x00_desc_read(rxd, 3, &rxd3);
 815         rt2x00_desc_read(rxwi, 0, &rxwi0);
 816         rt2x00_desc_read(rxwi, 1, &rxwi1);
 817         rt2x00_desc_read(rxwi, 2, &rxwi2);
 818         rt2x00_desc_read(rxwi, 3, &rxwi3);
 819
 820         if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
 821                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
 822
 823         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
 824                 /*
 825                  * Unfortunately we don't know the cipher type used during
 826                  * decryption. This prevents us from correct providing
 827                  * correct statistics through debugfs.
 828                  */
 829                 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
 830                 rxdesc->cipher_status =
 831                     rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
 832         }
 833
 834         if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
 835                 /*
 836                  * Hardware has stripped IV/EIV data from 802.11 frame during
 837                  * decryption. Unfortunately the descriptor doesn't contain
 838                  * any fields with the EIV/IV data either, so they can't
 839                  * be restored by rt2x00lib.
 840                  */
 841                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
 842
 843                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
 844                         rxdesc->flags |= RX_FLAG_DECRYPTED;
 845                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
 846                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
 847         }
 848
 849         if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
 850                 rxdesc->dev_flags |= RXDONE_MY_BSS;
 851
 852         if (rt2x00_get_field32(rxd3, RXD_W3_L2PAD))
 853                 rxdesc->dev_flags |= RXDONE_L2PAD;
 854
 855         if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
 856                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 857
 858         if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
 859                 rxdesc->flags |= RX_FLAG_40MHZ;
 860
 861         /*
 862          * Detect RX rate, always use MCS as signal type.
 863          */
 864         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 865         rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
 866         rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
 867
 868         /*
 869          * Mask of 0x8 bit to remove the short preamble flag.
 870          */
 871         if (rxdesc->rate_mode == RATE_MODE_CCK)
 872                 rxdesc->signal &= ~0x8;
 873
 874         rxdesc->rssi =
 875             (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
 876              rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
 877
 878         rxdesc->noise =
 879             (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
 880              rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
 881
 882         rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 883
 884         /*
 885          * Set RX IDX in register to inform hardware that we have handled
 886          * this entry and it is available for reuse again.
 887          */
 888         rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
 889
 890         /*
 891          * Remove TXWI descriptor from start of buffer.
 892          */
 893         skb_pull(entry->skb, RXWI_DESC_SIZE);
 894 }
 895
 896 /*
 897  * Interrupt functions.
 898  */
 899 static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
 900 {
 901         struct data_queue *queue;
 902         struct queue_entry *entry;
 903         __le32 *txwi;
 904         struct txdone_entry_desc txdesc;
 905         u32 word;
 906         u32 reg;
 907         u32 old_reg;
 908         int wcid, ack, pid, tx_wcid, tx_ack, tx_pid;
 909         u16 mcs, real_mcs;
 910
 911         /*
 912          * During each loop we will compare the freshly read
 913          * TX_STA_FIFO register value with the value read from
 914          * the previous loop. If the 2 values are equal then
 915          * we should stop processing because the chance it
 916          * quite big that the device has been unplugged and
 917          * we risk going into an endless loop.
 918          */
 919         old_reg = 0;
 920
 921         while (1) {
 922                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
 923                 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
 924                         break;
 925
 926                 if (old_reg == reg)
 927                         break;
 928                 old_reg = reg;
 929
 930                 wcid    = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
 931                 ack     = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
 932                 pid     = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
 933
 934                 /*
 935                  * Skip this entry when it contains an invalid
 936                  * queue identication number.
 937                  */
 938                 if (pid <= 0 || pid > QID_RX)
 939                         continue;
 940
 941                 queue = rt2x00queue_get_queue(rt2x00dev, pid - 1);
 942                 if (unlikely(!queue))
 943                         continue;
 944
 945                 /*
 946                  * Inside each queue, we process each entry in a chronological
 947                  * order. We first check that the queue is not empty.
 948                  */
 949                 if (rt2x00queue_empty(queue))
 950                         continue;
 951                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
 952
 953                 /* Check if we got a match by looking at WCID/ACK/PID
 954                  * fields */
 955                 txwi = (__le32 *)(entry->skb->data -
 956                                   rt2x00dev->ops->extra_tx_headroom);
 957
 958                 rt2x00_desc_read(txwi, 1, &word);
 959                 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
 960                 tx_ack  = rt2x00_get_field32(word, TXWI_W1_ACK);
 961                 tx_pid  = rt2x00_get_field32(word, TXWI_W1_PACKETID);
 962
 963                 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid))
 964                         WARNING(rt2x00dev, "invalid TX_STA_FIFO content\n");
 965
 966                 /*
 967                  * Obtain the status about this packet.
 968                  */
 969                 txdesc.flags = 0;
 970                 rt2x00_desc_read(txwi, 0, &word);
 971                 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 972                 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
 973
 974                 /*
 975                  * Ralink has a retry mechanism using a global fallback
 976                  * table. We setup this fallback table to try the immediate
 977                  * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 978                  * always contains the MCS used for the last transmission, be
 979                  * it successful or not.
 980                  */
 981                 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS)) {
 982                         /*
 983                          * Transmission succeeded. The number of retries is
 984                          * mcs - real_mcs
 985                          */
 986                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 987                         txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 988                 } else {
 989                         /*
 990                          * Transmission failed. The number of retries is
 991                          * always 7 in this case (for a total number of 8
 992                          * frames sent).
 993                          */
 994                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
 995                         txdesc.retry = 7;
 996                 }
 997
 998                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 999
1000
1001                 rt2x00lib_txdone(entry, &txdesc);
1002         }
1003 }
1004
1005 static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
1006 {
1007         struct ieee80211_conf conf = { .flags = 0 };
1008         struct rt2x00lib_conf libconf = { .conf = &conf };
1009
1010         rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
1011 }
1012
1013 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
1014 {
1015         struct rt2x00_dev *rt2x00dev = dev_instance;
1016         u32 reg;
1017
1018         /* Read status and ACK all interrupts */
1019         rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1020         rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1021
1022         if (!reg)
1023                 return IRQ_NONE;
1024
1025         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1026                 return IRQ_HANDLED;
1027
1028         /*
1029          * 1 - Rx ring done interrupt.
1030          */
1031         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
1032                 rt2x00pci_rxdone(rt2x00dev);
1033
1034         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
1035                 rt2800pci_txdone(rt2x00dev);
1036
1037         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
1038                 rt2800pci_wakeup(rt2x00dev);
1039
1040         return IRQ_HANDLED;
1041 }
1042
1043 /*
1044  * Device probe functions.
1045  */
1046 static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1047 {
1048         /*
1049          * Read EEPROM into buffer
1050          */
1051         if (rt2x00_is_soc(rt2x00dev))
1052                 rt2800pci_read_eeprom_soc(rt2x00dev);
1053         else if (rt2800pci_efuse_detect(rt2x00dev))
1054                 rt2800pci_read_eeprom_efuse(rt2x00dev);
1055         else
1056                 rt2800pci_read_eeprom_pci(rt2x00dev);
1057
1058         return rt2800_validate_eeprom(rt2x00dev);
1059 }
1060
1061 static const struct rt2800_ops rt2800pci_rt2800_ops = {
1062         .register_read          = rt2x00pci_register_read,
1063         .register_read_lock     = rt2x00pci_register_read, /* same for PCI */
1064         .register_write         = rt2x00pci_register_write,
1065         .register_write_lock    = rt2x00pci_register_write, /* same for PCI */
1066
1067         .register_multiread     = rt2x00pci_register_multiread,
1068         .register_multiwrite    = rt2x00pci_register_multiwrite,
1069
1070         .regbusy_read           = rt2x00pci_regbusy_read,
1071 };
1072
1073 static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1074 {
1075         int retval;
1076
1077         rt2x00dev->priv = (void *)&rt2800pci_rt2800_ops;
1078
1079         /*
1080          * Allocate eeprom data.
1081          */
1082         retval = rt2800pci_validate_eeprom(rt2x00dev);
1083         if (retval)
1084                 return retval;
1085
1086         retval = rt2800_init_eeprom(rt2x00dev);
1087         if (retval)
1088                 return retval;
1089
1090         /*
1091          * Initialize hw specifications.
1092          */
1093         retval = rt2800_probe_hw_mode(rt2x00dev);
1094         if (retval)
1095                 return retval;
1096
1097         /*
1098          * This device has multiple filters for control frames
1099          * and has a separate filter for PS Poll frames.
1100          */
1101         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
1102         __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
1103
1104         /*
1105          * This device requires firmware.
1106          */
1107         if (!rt2x00_is_soc(rt2x00dev))
1108                 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1109         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1110         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
1111         if (!modparam_nohwcrypt)
1112                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
1113
1114         /*
1115          * Set the rssi offset.
1116          */
1117         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1118
1119         return 0;
1120 }
1121
1122 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1123         .irq_handler            = rt2800pci_interrupt,
1124         .probe_hw               = rt2800pci_probe_hw,
1125         .get_firmware_name      = rt2800pci_get_firmware_name,
1126         .check_firmware         = rt2800pci_check_firmware,
1127         .load_firmware          = rt2800pci_load_firmware,
1128         .initialize             = rt2x00pci_initialize,
1129         .uninitialize           = rt2x00pci_uninitialize,
1130         .get_entry_state        = rt2800pci_get_entry_state,
1131         .clear_entry            = rt2800pci_clear_entry,
1132         .set_device_state       = rt2800pci_set_device_state,
1133         .rfkill_poll            = rt2800_rfkill_poll,
1134         .link_stats             = rt2800_link_stats,
1135         .reset_tuner            = rt2800_reset_tuner,
1136         .link_tuner             = rt2800_link_tuner,
1137         .write_tx_desc          = rt2800pci_write_tx_desc,
1138         .write_tx_data          = rt2x00pci_write_tx_data,
1139         .write_beacon           = rt2800pci_write_beacon,
1140         .kick_tx_queue          = rt2800pci_kick_tx_queue,
1141         .kill_tx_queue          = rt2800pci_kill_tx_queue,
1142         .fill_rxdone            = rt2800pci_fill_rxdone,
1143         .config_shared_key      = rt2800_config_shared_key,
1144         .config_pairwise_key    = rt2800_config_pairwise_key,
1145         .config_filter          = rt2800_config_filter,
1146         .config_intf            = rt2800_config_intf,
1147         .config_erp             = rt2800_config_erp,
1148         .config_ant             = rt2800_config_ant,
1149         .config                 = rt2800_config,
1150 };
1151
1152 static const struct data_queue_desc rt2800pci_queue_rx = {
1153         .entry_num              = RX_ENTRIES,
1154         .data_size              = AGGREGATION_SIZE,
1155         .desc_size              = RXD_DESC_SIZE,
1156         .priv_size              = sizeof(struct queue_entry_priv_pci),
1157 };
1158
1159 static const struct data_queue_desc rt2800pci_queue_tx = {
1160         .entry_num              = TX_ENTRIES,
1161         .data_size              = AGGREGATION_SIZE,
1162         .desc_size              = TXD_DESC_SIZE,
1163         .priv_size              = sizeof(struct queue_entry_priv_pci),
1164 };
1165
1166 static const struct data_queue_desc rt2800pci_queue_bcn = {
1167         .entry_num              = 8 * BEACON_ENTRIES,
1168         .data_size              = 0, /* No DMA required for beacons */
1169         .desc_size              = TXWI_DESC_SIZE,
1170         .priv_size              = sizeof(struct queue_entry_priv_pci),
1171 };
1172
1173 static const struct rt2x00_ops rt2800pci_ops = {
1174         .name                   = KBUILD_MODNAME,
1175         .max_sta_intf           = 1,
1176         .max_ap_intf            = 8,
1177         .eeprom_size            = EEPROM_SIZE,
1178         .rf_size                = RF_SIZE,
1179         .tx_queues              = NUM_TX_QUEUES,
1180         .extra_tx_headroom      = TXWI_DESC_SIZE,
1181         .rx                     = &rt2800pci_queue_rx,
1182         .tx                     = &rt2800pci_queue_tx,
1183         .bcn                    = &rt2800pci_queue_bcn,
1184         .lib                    = &rt2800pci_rt2x00_ops,
1185         .hw                     = &rt2800_mac80211_ops,
1186 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1187         .debugfs                = &rt2800_rt2x00debug,
1188 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1189 };
1190
1191 /*
1192  * RT2800pci module information.
1193  */
1194 #ifdef CONFIG_RT2800PCI_PCI
1195 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1196         { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1197         { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1198         { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1199         { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
1200         { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1201         { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1202         { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1203         { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1204         { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1205         { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1206         { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
1207         { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1208 #ifdef CONFIG_RT2800PCI_RT30XX
1209         { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1210         { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1211         { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
1212         { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1213 #endif
1214 #ifdef CONFIG_RT2800PCI_RT35XX
1215         { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1216         { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
1217         { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1218         { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1219         { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
1220 #endif
1221         { 0, }
1222 };
1223 #endif /* CONFIG_RT2800PCI_PCI */
1224
1225 MODULE_AUTHOR(DRV_PROJECT);
1226 MODULE_VERSION(DRV_VERSION);
1227 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1228 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1229 #ifdef CONFIG_RT2800PCI_PCI
1230 MODULE_FIRMWARE(FIRMWARE_RT2860);
1231 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1232 #endif /* CONFIG_RT2800PCI_PCI */
1233 MODULE_LICENSE("GPL");
1234
1235 #ifdef CONFIG_RT2800PCI_SOC
1236 static int rt2800soc_probe(struct platform_device *pdev)
1237 {
1238         return rt2x00soc_probe(pdev, &rt2800pci_ops);
1239 }
1240
1241 static struct platform_driver rt2800soc_driver = {
1242         .driver         = {
1243                 .name           = "rt2800_wmac",
1244                 .owner          = THIS_MODULE,
1245                 .mod_name       = KBUILD_MODNAME,
1246         },
1247         .probe          = rt2800soc_probe,
1248         .remove         = __devexit_p(rt2x00soc_remove),
1249         .suspend        = rt2x00soc_suspend,
1250         .resume         = rt2x00soc_resume,
1251 };
1252 #endif /* CONFIG_RT2800PCI_SOC */
1253
1254 #ifdef CONFIG_RT2800PCI_PCI
1255 static struct pci_driver rt2800pci_driver = {
1256         .name           = KBUILD_MODNAME,
1257         .id_table       = rt2800pci_device_table,
1258         .probe          = rt2x00pci_probe,
1259         .remove         = __devexit_p(rt2x00pci_remove),
1260         .suspend        = rt2x00pci_suspend,
1261         .resume         = rt2x00pci_resume,
1262 };
1263 #endif /* CONFIG_RT2800PCI_PCI */
1264
1265 static int __init rt2800pci_init(void)
1266 {
1267         int ret = 0;
1268
1269 #ifdef CONFIG_RT2800PCI_SOC
1270         ret = platform_driver_register(&rt2800soc_driver);
1271         if (ret)
1272                 return ret;
1273 #endif
1274 #ifdef CONFIG_RT2800PCI_PCI
1275         ret = pci_register_driver(&rt2800pci_driver);
1276         if (ret) {
1277 #ifdef CONFIG_RT2800PCI_SOC
1278                 platform_driver_unregister(&rt2800soc_driver);
1279 #endif
1280                 return ret;
1281         }
1282 #endif
1283
1284         return ret;
1285 }
1286
1287 static void __exit rt2800pci_exit(void)
1288 {
1289 #ifdef CONFIG_RT2800PCI_PCI
1290         pci_unregister_driver(&rt2800pci_driver);
1291 #endif
1292 #ifdef CONFIG_RT2800PCI_SOC
1293         platform_driver_unregister(&rt2800soc_driver);
1294 #endif
1295 }
1296
1297 module_init(rt2800pci_init);
1298 module_exit(rt2800pci_exit);