SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   3         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   4
   5         Based on the original rt2800pci.c and rt2800usb.c.
   6           Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
   7           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   8           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   9           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  10           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  11           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  12           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  13           <http://rt2x00.serialmonkey.com>
  14
  15         This program is free software; you can redistribute it and/or modify
  16         it under the terms of the GNU General Public License as published by
  17         the Free Software Foundation; either version 2 of the License, or
  18         (at your option) any later version.
  19
  20         This program is distributed in the hope that it will be useful,
  21         but WITHOUT ANY WARRANTY; without even the implied warranty of
  22         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23         GNU General Public License for more details.
  24
  25         You should have received a copy of the GNU General Public License
  26         along with this program; if not, write to the
  27         Free Software Foundation, Inc.,
  28         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  29  */
  30
  31 /*
  32         Module: rt2800lib
  33         Abstract: rt2800 generic device routines.
  34  */
  35
  36 #include <linux/kernel.h>
  37 #include <linux/module.h>
  38
  39 #include "rt2x00.h"
  40 #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
  41 #include "rt2x00usb.h"
  42 #endif
  43 #if defined(CONFIG_RT2X00_LIB_PCI) || defined(CONFIG_RT2X00_LIB_PCI_MODULE)
  44 #include "rt2x00pci.h"
  45 #endif
  46 #include "rt2800lib.h"
  47 #include "rt2800.h"
  48 #include "rt2800usb.h"
  49
  50 MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
  51 MODULE_DESCRIPTION("rt2800 library");
  52 MODULE_LICENSE("GPL");
  53
  54 /*
  55  * Register access.
  56  * All access to the CSR registers will go through the methods
  57  * rt2800_register_read and rt2800_register_write.
  58  * BBP and RF register require indirect register access,
  59  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  60  * These indirect registers work with busy bits,
  61  * and we will try maximal REGISTER_BUSY_COUNT times to access
  62  * the register while taking a REGISTER_BUSY_DELAY us delay
  63  * between each attampt. When the busy bit is still set at that time,
  64  * the access attempt is considered to have failed,
  65  * and we will print an error.
  66  * The _lock versions must be used if you already hold the csr_mutex
  67  */
  68 #define WAIT_FOR_BBP(__dev, __reg) \
  69         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  70 #define WAIT_FOR_RFCSR(__dev, __reg) \
  71         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  72 #define WAIT_FOR_RF(__dev, __reg) \
  73         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  74 #define WAIT_FOR_MCU(__dev, __reg) \
  75         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  76                             H2M_MAILBOX_CSR_OWNER, (__reg))
  77
  78 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  79                              const unsigned int word, const u8 value)
  80 {
  81         u32 reg;
  82
  83         mutex_lock(&rt2x00dev->csr_mutex);
  84
  85         /*
  86          * Wait until the BBP becomes available, afterwards we
  87          * can safely write the new data into the register.
  88          */
  89         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  90                 reg = 0;
  91                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
  92                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  93                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  94                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
  95                 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
  96                         rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
  97
  98                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
  99         }
 100
 101         mutex_unlock(&rt2x00dev->csr_mutex);
 102 }
 103
 104 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 105                             const unsigned int word, u8 *value)
 106 {
 107         u32 reg;
 108
 109         mutex_lock(&rt2x00dev->csr_mutex);
 110
 111         /*
 112          * Wait until the BBP becomes available, afterwards we
 113          * can safely write the read request into the register.
 114          * After the data has been written, we wait until hardware
 115          * returns the correct value, if at any time the register
 116          * doesn't become available in time, reg will be 0xffffffff
 117          * which means we return 0xff to the caller.
 118          */
 119         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 120                 reg = 0;
 121                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 122                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 123                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 124                 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
 125                         rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 126
 127                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 128
 129                 WAIT_FOR_BBP(rt2x00dev, &reg);
 130         }
 131
 132         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 133
 134         mutex_unlock(&rt2x00dev->csr_mutex);
 135 }
 136
 137 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 138                                const unsigned int word, const u8 value)
 139 {
 140         u32 reg;
 141
 142         mutex_lock(&rt2x00dev->csr_mutex);
 143
 144         /*
 145          * Wait until the RFCSR becomes available, afterwards we
 146          * can safely write the new data into the register.
 147          */
 148         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 149                 reg = 0;
 150                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 151                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 152                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 153                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 154
 155                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 156         }
 157
 158         mutex_unlock(&rt2x00dev->csr_mutex);
 159 }
 160
 161 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 162                               const unsigned int word, u8 *value)
 163 {
 164         u32 reg;
 165
 166         mutex_lock(&rt2x00dev->csr_mutex);
 167
 168         /*
 169          * Wait until the RFCSR becomes available, afterwards we
 170          * can safely write the read request into the register.
 171          * After the data has been written, we wait until hardware
 172          * returns the correct value, if at any time the register
 173          * doesn't become available in time, reg will be 0xffffffff
 174          * which means we return 0xff to the caller.
 175          */
 176         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 177                 reg = 0;
 178                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 179                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 180                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 181
 182                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 183
 184                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 185         }
 186
 187         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 188
 189         mutex_unlock(&rt2x00dev->csr_mutex);
 190 }
 191
 192 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 193                             const unsigned int word, const u32 value)
 194 {
 195         u32 reg;
 196
 197         mutex_lock(&rt2x00dev->csr_mutex);
 198
 199         /*
 200          * Wait until the RF becomes available, afterwards we
 201          * can safely write the new data into the register.
 202          */
 203         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 204                 reg = 0;
 205                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 206                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 207                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 208                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 209
 210                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 211                 rt2x00_rf_write(rt2x00dev, word, value);
 212         }
 213
 214         mutex_unlock(&rt2x00dev->csr_mutex);
 215 }
 216
 217 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 218                         const u8 command, const u8 token,
 219                         const u8 arg0, const u8 arg1)
 220 {
 221         u32 reg;
 222
 223         /*
 224          * SOC devices don't support MCU requests.
 225          */
 226         if (rt2x00_is_soc(rt2x00dev))
 227                 return;
 228
 229         mutex_lock(&rt2x00dev->csr_mutex);
 230
 231         /*
 232          * Wait until the MCU becomes available, afterwards we
 233          * can safely write the new data into the register.
 234          */
 235         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 236                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 237                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 238                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 239                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 240                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 241
 242                 reg = 0;
 243                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 244                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 245         }
 246
 247         mutex_unlock(&rt2x00dev->csr_mutex);
 248 }
 249 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 250
 251 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 252 {
 253         unsigned int i;
 254         u32 reg;
 255
 256         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 257                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 258                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 259                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 260                         return 0;
 261
 262                 msleep(1);
 263         }
 264
 265         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
 266         return -EACCES;
 267 }
 268 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 269
 270 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 271 const struct rt2x00debug rt2800_rt2x00debug = {
 272         .owner  = THIS_MODULE,
 273         .csr    = {
 274                 .read           = rt2800_register_read,
 275                 .write          = rt2800_register_write,
 276                 .flags          = RT2X00DEBUGFS_OFFSET,
 277                 .word_base      = CSR_REG_BASE,
 278                 .word_size      = sizeof(u32),
 279                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 280         },
 281         .eeprom = {
 282                 .read           = rt2x00_eeprom_read,
 283                 .write          = rt2x00_eeprom_write,
 284                 .word_base      = EEPROM_BASE,
 285                 .word_size      = sizeof(u16),
 286                 .word_count     = EEPROM_SIZE / sizeof(u16),
 287         },
 288         .bbp    = {
 289                 .read           = rt2800_bbp_read,
 290                 .write          = rt2800_bbp_write,
 291                 .word_base      = BBP_BASE,
 292                 .word_size      = sizeof(u8),
 293                 .word_count     = BBP_SIZE / sizeof(u8),
 294         },
 295         .rf     = {
 296                 .read           = rt2x00_rf_read,
 297                 .write          = rt2800_rf_write,
 298                 .word_base      = RF_BASE,
 299                 .word_size      = sizeof(u32),
 300                 .word_count     = RF_SIZE / sizeof(u32),
 301         },
 302 };
 303 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 304 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 305
 306 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 307 {
 308         u32 reg;
 309
 310         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 311         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 312 }
 313 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 314
 315 #ifdef CONFIG_RT2X00_LIB_LEDS
 316 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 317                                   enum led_brightness brightness)
 318 {
 319         struct rt2x00_led *led =
 320             container_of(led_cdev, struct rt2x00_led, led_dev);
 321         unsigned int enabled = brightness != LED_OFF;
 322         unsigned int bg_mode =
 323             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 324         unsigned int polarity =
 325                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 326                                    EEPROM_FREQ_LED_POLARITY);
 327         unsigned int ledmode =
 328                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 329                                    EEPROM_FREQ_LED_MODE);
 330
 331         if (led->type == LED_TYPE_RADIO) {
 332                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 333                                       enabled ? 0x20 : 0);
 334         } else if (led->type == LED_TYPE_ASSOC) {
 335                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 336                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 337         } else if (led->type == LED_TYPE_QUALITY) {
 338                 /*
 339                  * The brightness is divided into 6 levels (0 - 5),
 340                  * The specs tell us the following levels:
 341                  *      0, 1 ,3, 7, 15, 31
 342                  * to determine the level in a simple way we can simply
 343                  * work with bitshifting:
 344                  *      (1 << level) - 1
 345                  */
 346                 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 347                                       (1 << brightness / (LED_FULL / 6)) - 1,
 348                                       polarity);
 349         }
 350 }
 351
 352 static int rt2800_blink_set(struct led_classdev *led_cdev,
 353                             unsigned long *delay_on, unsigned long *delay_off)
 354 {
 355         struct rt2x00_led *led =
 356             container_of(led_cdev, struct rt2x00_led, led_dev);
 357         u32 reg;
 358
 359         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 360         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 361         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 362         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 363
 364         return 0;
 365 }
 366
 367 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 368                      struct rt2x00_led *led, enum led_type type)
 369 {
 370         led->rt2x00dev = rt2x00dev;
 371         led->type = type;
 372         led->led_dev.brightness_set = rt2800_brightness_set;
 373         led->led_dev.blink_set = rt2800_blink_set;
 374         led->flags = LED_INITIALIZED;
 375 }
 376 #endif /* CONFIG_RT2X00_LIB_LEDS */
 377
 378 /*
 379  * Configuration handlers.
 380  */
 381 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 382                                     struct rt2x00lib_crypto *crypto,
 383                                     struct ieee80211_key_conf *key)
 384 {
 385         struct mac_wcid_entry wcid_entry;
 386         struct mac_iveiv_entry iveiv_entry;
 387         u32 offset;
 388         u32 reg;
 389
 390         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 391
 392         rt2800_register_read(rt2x00dev, offset, &reg);
 393         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 394                            !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 395         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 396                            (crypto->cmd == SET_KEY) * crypto->cipher);
 397         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 398                            (crypto->cmd == SET_KEY) * crypto->bssidx);
 399         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 400         rt2800_register_write(rt2x00dev, offset, reg);
 401
 402         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 403
 404         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 405         if ((crypto->cipher == CIPHER_TKIP) ||
 406             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 407             (crypto->cipher == CIPHER_AES))
 408                 iveiv_entry.iv[3] |= 0x20;
 409         iveiv_entry.iv[3] |= key->keyidx << 6;
 410         rt2800_register_multiwrite(rt2x00dev, offset,
 411                                       &iveiv_entry, sizeof(iveiv_entry));
 412
 413         offset = MAC_WCID_ENTRY(key->hw_key_idx);
 414
 415         memset(&wcid_entry, 0, sizeof(wcid_entry));
 416         if (crypto->cmd == SET_KEY)
 417                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 418         rt2800_register_multiwrite(rt2x00dev, offset,
 419                                       &wcid_entry, sizeof(wcid_entry));
 420 }
 421
 422 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
 423                              struct rt2x00lib_crypto *crypto,
 424                              struct ieee80211_key_conf *key)
 425 {
 426         struct hw_key_entry key_entry;
 427         struct rt2x00_field32 field;
 428         u32 offset;
 429         u32 reg;
 430
 431         if (crypto->cmd == SET_KEY) {
 432                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 433
 434                 memcpy(key_entry.key, crypto->key,
 435                        sizeof(key_entry.key));
 436                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 437                        sizeof(key_entry.tx_mic));
 438                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 439                        sizeof(key_entry.rx_mic));
 440
 441                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 442                 rt2800_register_multiwrite(rt2x00dev, offset,
 443                                               &key_entry, sizeof(key_entry));
 444         }
 445
 446         /*
 447          * The cipher types are stored over multiple registers
 448          * starting with SHARED_KEY_MODE_BASE each word will have
 449          * 32 bits and contains the cipher types for 2 bssidx each.
 450          * Using the correct defines correctly will cause overhead,
 451          * so just calculate the correct offset.
 452          */
 453         field.bit_offset = 4 * (key->hw_key_idx % 8);
 454         field.bit_mask = 0x7 << field.bit_offset;
 455
 456         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
 457
 458         rt2800_register_read(rt2x00dev, offset, &reg);
 459         rt2x00_set_field32(&reg, field,
 460                            (crypto->cmd == SET_KEY) * crypto->cipher);
 461         rt2800_register_write(rt2x00dev, offset, reg);
 462
 463         /*
 464          * Update WCID information
 465          */
 466         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
 467
 468         return 0;
 469 }
 470 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
 471
 472 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 473                                struct rt2x00lib_crypto *crypto,
 474                                struct ieee80211_key_conf *key)
 475 {
 476         struct hw_key_entry key_entry;
 477         u32 offset;
 478
 479         if (crypto->cmd == SET_KEY) {
 480                 /*
 481                  * 1 pairwise key is possible per AID, this means that the AID
 482                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
 483                  * last possible shared key entry.
 484                  */
 485                 if (crypto->aid > (256 - 32))
 486                         return -ENOSPC;
 487
 488                 key->hw_key_idx = 32 + crypto->aid;
 489
 490                 memcpy(key_entry.key, crypto->key,
 491                        sizeof(key_entry.key));
 492                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 493                        sizeof(key_entry.tx_mic));
 494                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 495                        sizeof(key_entry.rx_mic));
 496
 497                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 498                 rt2800_register_multiwrite(rt2x00dev, offset,
 499                                               &key_entry, sizeof(key_entry));
 500         }
 501
 502         /*
 503          * Update WCID information
 504          */
 505         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
 506
 507         return 0;
 508 }
 509 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
 510
 511 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
 512                           const unsigned int filter_flags)
 513 {
 514         u32 reg;
 515
 516         /*
 517          * Start configuration steps.
 518          * Note that the version error will always be dropped
 519          * and broadcast frames will always be accepted since
 520          * there is no filter for it at this time.
 521          */
 522         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
 523         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 524                            !(filter_flags & FIF_FCSFAIL));
 525         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 526                            !(filter_flags & FIF_PLCPFAIL));
 527         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 528                            !(filter_flags & FIF_PROMISC_IN_BSS));
 529         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
 530         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 531         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 532                            !(filter_flags & FIF_ALLMULTI));
 533         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 534         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 535         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 536                            !(filter_flags & FIF_CONTROL));
 537         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 538                            !(filter_flags & FIF_CONTROL));
 539         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 540                            !(filter_flags & FIF_CONTROL));
 541         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 542                            !(filter_flags & FIF_CONTROL));
 543         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 544                            !(filter_flags & FIF_CONTROL));
 545         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 546                            !(filter_flags & FIF_PSPOLL));
 547         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
 548         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
 549         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 550                            !(filter_flags & FIF_CONTROL));
 551         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 552 }
 553 EXPORT_SYMBOL_GPL(rt2800_config_filter);
 554
 555 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
 556                         struct rt2x00intf_conf *conf, const unsigned int flags)
 557 {
 558         unsigned int beacon_base;
 559         u32 reg;
 560
 561         if (flags & CONFIG_UPDATE_TYPE) {
 562                 /*
 563                  * Clear current synchronisation setup.
 564                  * For the Beacon base registers we only need to clear
 565                  * the first byte since that byte contains the VALID and OWNER
 566                  * bits which (when set to 0) will invalidate the entire beacon.
 567                  */
 568                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 569                 rt2800_register_write(rt2x00dev, beacon_base, 0);
 570
 571                 /*
 572                  * Enable synchronisation.
 573                  */
 574                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 575                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 576                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 577                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
 578                                    (conf->sync == TSF_SYNC_BEACON));
 579                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 580         }
 581
 582         if (flags & CONFIG_UPDATE_MAC) {
 583                 reg = le32_to_cpu(conf->mac[1]);
 584                 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 585                 conf->mac[1] = cpu_to_le32(reg);
 586
 587                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 588                                               conf->mac, sizeof(conf->mac));
 589         }
 590
 591         if (flags & CONFIG_UPDATE_BSSID) {
 592                 reg = le32_to_cpu(conf->bssid[1]);
 593                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
 594                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 595                 conf->bssid[1] = cpu_to_le32(reg);
 596
 597                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 598                                               conf->bssid, sizeof(conf->bssid));
 599         }
 600 }
 601 EXPORT_SYMBOL_GPL(rt2800_config_intf);
 602
 603 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
 604 {
 605         u32 reg;
 606
 607         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
 608         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
 609                            !!erp->short_preamble);
 610         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 611                            !!erp->short_preamble);
 612         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 613
 614         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
 615         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 616                            erp->cts_protection ? 2 : 0);
 617         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 618
 619         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 620                                  erp->basic_rates);
 621         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
 622
 623         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
 624         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
 625         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 626
 627         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
 628         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
 629         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
 630         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 631         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 632
 633         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 634         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 635                            erp->beacon_int * 16);
 636         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 637 }
 638 EXPORT_SYMBOL_GPL(rt2800_config_erp);
 639
 640 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
 641 {
 642         u8 r1;
 643         u8 r3;
 644
 645         rt2800_bbp_read(rt2x00dev, 1, &r1);
 646         rt2800_bbp_read(rt2x00dev, 3, &r3);
 647
 648         /*
 649          * Configure the TX antenna.
 650          */
 651         switch ((int)ant->tx) {
 652         case 1:
 653                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
 654                 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
 655                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 656                 break;
 657         case 2:
 658                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
 659                 break;
 660         case 3:
 661                 /* Do nothing */
 662                 break;
 663         }
 664
 665         /*
 666          * Configure the RX antenna.
 667          */
 668         switch ((int)ant->rx) {
 669         case 1:
 670                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 671                 break;
 672         case 2:
 673                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 674                 break;
 675         case 3:
 676                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 677                 break;
 678         }
 679
 680         rt2800_bbp_write(rt2x00dev, 3, r3);
 681         rt2800_bbp_write(rt2x00dev, 1, r1);
 682 }
 683 EXPORT_SYMBOL_GPL(rt2800_config_ant);
 684
 685 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 686                                    struct rt2x00lib_conf *libconf)
 687 {
 688         u16 eeprom;
 689         short lna_gain;
 690
 691         if (libconf->rf.channel <= 14) {
 692                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 693                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 694         } else if (libconf->rf.channel <= 64) {
 695                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 696                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 697         } else if (libconf->rf.channel <= 128) {
 698                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 699                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
 700         } else {
 701                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 702                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
 703         }
 704
 705         rt2x00dev->lna_gain = lna_gain;
 706 }
 707
 708 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
 709                                          struct ieee80211_conf *conf,
 710                                          struct rf_channel *rf,
 711                                          struct channel_info *info)
 712 {
 713         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 714
 715         if (rt2x00dev->default_ant.tx == 1)
 716                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 717
 718         if (rt2x00dev->default_ant.rx == 1) {
 719                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 720                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 721         } else if (rt2x00dev->default_ant.rx == 2)
 722                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 723
 724         if (rf->channel > 14) {
 725                 /*
 726                  * When TX power is below 0, we should increase it by 7 to
 727                  * make it a positive value (Minumum value is -7).
 728                  * However this means that values between 0 and 7 have
 729                  * double meaning, and we should set a 7DBm boost flag.
 730                  */
 731                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 732                                    (info->tx_power1 >= 0));
 733
 734                 if (info->tx_power1 < 0)
 735                         info->tx_power1 += 7;
 736
 737                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
 738                                    TXPOWER_A_TO_DEV(info->tx_power1));
 739
 740                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 741                                    (info->tx_power2 >= 0));
 742
 743                 if (info->tx_power2 < 0)
 744                         info->tx_power2 += 7;
 745
 746                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
 747                                    TXPOWER_A_TO_DEV(info->tx_power2));
 748         } else {
 749                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
 750                                    TXPOWER_G_TO_DEV(info->tx_power1));
 751                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
 752                                    TXPOWER_G_TO_DEV(info->tx_power2));
 753         }
 754
 755         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
 756
 757         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 758         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 759         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 760         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 761
 762         udelay(200);
 763
 764         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 765         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 766         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 767         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 768
 769         udelay(200);
 770
 771         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 772         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 773         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 774         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 775 }
 776
 777 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
 778                                          struct ieee80211_conf *conf,
 779                                          struct rf_channel *rf,
 780                                          struct channel_info *info)
 781 {
 782         u8 rfcsr;
 783
 784         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
 785         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
 786
 787         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
 788         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
 789         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
 790
 791         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
 792         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
 793                           TXPOWER_G_TO_DEV(info->tx_power1));
 794         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
 795
 796         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
 797         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 798         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
 799
 800         rt2800_rfcsr_write(rt2x00dev, 24,
 801                               rt2x00dev->calibration[conf_is_ht40(conf)]);
 802
 803         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
 804         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 805         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
 806 }
 807
 808 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
 809                                   struct ieee80211_conf *conf,
 810                                   struct rf_channel *rf,
 811                                   struct channel_info *info)
 812 {
 813         u32 reg;
 814         unsigned int tx_pin;
 815         u8 bbp;
 816
 817         if (rt2x00_rf(rt2x00dev, RF2020) ||
 818             rt2x00_rf(rt2x00dev, RF3020) ||
 819             rt2x00_rf(rt2x00dev, RF3021) ||
 820             rt2x00_rf(rt2x00dev, RF3022))
 821                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
 822         else
 823                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
 824
 825         /*
 826          * Change BBP settings
 827          */
 828         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 829         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 830         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 831         rt2800_bbp_write(rt2x00dev, 86, 0);
 832
 833         if (rf->channel <= 14) {
 834                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 835                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
 836                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 837                 } else {
 838                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
 839                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 840                 }
 841         } else {
 842                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
 843
 844                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 845                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 846                 else
 847                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 848         }
 849
 850         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 851         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
 852         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
 853         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
 854         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
 855
 856         tx_pin = 0;
 857
 858         /* Turn on unused PA or LNA when not using 1T or 1R */
 859         if (rt2x00dev->default_ant.tx != 1) {
 860                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
 861                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 862         }
 863
 864         /* Turn on unused PA or LNA when not using 1T or 1R */
 865         if (rt2x00dev->default_ant.rx != 1) {
 866                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 867                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 868         }
 869
 870         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
 871         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
 872         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 873         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 874         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
 875         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
 876
 877         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 878
 879         rt2800_bbp_read(rt2x00dev, 4, &bbp);
 880         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
 881         rt2800_bbp_write(rt2x00dev, 4, bbp);
 882
 883         rt2800_bbp_read(rt2x00dev, 3, &bbp);
 884         rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
 885         rt2800_bbp_write(rt2x00dev, 3, bbp);
 886
 887         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
 888                 if (conf_is_ht40(conf)) {
 889                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
 890                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
 891                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
 892                 } else {
 893                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
 894                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
 895                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
 896                 }
 897         }
 898
 899         msleep(1);
 900 }
 901
 902 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
 903                                   const int txpower)
 904 {
 905         u32 reg;
 906         u32 value = TXPOWER_G_TO_DEV(txpower);
 907         u8 r1;
 908
 909         rt2800_bbp_read(rt2x00dev, 1, &r1);
 910         rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
 911         rt2800_bbp_write(rt2x00dev, 1, r1);
 912
 913         rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
 914         rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
 915         rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
 916         rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
 917         rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
 918         rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
 919         rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
 920         rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
 921         rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
 922         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
 923
 924         rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
 925         rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
 926         rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
 927         rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
 928         rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
 929         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
 930         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
 931         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
 932         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
 933         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
 934
 935         rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
 936         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
 937         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
 938         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
 939         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
 940         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
 941         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
 942         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
 943         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
 944         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
 945
 946         rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
 947         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
 948         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
 949         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
 950         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
 951         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
 952         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
 953         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
 954         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
 955         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
 956
 957         rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
 958         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
 959         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
 960         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
 961         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
 962         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
 963 }
 964
 965 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 966                                       struct rt2x00lib_conf *libconf)
 967 {
 968         u32 reg;
 969
 970         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
 971         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
 972                            libconf->conf->short_frame_max_tx_count);
 973         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
 974                            libconf->conf->long_frame_max_tx_count);
 975         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
 976 }
 977
 978 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
 979                              struct rt2x00lib_conf *libconf)
 980 {
 981         enum dev_state state =
 982             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 983                 STATE_SLEEP : STATE_AWAKE;
 984         u32 reg;
 985
 986         if (state == STATE_SLEEP) {
 987                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
 988
 989                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
 990                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
 991                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
 992                                    libconf->conf->listen_interval - 1);
 993                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
 994                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
 995
 996                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 997         } else {
 998                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
 999                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1000                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1001                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1002                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1003
1004                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1005         }
1006 }
1007
1008 void rt2800_config(struct rt2x00_dev *rt2x00dev,
1009                    struct rt2x00lib_conf *libconf,
1010                    const unsigned int flags)
1011 {
1012         /* Always recalculate LNA gain before changing configuration */
1013         rt2800_config_lna_gain(rt2x00dev, libconf);
1014
1015         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1016                 rt2800_config_channel(rt2x00dev, libconf->conf,
1017                                       &libconf->rf, &libconf->channel);
1018         if (flags & IEEE80211_CONF_CHANGE_POWER)
1019                 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1020         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1021                 rt2800_config_retry_limit(rt2x00dev, libconf);
1022         if (flags & IEEE80211_CONF_CHANGE_PS)
1023                 rt2800_config_ps(rt2x00dev, libconf);
1024 }
1025 EXPORT_SYMBOL_GPL(rt2800_config);
1026
1027 /*
1028  * Link tuning
1029  */
1030 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1031 {
1032         u32 reg;
1033
1034         /*
1035          * Update FCS error count from register.
1036          */
1037         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1038         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1039 }
1040 EXPORT_SYMBOL_GPL(rt2800_link_stats);
1041
1042 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1043 {
1044         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1045                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1046                     rt2x00_rt(rt2x00dev, RT3071) ||
1047                     rt2x00_rt(rt2x00dev, RT3090) ||
1048                     rt2x00_rt(rt2x00dev, RT3390))
1049                         return 0x1c + (2 * rt2x00dev->lna_gain);
1050                 else
1051                         return 0x2e + rt2x00dev->lna_gain;
1052         }
1053
1054         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1055                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1056         else
1057                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1058 }
1059
1060 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1061                                   struct link_qual *qual, u8 vgc_level)
1062 {
1063         if (qual->vgc_level != vgc_level) {
1064                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1065                 qual->vgc_level = vgc_level;
1066                 qual->vgc_level_reg = vgc_level;
1067         }
1068 }
1069
1070 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1071 {
1072         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1073 }
1074 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1075
1076 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1077                        const u32 count)
1078 {
1079         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
1080                 return;
1081
1082         /*
1083          * When RSSI is better then -80 increase VGC level with 0x10
1084          */
1085         rt2800_set_vgc(rt2x00dev, qual,
1086                        rt2800_get_default_vgc(rt2x00dev) +
1087                        ((qual->rssi > -80) * 0x10));
1088 }
1089 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1090
1091 /*
1092  * Initialization functions.
1093  */
1094 int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1095 {
1096         u32 reg;
1097         u16 eeprom;
1098         unsigned int i;
1099
1100         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1101         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1102         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1103         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1104         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1105         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1106         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1107
1108         if (rt2x00_is_usb(rt2x00dev)) {
1109                 /*
1110                  * Wait until BBP and RF are ready.
1111                  */
1112                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1113                         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1114                         if (reg && reg != ~0)
1115                                 break;
1116                         msleep(1);
1117                 }
1118
1119                 if (i == REGISTER_BUSY_COUNT) {
1120                         ERROR(rt2x00dev, "Unstable hardware.\n");
1121                         return -EBUSY;
1122                 }
1123
1124                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1125                 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
1126                                       reg & ~0x00002000);
1127         } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) {
1128                 /*
1129                  * Reset DMA indexes
1130                  */
1131                 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1132                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1133                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1134                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1135                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1136                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1137                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1138                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1139                 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1140
1141                 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1142                 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1143
1144                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1145         }
1146
1147         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1148         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1149         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1150         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1151
1152         if (rt2x00_is_usb(rt2x00dev)) {
1153                 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1154 #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
1155                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1156                                             USB_MODE_RESET, REGISTER_TIMEOUT);
1157 #endif
1158         }
1159
1160         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1161
1162         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1163         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1164         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1165         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1166         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1167         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1168
1169         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1170         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1171         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1172         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1173         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1174         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1175
1176         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1177         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1178
1179         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1180
1181         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1182         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1183         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1184         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1185         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1186         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1187         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1188         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1189
1190         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1191
1192         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1193         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1194         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1195         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1196
1197         if (rt2x00_rt(rt2x00dev, RT3071) ||
1198             rt2x00_rt(rt2x00dev, RT3090) ||
1199             rt2x00_rt(rt2x00dev, RT3390)) {
1200                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1201                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1202                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1203                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1204                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
1205                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1206                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1207                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1208                                                       0x0000002c);
1209                         else
1210                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1211                                                       0x0000000f);
1212                 } else {
1213                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1214                 }
1215                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, reg);
1216         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
1217                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1218
1219                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1220                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1221                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1222                 } else {
1223                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1224                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1225                 }
1226         } else {
1227                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1228                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1229         }
1230
1231         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1232         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1233         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1234         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1235         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1236         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1237         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1238         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1239         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1240         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1241
1242         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1243         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1244         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
1245         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1246         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1247
1248         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1249         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1250         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
1251             rt2x00_rt(rt2x00dev, RT2883) ||
1252             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
1253                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1254         else
1255                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1256         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1257         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1258         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1259
1260         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1261         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1262         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1263         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1264         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1265         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1266         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1267         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1268         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1269
1270         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1271
1272         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1273         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1274         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1275         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1276         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1277         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1278         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1279         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1280
1281         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1282         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1283         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
1284         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1285         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1286         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
1287         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1288         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1289         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1290
1291         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1292         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
1293         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1294         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1295         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1296         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1297         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1298         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1299         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1300         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1301         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
1302         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1303
1304         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1305         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
1306         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1307         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1308         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1309         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1310         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1311         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1312         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1313         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1314         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
1315         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1316
1317         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1318         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1319         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1320         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1321         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1322         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1323         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1324         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1325         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1326         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1327         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
1328         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1329
1330         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1331         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1332         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL,
1333                            !rt2x00_is_usb(rt2x00dev));
1334         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1335         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1336         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1337         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1338         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1339         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1340         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1341         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
1342         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1343
1344         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1345         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1346         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1347         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1348         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1349         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1350         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1351         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1352         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1353         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1354         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
1355         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1356
1357         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1358         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1359         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1360         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1361         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1362         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1363         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1364         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1365         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1366         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1367         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
1368         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1369
1370         if (rt2x00_is_usb(rt2x00dev)) {
1371                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1372
1373                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1374                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1375                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1376                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1377                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1378                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1379                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1380                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1381                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1382                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1383                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1384         }
1385
1386         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1387         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1388
1389         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1390         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1391         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1392                            IEEE80211_MAX_RTS_THRESHOLD);
1393         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1394         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1395
1396         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1397
1398         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1399         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 32);
1400         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 32);
1401         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
1402         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
1403         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
1404         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1405
1406         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1407
1408         /*
1409          * ASIC will keep garbage value after boot, clear encryption keys.
1410          */
1411         for (i = 0; i < 4; i++)
1412                 rt2800_register_write(rt2x00dev,
1413                                          SHARED_KEY_MODE_ENTRY(i), 0);
1414
1415         for (i = 0; i < 256; i++) {
1416                 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1417                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1418                                               wcid, sizeof(wcid));
1419
1420                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1421                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1422         }
1423
1424         /*
1425          * Clear all beacons
1426          * For the Beacon base registers we only need to clear
1427          * the first byte since that byte contains the VALID and OWNER
1428          * bits which (when set to 0) will invalidate the entire beacon.
1429          */
1430         rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1431         rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1432         rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1433         rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1434         rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1435         rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1436         rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1437         rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1438
1439         if (rt2x00_is_usb(rt2x00dev)) {
1440                 rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1441                 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1442                 rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1443         }
1444
1445         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1446         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1447         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1448         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1449         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1450         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1451         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1452         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1453         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1454         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1455
1456         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1457         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1458         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1459         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1460         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1461         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1462         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1463         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1464         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1465         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1466
1467         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1468         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1469         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1470         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1471         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1472         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1473         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1474         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1475         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1476         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1477
1478         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1479         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1480         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1481         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1482         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1483         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1484
1485         /*
1486          * We must clear the error counters.
1487          * These registers are cleared on read,
1488          * so we may pass a useless variable to store the value.
1489          */
1490         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1491         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1492         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1493         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1494         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1495         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1496
1497         return 0;
1498 }
1499 EXPORT_SYMBOL_GPL(rt2800_init_registers);
1500
1501 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1502 {
1503         unsigned int i;
1504         u32 reg;
1505
1506         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1507                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1508                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1509                         return 0;
1510
1511                 udelay(REGISTER_BUSY_DELAY);
1512         }
1513
1514         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1515         return -EACCES;
1516 }
1517
1518 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1519 {
1520         unsigned int i;
1521         u8 value;
1522
1523         /*
1524          * BBP was enabled after firmware was loaded,
1525          * but we need to reactivate it now.
1526          */
1527         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1528         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1529         msleep(1);
1530
1531         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1532                 rt2800_bbp_read(rt2x00dev, 0, &value);
1533                 if ((value != 0xff) && (value != 0x00))
1534                         return 0;
1535                 udelay(REGISTER_BUSY_DELAY);
1536         }
1537
1538         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1539         return -EACCES;
1540 }
1541
1542 int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1543 {
1544         unsigned int i;
1545         u16 eeprom;
1546         u8 reg_id;
1547         u8 value;
1548
1549         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1550                      rt2800_wait_bbp_ready(rt2x00dev)))
1551                 return -EACCES;
1552
1553         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1554         rt2800_bbp_write(rt2x00dev, 66, 0x38);
1555
1556         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1557                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1558                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1559         } else {
1560                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
1561                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
1562         }
1563
1564         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1565
1566         if (rt2x00_rt(rt2x00dev, RT3070) ||
1567             rt2x00_rt(rt2x00dev, RT3071) ||
1568             rt2x00_rt(rt2x00dev, RT3090) ||
1569             rt2x00_rt(rt2x00dev, RT3390)) {
1570                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
1571                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
1572                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
1573         } else {
1574                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
1575         }
1576
1577         rt2800_bbp_write(rt2x00dev, 82, 0x62);
1578         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1579
1580         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D) ||
1581             rt2x00_rt_rev(rt2x00dev, RT2870, REV_RT2870D))
1582                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1583         else
1584                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1585
1586         rt2800_bbp_write(rt2x00dev, 86, 0x00);
1587         rt2800_bbp_write(rt2x00dev, 91, 0x04);
1588         rt2800_bbp_write(rt2x00dev, 92, 0x00);
1589
1590         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
1591             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
1592             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
1593             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
1594                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1595         else
1596                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
1597
1598         rt2800_bbp_write(rt2x00dev, 105, 0x05);
1599         rt2800_bbp_write(rt2x00dev, 106, 0x35);
1600
1601         if (rt2x00_rt(rt2x00dev, RT3071) ||
1602             rt2x00_rt(rt2x00dev, RT3090) ||
1603             rt2x00_rt(rt2x00dev, RT3390)) {
1604                 rt2800_bbp_read(rt2x00dev, 138, &value);
1605
1606                 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1607                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
1608                         value |= 0x20;
1609                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
1610                         value &= ~0x02;
1611
1612                 rt2800_bbp_write(rt2x00dev, 138, value);
1613         }
1614
1615         if (rt2x00_rt(rt2x00dev, RT2872)) {
1616                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1617                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1618                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
1619         }
1620
1621         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1622                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1623
1624                 if (eeprom != 0xffff && eeprom != 0x0000) {
1625                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1626                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1627                         rt2800_bbp_write(rt2x00dev, reg_id, value);
1628                 }
1629         }
1630
1631         return 0;
1632 }
1633 EXPORT_SYMBOL_GPL(rt2800_init_bbp);
1634
1635 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1636                                 bool bw40, u8 rfcsr24, u8 filter_target)
1637 {
1638         unsigned int i;
1639         u8 bbp;
1640         u8 rfcsr;
1641         u8 passband;
1642         u8 stopband;
1643         u8 overtuned = 0;
1644
1645         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1646
1647         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1648         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1649         rt2800_bbp_write(rt2x00dev, 4, bbp);
1650
1651         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1652         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1653         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1654
1655         /*
1656          * Set power & frequency of passband test tone
1657          */
1658         rt2800_bbp_write(rt2x00dev, 24, 0);
1659
1660         for (i = 0; i < 100; i++) {
1661                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1662                 msleep(1);
1663
1664                 rt2800_bbp_read(rt2x00dev, 55, &passband);
1665                 if (passband)
1666                         break;
1667         }
1668
1669         /*
1670          * Set power & frequency of stopband test tone
1671          */
1672         rt2800_bbp_write(rt2x00dev, 24, 0x06);
1673
1674         for (i = 0; i < 100; i++) {
1675                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1676                 msleep(1);
1677
1678                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1679
1680                 if ((passband - stopband) <= filter_target) {
1681                         rfcsr24++;
1682                         overtuned += ((passband - stopband) == filter_target);
1683                 } else
1684                         break;
1685
1686                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1687         }
1688
1689         rfcsr24 -= !!overtuned;
1690
1691         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1692         return rfcsr24;
1693 }
1694
1695 int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1696 {
1697         u8 rfcsr;
1698         u8 bbp;
1699         u32 reg;
1700         u16 eeprom;
1701
1702         if (!rt2x00_rt(rt2x00dev, RT3070) &&
1703             !rt2x00_rt(rt2x00dev, RT3071) &&
1704             !rt2x00_rt(rt2x00dev, RT3090) &&
1705             !rt2x00_rt(rt2x00dev, RT3390))
1706                 return 0;
1707
1708         /*
1709          * Init RF calibration.
1710          */
1711         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1712         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1713         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1714         msleep(1);
1715         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1716         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1717
1718         if (rt2x00_rt(rt2x00dev, RT3070) ||
1719             rt2x00_rt(rt2x00dev, RT3071) ||
1720             rt2x00_rt(rt2x00dev, RT3090)) {
1721                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1722                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1723                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1724                 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1725                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1726                 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
1727                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1728                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1729                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1730                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1731                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1732                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1733                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1734                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1735                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1736                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1737                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1738                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1739                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1740         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
1741                 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
1742                 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
1743                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
1744                 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
1745                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1746                 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
1747                 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
1748                 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
1749                 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
1750                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1751                 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
1752                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1753                 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
1754                 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
1755                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1756                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1757                 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
1758                 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
1759                 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
1760                 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
1761                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
1762                 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
1763                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1764                 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
1765                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1766                 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1767                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1768                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1769                 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
1770                 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
1771                 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
1772                 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
1773         }
1774
1775         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1776                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1777                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
1778                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1779                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
1780         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
1781                    rt2x00_rt(rt2x00dev, RT3090)) {
1782                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1783                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
1784                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1785
1786                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
1787
1788                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1789                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
1790                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1791                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
1792                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1793                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1794                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1795                         else
1796                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
1797                 }
1798                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
1799         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
1800                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1801                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
1802                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1803         }
1804
1805         /*
1806          * Set RX Filter calibration for 20MHz and 40MHz
1807          */
1808         if (rt2x00_rt(rt2x00dev, RT3070)) {
1809                 rt2x00dev->calibration[0] =
1810                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1811                 rt2x00dev->calibration[1] =
1812                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1813         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
1814                    rt2x00_rt(rt2x00dev, RT3090) ||
1815                    rt2x00_rt(rt2x00dev, RT3390)) {
1816                 rt2x00dev->calibration[0] =
1817                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
1818                 rt2x00dev->calibration[1] =
1819                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
1820         }
1821
1822         /*
1823          * Set back to initial state
1824          */
1825         rt2800_bbp_write(rt2x00dev, 24, 0);
1826
1827         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1828         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1829         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1830
1831         /*
1832          * set BBP back to BW20
1833          */
1834         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1835         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1836         rt2800_bbp_write(rt2x00dev, 4, bbp);
1837
1838         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
1839             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1840             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1841             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
1842                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1843
1844         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
1845         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
1846         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
1847
1848         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1849         rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
1850         if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1851             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1852             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
1853                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1854                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1855                         rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
1856         }
1857         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
1858         if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
1859                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
1860                                   rt2x00_get_field16(eeprom,
1861                                                    EEPROM_TXMIXER_GAIN_BG_VAL));
1862         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1863
1864         if (rt2x00_rt(rt2x00dev, RT3090)) {
1865                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
1866
1867                 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1868                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
1869                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
1870                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
1871                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
1872
1873                 rt2800_bbp_write(rt2x00dev, 138, bbp);
1874         }
1875
1876         if (rt2x00_rt(rt2x00dev, RT3071) ||
1877             rt2x00_rt(rt2x00dev, RT3090) ||
1878             rt2x00_rt(rt2x00dev, RT3390)) {
1879                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1880                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1881                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1882                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1883                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1884                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1885                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1886
1887                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
1888                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
1889                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
1890
1891                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
1892                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
1893                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
1894
1895                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
1896                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
1897                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
1898         }
1899
1900         if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
1901                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
1902                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
1903                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
1904                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
1905                 else
1906                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
1907                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
1908                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
1909                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
1910                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
1911         }
1912
1913         return 0;
1914 }
1915 EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
1916
1917 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
1918 {
1919         u32 reg;
1920
1921         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
1922
1923         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
1924 }
1925 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
1926
1927 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
1928 {
1929         u32 reg;
1930
1931         mutex_lock(&rt2x00dev->csr_mutex);
1932
1933         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
1934         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
1935         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
1936         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
1937         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
1938
1939         /* Wait until the EEPROM has been loaded */
1940         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
1941
1942         /* Apparently the data is read from end to start */
1943         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
1944                                         (u32 *)&rt2x00dev->eeprom[i]);
1945         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
1946                                         (u32 *)&rt2x00dev->eeprom[i + 2]);
1947         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
1948                                         (u32 *)&rt2x00dev->eeprom[i + 4]);
1949         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
1950                                         (u32 *)&rt2x00dev->eeprom[i + 6]);
1951
1952         mutex_unlock(&rt2x00dev->csr_mutex);
1953 }
1954
1955 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
1956 {
1957         unsigned int i;
1958
1959         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
1960                 rt2800_efuse_read(rt2x00dev, i);
1961 }
1962 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
1963
1964 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1965 {
1966         u16 word;
1967         u8 *mac;
1968         u8 default_lna_gain;
1969
1970         /*
1971          * Start validation of the data that has been read.
1972          */
1973         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1974         if (!is_valid_ether_addr(mac)) {
1975                 random_ether_addr(mac);
1976                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1977         }
1978
1979         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1980         if (word == 0xffff) {
1981                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1982                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
1983                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
1984                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1985                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1986         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
1987                    rt2x00_rt(rt2x00dev, RT2870) ||
1988                    rt2x00_rt(rt2x00dev, RT2872) ||
1989                    rt2x00_rt(rt2x00dev, RT2872)) {
1990                 /*
1991                  * There is a max of 2 RX streams for RT28x0 series
1992                  */
1993                 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
1994                         rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1995                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1996         }
1997
1998         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1999         if (word == 0xffff) {
2000                 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2001                 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2002                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2003                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2004                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2005                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2006                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2007                 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2008                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2009                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2010                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2011                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2012         }
2013
2014         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2015         if ((word & 0x00ff) == 0x00ff) {
2016                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2017                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2018                                    LED_MODE_TXRX_ACTIVITY);
2019                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2020                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2021                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2022                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2023                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2024                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2025         }
2026
2027         /*
2028          * During the LNA validation we are going to use
2029          * lna0 as correct value. Note that EEPROM_LNA
2030          * is never validated.
2031          */
2032         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2033         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2034
2035         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2036         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2037                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2038         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2039                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2040         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2041
2042         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2043         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2044                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2045         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2046             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2047                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2048                                    default_lna_gain);
2049         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2050
2051         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2052         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2053                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2054         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2055                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2056         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2057
2058         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2059         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2060                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2061         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2062             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2063                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2064                                    default_lna_gain);
2065         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2066
2067         return 0;
2068 }
2069 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2070
2071 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2072 {
2073         u32 reg;
2074         u16 value;
2075         u16 eeprom;
2076
2077         /*
2078          * Read EEPROM word for configuration.
2079          */
2080         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2081
2082         /*
2083          * Identify RF chipset.
2084          */
2085         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2086         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2087
2088         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2089                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2090
2091         if (!rt2x00_rt(rt2x00dev, RT2860) &&
2092             !rt2x00_rt(rt2x00dev, RT2870) &&
2093             !rt2x00_rt(rt2x00dev, RT2872) &&
2094             !rt2x00_rt(rt2x00dev, RT2883) &&
2095             !rt2x00_rt(rt2x00dev, RT3070) &&
2096             !rt2x00_rt(rt2x00dev, RT3071) &&
2097             !rt2x00_rt(rt2x00dev, RT3090) &&
2098             !rt2x00_rt(rt2x00dev, RT3390) &&
2099             !rt2x00_rt(rt2x00dev, RT3572)) {
2100                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2101                 return -ENODEV;
2102         }
2103
2104         if (!rt2x00_rf(rt2x00dev, RF2820) &&
2105             !rt2x00_rf(rt2x00dev, RF2850) &&
2106             !rt2x00_rf(rt2x00dev, RF2720) &&
2107             !rt2x00_rf(rt2x00dev, RF2750) &&
2108             !rt2x00_rf(rt2x00dev, RF3020) &&
2109             !rt2x00_rf(rt2x00dev, RF2020) &&
2110             !rt2x00_rf(rt2x00dev, RF3021) &&
2111             !rt2x00_rf(rt2x00dev, RF3022) &&
2112             !rt2x00_rf(rt2x00dev, RF3052)) {
2113                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2114                 return -ENODEV;
2115         }
2116
2117         /*
2118          * Identify default antenna configuration.
2119          */
2120         rt2x00dev->default_ant.tx =
2121             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2122         rt2x00dev->default_ant.rx =
2123             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2124
2125         /*
2126          * Read frequency offset and RF programming sequence.
2127          */
2128         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2129         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2130
2131         /*
2132          * Read external LNA informations.
2133          */
2134         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2135
2136         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2137                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2138         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2139                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2140
2141         /*
2142          * Detect if this device has an hardware controlled radio.
2143          */
2144         if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2145                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2146
2147         /*
2148          * Store led settings, for correct led behaviour.
2149          */
2150 #ifdef CONFIG_RT2X00_LIB_LEDS
2151         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2152         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2153         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2154
2155         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2156 #endif /* CONFIG_RT2X00_LIB_LEDS */
2157
2158         return 0;
2159 }
2160 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
2161
2162 /*
2163  * RF value list for rt28x0
2164  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2165  */
2166 static const struct rf_channel rf_vals[] = {
2167         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2168         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2169         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2170         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2171         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2172         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2173         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2174         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2175         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2176         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2177         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2178         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2179         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2180         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2181
2182         /* 802.11 UNI / HyperLan 2 */
2183         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2184         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2185         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2186         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2187         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2188         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2189         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2190         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2191         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2192         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2193         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2194         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2195
2196         /* 802.11 HyperLan 2 */
2197         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2198         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2199         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2200         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2201         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2202         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2203         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2204         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2205         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2206         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2207         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2208         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2209         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2210         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2211         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2212         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2213
2214         /* 802.11 UNII */
2215         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2216         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2217         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2218         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2219         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2220         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2221         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2222         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2223         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2224         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2225         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2226
2227         /* 802.11 Japan */
2228         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2229         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2230         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2231         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2232         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2233         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2234         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2235 };
2236
2237 /*
2238  * RF value list for rt3070
2239  * Supports: 2.4 GHz
2240  */
2241 static const struct rf_channel rf_vals_302x[] = {
2242         {1,  241, 2, 2 },
2243         {2,  241, 2, 7 },
2244         {3,  242, 2, 2 },
2245         {4,  242, 2, 7 },
2246         {5,  243, 2, 2 },
2247         {6,  243, 2, 7 },
2248         {7,  244, 2, 2 },
2249         {8,  244, 2, 7 },
2250         {9,  245, 2, 2 },
2251         {10, 245, 2, 7 },
2252         {11, 246, 2, 2 },
2253         {12, 246, 2, 7 },
2254         {13, 247, 2, 2 },
2255         {14, 248, 2, 4 },
2256 };
2257
2258 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2259 {
2260         struct hw_mode_spec *spec = &rt2x00dev->spec;
2261         struct channel_info *info;
2262         char *tx_power1;
2263         char *tx_power2;
2264         unsigned int i;
2265         u16 eeprom;
2266
2267         /*
2268          * Disable powersaving as default on PCI devices.
2269          */
2270         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
2271                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2272
2273         /*
2274          * Initialize all hw fields.
2275          */
2276         rt2x00dev->hw->flags =
2277             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2278             IEEE80211_HW_SIGNAL_DBM |
2279             IEEE80211_HW_SUPPORTS_PS |
2280             IEEE80211_HW_PS_NULLFUNC_STACK;
2281
2282         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2283         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2284                                 rt2x00_eeprom_addr(rt2x00dev,
2285                                                    EEPROM_MAC_ADDR_0));
2286
2287         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2288
2289         /*
2290          * Initialize hw_mode information.
2291          */
2292         spec->supported_bands = SUPPORT_BAND_2GHZ;
2293         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2294
2295         if (rt2x00_rf(rt2x00dev, RF2820) ||
2296             rt2x00_rf(rt2x00dev, RF2720) ||
2297             rt2x00_rf(rt2x00dev, RF3052)) {
2298                 spec->num_channels = 14;
2299                 spec->channels = rf_vals;
2300         } else if (rt2x00_rf(rt2x00dev, RF2850) || rt2x00_rf(rt2x00dev, RF2750)) {
2301                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2302                 spec->num_channels = ARRAY_SIZE(rf_vals);
2303                 spec->channels = rf_vals;
2304         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
2305                    rt2x00_rf(rt2x00dev, RF2020) ||
2306                    rt2x00_rf(rt2x00dev, RF3021) ||
2307                    rt2x00_rf(rt2x00dev, RF3022)) {
2308                 spec->num_channels = ARRAY_SIZE(rf_vals_302x);
2309                 spec->channels = rf_vals_302x;
2310         }
2311
2312         /*
2313          * Initialize HT information.
2314          */
2315         if (!rt2x00_rf(rt2x00dev, RF2020))
2316                 spec->ht.ht_supported = true;
2317         else
2318                 spec->ht.ht_supported = false;
2319
2320         spec->ht.cap =
2321             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2322             IEEE80211_HT_CAP_GRN_FLD |
2323             IEEE80211_HT_CAP_SGI_20 |
2324             IEEE80211_HT_CAP_SGI_40 |
2325             IEEE80211_HT_CAP_TX_STBC |
2326             IEEE80211_HT_CAP_RX_STBC;
2327         spec->ht.ampdu_factor = 3;
2328         spec->ht.ampdu_density = 4;
2329         spec->ht.mcs.tx_params =
2330             IEEE80211_HT_MCS_TX_DEFINED |
2331             IEEE80211_HT_MCS_TX_RX_DIFF |
2332             ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2333                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2334
2335         switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2336         case 3:
2337                 spec->ht.mcs.rx_mask[2] = 0xff;
2338         case 2:
2339                 spec->ht.mcs.rx_mask[1] = 0xff;
2340         case 1:
2341                 spec->ht.mcs.rx_mask[0] = 0xff;
2342                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2343                 break;
2344         }
2345
2346         /*
2347          * Create channel information array
2348          */
2349         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2350         if (!info)
2351                 return -ENOMEM;
2352
2353         spec->channels_info = info;
2354
2355         tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2356         tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2357
2358         for (i = 0; i < 14; i++) {
2359                 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2360                 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2361         }
2362
2363         if (spec->num_channels > 14) {
2364                 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2365                 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2366
2367                 for (i = 14; i < spec->num_channels; i++) {
2368                         info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2369                         info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2370                 }
2371         }
2372
2373         return 0;
2374 }
2375 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
2376
2377 /*
2378  * IEEE80211 stack callback functions.
2379  */
2380 static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2381                                 u32 *iv32, u16 *iv16)
2382 {
2383         struct rt2x00_dev *rt2x00dev = hw->priv;
2384         struct mac_iveiv_entry iveiv_entry;
2385         u32 offset;
2386
2387         offset = MAC_IVEIV_ENTRY(hw_key_idx);
2388         rt2800_register_multiread(rt2x00dev, offset,
2389                                       &iveiv_entry, sizeof(iveiv_entry));
2390
2391         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
2392         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2393 }
2394
2395 static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2396 {
2397         struct rt2x00_dev *rt2x00dev = hw->priv;
2398         u32 reg;
2399         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2400
2401         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2402         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2403         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2404
2405         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2406         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2407         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2408
2409         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2410         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2411         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2412
2413         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2414         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2415         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2416
2417         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2418         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2419         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2420
2421         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2422         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2423         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2424
2425         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2426         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2427         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2428
2429         return 0;
2430 }
2431
2432 static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2433                           const struct ieee80211_tx_queue_params *params)
2434 {
2435         struct rt2x00_dev *rt2x00dev = hw->priv;
2436         struct data_queue *queue;
2437         struct rt2x00_field32 field;
2438         int retval;
2439         u32 reg;
2440         u32 offset;
2441
2442         /*
2443          * First pass the configuration through rt2x00lib, that will
2444          * update the queue settings and validate the input. After that
2445          * we are free to update the registers based on the value
2446          * in the queue parameter.
2447          */
2448         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2449         if (retval)
2450                 return retval;
2451
2452         /*
2453          * We only need to perform additional register initialization
2454          * for WMM queues/
2455          */
2456         if (queue_idx >= 4)
2457                 return 0;
2458
2459         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2460
2461         /* Update WMM TXOP register */
2462         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2463         field.bit_offset = (queue_idx & 1) * 16;
2464         field.bit_mask = 0xffff << field.bit_offset;
2465
2466         rt2800_register_read(rt2x00dev, offset, &reg);
2467         rt2x00_set_field32(&reg, field, queue->txop);
2468         rt2800_register_write(rt2x00dev, offset, reg);
2469
2470         /* Update WMM registers */
2471         field.bit_offset = queue_idx * 4;
2472         field.bit_mask = 0xf << field.bit_offset;
2473
2474         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2475         rt2x00_set_field32(&reg, field, queue->aifs);
2476         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2477
2478         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2479         rt2x00_set_field32(&reg, field, queue->cw_min);
2480         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2481
2482         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2483         rt2x00_set_field32(&reg, field, queue->cw_max);
2484         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2485
2486         /* Update EDCA registers */
2487         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2488
2489         rt2800_register_read(rt2x00dev, offset, &reg);
2490         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2491         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2492         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2493         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2494         rt2800_register_write(rt2x00dev, offset, reg);
2495
2496         return 0;
2497 }
2498
2499 static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2500 {
2501         struct rt2x00_dev *rt2x00dev = hw->priv;
2502         u64 tsf;
2503         u32 reg;
2504
2505         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2506         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2507         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2508         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2509
2510         return tsf;
2511 }
2512
2513 const struct ieee80211_ops rt2800_mac80211_ops = {
2514         .tx                     = rt2x00mac_tx,
2515         .start                  = rt2x00mac_start,
2516         .stop                   = rt2x00mac_stop,
2517         .add_interface          = rt2x00mac_add_interface,
2518         .remove_interface       = rt2x00mac_remove_interface,
2519         .config                 = rt2x00mac_config,
2520         .configure_filter       = rt2x00mac_configure_filter,
2521         .set_tim                = rt2x00mac_set_tim,
2522         .set_key                = rt2x00mac_set_key,
2523         .get_stats              = rt2x00mac_get_stats,
2524         .get_tkip_seq           = rt2800_get_tkip_seq,
2525         .set_rts_threshold      = rt2800_set_rts_threshold,
2526         .bss_info_changed       = rt2x00mac_bss_info_changed,
2527         .conf_tx                = rt2800_conf_tx,
2528         .get_tsf                = rt2800_get_tsf,
2529         .rfkill_poll            = rt2x00mac_rfkill_poll,
2530 };
2531 EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);