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   1 /*
   2         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   3
   4         Based on the original rt2800pci.c and rt2800usb.c.
   5           Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
   6           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   7           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   8           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
   9           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  10           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  11           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  12           <http://rt2x00.serialmonkey.com>
  13
  14         This program is free software; you can redistribute it and/or modify
  15         it under the terms of the GNU General Public License as published by
  16         the Free Software Foundation; either version 2 of the License, or
  17         (at your option) any later version.
  18
  19         This program is distributed in the hope that it will be useful,
  20         but WITHOUT ANY WARRANTY; without even the implied warranty of
  21         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22         GNU General Public License for more details.
  23
  24         You should have received a copy of the GNU General Public License
  25         along with this program; if not, write to the
  26         Free Software Foundation, Inc.,
  27         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  28  */
  29
  30 /*
  31         Module: rt2800lib
  32         Abstract: rt2800 generic device routines.
  33  */
  34
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37
  38 #include "rt2x00.h"
  39 #ifdef CONFIG_RT2800USB
  40 #include "rt2x00usb.h"
  41 #endif
  42 #include "rt2800lib.h"
  43 #include "rt2800.h"
  44 #include "rt2800usb.h"
  45
  46 MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
  47 MODULE_DESCRIPTION("rt2800 library");
  48 MODULE_LICENSE("GPL");
  49
  50 /*
  51  * Register access.
  52  * All access to the CSR registers will go through the methods
  53  * rt2800_register_read and rt2800_register_write.
  54  * BBP and RF register require indirect register access,
  55  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  56  * These indirect registers work with busy bits,
  57  * and we will try maximal REGISTER_BUSY_COUNT times to access
  58  * the register while taking a REGISTER_BUSY_DELAY us delay
  59  * between each attampt. When the busy bit is still set at that time,
  60  * the access attempt is considered to have failed,
  61  * and we will print an error.
  62  * The _lock versions must be used if you already hold the csr_mutex
  63  */
  64 #define WAIT_FOR_BBP(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  66 #define WAIT_FOR_RFCSR(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  68 #define WAIT_FOR_RF(__dev, __reg) \
  69         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  70 #define WAIT_FOR_MCU(__dev, __reg) \
  71         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  72                             H2M_MAILBOX_CSR_OWNER, (__reg))
  73
  74 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  75                              const unsigned int word, const u8 value)
  76 {
  77         u32 reg;
  78
  79         mutex_lock(&rt2x00dev->csr_mutex);
  80
  81         /*
  82          * Wait until the BBP becomes available, afterwards we
  83          * can safely write the new data into the register.
  84          */
  85         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  86                 reg = 0;
  87                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
  88                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  89                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  90                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
  91                 if (rt2x00_intf_is_pci(rt2x00dev))
  92                         rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
  93
  94                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
  95         }
  96
  97         mutex_unlock(&rt2x00dev->csr_mutex);
  98 }
  99
 100 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 101                             const unsigned int word, u8 *value)
 102 {
 103         u32 reg;
 104
 105         mutex_lock(&rt2x00dev->csr_mutex);
 106
 107         /*
 108          * Wait until the BBP becomes available, afterwards we
 109          * can safely write the read request into the register.
 110          * After the data has been written, we wait until hardware
 111          * returns the correct value, if at any time the register
 112          * doesn't become available in time, reg will be 0xffffffff
 113          * which means we return 0xff to the caller.
 114          */
 115         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 116                 reg = 0;
 117                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 118                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 119                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 120                 if (rt2x00_intf_is_pci(rt2x00dev))
 121                         rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 122
 123                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 124
 125                 WAIT_FOR_BBP(rt2x00dev, &reg);
 126         }
 127
 128         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 129
 130         mutex_unlock(&rt2x00dev->csr_mutex);
 131 }
 132
 133 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 134                                const unsigned int word, const u8 value)
 135 {
 136         u32 reg;
 137
 138         mutex_lock(&rt2x00dev->csr_mutex);
 139
 140         /*
 141          * Wait until the RFCSR becomes available, afterwards we
 142          * can safely write the new data into the register.
 143          */
 144         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 145                 reg = 0;
 146                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 147                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 148                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 149                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 150
 151                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 152         }
 153
 154         mutex_unlock(&rt2x00dev->csr_mutex);
 155 }
 156
 157 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 158                               const unsigned int word, u8 *value)
 159 {
 160         u32 reg;
 161
 162         mutex_lock(&rt2x00dev->csr_mutex);
 163
 164         /*
 165          * Wait until the RFCSR becomes available, afterwards we
 166          * can safely write the read request into the register.
 167          * After the data has been written, we wait until hardware
 168          * returns the correct value, if at any time the register
 169          * doesn't become available in time, reg will be 0xffffffff
 170          * which means we return 0xff to the caller.
 171          */
 172         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 173                 reg = 0;
 174                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 175                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 176                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 177
 178                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 179
 180                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 181         }
 182
 183         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 184
 185         mutex_unlock(&rt2x00dev->csr_mutex);
 186 }
 187
 188 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 189                             const unsigned int word, const u32 value)
 190 {
 191         u32 reg;
 192
 193         mutex_lock(&rt2x00dev->csr_mutex);
 194
 195         /*
 196          * Wait until the RF becomes available, afterwards we
 197          * can safely write the new data into the register.
 198          */
 199         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 200                 reg = 0;
 201                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 202                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 203                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 204                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 205
 206                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 207                 rt2x00_rf_write(rt2x00dev, word, value);
 208         }
 209
 210         mutex_unlock(&rt2x00dev->csr_mutex);
 211 }
 212
 213 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 214                         const u8 command, const u8 token,
 215                         const u8 arg0, const u8 arg1)
 216 {
 217         u32 reg;
 218
 219         if (rt2x00_intf_is_pci(rt2x00dev)) {
 220                 /*
 221                 * RT2880 and RT3052 don't support MCU requests.
 222                 */
 223                 if (rt2x00_rt(&rt2x00dev->chip, RT2880) ||
 224                     rt2x00_rt(&rt2x00dev->chip, RT3052))
 225                         return;
 226         }
 227
 228         mutex_lock(&rt2x00dev->csr_mutex);
 229
 230         /*
 231          * Wait until the MCU becomes available, afterwards we
 232          * can safely write the new data into the register.
 233          */
 234         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 235                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 236                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 237                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 238                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 239                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 240
 241                 reg = 0;
 242                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 243                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 244         }
 245
 246         mutex_unlock(&rt2x00dev->csr_mutex);
 247 }
 248 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 249
 250 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 251 const struct rt2x00debug rt2800_rt2x00debug = {
 252         .owner  = THIS_MODULE,
 253         .csr    = {
 254                 .read           = rt2800_register_read,
 255                 .write          = rt2800_register_write,
 256                 .flags          = RT2X00DEBUGFS_OFFSET,
 257                 .word_base      = CSR_REG_BASE,
 258                 .word_size      = sizeof(u32),
 259                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 260         },
 261         .eeprom = {
 262                 .read           = rt2x00_eeprom_read,
 263                 .write          = rt2x00_eeprom_write,
 264                 .word_base      = EEPROM_BASE,
 265                 .word_size      = sizeof(u16),
 266                 .word_count     = EEPROM_SIZE / sizeof(u16),
 267         },
 268         .bbp    = {
 269                 .read           = rt2800_bbp_read,
 270                 .write          = rt2800_bbp_write,
 271                 .word_base      = BBP_BASE,
 272                 .word_size      = sizeof(u8),
 273                 .word_count     = BBP_SIZE / sizeof(u8),
 274         },
 275         .rf     = {
 276                 .read           = rt2x00_rf_read,
 277                 .write          = rt2800_rf_write,
 278                 .word_base      = RF_BASE,
 279                 .word_size      = sizeof(u32),
 280                 .word_count     = RF_SIZE / sizeof(u32),
 281         },
 282 };
 283 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 284 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 285
 286 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 287 {
 288         u32 reg;
 289
 290         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 291         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 292 }
 293 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 294
 295 #ifdef CONFIG_RT2X00_LIB_LEDS
 296 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 297                                   enum led_brightness brightness)
 298 {
 299         struct rt2x00_led *led =
 300             container_of(led_cdev, struct rt2x00_led, led_dev);
 301         unsigned int enabled = brightness != LED_OFF;
 302         unsigned int bg_mode =
 303             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 304         unsigned int polarity =
 305                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 306                                    EEPROM_FREQ_LED_POLARITY);
 307         unsigned int ledmode =
 308                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 309                                    EEPROM_FREQ_LED_MODE);
 310
 311         if (led->type == LED_TYPE_RADIO) {
 312                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 313                                       enabled ? 0x20 : 0);
 314         } else if (led->type == LED_TYPE_ASSOC) {
 315                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 316                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 317         } else if (led->type == LED_TYPE_QUALITY) {
 318                 /*
 319                  * The brightness is divided into 6 levels (0 - 5),
 320                  * The specs tell us the following levels:
 321                  *      0, 1 ,3, 7, 15, 31
 322                  * to determine the level in a simple way we can simply
 323                  * work with bitshifting:
 324                  *      (1 << level) - 1
 325                  */
 326                 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 327                                       (1 << brightness / (LED_FULL / 6)) - 1,
 328                                       polarity);
 329         }
 330 }
 331
 332 static int rt2800_blink_set(struct led_classdev *led_cdev,
 333                             unsigned long *delay_on, unsigned long *delay_off)
 334 {
 335         struct rt2x00_led *led =
 336             container_of(led_cdev, struct rt2x00_led, led_dev);
 337         u32 reg;
 338
 339         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 340         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 341         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 342         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
 343         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
 344         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
 345         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
 346         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
 347         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 348
 349         return 0;
 350 }
 351
 352 void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 353                      struct rt2x00_led *led, enum led_type type)
 354 {
 355         led->rt2x00dev = rt2x00dev;
 356         led->type = type;
 357         led->led_dev.brightness_set = rt2800_brightness_set;
 358         led->led_dev.blink_set = rt2800_blink_set;
 359         led->flags = LED_INITIALIZED;
 360 }
 361 EXPORT_SYMBOL_GPL(rt2800_init_led);
 362 #endif /* CONFIG_RT2X00_LIB_LEDS */
 363
 364 /*
 365  * Configuration handlers.
 366  */
 367 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 368                                     struct rt2x00lib_crypto *crypto,
 369                                     struct ieee80211_key_conf *key)
 370 {
 371         struct mac_wcid_entry wcid_entry;
 372         struct mac_iveiv_entry iveiv_entry;
 373         u32 offset;
 374         u32 reg;
 375
 376         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 377
 378         rt2800_register_read(rt2x00dev, offset, &reg);
 379         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 380                            !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 381         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 382                            (crypto->cmd == SET_KEY) * crypto->cipher);
 383         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 384                            (crypto->cmd == SET_KEY) * crypto->bssidx);
 385         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 386         rt2800_register_write(rt2x00dev, offset, reg);
 387
 388         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 389
 390         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 391         if ((crypto->cipher == CIPHER_TKIP) ||
 392             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 393             (crypto->cipher == CIPHER_AES))
 394                 iveiv_entry.iv[3] |= 0x20;
 395         iveiv_entry.iv[3] |= key->keyidx << 6;
 396         rt2800_register_multiwrite(rt2x00dev, offset,
 397                                       &iveiv_entry, sizeof(iveiv_entry));
 398
 399         offset = MAC_WCID_ENTRY(key->hw_key_idx);
 400
 401         memset(&wcid_entry, 0, sizeof(wcid_entry));
 402         if (crypto->cmd == SET_KEY)
 403                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 404         rt2800_register_multiwrite(rt2x00dev, offset,
 405                                       &wcid_entry, sizeof(wcid_entry));
 406 }
 407
 408 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
 409                              struct rt2x00lib_crypto *crypto,
 410                              struct ieee80211_key_conf *key)
 411 {
 412         struct hw_key_entry key_entry;
 413         struct rt2x00_field32 field;
 414         u32 offset;
 415         u32 reg;
 416
 417         if (crypto->cmd == SET_KEY) {
 418                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 419
 420                 memcpy(key_entry.key, crypto->key,
 421                        sizeof(key_entry.key));
 422                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 423                        sizeof(key_entry.tx_mic));
 424                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 425                        sizeof(key_entry.rx_mic));
 426
 427                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 428                 rt2800_register_multiwrite(rt2x00dev, offset,
 429                                               &key_entry, sizeof(key_entry));
 430         }
 431
 432         /*
 433          * The cipher types are stored over multiple registers
 434          * starting with SHARED_KEY_MODE_BASE each word will have
 435          * 32 bits and contains the cipher types for 2 bssidx each.
 436          * Using the correct defines correctly will cause overhead,
 437          * so just calculate the correct offset.
 438          */
 439         field.bit_offset = 4 * (key->hw_key_idx % 8);
 440         field.bit_mask = 0x7 << field.bit_offset;
 441
 442         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
 443
 444         rt2800_register_read(rt2x00dev, offset, &reg);
 445         rt2x00_set_field32(&reg, field,
 446                            (crypto->cmd == SET_KEY) * crypto->cipher);
 447         rt2800_register_write(rt2x00dev, offset, reg);
 448
 449         /*
 450          * Update WCID information
 451          */
 452         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
 453
 454         return 0;
 455 }
 456 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
 457
 458 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 459                                struct rt2x00lib_crypto *crypto,
 460                                struct ieee80211_key_conf *key)
 461 {
 462         struct hw_key_entry key_entry;
 463         u32 offset;
 464
 465         if (crypto->cmd == SET_KEY) {
 466                 /*
 467                  * 1 pairwise key is possible per AID, this means that the AID
 468                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
 469                  * last possible shared key entry.
 470                  */
 471                 if (crypto->aid > (256 - 32))
 472                         return -ENOSPC;
 473
 474                 key->hw_key_idx = 32 + crypto->aid;
 475
 476                 memcpy(key_entry.key, crypto->key,
 477                        sizeof(key_entry.key));
 478                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 479                        sizeof(key_entry.tx_mic));
 480                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 481                        sizeof(key_entry.rx_mic));
 482
 483                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 484                 rt2800_register_multiwrite(rt2x00dev, offset,
 485                                               &key_entry, sizeof(key_entry));
 486         }
 487
 488         /*
 489          * Update WCID information
 490          */
 491         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
 492
 493         return 0;
 494 }
 495 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
 496
 497 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
 498                           const unsigned int filter_flags)
 499 {
 500         u32 reg;
 501
 502         /*
 503          * Start configuration steps.
 504          * Note that the version error will always be dropped
 505          * and broadcast frames will always be accepted since
 506          * there is no filter for it at this time.
 507          */
 508         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
 509         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 510                            !(filter_flags & FIF_FCSFAIL));
 511         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 512                            !(filter_flags & FIF_PLCPFAIL));
 513         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 514                            !(filter_flags & FIF_PROMISC_IN_BSS));
 515         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
 516         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 517         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 518                            !(filter_flags & FIF_ALLMULTI));
 519         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 520         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 521         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 522                            !(filter_flags & FIF_CONTROL));
 523         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 524                            !(filter_flags & FIF_CONTROL));
 525         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 526                            !(filter_flags & FIF_CONTROL));
 527         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 528                            !(filter_flags & FIF_CONTROL));
 529         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 530                            !(filter_flags & FIF_CONTROL));
 531         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 532                            !(filter_flags & FIF_PSPOLL));
 533         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
 534         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
 535         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 536                            !(filter_flags & FIF_CONTROL));
 537         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 538 }
 539 EXPORT_SYMBOL_GPL(rt2800_config_filter);
 540
 541 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
 542                         struct rt2x00intf_conf *conf, const unsigned int flags)
 543 {
 544         unsigned int beacon_base;
 545         u32 reg;
 546
 547         if (flags & CONFIG_UPDATE_TYPE) {
 548                 /*
 549                  * Clear current synchronisation setup.
 550                  * For the Beacon base registers we only need to clear
 551                  * the first byte since that byte contains the VALID and OWNER
 552                  * bits which (when set to 0) will invalidate the entire beacon.
 553                  */
 554                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 555                 rt2800_register_write(rt2x00dev, beacon_base, 0);
 556
 557                 /*
 558                  * Enable synchronisation.
 559                  */
 560                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 561                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 562                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 563                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 564                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 565         }
 566
 567         if (flags & CONFIG_UPDATE_MAC) {
 568                 reg = le32_to_cpu(conf->mac[1]);
 569                 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 570                 conf->mac[1] = cpu_to_le32(reg);
 571
 572                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 573                                               conf->mac, sizeof(conf->mac));
 574         }
 575
 576         if (flags & CONFIG_UPDATE_BSSID) {
 577                 reg = le32_to_cpu(conf->bssid[1]);
 578                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
 579                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 580                 conf->bssid[1] = cpu_to_le32(reg);
 581
 582                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 583                                               conf->bssid, sizeof(conf->bssid));
 584         }
 585 }
 586 EXPORT_SYMBOL_GPL(rt2800_config_intf);
 587
 588 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
 589 {
 590         u32 reg;
 591
 592         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
 593         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
 594         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
 595
 596         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
 597         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
 598                            !!erp->short_preamble);
 599         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 600                            !!erp->short_preamble);
 601         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 602
 603         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
 604         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 605                            erp->cts_protection ? 2 : 0);
 606         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 607
 608         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 609                                  erp->basic_rates);
 610         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
 611
 612         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
 613         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
 614         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
 615         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 616
 617         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
 618         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
 619         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
 620         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
 621         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 622         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
 623         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 624
 625         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 626         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 627                            erp->beacon_int * 16);
 628         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 629 }
 630 EXPORT_SYMBOL_GPL(rt2800_config_erp);
 631
 632 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
 633 {
 634         u8 r1;
 635         u8 r3;
 636
 637         rt2800_bbp_read(rt2x00dev, 1, &r1);
 638         rt2800_bbp_read(rt2x00dev, 3, &r3);
 639
 640         /*
 641          * Configure the TX antenna.
 642          */
 643         switch ((int)ant->tx) {
 644         case 1:
 645                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
 646                 if (rt2x00_intf_is_pci(rt2x00dev))
 647                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 648                 break;
 649         case 2:
 650                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
 651                 break;
 652         case 3:
 653                 /* Do nothing */
 654                 break;
 655         }
 656
 657         /*
 658          * Configure the RX antenna.
 659          */
 660         switch ((int)ant->rx) {
 661         case 1:
 662                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 663                 break;
 664         case 2:
 665                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 666                 break;
 667         case 3:
 668                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 669                 break;
 670         }
 671
 672         rt2800_bbp_write(rt2x00dev, 3, r3);
 673         rt2800_bbp_write(rt2x00dev, 1, r1);
 674 }
 675 EXPORT_SYMBOL_GPL(rt2800_config_ant);
 676
 677 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 678                                    struct rt2x00lib_conf *libconf)
 679 {
 680         u16 eeprom;
 681         short lna_gain;
 682
 683         if (libconf->rf.channel <= 14) {
 684                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 685                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 686         } else if (libconf->rf.channel <= 64) {
 687                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 688                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 689         } else if (libconf->rf.channel <= 128) {
 690                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 691                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
 692         } else {
 693                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 694                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
 695         }
 696
 697         rt2x00dev->lna_gain = lna_gain;
 698 }
 699
 700 static void rt2800_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
 701                                        struct ieee80211_conf *conf,
 702                                        struct rf_channel *rf,
 703                                        struct channel_info *info)
 704 {
 705         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 706
 707         if (rt2x00dev->default_ant.tx == 1)
 708                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 709
 710         if (rt2x00dev->default_ant.rx == 1) {
 711                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 712                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 713         } else if (rt2x00dev->default_ant.rx == 2)
 714                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 715
 716         if (rf->channel > 14) {
 717                 /*
 718                  * When TX power is below 0, we should increase it by 7 to
 719                  * make it a positive value (Minumum value is -7).
 720                  * However this means that values between 0 and 7 have
 721                  * double meaning, and we should set a 7DBm boost flag.
 722                  */
 723                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 724                                    (info->tx_power1 >= 0));
 725
 726                 if (info->tx_power1 < 0)
 727                         info->tx_power1 += 7;
 728
 729                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
 730                                    TXPOWER_A_TO_DEV(info->tx_power1));
 731
 732                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 733                                    (info->tx_power2 >= 0));
 734
 735                 if (info->tx_power2 < 0)
 736                         info->tx_power2 += 7;
 737
 738                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
 739                                    TXPOWER_A_TO_DEV(info->tx_power2));
 740         } else {
 741                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
 742                                    TXPOWER_G_TO_DEV(info->tx_power1));
 743                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
 744                                    TXPOWER_G_TO_DEV(info->tx_power2));
 745         }
 746
 747         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
 748
 749         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 750         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 751         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 752         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 753
 754         udelay(200);
 755
 756         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 757         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 758         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 759         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 760
 761         udelay(200);
 762
 763         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 764         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 765         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 766         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 767 }
 768
 769 static void rt2800_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
 770                                        struct ieee80211_conf *conf,
 771                                        struct rf_channel *rf,
 772                                        struct channel_info *info)
 773 {
 774         u8 rfcsr;
 775
 776         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
 777         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
 778
 779         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
 780         rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
 781         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
 782
 783         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
 784         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
 785                           TXPOWER_G_TO_DEV(info->tx_power1));
 786         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
 787
 788         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
 789         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 790         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
 791
 792         rt2800_rfcsr_write(rt2x00dev, 24,
 793                               rt2x00dev->calibration[conf_is_ht40(conf)]);
 794
 795         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
 796         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 797         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
 798 }
 799
 800 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
 801                                   struct ieee80211_conf *conf,
 802                                   struct rf_channel *rf,
 803                                   struct channel_info *info)
 804 {
 805         u32 reg;
 806         unsigned int tx_pin;
 807         u8 bbp;
 808
 809         if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
 810                 rt2800_config_channel_rt2x(rt2x00dev, conf, rf, info);
 811         else
 812                 rt2800_config_channel_rt3x(rt2x00dev, conf, rf, info);
 813
 814         /*
 815          * Change BBP settings
 816          */
 817         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 818         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 819         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 820         rt2800_bbp_write(rt2x00dev, 86, 0);
 821
 822         if (rf->channel <= 14) {
 823                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 824                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
 825                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 826                 } else {
 827                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
 828                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 829                 }
 830         } else {
 831                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
 832
 833                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 834                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 835                 else
 836                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 837         }
 838
 839         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 840         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
 841         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
 842         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
 843         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
 844
 845         tx_pin = 0;
 846
 847         /* Turn on unused PA or LNA when not using 1T or 1R */
 848         if (rt2x00dev->default_ant.tx != 1) {
 849                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
 850                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 851         }
 852
 853         /* Turn on unused PA or LNA when not using 1T or 1R */
 854         if (rt2x00dev->default_ant.rx != 1) {
 855                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 856                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 857         }
 858
 859         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
 860         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
 861         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 862         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 863         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
 864         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
 865
 866         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 867
 868         rt2800_bbp_read(rt2x00dev, 4, &bbp);
 869         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
 870         rt2800_bbp_write(rt2x00dev, 4, bbp);
 871
 872         rt2800_bbp_read(rt2x00dev, 3, &bbp);
 873         rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
 874         rt2800_bbp_write(rt2x00dev, 3, bbp);
 875
 876         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
 877                 if (conf_is_ht40(conf)) {
 878                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
 879                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
 880                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
 881                 } else {
 882                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
 883                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
 884                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
 885                 }
 886         }
 887
 888         msleep(1);
 889 }
 890
 891 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
 892                                   const int txpower)
 893 {
 894         u32 reg;
 895         u32 value = TXPOWER_G_TO_DEV(txpower);
 896         u8 r1;
 897
 898         rt2800_bbp_read(rt2x00dev, 1, &r1);
 899         rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
 900         rt2800_bbp_write(rt2x00dev, 1, r1);
 901
 902         rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
 903         rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
 904         rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
 905         rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
 906         rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
 907         rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
 908         rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
 909         rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
 910         rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
 911         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
 912
 913         rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
 914         rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
 915         rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
 916         rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
 917         rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
 918         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
 919         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
 920         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
 921         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
 922         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
 923
 924         rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
 925         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
 926         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
 927         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
 928         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
 929         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
 930         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
 931         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
 932         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
 933         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
 934
 935         rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
 936         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
 937         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
 938         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
 939         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
 940         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
 941         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
 942         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
 943         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
 944         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
 945
 946         rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
 947         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
 948         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
 949         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
 950         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
 951         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
 952 }
 953
 954 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 955                                       struct rt2x00lib_conf *libconf)
 956 {
 957         u32 reg;
 958
 959         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
 960         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
 961                            libconf->conf->short_frame_max_tx_count);
 962         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
 963                            libconf->conf->long_frame_max_tx_count);
 964         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
 965         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
 966         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
 967         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
 968         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
 969 }
 970
 971 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
 972                              struct rt2x00lib_conf *libconf)
 973 {
 974         enum dev_state state =
 975             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 976                 STATE_SLEEP : STATE_AWAKE;
 977         u32 reg;
 978
 979         if (state == STATE_SLEEP) {
 980                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
 981
 982                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
 983                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
 984                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
 985                                    libconf->conf->listen_interval - 1);
 986                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
 987                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
 988
 989                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 990         } else {
 991                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 992
 993                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
 994                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
 995                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
 996                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
 997                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
 998         }
 999 }
1000
1001 void rt2800_config(struct rt2x00_dev *rt2x00dev,
1002                    struct rt2x00lib_conf *libconf,
1003                    const unsigned int flags)
1004 {
1005         /* Always recalculate LNA gain before changing configuration */
1006         rt2800_config_lna_gain(rt2x00dev, libconf);
1007
1008         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1009                 rt2800_config_channel(rt2x00dev, libconf->conf,
1010                                       &libconf->rf, &libconf->channel);
1011         if (flags & IEEE80211_CONF_CHANGE_POWER)
1012                 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1013         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1014                 rt2800_config_retry_limit(rt2x00dev, libconf);
1015         if (flags & IEEE80211_CONF_CHANGE_PS)
1016                 rt2800_config_ps(rt2x00dev, libconf);
1017 }
1018 EXPORT_SYMBOL_GPL(rt2800_config);
1019
1020 /*
1021  * Link tuning
1022  */
1023 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1024 {
1025         u32 reg;
1026
1027         /*
1028          * Update FCS error count from register.
1029          */
1030         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1031         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1032 }
1033 EXPORT_SYMBOL_GPL(rt2800_link_stats);
1034
1035 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1036 {
1037         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1038                 if (rt2x00_intf_is_usb(rt2x00dev) &&
1039                     rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
1040                         return 0x1c + (2 * rt2x00dev->lna_gain);
1041                 else
1042                         return 0x2e + rt2x00dev->lna_gain;
1043         }
1044
1045         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1046                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1047         else
1048                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1049 }
1050
1051 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1052                                   struct link_qual *qual, u8 vgc_level)
1053 {
1054         if (qual->vgc_level != vgc_level) {
1055                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1056                 qual->vgc_level = vgc_level;
1057                 qual->vgc_level_reg = vgc_level;
1058         }
1059 }
1060
1061 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1062 {
1063         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1064 }
1065 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1066
1067 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1068                        const u32 count)
1069 {
1070         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1071                 return;
1072
1073         /*
1074          * When RSSI is better then -80 increase VGC level with 0x10
1075          */
1076         rt2800_set_vgc(rt2x00dev, qual,
1077                        rt2800_get_default_vgc(rt2x00dev) +
1078                        ((qual->rssi > -80) * 0x10));
1079 }
1080 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1081
1082 /*
1083  * Initialization functions.
1084  */
1085 int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1086 {
1087         u32 reg;
1088         unsigned int i;
1089
1090         if (rt2x00_intf_is_usb(rt2x00dev)) {
1091                 /*
1092                  * Wait untill BBP and RF are ready.
1093                  */
1094                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1095                         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1096                         if (reg && reg != ~0)
1097                                 break;
1098                         msleep(1);
1099                 }
1100
1101                 if (i == REGISTER_BUSY_COUNT) {
1102                         ERROR(rt2x00dev, "Unstable hardware.\n");
1103                         return -EBUSY;
1104                 }
1105
1106                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1107                 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
1108                                       reg & ~0x00002000);
1109         } else if (rt2x00_intf_is_pci(rt2x00dev))
1110                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1111
1112         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1113         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1114         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1115         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1116
1117         if (rt2x00_intf_is_usb(rt2x00dev)) {
1118                 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1119 #ifdef CONFIG_RT2800USB
1120                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1121                                             USB_MODE_RESET, REGISTER_TIMEOUT);
1122 #endif
1123         }
1124
1125         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1126
1127         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1128         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1129         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1130         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1131         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1132         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1133
1134         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1135         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1136         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1137         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1138         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1139         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1140
1141         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1142         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1143
1144         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1145
1146         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1147         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1148         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1149         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1150         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1151         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1152         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1153         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1154
1155         if (rt2x00_intf_is_usb(rt2x00dev) &&
1156             rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1157                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1158                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1159                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1160         } else {
1161                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1162                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1163         }
1164
1165         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1166         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1167         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1168         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1169         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1170         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1171         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1172         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1173         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1174         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1175
1176         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1177         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1178         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1179         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1180
1181         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1182         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1183         if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1184             rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1185                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1186         else
1187                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1188         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1189         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1190         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1191
1192         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1193
1194         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1195         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1196         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1197         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1198         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1199         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1200         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1201
1202         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1203         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1204         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1205         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1206         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1207         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1208         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1209         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1210         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1211         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1212         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1213
1214         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1215         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1216         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1217         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1218         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1219         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1220         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1221         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1222         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1223         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1224         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1225
1226         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1227         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1228         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1229         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1230         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1231         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1232         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1233         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1234         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1235         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1236         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1237
1238         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1239         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1240         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1241         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1242         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1243         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1244         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1245         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1246         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1247         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1248         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1249
1250         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1251         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1252         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1253         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1254         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1255         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1256         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1257         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1258         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1259         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1260         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1261
1262         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1263         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1264         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1265         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1266         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1267         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1268         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1269         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1270         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1271         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1272         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1273
1274         if (rt2x00_intf_is_usb(rt2x00dev)) {
1275                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1276
1277                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1278                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1279                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1280                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1281                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1282                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1283                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1284                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1285                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1286                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1287                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1288         }
1289
1290         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1291         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1292
1293         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1294         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1295         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1296                            IEEE80211_MAX_RTS_THRESHOLD);
1297         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1298         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1299
1300         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1301         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1302
1303         /*
1304          * ASIC will keep garbage value after boot, clear encryption keys.
1305          */
1306         for (i = 0; i < 4; i++)
1307                 rt2800_register_write(rt2x00dev,
1308                                          SHARED_KEY_MODE_ENTRY(i), 0);
1309
1310         for (i = 0; i < 256; i++) {
1311                 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1312                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1313                                               wcid, sizeof(wcid));
1314
1315                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1316                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1317         }
1318
1319         /*
1320          * Clear all beacons
1321          * For the Beacon base registers we only need to clear
1322          * the first byte since that byte contains the VALID and OWNER
1323          * bits which (when set to 0) will invalidate the entire beacon.
1324          */
1325         rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1326         rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1327         rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1328         rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1329         rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1330         rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1331         rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1332         rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1333
1334         if (rt2x00_intf_is_usb(rt2x00dev)) {
1335                 rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1336                 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1337                 rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1338         }
1339
1340         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1341         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1342         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1343         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1344         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1345         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1346         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1347         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1348         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1349         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1350
1351         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1352         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1353         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1354         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1355         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1356         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1357         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1358         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1359         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1360         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1361
1362         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1363         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1364         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1365         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1366         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1367         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1368         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1369         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1370         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1371         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1372
1373         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1374         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1375         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1376         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1377         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1378         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1379
1380         /*
1381          * We must clear the error counters.
1382          * These registers are cleared on read,
1383          * so we may pass a useless variable to store the value.
1384          */
1385         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1386         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1387         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1388         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1389         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1390         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1391
1392         return 0;
1393 }
1394 EXPORT_SYMBOL_GPL(rt2800_init_registers);
1395
1396 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1397 {
1398         unsigned int i;
1399         u32 reg;
1400
1401         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1402                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1403                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1404                         return 0;
1405
1406                 udelay(REGISTER_BUSY_DELAY);
1407         }
1408
1409         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1410         return -EACCES;
1411 }
1412
1413 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1414 {
1415         unsigned int i;
1416         u8 value;
1417
1418         /*
1419          * BBP was enabled after firmware was loaded,
1420          * but we need to reactivate it now.
1421          */
1422         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1423         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1424         msleep(1);
1425
1426         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1427                 rt2800_bbp_read(rt2x00dev, 0, &value);
1428                 if ((value != 0xff) && (value != 0x00))
1429                         return 0;
1430                 udelay(REGISTER_BUSY_DELAY);
1431         }
1432
1433         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1434         return -EACCES;
1435 }
1436
1437 int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1438 {
1439         unsigned int i;
1440         u16 eeprom;
1441         u8 reg_id;
1442         u8 value;
1443
1444         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1445                      rt2800_wait_bbp_ready(rt2x00dev)))
1446                 return -EACCES;
1447
1448         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1449         rt2800_bbp_write(rt2x00dev, 66, 0x38);
1450         rt2800_bbp_write(rt2x00dev, 69, 0x12);
1451         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1452         rt2800_bbp_write(rt2x00dev, 73, 0x10);
1453         rt2800_bbp_write(rt2x00dev, 81, 0x37);
1454         rt2800_bbp_write(rt2x00dev, 82, 0x62);
1455         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1456         rt2800_bbp_write(rt2x00dev, 84, 0x99);
1457         rt2800_bbp_write(rt2x00dev, 86, 0x00);
1458         rt2800_bbp_write(rt2x00dev, 91, 0x04);
1459         rt2800_bbp_write(rt2x00dev, 92, 0x00);
1460         rt2800_bbp_write(rt2x00dev, 103, 0x00);
1461         rt2800_bbp_write(rt2x00dev, 105, 0x05);
1462
1463         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1464                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1465                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1466         }
1467
1468         if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
1469                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1470
1471         if (rt2x00_intf_is_usb(rt2x00dev) &&
1472             rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1473                 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1474                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1475                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1476         }
1477
1478         if (rt2x00_intf_is_pci(rt2x00dev) &&
1479             rt2x00_rt(&rt2x00dev->chip, RT3052)) {
1480                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1481                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1482                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
1483         }
1484
1485         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1486                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1487
1488                 if (eeprom != 0xffff && eeprom != 0x0000) {
1489                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1490                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1491                         rt2800_bbp_write(rt2x00dev, reg_id, value);
1492                 }
1493         }
1494
1495         return 0;
1496 }
1497 EXPORT_SYMBOL_GPL(rt2800_init_bbp);
1498
1499 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1500                                 bool bw40, u8 rfcsr24, u8 filter_target)
1501 {
1502         unsigned int i;
1503         u8 bbp;
1504         u8 rfcsr;
1505         u8 passband;
1506         u8 stopband;
1507         u8 overtuned = 0;
1508
1509         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1510
1511         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1512         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1513         rt2800_bbp_write(rt2x00dev, 4, bbp);
1514
1515         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1516         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1517         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1518
1519         /*
1520          * Set power & frequency of passband test tone
1521          */
1522         rt2800_bbp_write(rt2x00dev, 24, 0);
1523
1524         for (i = 0; i < 100; i++) {
1525                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1526                 msleep(1);
1527
1528                 rt2800_bbp_read(rt2x00dev, 55, &passband);
1529                 if (passband)
1530                         break;
1531         }
1532
1533         /*
1534          * Set power & frequency of stopband test tone
1535          */
1536         rt2800_bbp_write(rt2x00dev, 24, 0x06);
1537
1538         for (i = 0; i < 100; i++) {
1539                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1540                 msleep(1);
1541
1542                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1543
1544                 if ((passband - stopband) <= filter_target) {
1545                         rfcsr24++;
1546                         overtuned += ((passband - stopband) == filter_target);
1547                 } else
1548                         break;
1549
1550                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1551         }
1552
1553         rfcsr24 -= !!overtuned;
1554
1555         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1556         return rfcsr24;
1557 }
1558
1559 int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1560 {
1561         u8 rfcsr;
1562         u8 bbp;
1563
1564         if (rt2x00_intf_is_usb(rt2x00dev) &&
1565             rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1566                 return 0;
1567
1568         if (rt2x00_intf_is_pci(rt2x00dev)) {
1569                 if (!rt2x00_rf(&rt2x00dev->chip, RF3020) &&
1570                     !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
1571                     !rt2x00_rf(&rt2x00dev->chip, RF3022))
1572                         return 0;
1573         }
1574
1575         /*
1576          * Init RF calibration.
1577          */
1578         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1579         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1580         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1581         msleep(1);
1582         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1583         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1584
1585         if (rt2x00_intf_is_usb(rt2x00dev)) {
1586                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1587                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1588                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1589                 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1590                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1591                 rt2800_rfcsr_write(rt2x00dev, 10, 0x71);
1592                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1593                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1594                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1595                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1596                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1597                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1598                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1599                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1600                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1601                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1602                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1603                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1604                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1605                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1606         } else if (rt2x00_intf_is_pci(rt2x00dev)) {
1607                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
1608                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
1609                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
1610                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
1611                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1612                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1613                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1614                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
1615                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
1616                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1617                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
1618                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1619                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
1620                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
1621                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1622                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1623                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1624                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1625                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1626                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1627                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1628                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1629                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1630                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
1631                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1632                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1633                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
1634                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
1635                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
1636                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
1637         }
1638
1639         /*
1640          * Set RX Filter calibration for 20MHz and 40MHz
1641          */
1642         rt2x00dev->calibration[0] =
1643             rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1644         rt2x00dev->calibration[1] =
1645             rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1646
1647         /*
1648          * Set back to initial state
1649          */
1650         rt2800_bbp_write(rt2x00dev, 24, 0);
1651
1652         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1653         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1654         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1655
1656         /*
1657          * set BBP back to BW20
1658          */
1659         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1660         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1661         rt2800_bbp_write(rt2x00dev, 4, bbp);
1662
1663         return 0;
1664 }
1665 EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
1666
1667 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
1668 {
1669         u32 reg;
1670
1671         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
1672
1673         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
1674 }
1675 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
1676
1677 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
1678 {
1679         u32 reg;
1680
1681         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
1682         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
1683         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
1684         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
1685         rt2800_register_write(rt2x00dev, EFUSE_CTRL, reg);
1686
1687         /* Wait until the EEPROM has been loaded */
1688         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
1689
1690         /* Apparently the data is read from end to start */
1691         rt2800_register_read(rt2x00dev, EFUSE_DATA3,
1692                                 (u32 *)&rt2x00dev->eeprom[i]);
1693         rt2800_register_read(rt2x00dev, EFUSE_DATA2,
1694                                 (u32 *)&rt2x00dev->eeprom[i + 2]);
1695         rt2800_register_read(rt2x00dev, EFUSE_DATA1,
1696                                 (u32 *)&rt2x00dev->eeprom[i + 4]);
1697         rt2800_register_read(rt2x00dev, EFUSE_DATA0,
1698                                 (u32 *)&rt2x00dev->eeprom[i + 6]);
1699 }
1700
1701 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
1702 {
1703         unsigned int i;
1704
1705         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
1706                 rt2800_efuse_read(rt2x00dev, i);
1707 }
1708 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
1709
1710 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1711 {
1712         u16 word;
1713         u8 *mac;
1714         u8 default_lna_gain;
1715
1716         /*
1717          * Start validation of the data that has been read.
1718          */
1719         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1720         if (!is_valid_ether_addr(mac)) {
1721                 random_ether_addr(mac);
1722                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1723         }
1724
1725         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1726         if (word == 0xffff) {
1727                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1728                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
1729                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
1730                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1731                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1732         } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
1733                 /*
1734                  * There is a max of 2 RX streams for RT28x0 series
1735                  */
1736                 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
1737                         rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1738                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1739         }
1740
1741         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1742         if (word == 0xffff) {
1743                 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
1744                 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
1745                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1746                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1747                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1748                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
1749                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
1750                 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
1751                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
1752                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
1753                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1754                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1755         }
1756
1757         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1758         if ((word & 0x00ff) == 0x00ff) {
1759                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1760                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
1761                                    LED_MODE_TXRX_ACTIVITY);
1762                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
1763                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1764                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
1765                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
1766                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
1767                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1768         }
1769
1770         /*
1771          * During the LNA validation we are going to use
1772          * lna0 as correct value. Note that EEPROM_LNA
1773          * is never validated.
1774          */
1775         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
1776         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
1777
1778         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
1779         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
1780                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
1781         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
1782                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
1783         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
1784
1785         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
1786         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
1787                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
1788         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
1789             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
1790                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
1791                                    default_lna_gain);
1792         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
1793
1794         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
1795         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
1796                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
1797         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
1798                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
1799         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
1800
1801         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
1802         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
1803                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
1804         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
1805             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
1806                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
1807                                    default_lna_gain);
1808         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
1809
1810         return 0;
1811 }
1812 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
1813
1814 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
1815 {
1816         u32 reg;
1817         u16 value;
1818         u16 eeprom;
1819
1820         /*
1821          * Read EEPROM word for configuration.
1822          */
1823         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1824
1825         /*
1826          * Identify RF chipset.
1827          */
1828         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1829         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1830
1831         if (rt2x00_intf_is_usb(rt2x00dev)) {
1832                 struct rt2x00_chip *chip = &rt2x00dev->chip;
1833
1834                 rt2x00_set_chip(rt2x00dev, RT2870, value, reg);
1835
1836                 /*
1837                  * The check for rt2860 is not a typo, some rt2870 hardware
1838                  * identifies itself as rt2860 in the CSR register.
1839                  */
1840                 if (!rt2x00_check_rev(chip, 0xfff00000, 0x28600000) &&
1841                     !rt2x00_check_rev(chip, 0xfff00000, 0x28700000) &&
1842                     !rt2x00_check_rev(chip, 0xfff00000, 0x28800000) &&
1843                     !rt2x00_check_rev(chip, 0xffff0000, 0x30700000)) {
1844                         ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1845                         return -ENODEV;
1846                 }
1847         } else if (rt2x00_intf_is_pci(rt2x00dev))
1848                 rt2x00_set_chip_rf(rt2x00dev, value, reg);
1849
1850         if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
1851             !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
1852             !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
1853             !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
1854             !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
1855             !rt2x00_rf(&rt2x00dev->chip, RF2020) &&
1856             (rt2x00_intf_is_usb(rt2x00dev) ||
1857              (rt2x00_intf_is_pci(rt2x00dev) &&
1858               !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
1859               !rt2x00_rf(&rt2x00dev->chip, RF3022)))) {
1860                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1861                 return -ENODEV;
1862         }
1863
1864         /*
1865          * Identify default antenna configuration.
1866          */
1867         rt2x00dev->default_ant.tx =
1868             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
1869         rt2x00dev->default_ant.rx =
1870             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
1871
1872         /*
1873          * Read frequency offset and RF programming sequence.
1874          */
1875         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1876         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1877
1878         /*
1879          * Read external LNA informations.
1880          */
1881         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1882
1883         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
1884                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1885         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1886                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1887
1888         /*
1889          * Detect if this device has an hardware controlled radio.
1890          */
1891         if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
1892                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1893
1894         /*
1895          * Store led settings, for correct led behaviour.
1896          */
1897 #ifdef CONFIG_RT2X00_LIB_LEDS
1898         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1899         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1900         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
1901
1902         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
1903 #endif /* CONFIG_RT2X00_LIB_LEDS */
1904
1905         return 0;
1906 }
1907 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
1908
1909 /*
1910  * RF value list for rt28x0
1911  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
1912  */
1913 static const struct rf_channel rf_vals[] = {
1914         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
1915         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
1916         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
1917         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
1918         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
1919         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
1920         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
1921         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
1922         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
1923         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
1924         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
1925         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
1926         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
1927         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
1928
1929         /* 802.11 UNI / HyperLan 2 */
1930         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
1931         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
1932         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
1933         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
1934         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
1935         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
1936         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
1937         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
1938         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
1939         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
1940         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
1941         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
1942
1943         /* 802.11 HyperLan 2 */
1944         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
1945         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
1946         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
1947         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
1948         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
1949         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
1950         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
1951         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
1952         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
1953         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
1954         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
1955         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
1956         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
1957         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
1958         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
1959         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
1960
1961         /* 802.11 UNII */
1962         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
1963         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
1964         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
1965         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
1966         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
1967         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
1968         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
1969         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
1970         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
1971         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
1972         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
1973
1974         /* 802.11 Japan */
1975         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
1976         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
1977         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
1978         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
1979         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
1980         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
1981         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
1982 };
1983
1984 /*
1985  * RF value list for rt3070
1986  * Supports: 2.4 GHz
1987  */
1988 static const struct rf_channel rf_vals_3070[] = {
1989         {1,  241, 2, 2 },
1990         {2,  241, 2, 7 },
1991         {3,  242, 2, 2 },
1992         {4,  242, 2, 7 },
1993         {5,  243, 2, 2 },
1994         {6,  243, 2, 7 },
1995         {7,  244, 2, 2 },
1996         {8,  244, 2, 7 },
1997         {9,  245, 2, 2 },
1998         {10, 245, 2, 7 },
1999         {11, 246, 2, 2 },
2000         {12, 246, 2, 7 },
2001         {13, 247, 2, 2 },
2002         {14, 248, 2, 4 },
2003 };
2004
2005 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2006 {
2007         struct rt2x00_chip *chip = &rt2x00dev->chip;
2008         struct hw_mode_spec *spec = &rt2x00dev->spec;
2009         struct channel_info *info;
2010         char *tx_power1;
2011         char *tx_power2;
2012         unsigned int i;
2013         u16 eeprom;
2014
2015         /*
2016          * Initialize all hw fields.
2017          */
2018         rt2x00dev->hw->flags =
2019             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2020             IEEE80211_HW_SIGNAL_DBM |
2021             IEEE80211_HW_SUPPORTS_PS |
2022             IEEE80211_HW_PS_NULLFUNC_STACK;
2023
2024         if (rt2x00_intf_is_usb(rt2x00dev))
2025                 rt2x00dev->hw->extra_tx_headroom =
2026                         TXINFO_DESC_SIZE + TXWI_DESC_SIZE;
2027         else if (rt2x00_intf_is_pci(rt2x00dev))
2028                 rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE;
2029
2030         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2031         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2032                                 rt2x00_eeprom_addr(rt2x00dev,
2033                                                    EEPROM_MAC_ADDR_0));
2034
2035         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2036
2037         /*
2038          * Initialize hw_mode information.
2039          */
2040         spec->supported_bands = SUPPORT_BAND_2GHZ;
2041         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2042
2043         if (rt2x00_rf(chip, RF2820) ||
2044             rt2x00_rf(chip, RF2720) ||
2045             (rt2x00_intf_is_pci(rt2x00dev) &&
2046              (rt2x00_rf(chip, RF3020) ||
2047               rt2x00_rf(chip, RF3021) ||
2048               rt2x00_rf(chip, RF3022) ||
2049               rt2x00_rf(chip, RF2020) ||
2050               rt2x00_rf(chip, RF3052)))) {
2051                 spec->num_channels = 14;
2052                 spec->channels = rf_vals;
2053         } else if (rt2x00_rf(chip, RF2850) ||
2054                    rt2x00_rf(chip, RF2750)) {
2055                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2056                 spec->num_channels = ARRAY_SIZE(rf_vals);
2057                 spec->channels = rf_vals;
2058         } else if (rt2x00_intf_is_usb(rt2x00dev) &&
2059                     (rt2x00_rf(chip, RF3020) ||
2060                      rt2x00_rf(chip, RF2020))) {
2061                 spec->num_channels = ARRAY_SIZE(rf_vals_3070);
2062                 spec->channels = rf_vals_3070;
2063         }
2064
2065         /*
2066          * Initialize HT information.
2067          */
2068         spec->ht.ht_supported = true;
2069         spec->ht.cap =
2070             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2071             IEEE80211_HT_CAP_GRN_FLD |
2072             IEEE80211_HT_CAP_SGI_20 |
2073             IEEE80211_HT_CAP_SGI_40 |
2074             IEEE80211_HT_CAP_TX_STBC |
2075             IEEE80211_HT_CAP_RX_STBC |
2076             IEEE80211_HT_CAP_PSMP_SUPPORT;
2077         spec->ht.ampdu_factor = 3;
2078         spec->ht.ampdu_density = 4;
2079         spec->ht.mcs.tx_params =
2080             IEEE80211_HT_MCS_TX_DEFINED |
2081             IEEE80211_HT_MCS_TX_RX_DIFF |
2082             ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2083                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2084
2085         switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2086         case 3:
2087                 spec->ht.mcs.rx_mask[2] = 0xff;
2088         case 2:
2089                 spec->ht.mcs.rx_mask[1] = 0xff;
2090         case 1:
2091                 spec->ht.mcs.rx_mask[0] = 0xff;
2092                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2093                 break;
2094         }
2095
2096         /*
2097          * Create channel information array
2098          */
2099         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2100         if (!info)
2101                 return -ENOMEM;
2102
2103         spec->channels_info = info;
2104
2105         tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2106         tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2107
2108         for (i = 0; i < 14; i++) {
2109                 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2110                 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2111         }
2112
2113         if (spec->num_channels > 14) {
2114                 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2115                 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2116
2117                 for (i = 14; i < spec->num_channels; i++) {
2118                         info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2119                         info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2120                 }
2121         }
2122
2123         return 0;
2124 }
2125 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
2126
2127 /*
2128  * IEEE80211 stack callback functions.
2129  */
2130 static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2131                                 u32 *iv32, u16 *iv16)
2132 {
2133         struct rt2x00_dev *rt2x00dev = hw->priv;
2134         struct mac_iveiv_entry iveiv_entry;
2135         u32 offset;
2136
2137         offset = MAC_IVEIV_ENTRY(hw_key_idx);
2138         rt2800_register_multiread(rt2x00dev, offset,
2139                                       &iveiv_entry, sizeof(iveiv_entry));
2140
2141         memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2142         memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2143 }
2144
2145 static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2146 {
2147         struct rt2x00_dev *rt2x00dev = hw->priv;
2148         u32 reg;
2149         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2150
2151         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2152         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2153         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2154
2155         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2156         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2157         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2158
2159         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2160         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2161         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2162
2163         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2164         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2165         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2166
2167         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2168         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2169         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2170
2171         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2172         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2173         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2174
2175         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2176         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2177         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2178
2179         return 0;
2180 }
2181
2182 static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2183                           const struct ieee80211_tx_queue_params *params)
2184 {
2185         struct rt2x00_dev *rt2x00dev = hw->priv;
2186         struct data_queue *queue;
2187         struct rt2x00_field32 field;
2188         int retval;
2189         u32 reg;
2190         u32 offset;
2191
2192         /*
2193          * First pass the configuration through rt2x00lib, that will
2194          * update the queue settings and validate the input. After that
2195          * we are free to update the registers based on the value
2196          * in the queue parameter.
2197          */
2198         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2199         if (retval)
2200                 return retval;
2201
2202         /*
2203          * We only need to perform additional register initialization
2204          * for WMM queues/
2205          */
2206         if (queue_idx >= 4)
2207                 return 0;
2208
2209         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2210
2211         /* Update WMM TXOP register */
2212         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2213         field.bit_offset = (queue_idx & 1) * 16;
2214         field.bit_mask = 0xffff << field.bit_offset;
2215
2216         rt2800_register_read(rt2x00dev, offset, &reg);
2217         rt2x00_set_field32(&reg, field, queue->txop);
2218         rt2800_register_write(rt2x00dev, offset, reg);
2219
2220         /* Update WMM registers */
2221         field.bit_offset = queue_idx * 4;
2222         field.bit_mask = 0xf << field.bit_offset;
2223
2224         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2225         rt2x00_set_field32(&reg, field, queue->aifs);
2226         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2227
2228         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2229         rt2x00_set_field32(&reg, field, queue->cw_min);
2230         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2231
2232         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2233         rt2x00_set_field32(&reg, field, queue->cw_max);
2234         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2235
2236         /* Update EDCA registers */
2237         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2238
2239         rt2800_register_read(rt2x00dev, offset, &reg);
2240         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2241         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2242         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2243         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2244         rt2800_register_write(rt2x00dev, offset, reg);
2245
2246         return 0;
2247 }
2248
2249 static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2250 {
2251         struct rt2x00_dev *rt2x00dev = hw->priv;
2252         u64 tsf;
2253         u32 reg;
2254
2255         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2256         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2257         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2258         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2259
2260         return tsf;
2261 }
2262
2263 const struct ieee80211_ops rt2800_mac80211_ops = {
2264         .tx                     = rt2x00mac_tx,
2265         .start                  = rt2x00mac_start,
2266         .stop                   = rt2x00mac_stop,
2267         .add_interface          = rt2x00mac_add_interface,
2268         .remove_interface       = rt2x00mac_remove_interface,
2269         .config                 = rt2x00mac_config,
2270         .configure_filter       = rt2x00mac_configure_filter,
2271         .set_tim                = rt2x00mac_set_tim,
2272         .set_key                = rt2x00mac_set_key,
2273         .get_stats              = rt2x00mac_get_stats,
2274         .get_tkip_seq           = rt2800_get_tkip_seq,
2275         .set_rts_threshold      = rt2800_set_rts_threshold,
2276         .bss_info_changed       = rt2x00mac_bss_info_changed,
2277         .conf_tx                = rt2800_conf_tx,
2278         .get_tx_stats           = rt2x00mac_get_tx_stats,
2279         .get_tsf                = rt2800_get_tsf,
2280         .rfkill_poll            = rt2x00mac_rfkill_poll,
2281 };
2282 EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);