SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   3         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   4
   5         Based on the original rt2800pci.c and rt2800usb.c.
   6           Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
   7           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   8           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   9           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  10           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  11           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  12           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  13           <http://rt2x00.serialmonkey.com>
  14
  15         This program is free software; you can redistribute it and/or modify
  16         it under the terms of the GNU General Public License as published by
  17         the Free Software Foundation; either version 2 of the License, or
  18         (at your option) any later version.
  19
  20         This program is distributed in the hope that it will be useful,
  21         but WITHOUT ANY WARRANTY; without even the implied warranty of
  22         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23         GNU General Public License for more details.
  24
  25         You should have received a copy of the GNU General Public License
  26         along with this program; if not, write to the
  27         Free Software Foundation, Inc.,
  28         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  29  */
  30
  31 /*
  32         Module: rt2800lib
  33         Abstract: rt2800 generic device routines.
  34  */
  35
  36 #include <linux/kernel.h>
  37 #include <linux/module.h>
  38
  39 #include "rt2x00.h"
  40 #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
  41 #include "rt2x00usb.h"
  42 #endif
  43 #include "rt2800lib.h"
  44 #include "rt2800.h"
  45 #include "rt2800usb.h"
  46
  47 MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
  48 MODULE_DESCRIPTION("rt2800 library");
  49 MODULE_LICENSE("GPL");
  50
  51 /*
  52  * Register access.
  53  * All access to the CSR registers will go through the methods
  54  * rt2800_register_read and rt2800_register_write.
  55  * BBP and RF register require indirect register access,
  56  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  57  * These indirect registers work with busy bits,
  58  * and we will try maximal REGISTER_BUSY_COUNT times to access
  59  * the register while taking a REGISTER_BUSY_DELAY us delay
  60  * between each attampt. When the busy bit is still set at that time,
  61  * the access attempt is considered to have failed,
  62  * and we will print an error.
  63  * The _lock versions must be used if you already hold the csr_mutex
  64  */
  65 #define WAIT_FOR_BBP(__dev, __reg) \
  66         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  67 #define WAIT_FOR_RFCSR(__dev, __reg) \
  68         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  69 #define WAIT_FOR_RF(__dev, __reg) \
  70         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  71 #define WAIT_FOR_MCU(__dev, __reg) \
  72         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  73                             H2M_MAILBOX_CSR_OWNER, (__reg))
  74
  75 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  76 {
  77         /* check for rt2872 on SoC */
  78         if (!rt2x00_is_soc(rt2x00dev) ||
  79             !rt2x00_rt(rt2x00dev, RT2872))
  80                 return false;
  81
  82         /* we know for sure that these rf chipsets are used on rt305x boards */
  83         if (rt2x00_rf(rt2x00dev, RF3020) ||
  84             rt2x00_rf(rt2x00dev, RF3021) ||
  85             rt2x00_rf(rt2x00dev, RF3022))
  86                 return true;
  87
  88         NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
  89         return false;
  90 }
  91
  92 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  93                              const unsigned int word, const u8 value)
  94 {
  95         u32 reg;
  96
  97         mutex_lock(&rt2x00dev->csr_mutex);
  98
  99         /*
 100          * Wait until the BBP becomes available, afterwards we
 101          * can safely write the new data into the register.
 102          */
 103         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 104                 reg = 0;
 105                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 106                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 107                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 108                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 109                 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
 110                         rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 111
 112                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 113         }
 114
 115         mutex_unlock(&rt2x00dev->csr_mutex);
 116 }
 117
 118 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 119                             const unsigned int word, u8 *value)
 120 {
 121         u32 reg;
 122
 123         mutex_lock(&rt2x00dev->csr_mutex);
 124
 125         /*
 126          * Wait until the BBP becomes available, afterwards we
 127          * can safely write the read request into the register.
 128          * After the data has been written, we wait until hardware
 129          * returns the correct value, if at any time the register
 130          * doesn't become available in time, reg will be 0xffffffff
 131          * which means we return 0xff to the caller.
 132          */
 133         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 134                 reg = 0;
 135                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 136                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 137                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 138                 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
 139                         rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 140
 141                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 142
 143                 WAIT_FOR_BBP(rt2x00dev, &reg);
 144         }
 145
 146         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 147
 148         mutex_unlock(&rt2x00dev->csr_mutex);
 149 }
 150
 151 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 152                                const unsigned int word, const u8 value)
 153 {
 154         u32 reg;
 155
 156         mutex_lock(&rt2x00dev->csr_mutex);
 157
 158         /*
 159          * Wait until the RFCSR becomes available, afterwards we
 160          * can safely write the new data into the register.
 161          */
 162         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 163                 reg = 0;
 164                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 165                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 166                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 167                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 168
 169                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 170         }
 171
 172         mutex_unlock(&rt2x00dev->csr_mutex);
 173 }
 174
 175 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 176                               const unsigned int word, u8 *value)
 177 {
 178         u32 reg;
 179
 180         mutex_lock(&rt2x00dev->csr_mutex);
 181
 182         /*
 183          * Wait until the RFCSR becomes available, afterwards we
 184          * can safely write the read request into the register.
 185          * After the data has been written, we wait until hardware
 186          * returns the correct value, if at any time the register
 187          * doesn't become available in time, reg will be 0xffffffff
 188          * which means we return 0xff to the caller.
 189          */
 190         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 191                 reg = 0;
 192                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 193                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 194                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 195
 196                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 197
 198                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 199         }
 200
 201         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 202
 203         mutex_unlock(&rt2x00dev->csr_mutex);
 204 }
 205
 206 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 207                             const unsigned int word, const u32 value)
 208 {
 209         u32 reg;
 210
 211         mutex_lock(&rt2x00dev->csr_mutex);
 212
 213         /*
 214          * Wait until the RF becomes available, afterwards we
 215          * can safely write the new data into the register.
 216          */
 217         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 218                 reg = 0;
 219                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 220                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 221                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 222                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 223
 224                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 225                 rt2x00_rf_write(rt2x00dev, word, value);
 226         }
 227
 228         mutex_unlock(&rt2x00dev->csr_mutex);
 229 }
 230
 231 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 232                         const u8 command, const u8 token,
 233                         const u8 arg0, const u8 arg1)
 234 {
 235         u32 reg;
 236
 237         /*
 238          * SOC devices don't support MCU requests.
 239          */
 240         if (rt2x00_is_soc(rt2x00dev))
 241                 return;
 242
 243         mutex_lock(&rt2x00dev->csr_mutex);
 244
 245         /*
 246          * Wait until the MCU becomes available, afterwards we
 247          * can safely write the new data into the register.
 248          */
 249         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 250                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 251                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 252                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 253                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 254                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 255
 256                 reg = 0;
 257                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 258                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 259         }
 260
 261         mutex_unlock(&rt2x00dev->csr_mutex);
 262 }
 263 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 264
 265 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 266 {
 267         unsigned int i;
 268         u32 reg;
 269
 270         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 271                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 272                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 273                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 274                         return 0;
 275
 276                 msleep(1);
 277         }
 278
 279         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
 280         return -EACCES;
 281 }
 282 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 283
 284 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 285 const struct rt2x00debug rt2800_rt2x00debug = {
 286         .owner  = THIS_MODULE,
 287         .csr    = {
 288                 .read           = rt2800_register_read,
 289                 .write          = rt2800_register_write,
 290                 .flags          = RT2X00DEBUGFS_OFFSET,
 291                 .word_base      = CSR_REG_BASE,
 292                 .word_size      = sizeof(u32),
 293                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 294         },
 295         .eeprom = {
 296                 .read           = rt2x00_eeprom_read,
 297                 .write          = rt2x00_eeprom_write,
 298                 .word_base      = EEPROM_BASE,
 299                 .word_size      = sizeof(u16),
 300                 .word_count     = EEPROM_SIZE / sizeof(u16),
 301         },
 302         .bbp    = {
 303                 .read           = rt2800_bbp_read,
 304                 .write          = rt2800_bbp_write,
 305                 .word_base      = BBP_BASE,
 306                 .word_size      = sizeof(u8),
 307                 .word_count     = BBP_SIZE / sizeof(u8),
 308         },
 309         .rf     = {
 310                 .read           = rt2x00_rf_read,
 311                 .write          = rt2800_rf_write,
 312                 .word_base      = RF_BASE,
 313                 .word_size      = sizeof(u32),
 314                 .word_count     = RF_SIZE / sizeof(u32),
 315         },
 316 };
 317 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 318 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 319
 320 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 321 {
 322         u32 reg;
 323
 324         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 325         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 326 }
 327 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 328
 329 #ifdef CONFIG_RT2X00_LIB_LEDS
 330 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 331                                   enum led_brightness brightness)
 332 {
 333         struct rt2x00_led *led =
 334             container_of(led_cdev, struct rt2x00_led, led_dev);
 335         unsigned int enabled = brightness != LED_OFF;
 336         unsigned int bg_mode =
 337             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 338         unsigned int polarity =
 339                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 340                                    EEPROM_FREQ_LED_POLARITY);
 341         unsigned int ledmode =
 342                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 343                                    EEPROM_FREQ_LED_MODE);
 344
 345         if (led->type == LED_TYPE_RADIO) {
 346                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 347                                       enabled ? 0x20 : 0);
 348         } else if (led->type == LED_TYPE_ASSOC) {
 349                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 350                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 351         } else if (led->type == LED_TYPE_QUALITY) {
 352                 /*
 353                  * The brightness is divided into 6 levels (0 - 5),
 354                  * The specs tell us the following levels:
 355                  *      0, 1 ,3, 7, 15, 31
 356                  * to determine the level in a simple way we can simply
 357                  * work with bitshifting:
 358                  *      (1 << level) - 1
 359                  */
 360                 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 361                                       (1 << brightness / (LED_FULL / 6)) - 1,
 362                                       polarity);
 363         }
 364 }
 365
 366 static int rt2800_blink_set(struct led_classdev *led_cdev,
 367                             unsigned long *delay_on, unsigned long *delay_off)
 368 {
 369         struct rt2x00_led *led =
 370             container_of(led_cdev, struct rt2x00_led, led_dev);
 371         u32 reg;
 372
 373         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 374         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 375         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 376         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 377
 378         return 0;
 379 }
 380
 381 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 382                      struct rt2x00_led *led, enum led_type type)
 383 {
 384         led->rt2x00dev = rt2x00dev;
 385         led->type = type;
 386         led->led_dev.brightness_set = rt2800_brightness_set;
 387         led->led_dev.blink_set = rt2800_blink_set;
 388         led->flags = LED_INITIALIZED;
 389 }
 390 #endif /* CONFIG_RT2X00_LIB_LEDS */
 391
 392 /*
 393  * Configuration handlers.
 394  */
 395 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 396                                     struct rt2x00lib_crypto *crypto,
 397                                     struct ieee80211_key_conf *key)
 398 {
 399         struct mac_wcid_entry wcid_entry;
 400         struct mac_iveiv_entry iveiv_entry;
 401         u32 offset;
 402         u32 reg;
 403
 404         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 405
 406         rt2800_register_read(rt2x00dev, offset, &reg);
 407         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 408                            !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 409         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 410                            (crypto->cmd == SET_KEY) * crypto->cipher);
 411         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 412                            (crypto->cmd == SET_KEY) * crypto->bssidx);
 413         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 414         rt2800_register_write(rt2x00dev, offset, reg);
 415
 416         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 417
 418         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 419         if ((crypto->cipher == CIPHER_TKIP) ||
 420             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 421             (crypto->cipher == CIPHER_AES))
 422                 iveiv_entry.iv[3] |= 0x20;
 423         iveiv_entry.iv[3] |= key->keyidx << 6;
 424         rt2800_register_multiwrite(rt2x00dev, offset,
 425                                       &iveiv_entry, sizeof(iveiv_entry));
 426
 427         offset = MAC_WCID_ENTRY(key->hw_key_idx);
 428
 429         memset(&wcid_entry, 0, sizeof(wcid_entry));
 430         if (crypto->cmd == SET_KEY)
 431                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 432         rt2800_register_multiwrite(rt2x00dev, offset,
 433                                       &wcid_entry, sizeof(wcid_entry));
 434 }
 435
 436 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
 437                              struct rt2x00lib_crypto *crypto,
 438                              struct ieee80211_key_conf *key)
 439 {
 440         struct hw_key_entry key_entry;
 441         struct rt2x00_field32 field;
 442         u32 offset;
 443         u32 reg;
 444
 445         if (crypto->cmd == SET_KEY) {
 446                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 447
 448                 memcpy(key_entry.key, crypto->key,
 449                        sizeof(key_entry.key));
 450                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 451                        sizeof(key_entry.tx_mic));
 452                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 453                        sizeof(key_entry.rx_mic));
 454
 455                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 456                 rt2800_register_multiwrite(rt2x00dev, offset,
 457                                               &key_entry, sizeof(key_entry));
 458         }
 459
 460         /*
 461          * The cipher types are stored over multiple registers
 462          * starting with SHARED_KEY_MODE_BASE each word will have
 463          * 32 bits and contains the cipher types for 2 bssidx each.
 464          * Using the correct defines correctly will cause overhead,
 465          * so just calculate the correct offset.
 466          */
 467         field.bit_offset = 4 * (key->hw_key_idx % 8);
 468         field.bit_mask = 0x7 << field.bit_offset;
 469
 470         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
 471
 472         rt2800_register_read(rt2x00dev, offset, &reg);
 473         rt2x00_set_field32(&reg, field,
 474                            (crypto->cmd == SET_KEY) * crypto->cipher);
 475         rt2800_register_write(rt2x00dev, offset, reg);
 476
 477         /*
 478          * Update WCID information
 479          */
 480         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
 481
 482         return 0;
 483 }
 484 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
 485
 486 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 487                                struct rt2x00lib_crypto *crypto,
 488                                struct ieee80211_key_conf *key)
 489 {
 490         struct hw_key_entry key_entry;
 491         u32 offset;
 492
 493         if (crypto->cmd == SET_KEY) {
 494                 /*
 495                  * 1 pairwise key is possible per AID, this means that the AID
 496                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
 497                  * last possible shared key entry.
 498                  */
 499                 if (crypto->aid > (256 - 32))
 500                         return -ENOSPC;
 501
 502                 key->hw_key_idx = 32 + crypto->aid;
 503
 504                 memcpy(key_entry.key, crypto->key,
 505                        sizeof(key_entry.key));
 506                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 507                        sizeof(key_entry.tx_mic));
 508                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 509                        sizeof(key_entry.rx_mic));
 510
 511                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 512                 rt2800_register_multiwrite(rt2x00dev, offset,
 513                                               &key_entry, sizeof(key_entry));
 514         }
 515
 516         /*
 517          * Update WCID information
 518          */
 519         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
 520
 521         return 0;
 522 }
 523 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
 524
 525 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
 526                           const unsigned int filter_flags)
 527 {
 528         u32 reg;
 529
 530         /*
 531          * Start configuration steps.
 532          * Note that the version error will always be dropped
 533          * and broadcast frames will always be accepted since
 534          * there is no filter for it at this time.
 535          */
 536         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
 537         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 538                            !(filter_flags & FIF_FCSFAIL));
 539         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 540                            !(filter_flags & FIF_PLCPFAIL));
 541         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 542                            !(filter_flags & FIF_PROMISC_IN_BSS));
 543         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
 544         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 545         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 546                            !(filter_flags & FIF_ALLMULTI));
 547         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 548         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 549         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 550                            !(filter_flags & FIF_CONTROL));
 551         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 552                            !(filter_flags & FIF_CONTROL));
 553         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 554                            !(filter_flags & FIF_CONTROL));
 555         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 556                            !(filter_flags & FIF_CONTROL));
 557         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 558                            !(filter_flags & FIF_CONTROL));
 559         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 560                            !(filter_flags & FIF_PSPOLL));
 561         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
 562         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
 563         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 564                            !(filter_flags & FIF_CONTROL));
 565         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 566 }
 567 EXPORT_SYMBOL_GPL(rt2800_config_filter);
 568
 569 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
 570                         struct rt2x00intf_conf *conf, const unsigned int flags)
 571 {
 572         unsigned int beacon_base;
 573         u32 reg;
 574
 575         if (flags & CONFIG_UPDATE_TYPE) {
 576                 /*
 577                  * Clear current synchronisation setup.
 578                  * For the Beacon base registers we only need to clear
 579                  * the first byte since that byte contains the VALID and OWNER
 580                  * bits which (when set to 0) will invalidate the entire beacon.
 581                  */
 582                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 583                 rt2800_register_write(rt2x00dev, beacon_base, 0);
 584
 585                 /*
 586                  * Enable synchronisation.
 587                  */
 588                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 589                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 590                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 591                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
 592                                    (conf->sync == TSF_SYNC_BEACON));
 593                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 594         }
 595
 596         if (flags & CONFIG_UPDATE_MAC) {
 597                 reg = le32_to_cpu(conf->mac[1]);
 598                 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 599                 conf->mac[1] = cpu_to_le32(reg);
 600
 601                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 602                                               conf->mac, sizeof(conf->mac));
 603         }
 604
 605         if (flags & CONFIG_UPDATE_BSSID) {
 606                 reg = le32_to_cpu(conf->bssid[1]);
 607                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
 608                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 609                 conf->bssid[1] = cpu_to_le32(reg);
 610
 611                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 612                                               conf->bssid, sizeof(conf->bssid));
 613         }
 614 }
 615 EXPORT_SYMBOL_GPL(rt2800_config_intf);
 616
 617 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
 618 {
 619         u32 reg;
 620
 621         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
 622         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
 623                            !!erp->short_preamble);
 624         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 625                            !!erp->short_preamble);
 626         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 627
 628         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
 629         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 630                            erp->cts_protection ? 2 : 0);
 631         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 632
 633         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 634                                  erp->basic_rates);
 635         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
 636
 637         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
 638         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
 639         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 640
 641         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
 642         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
 643         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
 644         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 645         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 646
 647         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 648         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 649                            erp->beacon_int * 16);
 650         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 651 }
 652 EXPORT_SYMBOL_GPL(rt2800_config_erp);
 653
 654 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
 655 {
 656         u8 r1;
 657         u8 r3;
 658
 659         rt2800_bbp_read(rt2x00dev, 1, &r1);
 660         rt2800_bbp_read(rt2x00dev, 3, &r3);
 661
 662         /*
 663          * Configure the TX antenna.
 664          */
 665         switch ((int)ant->tx) {
 666         case 1:
 667                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
 668                 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
 669                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 670                 break;
 671         case 2:
 672                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
 673                 break;
 674         case 3:
 675                 /* Do nothing */
 676                 break;
 677         }
 678
 679         /*
 680          * Configure the RX antenna.
 681          */
 682         switch ((int)ant->rx) {
 683         case 1:
 684                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 685                 break;
 686         case 2:
 687                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 688                 break;
 689         case 3:
 690                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 691                 break;
 692         }
 693
 694         rt2800_bbp_write(rt2x00dev, 3, r3);
 695         rt2800_bbp_write(rt2x00dev, 1, r1);
 696 }
 697 EXPORT_SYMBOL_GPL(rt2800_config_ant);
 698
 699 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 700                                    struct rt2x00lib_conf *libconf)
 701 {
 702         u16 eeprom;
 703         short lna_gain;
 704
 705         if (libconf->rf.channel <= 14) {
 706                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 707                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 708         } else if (libconf->rf.channel <= 64) {
 709                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 710                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 711         } else if (libconf->rf.channel <= 128) {
 712                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 713                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
 714         } else {
 715                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 716                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
 717         }
 718
 719         rt2x00dev->lna_gain = lna_gain;
 720 }
 721
 722 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
 723                                          struct ieee80211_conf *conf,
 724                                          struct rf_channel *rf,
 725                                          struct channel_info *info)
 726 {
 727         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 728
 729         if (rt2x00dev->default_ant.tx == 1)
 730                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 731
 732         if (rt2x00dev->default_ant.rx == 1) {
 733                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 734                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 735         } else if (rt2x00dev->default_ant.rx == 2)
 736                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 737
 738         if (rf->channel > 14) {
 739                 /*
 740                  * When TX power is below 0, we should increase it by 7 to
 741                  * make it a positive value (Minumum value is -7).
 742                  * However this means that values between 0 and 7 have
 743                  * double meaning, and we should set a 7DBm boost flag.
 744                  */
 745                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 746                                    (info->tx_power1 >= 0));
 747
 748                 if (info->tx_power1 < 0)
 749                         info->tx_power1 += 7;
 750
 751                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
 752                                    TXPOWER_A_TO_DEV(info->tx_power1));
 753
 754                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 755                                    (info->tx_power2 >= 0));
 756
 757                 if (info->tx_power2 < 0)
 758                         info->tx_power2 += 7;
 759
 760                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
 761                                    TXPOWER_A_TO_DEV(info->tx_power2));
 762         } else {
 763                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
 764                                    TXPOWER_G_TO_DEV(info->tx_power1));
 765                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
 766                                    TXPOWER_G_TO_DEV(info->tx_power2));
 767         }
 768
 769         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
 770
 771         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 772         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 773         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 774         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 775
 776         udelay(200);
 777
 778         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 779         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 780         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 781         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 782
 783         udelay(200);
 784
 785         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 786         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 787         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 788         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 789 }
 790
 791 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
 792                                          struct ieee80211_conf *conf,
 793                                          struct rf_channel *rf,
 794                                          struct channel_info *info)
 795 {
 796         u8 rfcsr;
 797
 798         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
 799         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
 800
 801         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
 802         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
 803         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
 804
 805         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
 806         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
 807                           TXPOWER_G_TO_DEV(info->tx_power1));
 808         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
 809
 810         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
 811         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
 812                           TXPOWER_G_TO_DEV(info->tx_power2));
 813         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
 814
 815         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
 816         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 817         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
 818
 819         rt2800_rfcsr_write(rt2x00dev, 24,
 820                               rt2x00dev->calibration[conf_is_ht40(conf)]);
 821
 822         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
 823         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 824         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
 825 }
 826
 827 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
 828                                   struct ieee80211_conf *conf,
 829                                   struct rf_channel *rf,
 830                                   struct channel_info *info)
 831 {
 832         u32 reg;
 833         unsigned int tx_pin;
 834         u8 bbp;
 835
 836         if (rt2x00_rf(rt2x00dev, RF2020) ||
 837             rt2x00_rf(rt2x00dev, RF3020) ||
 838             rt2x00_rf(rt2x00dev, RF3021) ||
 839             rt2x00_rf(rt2x00dev, RF3022))
 840                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
 841         else
 842                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
 843
 844         /*
 845          * Change BBP settings
 846          */
 847         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 848         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 849         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 850         rt2800_bbp_write(rt2x00dev, 86, 0);
 851
 852         if (rf->channel <= 14) {
 853                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 854                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
 855                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 856                 } else {
 857                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
 858                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 859                 }
 860         } else {
 861                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
 862
 863                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 864                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 865                 else
 866                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 867         }
 868
 869         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 870         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
 871         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
 872         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
 873         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
 874
 875         tx_pin = 0;
 876
 877         /* Turn on unused PA or LNA when not using 1T or 1R */
 878         if (rt2x00dev->default_ant.tx != 1) {
 879                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
 880                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 881         }
 882
 883         /* Turn on unused PA or LNA when not using 1T or 1R */
 884         if (rt2x00dev->default_ant.rx != 1) {
 885                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 886                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 887         }
 888
 889         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
 890         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
 891         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 892         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 893         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
 894         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
 895
 896         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 897
 898         rt2800_bbp_read(rt2x00dev, 4, &bbp);
 899         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
 900         rt2800_bbp_write(rt2x00dev, 4, bbp);
 901
 902         rt2800_bbp_read(rt2x00dev, 3, &bbp);
 903         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
 904         rt2800_bbp_write(rt2x00dev, 3, bbp);
 905
 906         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
 907                 if (conf_is_ht40(conf)) {
 908                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
 909                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
 910                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
 911                 } else {
 912                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
 913                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
 914                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
 915                 }
 916         }
 917
 918         msleep(1);
 919 }
 920
 921 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
 922                                   const int txpower)
 923 {
 924         u32 reg;
 925         u32 value = TXPOWER_G_TO_DEV(txpower);
 926         u8 r1;
 927
 928         rt2800_bbp_read(rt2x00dev, 1, &r1);
 929         rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
 930         rt2800_bbp_write(rt2x00dev, 1, r1);
 931
 932         rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
 933         rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
 934         rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
 935         rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
 936         rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
 937         rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
 938         rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
 939         rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
 940         rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
 941         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
 942
 943         rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
 944         rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
 945         rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
 946         rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
 947         rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
 948         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
 949         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
 950         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
 951         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
 952         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
 953
 954         rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
 955         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
 956         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
 957         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
 958         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
 959         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
 960         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
 961         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
 962         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
 963         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
 964
 965         rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
 966         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
 967         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
 968         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
 969         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
 970         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
 971         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
 972         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
 973         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
 974         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
 975
 976         rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
 977         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
 978         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
 979         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
 980         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
 981         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
 982 }
 983
 984 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 985                                       struct rt2x00lib_conf *libconf)
 986 {
 987         u32 reg;
 988
 989         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
 990         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
 991                            libconf->conf->short_frame_max_tx_count);
 992         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
 993                            libconf->conf->long_frame_max_tx_count);
 994         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
 995 }
 996
 997 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
 998                              struct rt2x00lib_conf *libconf)
 999 {
1000         enum dev_state state =
1001             (libconf->conf->flags & IEEE80211_CONF_PS) ?
1002                 STATE_SLEEP : STATE_AWAKE;
1003         u32 reg;
1004
1005         if (state == STATE_SLEEP) {
1006                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1007
1008                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1009                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1010                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1011                                    libconf->conf->listen_interval - 1);
1012                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1013                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1014
1015                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1016         } else {
1017                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1018                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1019                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1020                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1021                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1022
1023                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1024         }
1025 }
1026
1027 void rt2800_config(struct rt2x00_dev *rt2x00dev,
1028                    struct rt2x00lib_conf *libconf,
1029                    const unsigned int flags)
1030 {
1031         /* Always recalculate LNA gain before changing configuration */
1032         rt2800_config_lna_gain(rt2x00dev, libconf);
1033
1034         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1035                 rt2800_config_channel(rt2x00dev, libconf->conf,
1036                                       &libconf->rf, &libconf->channel);
1037         if (flags & IEEE80211_CONF_CHANGE_POWER)
1038                 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1039         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1040                 rt2800_config_retry_limit(rt2x00dev, libconf);
1041         if (flags & IEEE80211_CONF_CHANGE_PS)
1042                 rt2800_config_ps(rt2x00dev, libconf);
1043 }
1044 EXPORT_SYMBOL_GPL(rt2800_config);
1045
1046 /*
1047  * Link tuning
1048  */
1049 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1050 {
1051         u32 reg;
1052
1053         /*
1054          * Update FCS error count from register.
1055          */
1056         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1057         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1058 }
1059 EXPORT_SYMBOL_GPL(rt2800_link_stats);
1060
1061 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1062 {
1063         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1064                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1065                     rt2x00_rt(rt2x00dev, RT3071) ||
1066                     rt2x00_rt(rt2x00dev, RT3090) ||
1067                     rt2x00_rt(rt2x00dev, RT3390))
1068                         return 0x1c + (2 * rt2x00dev->lna_gain);
1069                 else
1070                         return 0x2e + rt2x00dev->lna_gain;
1071         }
1072
1073         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1074                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1075         else
1076                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1077 }
1078
1079 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1080                                   struct link_qual *qual, u8 vgc_level)
1081 {
1082         if (qual->vgc_level != vgc_level) {
1083                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1084                 qual->vgc_level = vgc_level;
1085                 qual->vgc_level_reg = vgc_level;
1086         }
1087 }
1088
1089 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1090 {
1091         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1092 }
1093 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1094
1095 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1096                        const u32 count)
1097 {
1098         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
1099                 return;
1100
1101         /*
1102          * When RSSI is better then -80 increase VGC level with 0x10
1103          */
1104         rt2800_set_vgc(rt2x00dev, qual,
1105                        rt2800_get_default_vgc(rt2x00dev) +
1106                        ((qual->rssi > -80) * 0x10));
1107 }
1108 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1109
1110 /*
1111  * Initialization functions.
1112  */
1113 int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1114 {
1115         u32 reg;
1116         u16 eeprom;
1117         unsigned int i;
1118
1119         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1120         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1121         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1122         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1123         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1124         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1125         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1126
1127         if (rt2x00_is_usb(rt2x00dev)) {
1128                 /*
1129                  * Wait until BBP and RF are ready.
1130                  */
1131                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1132                         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1133                         if (reg && reg != ~0)
1134                                 break;
1135                         msleep(1);
1136                 }
1137
1138                 if (i == REGISTER_BUSY_COUNT) {
1139                         ERROR(rt2x00dev, "Unstable hardware.\n");
1140                         return -EBUSY;
1141                 }
1142
1143                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1144                 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
1145                                       reg & ~0x00002000);
1146         } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) {
1147                 /*
1148                  * Reset DMA indexes
1149                  */
1150                 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1151                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1152                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1153                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1154                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1155                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1156                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1157                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1158                 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1159
1160                 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1161                 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1162
1163                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1164         }
1165
1166         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1167         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1168         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1169         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1170
1171         if (rt2x00_is_usb(rt2x00dev)) {
1172                 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1173 #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
1174                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1175                                             USB_MODE_RESET, REGISTER_TIMEOUT);
1176 #endif
1177         }
1178
1179         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1180
1181         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1182         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1183         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1184         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1185         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1186         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1187
1188         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1189         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1190         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1191         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1192         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1193         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1194
1195         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1196         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1197
1198         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1199
1200         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1201         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1202         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1203         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1204         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1205         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1206         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1207         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1208
1209         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1210
1211         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1212         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1213         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1214         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1215
1216         if (rt2x00_rt(rt2x00dev, RT3071) ||
1217             rt2x00_rt(rt2x00dev, RT3090) ||
1218             rt2x00_rt(rt2x00dev, RT3390)) {
1219                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1220                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1221                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1222                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1223                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
1224                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1225                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1226                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1227                                                       0x0000002c);
1228                         else
1229                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1230                                                       0x0000000f);
1231                 } else {
1232                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1233                 }
1234                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, reg);
1235         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
1236                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1237
1238                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1239                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1240                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1241                 } else {
1242                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1243                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1244                 }
1245         } else {
1246                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1247                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1248         }
1249
1250         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1251         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1252         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1253         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1254         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1255         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1256         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1257         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1258         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1259         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1260
1261         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1262         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1263         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
1264         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1265         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1266
1267         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1268         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1269         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
1270             rt2x00_rt(rt2x00dev, RT2883) ||
1271             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
1272                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1273         else
1274                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1275         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1276         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1277         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1278
1279         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1280         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1281         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1282         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1283         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1284         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1285         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1286         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1287         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1288
1289         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1290
1291         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1292         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1293         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1294         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1295         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1296         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1297         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1298         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1299
1300         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1301         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1302         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
1303         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1304         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1305         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
1306         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1307         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1308         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1309
1310         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1311         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
1312         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1313         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1314         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1315         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1316         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1317         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1318         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1319         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1320         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
1321         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1322
1323         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1324         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
1325         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1326         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1327         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1328         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1329         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1330         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1331         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1332         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1333         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
1334         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1335
1336         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1337         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1338         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1339         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1340         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1341         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1342         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1343         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1344         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1345         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1346         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
1347         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1348
1349         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1350         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1351         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL,
1352                            !rt2x00_is_usb(rt2x00dev));
1353         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1354         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1355         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1356         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1357         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1358         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1359         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1360         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
1361         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1362
1363         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1364         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1365         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1366         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1367         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1368         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1369         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1370         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1371         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1372         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1373         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
1374         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1375
1376         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1377         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1378         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1379         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1380         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1381         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1382         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1383         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1384         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1385         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1386         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
1387         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1388
1389         if (rt2x00_is_usb(rt2x00dev)) {
1390                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1391
1392                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1393                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1394                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1395                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1396                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1397                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1398                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1399                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1400                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1401                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1402                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1403         }
1404
1405         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1406         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1407
1408         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1409         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1410         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1411                            IEEE80211_MAX_RTS_THRESHOLD);
1412         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1413         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1414
1415         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1416
1417         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1418         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 32);
1419         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 32);
1420         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
1421         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
1422         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
1423         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1424
1425         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1426
1427         /*
1428          * ASIC will keep garbage value after boot, clear encryption keys.
1429          */
1430         for (i = 0; i < 4; i++)
1431                 rt2800_register_write(rt2x00dev,
1432                                          SHARED_KEY_MODE_ENTRY(i), 0);
1433
1434         for (i = 0; i < 256; i++) {
1435                 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1436                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1437                                               wcid, sizeof(wcid));
1438
1439                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1440                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1441         }
1442
1443         /*
1444          * Clear all beacons
1445          * For the Beacon base registers we only need to clear
1446          * the first byte since that byte contains the VALID and OWNER
1447          * bits which (when set to 0) will invalidate the entire beacon.
1448          */
1449         rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1450         rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1451         rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1452         rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1453         rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1454         rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1455         rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1456         rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1457
1458         if (rt2x00_is_usb(rt2x00dev)) {
1459                 rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1460                 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1461                 rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1462         }
1463
1464         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1465         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1466         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1467         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1468         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1469         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1470         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1471         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1472         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1473         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1474
1475         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1476         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1477         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1478         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1479         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1480         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1481         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1482         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1483         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1484         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1485
1486         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1487         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1488         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1489         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1490         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1491         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1492         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1493         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1494         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1495         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1496
1497         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1498         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1499         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1500         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1501         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1502         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1503
1504         /*
1505          * We must clear the error counters.
1506          * These registers are cleared on read,
1507          * so we may pass a useless variable to store the value.
1508          */
1509         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1510         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1511         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1512         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1513         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1514         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1515
1516         return 0;
1517 }
1518 EXPORT_SYMBOL_GPL(rt2800_init_registers);
1519
1520 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1521 {
1522         unsigned int i;
1523         u32 reg;
1524
1525         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1526                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1527                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1528                         return 0;
1529
1530                 udelay(REGISTER_BUSY_DELAY);
1531         }
1532
1533         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1534         return -EACCES;
1535 }
1536
1537 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1538 {
1539         unsigned int i;
1540         u8 value;
1541
1542         /*
1543          * BBP was enabled after firmware was loaded,
1544          * but we need to reactivate it now.
1545          */
1546         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1547         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1548         msleep(1);
1549
1550         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1551                 rt2800_bbp_read(rt2x00dev, 0, &value);
1552                 if ((value != 0xff) && (value != 0x00))
1553                         return 0;
1554                 udelay(REGISTER_BUSY_DELAY);
1555         }
1556
1557         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1558         return -EACCES;
1559 }
1560
1561 int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1562 {
1563         unsigned int i;
1564         u16 eeprom;
1565         u8 reg_id;
1566         u8 value;
1567
1568         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1569                      rt2800_wait_bbp_ready(rt2x00dev)))
1570                 return -EACCES;
1571
1572         if (rt2800_is_305x_soc(rt2x00dev))
1573                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1574
1575         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1576         rt2800_bbp_write(rt2x00dev, 66, 0x38);
1577
1578         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1579                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1580                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1581         } else {
1582                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
1583                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
1584         }
1585
1586         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1587
1588         if (rt2x00_rt(rt2x00dev, RT3070) ||
1589             rt2x00_rt(rt2x00dev, RT3071) ||
1590             rt2x00_rt(rt2x00dev, RT3090) ||
1591             rt2x00_rt(rt2x00dev, RT3390)) {
1592                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
1593                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
1594                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
1595         } else if (rt2800_is_305x_soc(rt2x00dev)) {
1596                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1597                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
1598         } else {
1599                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
1600         }
1601
1602         rt2800_bbp_write(rt2x00dev, 82, 0x62);
1603         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1604
1605         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D) ||
1606             rt2x00_rt_rev(rt2x00dev, RT2870, REV_RT2870D))
1607                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1608         else
1609                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1610
1611         rt2800_bbp_write(rt2x00dev, 86, 0x00);
1612         rt2800_bbp_write(rt2x00dev, 91, 0x04);
1613         rt2800_bbp_write(rt2x00dev, 92, 0x00);
1614
1615         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
1616             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
1617             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
1618             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
1619             rt2800_is_305x_soc(rt2x00dev))
1620                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1621         else
1622                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
1623
1624         if (rt2800_is_305x_soc(rt2x00dev))
1625                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
1626         else
1627                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1628         rt2800_bbp_write(rt2x00dev, 106, 0x35);
1629
1630         if (rt2x00_rt(rt2x00dev, RT3071) ||
1631             rt2x00_rt(rt2x00dev, RT3090) ||
1632             rt2x00_rt(rt2x00dev, RT3390)) {
1633                 rt2800_bbp_read(rt2x00dev, 138, &value);
1634
1635                 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1636                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
1637                         value |= 0x20;
1638                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
1639                         value &= ~0x02;
1640
1641                 rt2800_bbp_write(rt2x00dev, 138, value);
1642         }
1643
1644
1645         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1646                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1647
1648                 if (eeprom != 0xffff && eeprom != 0x0000) {
1649                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1650                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1651                         rt2800_bbp_write(rt2x00dev, reg_id, value);
1652                 }
1653         }
1654
1655         return 0;
1656 }
1657 EXPORT_SYMBOL_GPL(rt2800_init_bbp);
1658
1659 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1660                                 bool bw40, u8 rfcsr24, u8 filter_target)
1661 {
1662         unsigned int i;
1663         u8 bbp;
1664         u8 rfcsr;
1665         u8 passband;
1666         u8 stopband;
1667         u8 overtuned = 0;
1668
1669         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1670
1671         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1672         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1673         rt2800_bbp_write(rt2x00dev, 4, bbp);
1674
1675         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1676         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1677         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1678
1679         /*
1680          * Set power & frequency of passband test tone
1681          */
1682         rt2800_bbp_write(rt2x00dev, 24, 0);
1683
1684         for (i = 0; i < 100; i++) {
1685                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1686                 msleep(1);
1687
1688                 rt2800_bbp_read(rt2x00dev, 55, &passband);
1689                 if (passband)
1690                         break;
1691         }
1692
1693         /*
1694          * Set power & frequency of stopband test tone
1695          */
1696         rt2800_bbp_write(rt2x00dev, 24, 0x06);
1697
1698         for (i = 0; i < 100; i++) {
1699                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1700                 msleep(1);
1701
1702                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1703
1704                 if ((passband - stopband) <= filter_target) {
1705                         rfcsr24++;
1706                         overtuned += ((passband - stopband) == filter_target);
1707                 } else
1708                         break;
1709
1710                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1711         }
1712
1713         rfcsr24 -= !!overtuned;
1714
1715         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1716         return rfcsr24;
1717 }
1718
1719 int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1720 {
1721         u8 rfcsr;
1722         u8 bbp;
1723         u32 reg;
1724         u16 eeprom;
1725
1726         if (!rt2x00_rt(rt2x00dev, RT3070) &&
1727             !rt2x00_rt(rt2x00dev, RT3071) &&
1728             !rt2x00_rt(rt2x00dev, RT3090) &&
1729             !rt2x00_rt(rt2x00dev, RT3390) &&
1730             !rt2800_is_305x_soc(rt2x00dev))
1731                 return 0;
1732
1733         /*
1734          * Init RF calibration.
1735          */
1736         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1737         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1738         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1739         msleep(1);
1740         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1741         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1742
1743         if (rt2x00_rt(rt2x00dev, RT3070) ||
1744             rt2x00_rt(rt2x00dev, RT3071) ||
1745             rt2x00_rt(rt2x00dev, RT3090)) {
1746                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1747                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1748                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1749                 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1750                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1751                 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
1752                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1753                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1754                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1755                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1756                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1757                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1758                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1759                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1760                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1761                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1762                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1763                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1764                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1765         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
1766                 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
1767                 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
1768                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
1769                 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
1770                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1771                 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
1772                 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
1773                 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
1774                 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
1775                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1776                 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
1777                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1778                 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
1779                 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
1780                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1781                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1782                 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
1783                 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
1784                 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
1785                 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
1786                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
1787                 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
1788                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1789                 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
1790                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1791                 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1792                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1793                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1794                 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
1795                 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
1796                 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
1797                 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
1798         } else if (rt2800_is_305x_soc(rt2x00dev)) {
1799                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
1800                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
1801                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
1802                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
1803                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1804                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1805                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1806                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
1807                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
1808                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1809                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
1810                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1811                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
1812                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
1813                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1814                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1815                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1816                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1817                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1818                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1819                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1820                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1821                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1822                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
1823                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1824                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1825                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
1826                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
1827                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
1828                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
1829                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
1830                 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
1831                 return 0;
1832         }
1833
1834         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1835                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1836                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
1837                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1838                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
1839         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
1840                    rt2x00_rt(rt2x00dev, RT3090)) {
1841                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1842                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
1843                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1844
1845                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
1846
1847                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1848                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
1849                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1850                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
1851                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1852                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1853                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1854                         else
1855                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
1856                 }
1857                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
1858         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
1859                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1860                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
1861                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1862         }
1863
1864         /*
1865          * Set RX Filter calibration for 20MHz and 40MHz
1866          */
1867         if (rt2x00_rt(rt2x00dev, RT3070)) {
1868                 rt2x00dev->calibration[0] =
1869                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1870                 rt2x00dev->calibration[1] =
1871                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1872         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
1873                    rt2x00_rt(rt2x00dev, RT3090) ||
1874                    rt2x00_rt(rt2x00dev, RT3390)) {
1875                 rt2x00dev->calibration[0] =
1876                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
1877                 rt2x00dev->calibration[1] =
1878                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
1879         }
1880
1881         /*
1882          * Set back to initial state
1883          */
1884         rt2800_bbp_write(rt2x00dev, 24, 0);
1885
1886         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1887         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1888         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1889
1890         /*
1891          * set BBP back to BW20
1892          */
1893         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1894         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1895         rt2800_bbp_write(rt2x00dev, 4, bbp);
1896
1897         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
1898             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1899             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1900             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
1901                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1902
1903         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
1904         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
1905         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
1906
1907         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1908         rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
1909         if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1910             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1911             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
1912                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1913                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1914                         rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
1915         }
1916         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
1917         if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
1918                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
1919                                   rt2x00_get_field16(eeprom,
1920                                                    EEPROM_TXMIXER_GAIN_BG_VAL));
1921         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1922
1923         if (rt2x00_rt(rt2x00dev, RT3090)) {
1924                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
1925
1926                 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1927                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
1928                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
1929                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
1930                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
1931
1932                 rt2800_bbp_write(rt2x00dev, 138, bbp);
1933         }
1934
1935         if (rt2x00_rt(rt2x00dev, RT3071) ||
1936             rt2x00_rt(rt2x00dev, RT3090) ||
1937             rt2x00_rt(rt2x00dev, RT3390)) {
1938                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1939                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1940                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1941                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1942                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1943                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1944                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1945
1946                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
1947                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
1948                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
1949
1950                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
1951                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
1952                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
1953
1954                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
1955                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
1956                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
1957         }
1958
1959         if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
1960                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
1961                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
1962                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
1963                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
1964                 else
1965                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
1966                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
1967                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
1968                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
1969                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
1970         }
1971
1972         return 0;
1973 }
1974 EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
1975
1976 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
1977 {
1978         u32 reg;
1979
1980         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
1981
1982         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
1983 }
1984 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
1985
1986 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
1987 {
1988         u32 reg;
1989
1990         mutex_lock(&rt2x00dev->csr_mutex);
1991
1992         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
1993         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
1994         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
1995         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
1996         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
1997
1998         /* Wait until the EEPROM has been loaded */
1999         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
2000
2001         /* Apparently the data is read from end to start */
2002         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2003                                         (u32 *)&rt2x00dev->eeprom[i]);
2004         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2005                                         (u32 *)&rt2x00dev->eeprom[i + 2]);
2006         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2007                                         (u32 *)&rt2x00dev->eeprom[i + 4]);
2008         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2009                                         (u32 *)&rt2x00dev->eeprom[i + 6]);
2010
2011         mutex_unlock(&rt2x00dev->csr_mutex);
2012 }
2013
2014 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2015 {
2016         unsigned int i;
2017
2018         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
2019                 rt2800_efuse_read(rt2x00dev, i);
2020 }
2021 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2022
2023 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2024 {
2025         u16 word;
2026         u8 *mac;
2027         u8 default_lna_gain;
2028
2029         /*
2030          * Start validation of the data that has been read.
2031          */
2032         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2033         if (!is_valid_ether_addr(mac)) {
2034                 random_ether_addr(mac);
2035                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2036         }
2037
2038         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2039         if (word == 0xffff) {
2040                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2041                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2042                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2043                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2044                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2045         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
2046                    rt2x00_rt(rt2x00dev, RT2870) ||
2047                    rt2x00_rt(rt2x00dev, RT2872)) {
2048                 /*
2049                  * There is a max of 2 RX streams for RT28x0 series
2050                  */
2051                 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2052                         rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2053                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2054         }
2055
2056         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2057         if (word == 0xffff) {
2058                 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2059                 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2060                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2061                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2062                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2063                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2064                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2065                 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2066                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2067                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2068                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2069                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2070         }
2071
2072         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2073         if ((word & 0x00ff) == 0x00ff) {
2074                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2075                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2076                                    LED_MODE_TXRX_ACTIVITY);
2077                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2078                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2079                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2080                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2081                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2082                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2083         }
2084
2085         /*
2086          * During the LNA validation we are going to use
2087          * lna0 as correct value. Note that EEPROM_LNA
2088          * is never validated.
2089          */
2090         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2091         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2092
2093         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2094         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2095                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2096         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2097                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2098         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2099
2100         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2101         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2102                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2103         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2104             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2105                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2106                                    default_lna_gain);
2107         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2108
2109         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2110         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2111                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2112         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2113                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2114         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2115
2116         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2117         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2118                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2119         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2120             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2121                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2122                                    default_lna_gain);
2123         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2124
2125         return 0;
2126 }
2127 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2128
2129 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2130 {
2131         u32 reg;
2132         u16 value;
2133         u16 eeprom;
2134
2135         /*
2136          * Read EEPROM word for configuration.
2137          */
2138         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2139
2140         /*
2141          * Identify RF chipset.
2142          */
2143         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2144         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2145
2146         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2147                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2148
2149         if (!rt2x00_rt(rt2x00dev, RT2860) &&
2150             !rt2x00_rt(rt2x00dev, RT2870) &&
2151             !rt2x00_rt(rt2x00dev, RT2872) &&
2152             !rt2x00_rt(rt2x00dev, RT2883) &&
2153             !rt2x00_rt(rt2x00dev, RT3070) &&
2154             !rt2x00_rt(rt2x00dev, RT3071) &&
2155             !rt2x00_rt(rt2x00dev, RT3090) &&
2156             !rt2x00_rt(rt2x00dev, RT3390) &&
2157             !rt2x00_rt(rt2x00dev, RT3572)) {
2158                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2159                 return -ENODEV;
2160         }
2161
2162         if (!rt2x00_rf(rt2x00dev, RF2820) &&
2163             !rt2x00_rf(rt2x00dev, RF2850) &&
2164             !rt2x00_rf(rt2x00dev, RF2720) &&
2165             !rt2x00_rf(rt2x00dev, RF2750) &&
2166             !rt2x00_rf(rt2x00dev, RF3020) &&
2167             !rt2x00_rf(rt2x00dev, RF2020) &&
2168             !rt2x00_rf(rt2x00dev, RF3021) &&
2169             !rt2x00_rf(rt2x00dev, RF3022) &&
2170             !rt2x00_rf(rt2x00dev, RF3052)) {
2171                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2172                 return -ENODEV;
2173         }
2174
2175         /*
2176          * Identify default antenna configuration.
2177          */
2178         rt2x00dev->default_ant.tx =
2179             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2180         rt2x00dev->default_ant.rx =
2181             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2182
2183         /*
2184          * Read frequency offset and RF programming sequence.
2185          */
2186         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2187         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2188
2189         /*
2190          * Read external LNA informations.
2191          */
2192         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2193
2194         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2195                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2196         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2197                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2198
2199         /*
2200          * Detect if this device has an hardware controlled radio.
2201          */
2202         if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2203                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2204
2205         /*
2206          * Store led settings, for correct led behaviour.
2207          */
2208 #ifdef CONFIG_RT2X00_LIB_LEDS
2209         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2210         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2211         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2212
2213         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2214 #endif /* CONFIG_RT2X00_LIB_LEDS */
2215
2216         return 0;
2217 }
2218 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
2219
2220 /*
2221  * RF value list for rt28x0
2222  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2223  */
2224 static const struct rf_channel rf_vals[] = {
2225         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2226         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2227         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2228         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2229         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2230         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2231         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2232         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2233         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2234         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2235         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2236         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2237         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2238         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2239
2240         /* 802.11 UNI / HyperLan 2 */
2241         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2242         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2243         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2244         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2245         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2246         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2247         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2248         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2249         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2250         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2251         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2252         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2253
2254         /* 802.11 HyperLan 2 */
2255         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2256         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2257         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2258         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2259         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2260         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2261         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2262         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2263         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2264         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2265         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2266         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2267         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2268         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2269         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2270         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2271
2272         /* 802.11 UNII */
2273         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2274         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2275         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2276         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2277         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2278         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2279         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2280         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2281         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2282         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2283         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2284
2285         /* 802.11 Japan */
2286         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2287         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2288         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2289         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2290         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2291         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2292         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2293 };
2294
2295 /*
2296  * RF value list for rt3070
2297  * Supports: 2.4 GHz
2298  */
2299 static const struct rf_channel rf_vals_302x[] = {
2300         {1,  241, 2, 2 },
2301         {2,  241, 2, 7 },
2302         {3,  242, 2, 2 },
2303         {4,  242, 2, 7 },
2304         {5,  243, 2, 2 },
2305         {6,  243, 2, 7 },
2306         {7,  244, 2, 2 },
2307         {8,  244, 2, 7 },
2308         {9,  245, 2, 2 },
2309         {10, 245, 2, 7 },
2310         {11, 246, 2, 2 },
2311         {12, 246, 2, 7 },
2312         {13, 247, 2, 2 },
2313         {14, 248, 2, 4 },
2314 };
2315
2316 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2317 {
2318         struct hw_mode_spec *spec = &rt2x00dev->spec;
2319         struct channel_info *info;
2320         char *tx_power1;
2321         char *tx_power2;
2322         unsigned int i;
2323         u16 eeprom;
2324
2325         /*
2326          * Disable powersaving as default on PCI devices.
2327          */
2328         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
2329                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2330
2331         /*
2332          * Initialize all hw fields.
2333          */
2334         rt2x00dev->hw->flags =
2335             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2336             IEEE80211_HW_SIGNAL_DBM |
2337             IEEE80211_HW_SUPPORTS_PS |
2338             IEEE80211_HW_PS_NULLFUNC_STACK;
2339
2340         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2341         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2342                                 rt2x00_eeprom_addr(rt2x00dev,
2343                                                    EEPROM_MAC_ADDR_0));
2344
2345         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2346
2347         /*
2348          * Initialize hw_mode information.
2349          */
2350         spec->supported_bands = SUPPORT_BAND_2GHZ;
2351         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2352
2353         if (rt2x00_rf(rt2x00dev, RF2820) ||
2354             rt2x00_rf(rt2x00dev, RF2720) ||
2355             rt2x00_rf(rt2x00dev, RF3052)) {
2356                 spec->num_channels = 14;
2357                 spec->channels = rf_vals;
2358         } else if (rt2x00_rf(rt2x00dev, RF2850) || rt2x00_rf(rt2x00dev, RF2750)) {
2359                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2360                 spec->num_channels = ARRAY_SIZE(rf_vals);
2361                 spec->channels = rf_vals;
2362         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
2363                    rt2x00_rf(rt2x00dev, RF2020) ||
2364                    rt2x00_rf(rt2x00dev, RF3021) ||
2365                    rt2x00_rf(rt2x00dev, RF3022)) {
2366                 spec->num_channels = ARRAY_SIZE(rf_vals_302x);
2367                 spec->channels = rf_vals_302x;
2368         }
2369
2370         /*
2371          * Initialize HT information.
2372          */
2373         if (!rt2x00_rf(rt2x00dev, RF2020))
2374                 spec->ht.ht_supported = true;
2375         else
2376                 spec->ht.ht_supported = false;
2377
2378         /*
2379          * Don't set IEEE80211_HT_CAP_SUP_WIDTH_20_40 for now as it causes
2380          * reception problems with HT40 capable 11n APs
2381          */
2382         spec->ht.cap =
2383             IEEE80211_HT_CAP_GRN_FLD |
2384             IEEE80211_HT_CAP_SGI_20 |
2385             IEEE80211_HT_CAP_SGI_40 |
2386             IEEE80211_HT_CAP_TX_STBC |
2387             IEEE80211_HT_CAP_RX_STBC;
2388         spec->ht.ampdu_factor = 3;
2389         spec->ht.ampdu_density = 4;
2390         spec->ht.mcs.tx_params =
2391             IEEE80211_HT_MCS_TX_DEFINED |
2392             IEEE80211_HT_MCS_TX_RX_DIFF |
2393             ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2394                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2395
2396         switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2397         case 3:
2398                 spec->ht.mcs.rx_mask[2] = 0xff;
2399         case 2:
2400                 spec->ht.mcs.rx_mask[1] = 0xff;
2401         case 1:
2402                 spec->ht.mcs.rx_mask[0] = 0xff;
2403                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2404                 break;
2405         }
2406
2407         /*
2408          * Create channel information array
2409          */
2410         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2411         if (!info)
2412                 return -ENOMEM;
2413
2414         spec->channels_info = info;
2415
2416         tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2417         tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2418
2419         for (i = 0; i < 14; i++) {
2420                 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2421                 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2422         }
2423
2424         if (spec->num_channels > 14) {
2425                 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2426                 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2427
2428                 for (i = 14; i < spec->num_channels; i++) {
2429                         info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2430                         info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2431                 }
2432         }
2433
2434         return 0;
2435 }
2436 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
2437
2438 /*
2439  * IEEE80211 stack callback functions.
2440  */
2441 static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2442                                 u32 *iv32, u16 *iv16)
2443 {
2444         struct rt2x00_dev *rt2x00dev = hw->priv;
2445         struct mac_iveiv_entry iveiv_entry;
2446         u32 offset;
2447
2448         offset = MAC_IVEIV_ENTRY(hw_key_idx);
2449         rt2800_register_multiread(rt2x00dev, offset,
2450                                       &iveiv_entry, sizeof(iveiv_entry));
2451
2452         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
2453         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2454 }
2455
2456 static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2457 {
2458         struct rt2x00_dev *rt2x00dev = hw->priv;
2459         u32 reg;
2460         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2461
2462         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2463         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2464         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2465
2466         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2467         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2468         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2469
2470         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2471         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2472         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2473
2474         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2475         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2476         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2477
2478         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2479         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2480         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2481
2482         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2483         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2484         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2485
2486         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2487         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2488         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2489
2490         return 0;
2491 }
2492
2493 static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2494                           const struct ieee80211_tx_queue_params *params)
2495 {
2496         struct rt2x00_dev *rt2x00dev = hw->priv;
2497         struct data_queue *queue;
2498         struct rt2x00_field32 field;
2499         int retval;
2500         u32 reg;
2501         u32 offset;
2502
2503         /*
2504          * First pass the configuration through rt2x00lib, that will
2505          * update the queue settings and validate the input. After that
2506          * we are free to update the registers based on the value
2507          * in the queue parameter.
2508          */
2509         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2510         if (retval)
2511                 return retval;
2512
2513         /*
2514          * We only need to perform additional register initialization
2515          * for WMM queues/
2516          */
2517         if (queue_idx >= 4)
2518                 return 0;
2519
2520         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2521
2522         /* Update WMM TXOP register */
2523         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2524         field.bit_offset = (queue_idx & 1) * 16;
2525         field.bit_mask = 0xffff << field.bit_offset;
2526
2527         rt2800_register_read(rt2x00dev, offset, &reg);
2528         rt2x00_set_field32(&reg, field, queue->txop);
2529         rt2800_register_write(rt2x00dev, offset, reg);
2530
2531         /* Update WMM registers */
2532         field.bit_offset = queue_idx * 4;
2533         field.bit_mask = 0xf << field.bit_offset;
2534
2535         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2536         rt2x00_set_field32(&reg, field, queue->aifs);
2537         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2538
2539         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2540         rt2x00_set_field32(&reg, field, queue->cw_min);
2541         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2542
2543         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2544         rt2x00_set_field32(&reg, field, queue->cw_max);
2545         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2546
2547         /* Update EDCA registers */
2548         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2549
2550         rt2800_register_read(rt2x00dev, offset, &reg);
2551         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2552         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2553         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2554         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2555         rt2800_register_write(rt2x00dev, offset, reg);
2556
2557         return 0;
2558 }
2559
2560 static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2561 {
2562         struct rt2x00_dev *rt2x00dev = hw->priv;
2563         u64 tsf;
2564         u32 reg;
2565
2566         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2567         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2568         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2569         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2570
2571         return tsf;
2572 }
2573
2574 const struct ieee80211_ops rt2800_mac80211_ops = {
2575         .tx                     = rt2x00mac_tx,
2576         .start                  = rt2x00mac_start,
2577         .stop                   = rt2x00mac_stop,
2578         .add_interface          = rt2x00mac_add_interface,
2579         .remove_interface       = rt2x00mac_remove_interface,
2580         .config                 = rt2x00mac_config,
2581         .configure_filter       = rt2x00mac_configure_filter,
2582         .set_tim                = rt2x00mac_set_tim,
2583         .set_key                = rt2x00mac_set_key,
2584         .get_stats              = rt2x00mac_get_stats,
2585         .get_tkip_seq           = rt2800_get_tkip_seq,
2586         .set_rts_threshold      = rt2800_set_rts_threshold,
2587         .bss_info_changed       = rt2x00mac_bss_info_changed,
2588         .conf_tx                = rt2800_conf_tx,
2589         .get_tsf                = rt2800_get_tsf,
2590         .rfkill_poll            = rt2x00mac_rfkill_poll,
2591 };
2592 EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);