SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/rt2x00/rt2500pci.c

   1 /*
   2         Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2500pci
  23         Abstract: rt2500pci device specific routines.
  24         Supported chipsets: RT2560.
  25  */
  26
  27 /*
  28  * Set enviroment defines for rt2x00.h
  29  */
  30 #define DRV_NAME "rt2500pci"
  31
  32 #include <linux/delay.h>
  33 #include <linux/etherdevice.h>
  34 #include <linux/init.h>
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/pci.h>
  38 #include <linux/eeprom_93cx6.h>
  39
  40 #include "rt2x00.h"
  41 #include "rt2x00pci.h"
  42 #include "rt2500pci.h"
  43
  44 /*
  45  * Register access.
  46  * All access to the CSR registers will go through the methods
  47  * rt2x00pci_register_read and rt2x00pci_register_write.
  48  * BBP and RF register require indirect register access,
  49  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  50  * These indirect registers work with busy bits,
  51  * and we will try maximal REGISTER_BUSY_COUNT times to access
  52  * the register while taking a REGISTER_BUSY_DELAY us delay
  53  * between each attampt. When the busy bit is still set at that time,
  54  * the access attempt is considered to have failed,
  55  * and we will print an error.
  56  */
  57 static u32 rt2500pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
  58 {
  59         u32 reg;
  60         unsigned int i;
  61
  62         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  63                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  64                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  65                         break;
  66                 udelay(REGISTER_BUSY_DELAY);
  67         }
  68
  69         return reg;
  70 }
  71
  72 static void rt2500pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
  73                                 const unsigned int word, const u8 value)
  74 {
  75         u32 reg;
  76
  77         /*
  78          * Wait until the BBP becomes ready.
  79          */
  80         reg = rt2500pci_bbp_check(rt2x00dev);
  81         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  82                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  83                 return;
  84         }
  85
  86         /*
  87          * Write the data into the BBP.
  88          */
  89         reg = 0;
  90         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  91         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  92         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  93         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  94
  95         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  96 }
  97
  98 static void rt2500pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
  99                                const unsigned int word, u8 *value)
 100 {
 101         u32 reg;
 102
 103         /*
 104          * Wait until the BBP becomes ready.
 105          */
 106         reg = rt2500pci_bbp_check(rt2x00dev);
 107         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 108                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 109                 return;
 110         }
 111
 112         /*
 113          * Write the request into the BBP.
 114          */
 115         reg = 0;
 116         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 117         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 118         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 119
 120         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 121
 122         /*
 123          * Wait until the BBP becomes ready.
 124          */
 125         reg = rt2500pci_bbp_check(rt2x00dev);
 126         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 127                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 128                 *value = 0xff;
 129                 return;
 130         }
 131
 132         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 133 }
 134
 135 static void rt2500pci_rf_write(const struct rt2x00_dev *rt2x00dev,
 136                                const unsigned int word, const u32 value)
 137 {
 138         u32 reg;
 139         unsigned int i;
 140
 141         if (!word)
 142                 return;
 143
 144         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 145                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
 146                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
 147                         goto rf_write;
 148                 udelay(REGISTER_BUSY_DELAY);
 149         }
 150
 151         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
 152         return;
 153
 154 rf_write:
 155         reg = 0;
 156         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 157         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 158         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 159         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 160
 161         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 162         rt2x00_rf_write(rt2x00dev, word, value);
 163 }
 164
 165 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 166 {
 167         struct rt2x00_dev *rt2x00dev = eeprom->data;
 168         u32 reg;
 169
 170         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 171
 172         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 173         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 174         eeprom->reg_data_clock =
 175             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 176         eeprom->reg_chip_select =
 177             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 178 }
 179
 180 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 181 {
 182         struct rt2x00_dev *rt2x00dev = eeprom->data;
 183         u32 reg = 0;
 184
 185         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 186         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 187         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 188                            !!eeprom->reg_data_clock);
 189         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 190                            !!eeprom->reg_chip_select);
 191
 192         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 193 }
 194
 195 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 196 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 197
 198 static void rt2500pci_read_csr(const struct rt2x00_dev *rt2x00dev,
 199                                const unsigned int word, u32 *data)
 200 {
 201         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 202 }
 203
 204 static void rt2500pci_write_csr(const struct rt2x00_dev *rt2x00dev,
 205                                 const unsigned int word, u32 data)
 206 {
 207         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 208 }
 209
 210 static const struct rt2x00debug rt2500pci_rt2x00debug = {
 211         .owner  = THIS_MODULE,
 212         .csr    = {
 213                 .read           = rt2500pci_read_csr,
 214                 .write          = rt2500pci_write_csr,
 215                 .word_size      = sizeof(u32),
 216                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 217         },
 218         .eeprom = {
 219                 .read           = rt2x00_eeprom_read,
 220                 .write          = rt2x00_eeprom_write,
 221                 .word_size      = sizeof(u16),
 222                 .word_count     = EEPROM_SIZE / sizeof(u16),
 223         },
 224         .bbp    = {
 225                 .read           = rt2500pci_bbp_read,
 226                 .write          = rt2500pci_bbp_write,
 227                 .word_size      = sizeof(u8),
 228                 .word_count     = BBP_SIZE / sizeof(u8),
 229         },
 230         .rf     = {
 231                 .read           = rt2x00_rf_read,
 232                 .write          = rt2500pci_rf_write,
 233                 .word_size      = sizeof(u32),
 234                 .word_count     = RF_SIZE / sizeof(u32),
 235         },
 236 };
 237 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 238
 239 #ifdef CONFIG_RT2500PCI_RFKILL
 240 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 241 {
 242         u32 reg;
 243
 244         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 245         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 246 }
 247 #else
 248 #define rt2500pci_rfkill_poll   NULL
 249 #endif /* CONFIG_RT2500PCI_RFKILL */
 250
 251 /*
 252  * Configuration handlers.
 253  */
 254 static void rt2500pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
 255                                       __le32 *mac)
 256 {
 257         rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac,
 258                                       (2 * sizeof(__le32)));
 259 }
 260
 261 static void rt2500pci_config_bssid(struct rt2x00_dev *rt2x00dev,
 262                                    __le32 *bssid)
 263 {
 264         rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid,
 265                                       (2 * sizeof(__le32)));
 266 }
 267
 268 static void rt2500pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
 269                                   const int tsf_sync)
 270 {
 271         u32 reg;
 272
 273         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 274
 275         /*
 276          * Enable beacon config
 277          */
 278         rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 279         rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
 280                            PREAMBLE + get_duration(IEEE80211_HEADER, 2));
 281         rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN,
 282                            rt2x00lib_get_ring(rt2x00dev,
 283                                               IEEE80211_TX_QUEUE_BEACON)
 284                            ->tx_params.cw_min);
 285         rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 286
 287         /*
 288          * Enable synchronisation.
 289          */
 290         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 291         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 292         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 293         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 294         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, tsf_sync);
 295         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 296 }
 297
 298 static void rt2500pci_config_rate(struct rt2x00_dev *rt2x00dev, const int rate)
 299 {
 300         struct ieee80211_conf *conf = &rt2x00dev->hw->conf;
 301         u32 reg;
 302         u32 preamble;
 303         u16 value;
 304
 305         if (DEVICE_GET_RATE_FIELD(rate, PREAMBLE))
 306                 preamble = SHORT_PREAMBLE;
 307         else
 308                 preamble = PREAMBLE;
 309
 310         reg = DEVICE_GET_RATE_FIELD(rate, RATEMASK) & DEV_BASIC_RATEMASK;
 311         rt2x00pci_register_write(rt2x00dev, ARCSR1, reg);
 312
 313         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 314         value = ((conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) ?
 315                  SHORT_DIFS : DIFS) +
 316             PLCP + preamble + get_duration(ACK_SIZE, 10);
 317         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, value);
 318         value = SIFS + PLCP + preamble + get_duration(ACK_SIZE, 10);
 319         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, value);
 320         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 321
 322         preamble = DEVICE_GET_RATE_FIELD(rate, PREAMBLE) ? 0x08 : 0x00;
 323
 324         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 325         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble);
 326         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 327         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
 328         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 329
 330         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 331         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble);
 332         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 333         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
 334         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 335
 336         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 337         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble);
 338         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 339         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
 340         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 341
 342         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 343         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble);
 344         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 345         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
 346         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 347 }
 348
 349 static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 350                                      const int phymode)
 351 {
 352         struct ieee80211_hw_mode *mode;
 353         struct ieee80211_rate *rate;
 354
 355         if (phymode == MODE_IEEE80211A)
 356                 rt2x00dev->curr_hwmode = HWMODE_A;
 357         else if (phymode == MODE_IEEE80211B)
 358                 rt2x00dev->curr_hwmode = HWMODE_B;
 359         else
 360                 rt2x00dev->curr_hwmode = HWMODE_G;
 361
 362         mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode];
 363         rate = &mode->rates[mode->num_rates - 1];
 364
 365         rt2500pci_config_rate(rt2x00dev, rate->val2);
 366 }
 367
 368 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
 369                                      const int index, const int channel,
 370                                      const int txpower)
 371 {
 372         struct rf_channel reg;
 373         u8 r70;
 374
 375         /*
 376          * Fill rf_reg structure.
 377          */
 378         memcpy(&reg, &rt2x00dev->spec.channels[index], sizeof(reg));
 379
 380         /*
 381          * Set TXpower.
 382          */
 383         rt2x00_set_field32(&reg.rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 384
 385         /*
 386          * Switch on tuning bits.
 387          * For RT2523 devices we do not need to update the R1 register.
 388          */
 389         if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
 390                 rt2x00_set_field32(&reg.rf1, RF1_TUNER, 1);
 391         rt2x00_set_field32(&reg.rf3, RF3_TUNER, 1);
 392
 393         /*
 394          * For RT2525 we should first set the channel to half band higher.
 395          */
 396         if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
 397                 static const u32 vals[] = {
 398                         0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
 399                         0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
 400                         0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
 401                         0x00080d2e, 0x00080d3a
 402                 };
 403
 404                 rt2500pci_rf_write(rt2x00dev, 1, reg.rf1);
 405                 rt2500pci_rf_write(rt2x00dev, 2, vals[channel - 1]);
 406                 rt2500pci_rf_write(rt2x00dev, 3, reg.rf3);
 407                 if (reg.rf4)
 408                         rt2500pci_rf_write(rt2x00dev, 4, reg.rf4);
 409         }
 410
 411         rt2500pci_rf_write(rt2x00dev, 1, reg.rf1);
 412         rt2500pci_rf_write(rt2x00dev, 2, reg.rf2);
 413         rt2500pci_rf_write(rt2x00dev, 3, reg.rf3);
 414         if (reg.rf4)
 415                 rt2500pci_rf_write(rt2x00dev, 4, reg.rf4);
 416
 417         /*
 418          * Channel 14 requires the Japan filter bit to be set.
 419          */
 420         r70 = 0x46;
 421         rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, channel == 14);
 422         rt2500pci_bbp_write(rt2x00dev, 70, r70);
 423
 424         msleep(1);
 425
 426         /*
 427          * Switch off tuning bits.
 428          * For RT2523 devices we do not need to update the R1 register.
 429          */
 430         if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
 431                 rt2x00_set_field32(&reg.rf1, RF1_TUNER, 0);
 432                 rt2500pci_rf_write(rt2x00dev, 1, reg.rf1);
 433         }
 434
 435         rt2x00_set_field32(&reg.rf3, RF3_TUNER, 0);
 436         rt2500pci_rf_write(rt2x00dev, 3, reg.rf3);
 437
 438         /*
 439          * Clear false CRC during channel switch.
 440          */
 441         rt2x00pci_register_read(rt2x00dev, CNT0, &reg.rf1);
 442 }
 443
 444 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 445                                      const int txpower)
 446 {
 447         u32 rf3;
 448
 449         rt2x00_rf_read(rt2x00dev, 3, &rf3);
 450         rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 451         rt2500pci_rf_write(rt2x00dev, 3, rf3);
 452 }
 453
 454 static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 455                                      const int antenna_tx, const int antenna_rx)
 456 {
 457         u32 reg;
 458         u8 r14;
 459         u8 r2;
 460
 461         rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
 462         rt2500pci_bbp_read(rt2x00dev, 14, &r14);
 463         rt2500pci_bbp_read(rt2x00dev, 2, &r2);
 464
 465         /*
 466          * Configure the TX antenna.
 467          */
 468         switch (antenna_tx) {
 469         case ANTENNA_SW_DIVERSITY:
 470         case ANTENNA_HW_DIVERSITY:
 471                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
 472                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
 473                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
 474                 break;
 475         case ANTENNA_A:
 476                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
 477                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
 478                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
 479                 break;
 480         case ANTENNA_B:
 481                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
 482                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
 483                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
 484                 break;
 485         }
 486
 487         /*
 488          * Configure the RX antenna.
 489          */
 490         switch (antenna_rx) {
 491         case ANTENNA_SW_DIVERSITY:
 492         case ANTENNA_HW_DIVERSITY:
 493                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
 494                 break;
 495         case ANTENNA_A:
 496                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
 497                 break;
 498         case ANTENNA_B:
 499                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
 500                 break;
 501         }
 502
 503         /*
 504          * RT2525E and RT5222 need to flip TX I/Q
 505          */
 506         if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
 507             rt2x00_rf(&rt2x00dev->chip, RF5222)) {
 508                 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
 509                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
 510                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
 511
 512                 /*
 513                  * RT2525E does not need RX I/Q Flip.
 514                  */
 515                 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
 516                         rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
 517         } else {
 518                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
 519                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
 520         }
 521
 522         rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
 523         rt2500pci_bbp_write(rt2x00dev, 14, r14);
 524         rt2500pci_bbp_write(rt2x00dev, 2, r2);
 525 }
 526
 527 static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
 528                                       const int short_slot_time,
 529                                       const int beacon_int)
 530 {
 531         u32 reg;
 532
 533         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 534         rt2x00_set_field32(&reg, CSR11_SLOT_TIME,
 535                            short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME);
 536         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 537
 538         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 539         rt2x00_set_field32(&reg, CSR18_SIFS, SIFS);
 540         rt2x00_set_field32(&reg, CSR18_PIFS,
 541                            short_slot_time ? SHORT_PIFS : PIFS);
 542         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 543
 544         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 545         rt2x00_set_field32(&reg, CSR19_DIFS,
 546                            short_slot_time ? SHORT_DIFS : DIFS);
 547         rt2x00_set_field32(&reg, CSR19_EIFS, EIFS);
 548         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 549
 550         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 551         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 552         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 553         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 554
 555         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 556         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, beacon_int * 16);
 557         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, beacon_int * 16);
 558         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 559 }
 560
 561 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
 562                              const unsigned int flags,
 563                              struct ieee80211_conf *conf)
 564 {
 565         int short_slot_time = conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME;
 566
 567         if (flags & CONFIG_UPDATE_PHYMODE)
 568                 rt2500pci_config_phymode(rt2x00dev, conf->phymode);
 569         if (flags & CONFIG_UPDATE_CHANNEL)
 570                 rt2500pci_config_channel(rt2x00dev, conf->channel_val,
 571                                          conf->channel, conf->power_level);
 572         if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
 573                 rt2500pci_config_txpower(rt2x00dev, conf->power_level);
 574         if (flags & CONFIG_UPDATE_ANTENNA)
 575                 rt2500pci_config_antenna(rt2x00dev, conf->antenna_sel_tx,
 576                                          conf->antenna_sel_rx);
 577         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 578                 rt2500pci_config_duration(rt2x00dev, short_slot_time,
 579                                           conf->beacon_int);
 580 }
 581
 582 /*
 583  * LED functions.
 584  */
 585 static void rt2500pci_enable_led(struct rt2x00_dev *rt2x00dev)
 586 {
 587         u32 reg;
 588
 589         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 590
 591         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
 592         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
 593
 594         if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
 595                 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
 596                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
 597         } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
 598                 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
 599                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
 600         } else {
 601                 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
 602                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
 603         }
 604
 605         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 606 }
 607
 608 static void rt2500pci_disable_led(struct rt2x00_dev *rt2x00dev)
 609 {
 610         u32 reg;
 611
 612         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 613         rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
 614         rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
 615         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 616 }
 617
 618 /*
 619  * Link tuning
 620  */
 621 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev)
 622 {
 623         u32 reg;
 624
 625         /*
 626          * Update FCS error count from register.
 627          */
 628         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 629         rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 630
 631         /*
 632          * Update False CCA count from register.
 633          */
 634         rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
 635         rt2x00dev->link.false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
 636 }
 637
 638 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 639 {
 640         rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
 641         rt2x00dev->link.vgc_level = 0x48;
 642 }
 643
 644 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 645 {
 646         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
 647         u8 r17;
 648
 649         /*
 650          * To prevent collisions with MAC ASIC on chipsets
 651          * up to version C the link tuning should halt after 20
 652          * seconds.
 653          */
 654         if (rt2x00_get_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
 655             rt2x00dev->link.count > 20)
 656                 return;
 657
 658         rt2500pci_bbp_read(rt2x00dev, 17, &r17);
 659
 660         /*
 661          * Chipset versions C and lower should directly continue
 662          * to the dynamic CCA tuning.
 663          */
 664         if (rt2x00_get_rev(&rt2x00dev->chip) < RT2560_VERSION_D)
 665                 goto dynamic_cca_tune;
 666
 667         /*
 668          * A too low RSSI will cause too much false CCA which will
 669          * then corrupt the R17 tuning. To remidy this the tuning should
 670          * be stopped (While making sure the R17 value will not exceed limits)
 671          */
 672         if (rssi < -80 && rt2x00dev->link.count > 20) {
 673                 if (r17 >= 0x41) {
 674                         r17 = rt2x00dev->link.vgc_level;
 675                         rt2500pci_bbp_write(rt2x00dev, 17, r17);
 676                 }
 677                 return;
 678         }
 679
 680         /*
 681          * Special big-R17 for short distance
 682          */
 683         if (rssi >= -58) {
 684                 if (r17 != 0x50)
 685                         rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
 686                 return;
 687         }
 688
 689         /*
 690          * Special mid-R17 for middle distance
 691          */
 692         if (rssi >= -74) {
 693                 if (r17 != 0x41)
 694                         rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
 695                 return;
 696         }
 697
 698         /*
 699          * Leave short or middle distance condition, restore r17
 700          * to the dynamic tuning range.
 701          */
 702         if (r17 >= 0x41) {
 703                 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
 704                 return;
 705         }
 706
 707 dynamic_cca_tune:
 708
 709         /*
 710          * R17 is inside the dynamic tuning range,
 711          * start tuning the link based on the false cca counter.
 712          */
 713         if (rt2x00dev->link.false_cca > 512 && r17 < 0x40) {
 714                 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
 715                 rt2x00dev->link.vgc_level = r17;
 716         } else if (rt2x00dev->link.false_cca < 100 && r17 > 0x32) {
 717                 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
 718                 rt2x00dev->link.vgc_level = r17;
 719         }
 720 }
 721
 722 /*
 723  * Initialization functions.
 724  */
 725 static void rt2500pci_init_rxring(struct rt2x00_dev *rt2x00dev)
 726 {
 727         struct data_ring *ring = rt2x00dev->rx;
 728         struct data_desc *rxd;
 729         unsigned int i;
 730         u32 word;
 731
 732         memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
 733
 734         for (i = 0; i < ring->stats.limit; i++) {
 735                 rxd = ring->entry[i].priv;
 736
 737                 rt2x00_desc_read(rxd, 1, &word);
 738                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
 739                                    ring->entry[i].data_dma);
 740                 rt2x00_desc_write(rxd, 1, word);
 741
 742                 rt2x00_desc_read(rxd, 0, &word);
 743                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 744                 rt2x00_desc_write(rxd, 0, word);
 745         }
 746
 747         rt2x00_ring_index_clear(rt2x00dev->rx);
 748 }
 749
 750 static void rt2500pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
 751 {
 752         struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
 753         struct data_desc *txd;
 754         unsigned int i;
 755         u32 word;
 756
 757         memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
 758
 759         for (i = 0; i < ring->stats.limit; i++) {
 760                 txd = ring->entry[i].priv;
 761
 762                 rt2x00_desc_read(txd, 1, &word);
 763                 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
 764                                    ring->entry[i].data_dma);
 765                 rt2x00_desc_write(txd, 1, word);
 766
 767                 rt2x00_desc_read(txd, 0, &word);
 768                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 769                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 770                 rt2x00_desc_write(txd, 0, word);
 771         }
 772
 773         rt2x00_ring_index_clear(ring);
 774 }
 775
 776 static int rt2500pci_init_rings(struct rt2x00_dev *rt2x00dev)
 777 {
 778         u32 reg;
 779
 780         /*
 781          * Initialize rings.
 782          */
 783         rt2500pci_init_rxring(rt2x00dev);
 784         rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
 785         rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
 786         rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
 787         rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
 788
 789         /*
 790          * Initialize registers.
 791          */
 792         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 793         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
 794                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
 795         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
 796                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
 797         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
 798                            rt2x00dev->bcn[1].stats.limit);
 799         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
 800                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
 801         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 802
 803         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 804         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 805                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
 806         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 807
 808         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 809         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 810                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
 811         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 812
 813         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 814         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 815                            rt2x00dev->bcn[1].data_dma);
 816         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 817
 818         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 819         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 820                            rt2x00dev->bcn[0].data_dma);
 821         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 822
 823         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 824         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 825         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
 826         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 827
 828         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 829         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 830                            rt2x00dev->rx->data_dma);
 831         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 832
 833         return 0;
 834 }
 835
 836 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
 837 {
 838         u32 reg;
 839
 840         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 841         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 842         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
 843         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 844
 845         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 846         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 847         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 848         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 849         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 850
 851         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 852         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 853                            rt2x00dev->rx->data_size / 128);
 854         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 855
 856         /*
 857          * Always use CWmin and CWmax set in descriptor.
 858          */
 859         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 860         rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
 861         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 862
 863         rt2x00pci_register_write(rt2x00dev, CNT3, 0);
 864
 865         rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
 866         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
 867         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
 868         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
 869         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
 870         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
 871         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
 872         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
 873         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
 874         rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
 875
 876         rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
 877         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
 878         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
 879         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
 880         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
 881         rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
 882
 883         rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
 884         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
 885         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
 886         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
 887         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
 888         rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
 889
 890         rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
 891         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
 892         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
 893         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
 894         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
 895         rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
 896
 897         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 898         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
 899         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 900         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
 901         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 902         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
 903         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 904         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
 905         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
 906         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 907
 908         rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
 909         rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
 910         rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
 911         rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
 912         rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
 913         rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
 914         rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
 915         rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
 916         rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
 917
 918         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 919
 920         rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
 921         rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
 922
 923         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 924                 return -EBUSY;
 925
 926         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
 927         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 928
 929         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 930         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 931         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 932
 933         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 934         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 935         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
 936         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
 937         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 938         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
 939         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
 940         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 941
 942         rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
 943
 944         rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
 945
 946         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 947         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 948         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 949         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 950         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 951
 952         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 953         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 954         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 955         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 956
 957         /*
 958          * We must clear the FCS and FIFO error count.
 959          * These registers are cleared on read,
 960          * so we may pass a useless variable to store the value.
 961          */
 962         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 963         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 964
 965         return 0;
 966 }
 967
 968 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 969 {
 970         unsigned int i;
 971         u16 eeprom;
 972         u8 reg_id;
 973         u8 value;
 974
 975         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 976                 rt2500pci_bbp_read(rt2x00dev, 0, &value);
 977                 if ((value != 0xff) && (value != 0x00))
 978                         goto continue_csr_init;
 979                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
 980                 udelay(REGISTER_BUSY_DELAY);
 981         }
 982
 983         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 984         return -EACCES;
 985
 986 continue_csr_init:
 987         rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
 988         rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
 989         rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
 990         rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
 991         rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
 992         rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
 993         rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
 994         rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
 995         rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
 996         rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
 997         rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
 998         rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
 999         rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
1000         rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
1001         rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
1002         rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
1003         rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
1004         rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
1005         rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
1006         rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
1007         rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
1008         rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
1009         rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
1010         rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
1011         rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
1012         rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1013         rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1014         rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1015         rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1016         rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1017
1018         DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1019         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1020                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1021
1022                 if (eeprom != 0xffff && eeprom != 0x0000) {
1023                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1024                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1025                         DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1026                               reg_id, value);
1027                         rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1028                 }
1029         }
1030         DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1031
1032         return 0;
1033 }
1034
1035 /*
1036  * Device state switch handlers.
1037  */
1038 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1039                                 enum dev_state state)
1040 {
1041         u32 reg;
1042
1043         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1044         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1045                            state == STATE_RADIO_RX_OFF);
1046         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1047 }
1048
1049 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1050                                  enum dev_state state)
1051 {
1052         int mask = (state == STATE_RADIO_IRQ_OFF);
1053         u32 reg;
1054
1055         /*
1056          * When interrupts are being enabled, the interrupt registers
1057          * should clear the register to assure a clean state.
1058          */
1059         if (state == STATE_RADIO_IRQ_ON) {
1060                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1061                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1062         }
1063
1064         /*
1065          * Only toggle the interrupts bits we are going to use.
1066          * Non-checked interrupt bits are disabled by default.
1067          */
1068         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1069         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1070         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1071         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1072         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1073         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1074         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1075 }
1076
1077 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1078 {
1079         /*
1080          * Initialize all registers.
1081          */
1082         if (rt2500pci_init_rings(rt2x00dev) ||
1083             rt2500pci_init_registers(rt2x00dev) ||
1084             rt2500pci_init_bbp(rt2x00dev)) {
1085                 ERROR(rt2x00dev, "Register initialization failed.\n");
1086                 return -EIO;
1087         }
1088
1089         /*
1090          * Enable interrupts.
1091          */
1092         rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1093
1094         /*
1095          * Enable LED
1096          */
1097         rt2500pci_enable_led(rt2x00dev);
1098
1099         return 0;
1100 }
1101
1102 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1103 {
1104         u32 reg;
1105
1106         /*
1107          * Disable LED
1108          */
1109         rt2500pci_disable_led(rt2x00dev);
1110
1111         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1112
1113         /*
1114          * Disable synchronisation.
1115          */
1116         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1117
1118         /*
1119          * Cancel RX and TX.
1120          */
1121         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1122         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1123         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1124
1125         /*
1126          * Disable interrupts.
1127          */
1128         rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1129 }
1130
1131 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1132                                enum dev_state state)
1133 {
1134         u32 reg;
1135         unsigned int i;
1136         char put_to_sleep;
1137         char bbp_state;
1138         char rf_state;
1139
1140         put_to_sleep = (state != STATE_AWAKE);
1141
1142         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1143         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1144         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1145         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1146         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1147         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1148
1149         /*
1150          * Device is not guaranteed to be in the requested state yet.
1151          * We must wait until the register indicates that the
1152          * device has entered the correct state.
1153          */
1154         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1155                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1156                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1157                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1158                 if (bbp_state == state && rf_state == state)
1159                         return 0;
1160                 msleep(10);
1161         }
1162
1163         NOTICE(rt2x00dev, "Device failed to enter state %d, "
1164                "current device state: bbp %d and rf %d.\n",
1165                state, bbp_state, rf_state);
1166
1167         return -EBUSY;
1168 }
1169
1170 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1171                                       enum dev_state state)
1172 {
1173         int retval = 0;
1174
1175         switch (state) {
1176         case STATE_RADIO_ON:
1177                 retval = rt2500pci_enable_radio(rt2x00dev);
1178                 break;
1179         case STATE_RADIO_OFF:
1180                 rt2500pci_disable_radio(rt2x00dev);
1181                 break;
1182         case STATE_RADIO_RX_ON:
1183         case STATE_RADIO_RX_OFF:
1184                 rt2500pci_toggle_rx(rt2x00dev, state);
1185                 break;
1186         case STATE_DEEP_SLEEP:
1187         case STATE_SLEEP:
1188         case STATE_STANDBY:
1189         case STATE_AWAKE:
1190                 retval = rt2500pci_set_state(rt2x00dev, state);
1191                 break;
1192         default:
1193                 retval = -ENOTSUPP;
1194                 break;
1195         }
1196
1197         return retval;
1198 }
1199
1200 /*
1201  * TX descriptor initialization
1202  */
1203 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1204                                     struct data_desc *txd,
1205                                     struct txdata_entry_desc *desc,
1206                                     struct ieee80211_hdr *ieee80211hdr,
1207                                     unsigned int length,
1208                                     struct ieee80211_tx_control *control)
1209 {
1210         u32 word;
1211
1212         /*
1213          * Start writing the descriptor words.
1214          */
1215         rt2x00_desc_read(txd, 2, &word);
1216         rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1217         rt2x00_set_field32(&word, TXD_W2_AIFS, desc->aifs);
1218         rt2x00_set_field32(&word, TXD_W2_CWMIN, desc->cw_min);
1219         rt2x00_set_field32(&word, TXD_W2_CWMAX, desc->cw_max);
1220         rt2x00_desc_write(txd, 2, word);
1221
1222         rt2x00_desc_read(txd, 3, &word);
1223         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, desc->signal);
1224         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, desc->service);
1225         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, desc->length_low);
1226         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, desc->length_high);
1227         rt2x00_desc_write(txd, 3, word);
1228
1229         rt2x00_desc_read(txd, 10, &word);
1230         rt2x00_set_field32(&word, TXD_W10_RTS,
1231                            test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
1232         rt2x00_desc_write(txd, 10, word);
1233
1234         rt2x00_desc_read(txd, 0, &word);
1235         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1236         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1237         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1238                            test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1239         rt2x00_set_field32(&word, TXD_W0_ACK,
1240                            !(control->flags & IEEE80211_TXCTL_NO_ACK));
1241         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1242                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1243         rt2x00_set_field32(&word, TXD_W0_OFDM,
1244                            test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1245         rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1246         rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1247         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1248                            !!(control->flags &
1249                               IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1250         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1251         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1252         rt2x00_desc_write(txd, 0, word);
1253 }
1254
1255 /*
1256  * TX data initialization
1257  */
1258 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1259                                     unsigned int queue)
1260 {
1261         u32 reg;
1262
1263         if (queue == IEEE80211_TX_QUEUE_BEACON) {
1264                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1265                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1266                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1267                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1268                 }
1269                 return;
1270         }
1271
1272         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1273         if (queue == IEEE80211_TX_QUEUE_DATA0)
1274                 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
1275         else if (queue == IEEE80211_TX_QUEUE_DATA1)
1276                 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
1277         else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
1278                 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
1279         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1280 }
1281
1282 /*
1283  * RX control handlers
1284  */
1285 static void rt2500pci_fill_rxdone(struct data_entry *entry,
1286                                   struct rxdata_entry_desc *desc)
1287 {
1288         struct data_desc *rxd = entry->priv;
1289         u32 word0;
1290         u32 word2;
1291
1292         rt2x00_desc_read(rxd, 0, &word0);
1293         rt2x00_desc_read(rxd, 2, &word2);
1294
1295         desc->flags = 0;
1296         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1297                 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1298         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1299                 desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1300
1301         desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1302         desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1303             entry->ring->rt2x00dev->rssi_offset;
1304         desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1305         desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1306 }
1307
1308 /*
1309  * Interrupt functions.
1310  */
1311 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
1312 {
1313         struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1314         struct data_entry *entry;
1315         struct data_desc *txd;
1316         u32 word;
1317         int tx_status;
1318         int retry;
1319
1320         while (!rt2x00_ring_empty(ring)) {
1321                 entry = rt2x00_get_data_entry_done(ring);
1322                 txd = entry->priv;
1323                 rt2x00_desc_read(txd, 0, &word);
1324
1325                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1326                     !rt2x00_get_field32(word, TXD_W0_VALID))
1327                         break;
1328
1329                 /*
1330                  * Obtain the status about this packet.
1331                  */
1332                 tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
1333                 retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1334
1335                 rt2x00lib_txdone(entry, tx_status, retry);
1336
1337                 /*
1338                  * Make this entry available for reuse.
1339                  */
1340                 entry->flags = 0;
1341                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1342                 rt2x00_desc_write(txd, 0, word);
1343                 rt2x00_ring_index_done_inc(ring);
1344         }
1345
1346         /*
1347          * If the data ring was full before the txdone handler
1348          * we must make sure the packet queue in the mac80211 stack
1349          * is reenabled when the txdone handler has finished.
1350          */
1351         entry = ring->entry;
1352         if (!rt2x00_ring_full(ring))
1353                 ieee80211_wake_queue(rt2x00dev->hw,
1354                                      entry->tx_status.control.queue);
1355 }
1356
1357 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1358 {
1359         struct rt2x00_dev *rt2x00dev = dev_instance;
1360         u32 reg;
1361
1362         /*
1363          * Get the interrupt sources & saved to local variable.
1364          * Write register value back to clear pending interrupts.
1365          */
1366         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1367         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1368
1369         if (!reg)
1370                 return IRQ_NONE;
1371
1372         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1373                 return IRQ_HANDLED;
1374
1375         /*
1376          * Handle interrupts, walk through all bits
1377          * and run the tasks, the bits are checked in order of
1378          * priority.
1379          */
1380
1381         /*
1382          * 1 - Beacon timer expired interrupt.
1383          */
1384         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1385                 rt2x00lib_beacondone(rt2x00dev);
1386
1387         /*
1388          * 2 - Rx ring done interrupt.
1389          */
1390         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1391                 rt2x00pci_rxdone(rt2x00dev);
1392
1393         /*
1394          * 3 - Atim ring transmit done interrupt.
1395          */
1396         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1397                 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
1398
1399         /*
1400          * 4 - Priority ring transmit done interrupt.
1401          */
1402         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1403                 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1404
1405         /*
1406          * 5 - Tx ring transmit done interrupt.
1407          */
1408         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1409                 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1410
1411         return IRQ_HANDLED;
1412 }
1413
1414 /*
1415  * Device probe functions.
1416  */
1417 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1418 {
1419         struct eeprom_93cx6 eeprom;
1420         u32 reg;
1421         u16 word;
1422         u8 *mac;
1423
1424         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1425
1426         eeprom.data = rt2x00dev;
1427         eeprom.register_read = rt2500pci_eepromregister_read;
1428         eeprom.register_write = rt2500pci_eepromregister_write;
1429         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1430             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1431         eeprom.reg_data_in = 0;
1432         eeprom.reg_data_out = 0;
1433         eeprom.reg_data_clock = 0;
1434         eeprom.reg_chip_select = 0;
1435
1436         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1437                                EEPROM_SIZE / sizeof(u16));
1438
1439         /*
1440          * Start validation of the data that has been read.
1441          */
1442         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1443         if (!is_valid_ether_addr(mac)) {
1444                 DECLARE_MAC_BUF(macbuf);
1445
1446                 random_ether_addr(mac);
1447                 EEPROM(rt2x00dev, "MAC: %s\n",
1448                        print_mac(macbuf, mac));
1449         }
1450
1451         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1452         if (word == 0xffff) {
1453                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1454                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 0);
1455                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 0);
1456                 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE, 0);
1457                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1458                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1459                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1460                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1461                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1462         }
1463
1464         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1465         if (word == 0xffff) {
1466                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1467                 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1468                 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1469                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1470                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1471         }
1472
1473         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1474         if (word == 0xffff) {
1475                 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1476                                    DEFAULT_RSSI_OFFSET);
1477                 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1478                 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1479         }
1480
1481         return 0;
1482 }
1483
1484 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1485 {
1486         u32 reg;
1487         u16 value;
1488         u16 eeprom;
1489
1490         /*
1491          * Read EEPROM word for configuration.
1492          */
1493         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1494
1495         /*
1496          * Identify RF chipset.
1497          */
1498         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1499         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1500         rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1501
1502         if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1503             !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1504             !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1505             !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1506             !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1507             !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1508                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1509                 return -ENODEV;
1510         }
1511
1512         /*
1513          * Identify default antenna configuration.
1514          */
1515         rt2x00dev->hw->conf.antenna_sel_tx =
1516             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1517         rt2x00dev->hw->conf.antenna_sel_rx =
1518             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1519
1520         /*
1521          * Store led mode, for correct led behaviour.
1522          */
1523         rt2x00dev->led_mode =
1524             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1525
1526         /*
1527          * Detect if this device has an hardware controlled radio.
1528          */
1529 #ifdef CONFIG_RT2500PCI_RFKILL
1530         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1531                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1532 #endif /* CONFIG_RT2500PCI_RFKILL */
1533
1534         /*
1535          * Check if the BBP tuning should be enabled.
1536          */
1537         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1538
1539         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1540                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1541
1542         /*
1543          * Read the RSSI <-> dBm offset information.
1544          */
1545         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1546         rt2x00dev->rssi_offset =
1547             rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1548
1549         return 0;
1550 }
1551
1552 /*
1553  * RF value list for RF2522
1554  * Supports: 2.4 GHz
1555  */
1556 static const struct rf_channel rf_vals_bg_2522[] = {
1557         { 1,  0x00002050, 0x000c1fda, 0x00000101, 0 },
1558         { 2,  0x00002050, 0x000c1fee, 0x00000101, 0 },
1559         { 3,  0x00002050, 0x000c2002, 0x00000101, 0 },
1560         { 4,  0x00002050, 0x000c2016, 0x00000101, 0 },
1561         { 5,  0x00002050, 0x000c202a, 0x00000101, 0 },
1562         { 6,  0x00002050, 0x000c203e, 0x00000101, 0 },
1563         { 7,  0x00002050, 0x000c2052, 0x00000101, 0 },
1564         { 8,  0x00002050, 0x000c2066, 0x00000101, 0 },
1565         { 9,  0x00002050, 0x000c207a, 0x00000101, 0 },
1566         { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1567         { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1568         { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1569         { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1570         { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1571 };
1572
1573 /*
1574  * RF value list for RF2523
1575  * Supports: 2.4 GHz
1576  */
1577 static const struct rf_channel rf_vals_bg_2523[] = {
1578         { 1,  0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1579         { 2,  0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1580         { 3,  0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1581         { 4,  0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1582         { 5,  0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1583         { 6,  0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1584         { 7,  0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1585         { 8,  0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1586         { 9,  0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1587         { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1588         { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1589         { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1590         { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1591         { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1592 };
1593
1594 /*
1595  * RF value list for RF2524
1596  * Supports: 2.4 GHz
1597  */
1598 static const struct rf_channel rf_vals_bg_2524[] = {
1599         { 1,  0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1600         { 2,  0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1601         { 3,  0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1602         { 4,  0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1603         { 5,  0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1604         { 6,  0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1605         { 7,  0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1606         { 8,  0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1607         { 9,  0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1608         { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1609         { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1610         { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1611         { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1612         { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1613 };
1614
1615 /*
1616  * RF value list for RF2525
1617  * Supports: 2.4 GHz
1618  */
1619 static const struct rf_channel rf_vals_bg_2525[] = {
1620         { 1,  0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1621         { 2,  0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1622         { 3,  0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1623         { 4,  0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1624         { 5,  0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1625         { 6,  0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1626         { 7,  0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1627         { 8,  0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1628         { 9,  0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1629         { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1630         { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1631         { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1632         { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1633         { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1634 };
1635
1636 /*
1637  * RF value list for RF2525e
1638  * Supports: 2.4 GHz
1639  */
1640 static const struct rf_channel rf_vals_bg_2525e[] = {
1641         { 1,  0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1642         { 2,  0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1643         { 3,  0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1644         { 4,  0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1645         { 5,  0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1646         { 6,  0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1647         { 7,  0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1648         { 8,  0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1649         { 9,  0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1650         { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1651         { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1652         { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1653         { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1654         { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1655 };
1656
1657 /*
1658  * RF value list for RF5222
1659  * Supports: 2.4 GHz & 5.2 GHz
1660  */
1661 static const struct rf_channel rf_vals_5222[] = {
1662         { 1,  0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1663         { 2,  0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1664         { 3,  0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1665         { 4,  0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1666         { 5,  0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1667         { 6,  0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1668         { 7,  0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1669         { 8,  0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1670         { 9,  0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1671         { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1672         { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1673         { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1674         { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1675         { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1676
1677         /* 802.11 UNI / HyperLan 2 */
1678         { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1679         { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1680         { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1681         { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1682         { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1683         { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1684         { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1685         { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1686
1687         /* 802.11 HyperLan 2 */
1688         { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1689         { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1690         { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1691         { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1692         { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1693         { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1694         { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1695         { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1696         { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1697         { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1698
1699         /* 802.11 UNII */
1700         { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1701         { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1702         { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1703         { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1704         { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1705 };
1706
1707 static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1708 {
1709         struct hw_mode_spec *spec = &rt2x00dev->spec;
1710         u8 *txpower;
1711         unsigned int i;
1712
1713         /*
1714          * Initialize all hw fields.
1715          */
1716         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1717         rt2x00dev->hw->extra_tx_headroom = 0;
1718         rt2x00dev->hw->max_signal = MAX_SIGNAL;
1719         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1720         rt2x00dev->hw->queues = 2;
1721
1722         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1723         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1724                                 rt2x00_eeprom_addr(rt2x00dev,
1725                                                    EEPROM_MAC_ADDR_0));
1726
1727         /*
1728          * Convert tx_power array in eeprom.
1729          */
1730         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1731         for (i = 0; i < 14; i++)
1732                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1733
1734         /*
1735          * Initialize hw_mode information.
1736          */
1737         spec->num_modes = 2;
1738         spec->num_rates = 12;
1739         spec->tx_power_a = NULL;
1740         spec->tx_power_bg = txpower;
1741         spec->tx_power_default = DEFAULT_TXPOWER;
1742
1743         if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1744                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1745                 spec->channels = rf_vals_bg_2522;
1746         } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1747                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1748                 spec->channels = rf_vals_bg_2523;
1749         } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1750                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1751                 spec->channels = rf_vals_bg_2524;
1752         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1753                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1754                 spec->channels = rf_vals_bg_2525;
1755         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1756                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1757                 spec->channels = rf_vals_bg_2525e;
1758         } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1759                 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1760                 spec->channels = rf_vals_5222;
1761                 spec->num_modes = 3;
1762         }
1763 }
1764
1765 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1766 {
1767         int retval;
1768
1769         /*
1770          * Allocate eeprom data.
1771          */
1772         retval = rt2500pci_validate_eeprom(rt2x00dev);
1773         if (retval)
1774                 return retval;
1775
1776         retval = rt2500pci_init_eeprom(rt2x00dev);
1777         if (retval)
1778                 return retval;
1779
1780         /*
1781          * Initialize hw specifications.
1782          */
1783         rt2500pci_probe_hw_mode(rt2x00dev);
1784
1785         /*
1786          * This device requires the beacon ring
1787          */
1788         __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
1789
1790         /*
1791          * Set the rssi offset.
1792          */
1793         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1794
1795         return 0;
1796 }
1797
1798 /*
1799  * IEEE80211 stack callback functions.
1800  */
1801 static void rt2500pci_configure_filter(struct ieee80211_hw *hw,
1802                                        unsigned int changed_flags,
1803                                        unsigned int *total_flags,
1804                                        int mc_count,
1805                                        struct dev_addr_list *mc_list)
1806 {
1807         struct rt2x00_dev *rt2x00dev = hw->priv;
1808         struct interface *intf = &rt2x00dev->interface;
1809         u32 reg;
1810
1811         /*
1812          * Mask off any flags we are going to ignore from
1813          * the total_flags field.
1814          */
1815         *total_flags &=
1816             FIF_ALLMULTI |
1817             FIF_FCSFAIL |
1818             FIF_PLCPFAIL |
1819             FIF_CONTROL |
1820             FIF_OTHER_BSS |
1821             FIF_PROMISC_IN_BSS;
1822
1823         /*
1824          * Apply some rules to the filters:
1825          * - Some filters imply different filters to be set.
1826          * - Some things we can't filter out at all.
1827          * - Some filters are set based on interface type.
1828          */
1829         if (mc_count)
1830                 *total_flags |= FIF_ALLMULTI;
1831         if (*total_flags & FIF_OTHER_BSS ||
1832             *total_flags & FIF_PROMISC_IN_BSS)
1833                 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1834         if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
1835                 *total_flags |= FIF_PROMISC_IN_BSS;
1836
1837         /*
1838          * Check if there is any work left for us.
1839          */
1840         if (intf->filter == *total_flags)
1841                 return;
1842         intf->filter = *total_flags;
1843
1844         /*
1845          * Start configuration steps.
1846          * Note that the version error will always be dropped
1847          * and broadcast frames will always be accepted since
1848          * there is no filter for it at this time.
1849          */
1850         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1851         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1852                            !(*total_flags & FIF_FCSFAIL));
1853         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1854                            !(*total_flags & FIF_PLCPFAIL));
1855         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1856                            !(*total_flags & FIF_CONTROL));
1857         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1858                            !(*total_flags & FIF_PROMISC_IN_BSS));
1859         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1860                            !(*total_flags & FIF_PROMISC_IN_BSS));
1861         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1862         rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
1863                            !(*total_flags & FIF_ALLMULTI));
1864         rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
1865         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1866 }
1867
1868 static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1869                                      u32 short_retry, u32 long_retry)
1870 {
1871         struct rt2x00_dev *rt2x00dev = hw->priv;
1872         u32 reg;
1873
1874         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1875         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1876         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1877         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1878
1879         return 0;
1880 }
1881
1882 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1883 {
1884         struct rt2x00_dev *rt2x00dev = hw->priv;
1885         u64 tsf;
1886         u32 reg;
1887
1888         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1889         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1890         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1891         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1892
1893         return tsf;
1894 }
1895
1896 static void rt2500pci_reset_tsf(struct ieee80211_hw *hw)
1897 {
1898         struct rt2x00_dev *rt2x00dev = hw->priv;
1899
1900         rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1901         rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1902 }
1903
1904 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1905 {
1906         struct rt2x00_dev *rt2x00dev = hw->priv;
1907         u32 reg;
1908
1909         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1910         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1911 }
1912
1913 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1914         .tx                     = rt2x00mac_tx,
1915         .start                  = rt2x00mac_start,
1916         .stop                   = rt2x00mac_stop,
1917         .add_interface          = rt2x00mac_add_interface,
1918         .remove_interface       = rt2x00mac_remove_interface,
1919         .config                 = rt2x00mac_config,
1920         .config_interface       = rt2x00mac_config_interface,
1921         .configure_filter       = rt2500pci_configure_filter,
1922         .get_stats              = rt2x00mac_get_stats,
1923         .set_retry_limit        = rt2500pci_set_retry_limit,
1924         .conf_tx                = rt2x00mac_conf_tx,
1925         .get_tx_stats           = rt2x00mac_get_tx_stats,
1926         .get_tsf                = rt2500pci_get_tsf,
1927         .reset_tsf              = rt2500pci_reset_tsf,
1928         .beacon_update          = rt2x00pci_beacon_update,
1929         .tx_last_beacon         = rt2500pci_tx_last_beacon,
1930 };
1931
1932 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1933         .irq_handler            = rt2500pci_interrupt,
1934         .probe_hw               = rt2500pci_probe_hw,
1935         .initialize             = rt2x00pci_initialize,
1936         .uninitialize           = rt2x00pci_uninitialize,
1937         .set_device_state       = rt2500pci_set_device_state,
1938         .rfkill_poll            = rt2500pci_rfkill_poll,
1939         .link_stats             = rt2500pci_link_stats,
1940         .reset_tuner            = rt2500pci_reset_tuner,
1941         .link_tuner             = rt2500pci_link_tuner,
1942         .write_tx_desc          = rt2500pci_write_tx_desc,
1943         .write_tx_data          = rt2x00pci_write_tx_data,
1944         .kick_tx_queue          = rt2500pci_kick_tx_queue,
1945         .fill_rxdone            = rt2500pci_fill_rxdone,
1946         .config_mac_addr        = rt2500pci_config_mac_addr,
1947         .config_bssid           = rt2500pci_config_bssid,
1948         .config_type            = rt2500pci_config_type,
1949         .config                 = rt2500pci_config,
1950 };
1951
1952 static const struct rt2x00_ops rt2500pci_ops = {
1953         .name           = DRV_NAME,
1954         .rxd_size       = RXD_DESC_SIZE,
1955         .txd_size       = TXD_DESC_SIZE,
1956         .eeprom_size    = EEPROM_SIZE,
1957         .rf_size        = RF_SIZE,
1958         .lib            = &rt2500pci_rt2x00_ops,
1959         .hw             = &rt2500pci_mac80211_ops,
1960 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1961         .debugfs        = &rt2500pci_rt2x00debug,
1962 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1963 };
1964
1965 /*
1966  * RT2500pci module information.
1967  */
1968 static struct pci_device_id rt2500pci_device_table[] = {
1969         { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1970         { 0, }
1971 };
1972
1973 MODULE_AUTHOR(DRV_PROJECT);
1974 MODULE_VERSION(DRV_VERSION);
1975 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1976 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1977 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1978 MODULE_LICENSE("GPL");
1979
1980 static struct pci_driver rt2500pci_driver = {
1981         .name           = DRV_NAME,
1982         .id_table       = rt2500pci_device_table,
1983         .probe          = rt2x00pci_probe,
1984         .remove         = __devexit_p(rt2x00pci_remove),
1985         .suspend        = rt2x00pci_suspend,
1986         .resume         = rt2x00pci_resume,
1987 };
1988
1989 static int __init rt2500pci_init(void)
1990 {
1991         return pci_register_driver(&rt2500pci_driver);
1992 }
1993
1994 static void __exit rt2500pci_exit(void)
1995 {
1996         pci_unregister_driver(&rt2500pci_driver);
1997 }
1998
1999 module_init(rt2500pci_init);
2000 module_exit(rt2500pci_exit);