SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/rt2x00/rt2500pci.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2500pci
  23         Abstract: rt2500pci device specific routines.
  24         Supported chipsets: RT2560.
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00pci.h"
  37 #include "rt2500pci.h"
  38
  39 /*
  40  * Register access.
  41  * All access to the CSR registers will go through the methods
  42  * rt2x00pci_register_read and rt2x00pci_register_write.
  43  * BBP and RF register require indirect register access,
  44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  45  * These indirect registers work with busy bits,
  46  * and we will try maximal REGISTER_BUSY_COUNT times to access
  47  * the register while taking a REGISTER_BUSY_DELAY us delay
  48  * between each attampt. When the busy bit is still set at that time,
  49  * the access attempt is considered to have failed,
  50  * and we will print an error.
  51  */
  52 static u32 rt2500pci_bbp_check(struct rt2x00_dev *rt2x00dev)
  53 {
  54         u32 reg;
  55         unsigned int i;
  56
  57         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  58                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  59                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  60                         break;
  61                 udelay(REGISTER_BUSY_DELAY);
  62         }
  63
  64         return reg;
  65 }
  66
  67 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  68                                 const unsigned int word, const u8 value)
  69 {
  70         u32 reg;
  71
  72         /*
  73          * Wait until the BBP becomes ready.
  74          */
  75         reg = rt2500pci_bbp_check(rt2x00dev);
  76         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  77                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  78                 return;
  79         }
  80
  81         /*
  82          * Write the data into the BBP.
  83          */
  84         reg = 0;
  85         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  86         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  87         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  88         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  89
  90         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  91 }
  92
  93 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  94                                const unsigned int word, u8 *value)
  95 {
  96         u32 reg;
  97
  98         /*
  99          * Wait until the BBP becomes ready.
 100          */
 101         reg = rt2500pci_bbp_check(rt2x00dev);
 102         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 103                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 104                 return;
 105         }
 106
 107         /*
 108          * Write the request into the BBP.
 109          */
 110         reg = 0;
 111         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 112         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 113         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 114
 115         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 116
 117         /*
 118          * Wait until the BBP becomes ready.
 119          */
 120         reg = rt2500pci_bbp_check(rt2x00dev);
 121         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 122                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 123                 *value = 0xff;
 124                 return;
 125         }
 126
 127         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 128 }
 129
 130 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
 131                                const unsigned int word, const u32 value)
 132 {
 133         u32 reg;
 134         unsigned int i;
 135
 136         if (!word)
 137                 return;
 138
 139         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 140                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
 141                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
 142                         goto rf_write;
 143                 udelay(REGISTER_BUSY_DELAY);
 144         }
 145
 146         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
 147         return;
 148
 149 rf_write:
 150         reg = 0;
 151         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 152         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 153         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 154         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 155
 156         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 157         rt2x00_rf_write(rt2x00dev, word, value);
 158 }
 159
 160 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 161 {
 162         struct rt2x00_dev *rt2x00dev = eeprom->data;
 163         u32 reg;
 164
 165         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 166
 167         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 168         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 169         eeprom->reg_data_clock =
 170             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 171         eeprom->reg_chip_select =
 172             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 173 }
 174
 175 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 176 {
 177         struct rt2x00_dev *rt2x00dev = eeprom->data;
 178         u32 reg = 0;
 179
 180         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 181         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 182         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 183                            !!eeprom->reg_data_clock);
 184         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 185                            !!eeprom->reg_chip_select);
 186
 187         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 188 }
 189
 190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 191 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 192
 193 static void rt2500pci_read_csr(struct rt2x00_dev *rt2x00dev,
 194                                const unsigned int word, u32 *data)
 195 {
 196         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 197 }
 198
 199 static void rt2500pci_write_csr(struct rt2x00_dev *rt2x00dev,
 200                                 const unsigned int word, u32 data)
 201 {
 202         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 203 }
 204
 205 static const struct rt2x00debug rt2500pci_rt2x00debug = {
 206         .owner  = THIS_MODULE,
 207         .csr    = {
 208                 .read           = rt2500pci_read_csr,
 209                 .write          = rt2500pci_write_csr,
 210                 .word_size      = sizeof(u32),
 211                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 212         },
 213         .eeprom = {
 214                 .read           = rt2x00_eeprom_read,
 215                 .write          = rt2x00_eeprom_write,
 216                 .word_size      = sizeof(u16),
 217                 .word_count     = EEPROM_SIZE / sizeof(u16),
 218         },
 219         .bbp    = {
 220                 .read           = rt2500pci_bbp_read,
 221                 .write          = rt2500pci_bbp_write,
 222                 .word_size      = sizeof(u8),
 223                 .word_count     = BBP_SIZE / sizeof(u8),
 224         },
 225         .rf     = {
 226                 .read           = rt2x00_rf_read,
 227                 .write          = rt2500pci_rf_write,
 228                 .word_size      = sizeof(u32),
 229                 .word_count     = RF_SIZE / sizeof(u32),
 230         },
 231 };
 232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 233
 234 #ifdef CONFIG_RT2500PCI_RFKILL
 235 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 236 {
 237         u32 reg;
 238
 239         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 240         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 241 }
 242 #else
 243 #define rt2500pci_rfkill_poll   NULL
 244 #endif /* CONFIG_RT2500PCI_RFKILL */
 245
 246 #ifdef CONFIG_RT2500PCI_LEDS
 247 static void rt2500pci_led_brightness(struct led_classdev *led_cdev,
 248                                      enum led_brightness brightness)
 249 {
 250         struct rt2x00_led *led =
 251             container_of(led_cdev, struct rt2x00_led, led_dev);
 252         unsigned int enabled = brightness != LED_OFF;
 253         unsigned int activity =
 254             led->rt2x00dev->led_flags & LED_SUPPORT_ACTIVITY;
 255         u32 reg;
 256
 257         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 258
 259         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC) {
 260                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 261                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled && activity);
 262         }
 263
 264         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 265 }
 266 #else
 267 #define rt2500pci_led_brightness        NULL
 268 #endif /* CONFIG_RT2500PCI_LEDS */
 269
 270 /*
 271  * Configuration handlers.
 272  */
 273 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
 274                                     const unsigned int filter_flags)
 275 {
 276         u32 reg;
 277
 278         /*
 279          * Start configuration steps.
 280          * Note that the version error will always be dropped
 281          * and broadcast frames will always be accepted since
 282          * there is no filter for it at this time.
 283          */
 284         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 285         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
 286                            !(filter_flags & FIF_FCSFAIL));
 287         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
 288                            !(filter_flags & FIF_PLCPFAIL));
 289         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
 290                            !(filter_flags & FIF_CONTROL));
 291         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
 292                            !(filter_flags & FIF_PROMISC_IN_BSS));
 293         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
 294                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 295                            !rt2x00dev->intf_ap_count);
 296         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 297         rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
 298                            !(filter_flags & FIF_ALLMULTI));
 299         rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
 300         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 301 }
 302
 303 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
 304                                   struct rt2x00_intf *intf,
 305                                   struct rt2x00intf_conf *conf,
 306                                   const unsigned int flags)
 307 {
 308         struct data_queue *queue =
 309             rt2x00queue_get_queue(rt2x00dev, RT2X00_BCN_QUEUE_BEACON);
 310         unsigned int bcn_preload;
 311         u32 reg;
 312
 313         if (flags & CONFIG_UPDATE_TYPE) {
 314                 /*
 315                  * Enable beacon config
 316                  */
 317                 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
 318                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 319                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 320                 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
 321                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 322
 323                 /*
 324                  * Enable synchronisation.
 325                  */
 326                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 327                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 328                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 329                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 330                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 331         }
 332
 333         if (flags & CONFIG_UPDATE_MAC)
 334                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
 335                                               conf->mac, sizeof(conf->mac));
 336
 337         if (flags & CONFIG_UPDATE_BSSID)
 338                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
 339                                               conf->bssid, sizeof(conf->bssid));
 340 }
 341
 342 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
 343                                  struct rt2x00lib_erp *erp)
 344 {
 345         int preamble_mask;
 346         u32 reg;
 347
 348         /*
 349          * When short preamble is enabled, we should set bit 0x08
 350          */
 351         preamble_mask = erp->short_preamble << 3;
 352
 353         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 354         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
 355                            erp->ack_timeout);
 356         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
 357                            erp->ack_consume_time);
 358         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 359
 360         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 361         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
 362         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 363         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
 364         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 365
 366         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 367         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 368         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 369         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
 370         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 371
 372         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 373         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 374         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 375         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
 376         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 377
 378         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 379         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 380         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 381         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
 382         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 383 }
 384
 385 static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 386                                      const int basic_rate_mask)
 387 {
 388         rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
 389 }
 390
 391 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
 392                                      struct rf_channel *rf, const int txpower)
 393 {
 394         u8 r70;
 395
 396         /*
 397          * Set TXpower.
 398          */
 399         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 400
 401         /*
 402          * Switch on tuning bits.
 403          * For RT2523 devices we do not need to update the R1 register.
 404          */
 405         if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
 406                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 407         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 408
 409         /*
 410          * For RT2525 we should first set the channel to half band higher.
 411          */
 412         if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
 413                 static const u32 vals[] = {
 414                         0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
 415                         0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
 416                         0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
 417                         0x00080d2e, 0x00080d3a
 418                 };
 419
 420                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 421                 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
 422                 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 423                 if (rf->rf4)
 424                         rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 425         }
 426
 427         rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 428         rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
 429         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 430         if (rf->rf4)
 431                 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 432
 433         /*
 434          * Channel 14 requires the Japan filter bit to be set.
 435          */
 436         r70 = 0x46;
 437         rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
 438         rt2500pci_bbp_write(rt2x00dev, 70, r70);
 439
 440         msleep(1);
 441
 442         /*
 443          * Switch off tuning bits.
 444          * For RT2523 devices we do not need to update the R1 register.
 445          */
 446         if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
 447                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 448                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 449         }
 450
 451         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 452         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 453
 454         /*
 455          * Clear false CRC during channel switch.
 456          */
 457         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
 458 }
 459
 460 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 461                                      const int txpower)
 462 {
 463         u32 rf3;
 464
 465         rt2x00_rf_read(rt2x00dev, 3, &rf3);
 466         rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 467         rt2500pci_rf_write(rt2x00dev, 3, rf3);
 468 }
 469
 470 static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 471                                      struct antenna_setup *ant)
 472 {
 473         u32 reg;
 474         u8 r14;
 475         u8 r2;
 476
 477         /*
 478          * We should never come here because rt2x00lib is supposed
 479          * to catch this and send us the correct antenna explicitely.
 480          */
 481         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 482                ant->tx == ANTENNA_SW_DIVERSITY);
 483
 484         rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
 485         rt2500pci_bbp_read(rt2x00dev, 14, &r14);
 486         rt2500pci_bbp_read(rt2x00dev, 2, &r2);
 487
 488         /*
 489          * Configure the TX antenna.
 490          */
 491         switch (ant->tx) {
 492         case ANTENNA_A:
 493                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
 494                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
 495                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
 496                 break;
 497         case ANTENNA_B:
 498         default:
 499                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
 500                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
 501                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
 502                 break;
 503         }
 504
 505         /*
 506          * Configure the RX antenna.
 507          */
 508         switch (ant->rx) {
 509         case ANTENNA_A:
 510                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
 511                 break;
 512         case ANTENNA_B:
 513         default:
 514                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
 515                 break;
 516         }
 517
 518         /*
 519          * RT2525E and RT5222 need to flip TX I/Q
 520          */
 521         if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
 522             rt2x00_rf(&rt2x00dev->chip, RF5222)) {
 523                 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
 524                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
 525                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
 526
 527                 /*
 528                  * RT2525E does not need RX I/Q Flip.
 529                  */
 530                 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
 531                         rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
 532         } else {
 533                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
 534                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
 535         }
 536
 537         rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
 538         rt2500pci_bbp_write(rt2x00dev, 14, r14);
 539         rt2500pci_bbp_write(rt2x00dev, 2, r2);
 540 }
 541
 542 static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
 543                                       struct rt2x00lib_conf *libconf)
 544 {
 545         u32 reg;
 546
 547         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 548         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
 549         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 550
 551         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 552         rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
 553         rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
 554         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 555
 556         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 557         rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
 558         rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
 559         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 560
 561         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 562         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 563         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 564         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 565
 566         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 567         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
 568                            libconf->conf->beacon_int * 16);
 569         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
 570                            libconf->conf->beacon_int * 16);
 571         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 572 }
 573
 574 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
 575                              struct rt2x00lib_conf *libconf,
 576                              const unsigned int flags)
 577 {
 578         if (flags & CONFIG_UPDATE_PHYMODE)
 579                 rt2500pci_config_phymode(rt2x00dev, libconf->basic_rates);
 580         if (flags & CONFIG_UPDATE_CHANNEL)
 581                 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
 582                                          libconf->conf->power_level);
 583         if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
 584                 rt2500pci_config_txpower(rt2x00dev,
 585                                          libconf->conf->power_level);
 586         if (flags & CONFIG_UPDATE_ANTENNA)
 587                 rt2500pci_config_antenna(rt2x00dev, &libconf->ant);
 588         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 589                 rt2500pci_config_duration(rt2x00dev, libconf);
 590 }
 591
 592 /*
 593  * Link tuning
 594  */
 595 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
 596                                  struct link_qual *qual)
 597 {
 598         u32 reg;
 599
 600         /*
 601          * Update FCS error count from register.
 602          */
 603         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 604         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 605
 606         /*
 607          * Update False CCA count from register.
 608          */
 609         rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
 610         qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
 611 }
 612
 613 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 614 {
 615         rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
 616         rt2x00dev->link.vgc_level = 0x48;
 617 }
 618
 619 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 620 {
 621         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
 622         u8 r17;
 623
 624         /*
 625          * To prevent collisions with MAC ASIC on chipsets
 626          * up to version C the link tuning should halt after 20
 627          * seconds while being associated.
 628          */
 629         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
 630             rt2x00dev->intf_associated &&
 631             rt2x00dev->link.count > 20)
 632                 return;
 633
 634         rt2500pci_bbp_read(rt2x00dev, 17, &r17);
 635
 636         /*
 637          * Chipset versions C and lower should directly continue
 638          * to the dynamic CCA tuning. Chipset version D and higher
 639          * should go straight to dynamic CCA tuning when they
 640          * are not associated.
 641          */
 642         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D ||
 643             !rt2x00dev->intf_associated)
 644                 goto dynamic_cca_tune;
 645
 646         /*
 647          * A too low RSSI will cause too much false CCA which will
 648          * then corrupt the R17 tuning. To remidy this the tuning should
 649          * be stopped (While making sure the R17 value will not exceed limits)
 650          */
 651         if (rssi < -80 && rt2x00dev->link.count > 20) {
 652                 if (r17 >= 0x41) {
 653                         r17 = rt2x00dev->link.vgc_level;
 654                         rt2500pci_bbp_write(rt2x00dev, 17, r17);
 655                 }
 656                 return;
 657         }
 658
 659         /*
 660          * Special big-R17 for short distance
 661          */
 662         if (rssi >= -58) {
 663                 if (r17 != 0x50)
 664                         rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
 665                 return;
 666         }
 667
 668         /*
 669          * Special mid-R17 for middle distance
 670          */
 671         if (rssi >= -74) {
 672                 if (r17 != 0x41)
 673                         rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
 674                 return;
 675         }
 676
 677         /*
 678          * Leave short or middle distance condition, restore r17
 679          * to the dynamic tuning range.
 680          */
 681         if (r17 >= 0x41) {
 682                 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
 683                 return;
 684         }
 685
 686 dynamic_cca_tune:
 687
 688         /*
 689          * R17 is inside the dynamic tuning range,
 690          * start tuning the link based on the false cca counter.
 691          */
 692         if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
 693                 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
 694                 rt2x00dev->link.vgc_level = r17;
 695         } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
 696                 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
 697                 rt2x00dev->link.vgc_level = r17;
 698         }
 699 }
 700
 701 /*
 702  * Initialization functions.
 703  */
 704 static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
 705                                    struct queue_entry *entry)
 706 {
 707         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
 708         u32 word;
 709
 710         rt2x00_desc_read(priv_rx->desc, 1, &word);
 711         rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
 712         rt2x00_desc_write(priv_rx->desc, 1, word);
 713
 714         rt2x00_desc_read(priv_rx->desc, 0, &word);
 715         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 716         rt2x00_desc_write(priv_rx->desc, 0, word);
 717 }
 718
 719 static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev,
 720                                    struct queue_entry *entry)
 721 {
 722         struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
 723         u32 word;
 724
 725         rt2x00_desc_read(priv_tx->desc, 1, &word);
 726         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
 727         rt2x00_desc_write(priv_tx->desc, 1, word);
 728
 729         rt2x00_desc_read(priv_tx->desc, 0, &word);
 730         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 731         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 732         rt2x00_desc_write(priv_tx->desc, 0, word);
 733 }
 734
 735 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
 736 {
 737         struct queue_entry_priv_pci_rx *priv_rx;
 738         struct queue_entry_priv_pci_tx *priv_tx;
 739         u32 reg;
 740
 741         /*
 742          * Initialize registers.
 743          */
 744         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 745         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 746         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 747         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
 748         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 749         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 750
 751         priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
 752         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 753         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 754                            priv_tx->desc_dma);
 755         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 756
 757         priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
 758         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 759         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 760                            priv_tx->desc_dma);
 761         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 762
 763         priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
 764         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 765         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 766                            priv_tx->desc_dma);
 767         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 768
 769         priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
 770         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 771         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 772                            priv_tx->desc_dma);
 773         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 774
 775         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 776         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 777         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 778         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 779
 780         priv_rx = rt2x00dev->rx->entries[0].priv_data;
 781         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 782         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_rx->desc_dma);
 783         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 784
 785         return 0;
 786 }
 787
 788 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
 789 {
 790         u32 reg;
 791
 792         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 793         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 794         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
 795         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 796
 797         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 798         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 799         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 800         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 801         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 802
 803         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 804         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 805                            rt2x00dev->rx->data_size / 128);
 806         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 807
 808         /*
 809          * Always use CWmin and CWmax set in descriptor.
 810          */
 811         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 812         rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
 813         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 814
 815         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 816         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
 817         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
 818         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 819
 820         rt2x00pci_register_write(rt2x00dev, CNT3, 0);
 821
 822         rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
 823         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
 824         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
 825         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
 826         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
 827         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
 828         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
 829         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
 830         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
 831         rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
 832
 833         rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
 834         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
 835         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
 836         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
 837         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
 838         rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
 839
 840         rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
 841         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
 842         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
 843         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
 844         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
 845         rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
 846
 847         rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
 848         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
 849         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
 850         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
 851         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
 852         rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
 853
 854         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 855         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
 856         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 857         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
 858         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 859         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
 860         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 861         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
 862         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
 863         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 864
 865         rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
 866         rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
 867         rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
 868         rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
 869         rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
 870         rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
 871         rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
 872         rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
 873         rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
 874
 875         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 876
 877         rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
 878         rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
 879
 880         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 881                 return -EBUSY;
 882
 883         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
 884         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 885
 886         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 887         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 888         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 889
 890         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 891         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 892         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
 893         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
 894         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 895         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
 896         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
 897         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 898
 899         rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
 900
 901         rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
 902
 903         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 904         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 905         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 906         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 907         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 908
 909         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 910         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 911         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 912         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 913
 914         /*
 915          * We must clear the FCS and FIFO error count.
 916          * These registers are cleared on read,
 917          * so we may pass a useless variable to store the value.
 918          */
 919         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 920         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 921
 922         return 0;
 923 }
 924
 925 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 926 {
 927         unsigned int i;
 928         u16 eeprom;
 929         u8 reg_id;
 930         u8 value;
 931
 932         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 933                 rt2500pci_bbp_read(rt2x00dev, 0, &value);
 934                 if ((value != 0xff) && (value != 0x00))
 935                         goto continue_csr_init;
 936                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
 937                 udelay(REGISTER_BUSY_DELAY);
 938         }
 939
 940         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 941         return -EACCES;
 942
 943 continue_csr_init:
 944         rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
 945         rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
 946         rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
 947         rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
 948         rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
 949         rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
 950         rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
 951         rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
 952         rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
 953         rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
 954         rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
 955         rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
 956         rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
 957         rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
 958         rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
 959         rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
 960         rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
 961         rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
 962         rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
 963         rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
 964         rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
 965         rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
 966         rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
 967         rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
 968         rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
 969         rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
 970         rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
 971         rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
 972         rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
 973         rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
 974
 975         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 976                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
 977
 978                 if (eeprom != 0xffff && eeprom != 0x0000) {
 979                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
 980                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
 981                         rt2500pci_bbp_write(rt2x00dev, reg_id, value);
 982                 }
 983         }
 984
 985         return 0;
 986 }
 987
 988 /*
 989  * Device state switch handlers.
 990  */
 991 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 992                                 enum dev_state state)
 993 {
 994         u32 reg;
 995
 996         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 997         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
 998                            state == STATE_RADIO_RX_OFF);
 999         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1000 }
1001
1002 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1003                                  enum dev_state state)
1004 {
1005         int mask = (state == STATE_RADIO_IRQ_OFF);
1006         u32 reg;
1007
1008         /*
1009          * When interrupts are being enabled, the interrupt registers
1010          * should clear the register to assure a clean state.
1011          */
1012         if (state == STATE_RADIO_IRQ_ON) {
1013                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1014                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1015         }
1016
1017         /*
1018          * Only toggle the interrupts bits we are going to use.
1019          * Non-checked interrupt bits are disabled by default.
1020          */
1021         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1022         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1023         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1024         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1025         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1026         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1027         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1028 }
1029
1030 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1031 {
1032         /*
1033          * Initialize all registers.
1034          */
1035         if (rt2500pci_init_queues(rt2x00dev) ||
1036             rt2500pci_init_registers(rt2x00dev) ||
1037             rt2500pci_init_bbp(rt2x00dev)) {
1038                 ERROR(rt2x00dev, "Register initialization failed.\n");
1039                 return -EIO;
1040         }
1041
1042         /*
1043          * Enable interrupts.
1044          */
1045         rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1046
1047         return 0;
1048 }
1049
1050 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1051 {
1052         u32 reg;
1053
1054         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1055
1056         /*
1057          * Disable synchronisation.
1058          */
1059         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1060
1061         /*
1062          * Cancel RX and TX.
1063          */
1064         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1065         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1066         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1067
1068         /*
1069          * Disable interrupts.
1070          */
1071         rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1072 }
1073
1074 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1075                                enum dev_state state)
1076 {
1077         u32 reg;
1078         unsigned int i;
1079         char put_to_sleep;
1080         char bbp_state;
1081         char rf_state;
1082
1083         put_to_sleep = (state != STATE_AWAKE);
1084
1085         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1086         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1087         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1088         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1089         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1090         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1091
1092         /*
1093          * Device is not guaranteed to be in the requested state yet.
1094          * We must wait until the register indicates that the
1095          * device has entered the correct state.
1096          */
1097         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1098                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1099                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1100                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1101                 if (bbp_state == state && rf_state == state)
1102                         return 0;
1103                 msleep(10);
1104         }
1105
1106         NOTICE(rt2x00dev, "Device failed to enter state %d, "
1107                "current device state: bbp %d and rf %d.\n",
1108                state, bbp_state, rf_state);
1109
1110         return -EBUSY;
1111 }
1112
1113 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1114                                       enum dev_state state)
1115 {
1116         int retval = 0;
1117
1118         switch (state) {
1119         case STATE_RADIO_ON:
1120                 retval = rt2500pci_enable_radio(rt2x00dev);
1121                 break;
1122         case STATE_RADIO_OFF:
1123                 rt2500pci_disable_radio(rt2x00dev);
1124                 break;
1125         case STATE_RADIO_RX_ON:
1126         case STATE_RADIO_RX_ON_LINK:
1127                 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1128                 break;
1129         case STATE_RADIO_RX_OFF:
1130         case STATE_RADIO_RX_OFF_LINK:
1131                 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
1132                 break;
1133         case STATE_DEEP_SLEEP:
1134         case STATE_SLEEP:
1135         case STATE_STANDBY:
1136         case STATE_AWAKE:
1137                 retval = rt2500pci_set_state(rt2x00dev, state);
1138                 break;
1139         default:
1140                 retval = -ENOTSUPP;
1141                 break;
1142         }
1143
1144         return retval;
1145 }
1146
1147 /*
1148  * TX descriptor initialization
1149  */
1150 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1151                                     struct sk_buff *skb,
1152                                     struct txentry_desc *txdesc,
1153                                     struct ieee80211_tx_control *control)
1154 {
1155         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1156         __le32 *txd = skbdesc->desc;
1157         u32 word;
1158
1159         /*
1160          * Start writing the descriptor words.
1161          */
1162         rt2x00_desc_read(txd, 2, &word);
1163         rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1164         rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1165         rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1166         rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
1167         rt2x00_desc_write(txd, 2, word);
1168
1169         rt2x00_desc_read(txd, 3, &word);
1170         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1171         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1172         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1173         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
1174         rt2x00_desc_write(txd, 3, word);
1175
1176         rt2x00_desc_read(txd, 10, &word);
1177         rt2x00_set_field32(&word, TXD_W10_RTS,
1178                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1179         rt2x00_desc_write(txd, 10, word);
1180
1181         rt2x00_desc_read(txd, 0, &word);
1182         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1183         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1184         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1185                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1186         rt2x00_set_field32(&word, TXD_W0_ACK,
1187                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1188         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1189                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1190         rt2x00_set_field32(&word, TXD_W0_OFDM,
1191                            test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1192         rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1193         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1194         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1195                            !!(control->flags &
1196                               IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1197         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1198         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1199         rt2x00_desc_write(txd, 0, word);
1200 }
1201
1202 /*
1203  * TX data initialization
1204  */
1205 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1206                                     const unsigned int queue)
1207 {
1208         u32 reg;
1209
1210         if (queue == RT2X00_BCN_QUEUE_BEACON) {
1211                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1212                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1213                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1214                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1215                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1216                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1217                 }
1218                 return;
1219         }
1220
1221         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1222         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO,
1223                            (queue == IEEE80211_TX_QUEUE_DATA0));
1224         rt2x00_set_field32(&reg, TXCSR0_KICK_TX,
1225                            (queue == IEEE80211_TX_QUEUE_DATA1));
1226         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
1227                            (queue == RT2X00_BCN_QUEUE_ATIM));
1228         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1229 }
1230
1231 /*
1232  * RX control handlers
1233  */
1234 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1235                                   struct rxdone_entry_desc *rxdesc)
1236 {
1237         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1238         u32 word0;
1239         u32 word2;
1240
1241         rt2x00_desc_read(priv_rx->desc, 0, &word0);
1242         rt2x00_desc_read(priv_rx->desc, 2, &word2);
1243
1244         rxdesc->flags = 0;
1245         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1246                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1247         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1248                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1249
1250         /*
1251          * Obtain the status about this packet.
1252          * When frame was received with an OFDM bitrate,
1253          * the signal is the PLCP value. If it was received with
1254          * a CCK bitrate the signal is the rate in 100kbit/s.
1255          */
1256         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1257         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1258             entry->queue->rt2x00dev->rssi_offset;
1259         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1260
1261         rxdesc->dev_flags = 0;
1262         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1263                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1264         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1265                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1266 }
1267
1268 /*
1269  * Interrupt functions.
1270  */
1271 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1272                              const enum ieee80211_tx_queue queue_idx)
1273 {
1274         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1275         struct queue_entry_priv_pci_tx *priv_tx;
1276         struct queue_entry *entry;
1277         struct txdone_entry_desc txdesc;
1278         u32 word;
1279
1280         while (!rt2x00queue_empty(queue)) {
1281                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1282                 priv_tx = entry->priv_data;
1283                 rt2x00_desc_read(priv_tx->desc, 0, &word);
1284
1285                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1286                     !rt2x00_get_field32(word, TXD_W0_VALID))
1287                         break;
1288
1289                 /*
1290                  * Obtain the status about this packet.
1291                  */
1292                 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT);
1293                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1294
1295                 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1296         }
1297 }
1298
1299 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1300 {
1301         struct rt2x00_dev *rt2x00dev = dev_instance;
1302         u32 reg;
1303
1304         /*
1305          * Get the interrupt sources & saved to local variable.
1306          * Write register value back to clear pending interrupts.
1307          */
1308         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1309         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1310
1311         if (!reg)
1312                 return IRQ_NONE;
1313
1314         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1315                 return IRQ_HANDLED;
1316
1317         /*
1318          * Handle interrupts, walk through all bits
1319          * and run the tasks, the bits are checked in order of
1320          * priority.
1321          */
1322
1323         /*
1324          * 1 - Beacon timer expired interrupt.
1325          */
1326         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1327                 rt2x00lib_beacondone(rt2x00dev);
1328
1329         /*
1330          * 2 - Rx ring done interrupt.
1331          */
1332         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1333                 rt2x00pci_rxdone(rt2x00dev);
1334
1335         /*
1336          * 3 - Atim ring transmit done interrupt.
1337          */
1338         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1339                 rt2500pci_txdone(rt2x00dev, RT2X00_BCN_QUEUE_ATIM);
1340
1341         /*
1342          * 4 - Priority ring transmit done interrupt.
1343          */
1344         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1345                 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1346
1347         /*
1348          * 5 - Tx ring transmit done interrupt.
1349          */
1350         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1351                 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1352
1353         return IRQ_HANDLED;
1354 }
1355
1356 /*
1357  * Device probe functions.
1358  */
1359 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1360 {
1361         struct eeprom_93cx6 eeprom;
1362         u32 reg;
1363         u16 word;
1364         u8 *mac;
1365
1366         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1367
1368         eeprom.data = rt2x00dev;
1369         eeprom.register_read = rt2500pci_eepromregister_read;
1370         eeprom.register_write = rt2500pci_eepromregister_write;
1371         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1372             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1373         eeprom.reg_data_in = 0;
1374         eeprom.reg_data_out = 0;
1375         eeprom.reg_data_clock = 0;
1376         eeprom.reg_chip_select = 0;
1377
1378         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1379                                EEPROM_SIZE / sizeof(u16));
1380
1381         /*
1382          * Start validation of the data that has been read.
1383          */
1384         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1385         if (!is_valid_ether_addr(mac)) {
1386                 DECLARE_MAC_BUF(macbuf);
1387
1388                 random_ether_addr(mac);
1389                 EEPROM(rt2x00dev, "MAC: %s\n",
1390                        print_mac(macbuf, mac));
1391         }
1392
1393         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1394         if (word == 0xffff) {
1395                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1396                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1397                                    ANTENNA_SW_DIVERSITY);
1398                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1399                                    ANTENNA_SW_DIVERSITY);
1400                 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1401                                    LED_MODE_DEFAULT);
1402                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1403                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1404                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1405                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1406                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1407         }
1408
1409         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1410         if (word == 0xffff) {
1411                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1412                 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1413                 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1414                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1415                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1416         }
1417
1418         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1419         if (word == 0xffff) {
1420                 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1421                                    DEFAULT_RSSI_OFFSET);
1422                 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1423                 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1424         }
1425
1426         return 0;
1427 }
1428
1429 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1430 {
1431         u32 reg;
1432         u16 value;
1433         u16 eeprom;
1434
1435         /*
1436          * Read EEPROM word for configuration.
1437          */
1438         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1439
1440         /*
1441          * Identify RF chipset.
1442          */
1443         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1444         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1445         rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1446
1447         if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1448             !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1449             !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1450             !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1451             !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1452             !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1453                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1454                 return -ENODEV;
1455         }
1456
1457         /*
1458          * Identify default antenna configuration.
1459          */
1460         rt2x00dev->default_ant.tx =
1461             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1462         rt2x00dev->default_ant.rx =
1463             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1464
1465         /*
1466          * Store led mode, for correct led behaviour.
1467          */
1468 #ifdef CONFIG_RT2500PCI_LEDS
1469         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1470
1471         switch (value) {
1472         case LED_MODE_ASUS:
1473         case LED_MODE_ALPHA:
1474         case LED_MODE_DEFAULT:
1475                 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1476                 break;
1477         case LED_MODE_TXRX_ACTIVITY:
1478                 rt2x00dev->led_flags =
1479                     LED_SUPPORT_RADIO | LED_SUPPORT_ACTIVITY;
1480                 break;
1481         case LED_MODE_SIGNAL_STRENGTH:
1482                 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1483                 break;
1484         }
1485 #endif /* CONFIG_RT2500PCI_LEDS */
1486
1487         /*
1488          * Detect if this device has an hardware controlled radio.
1489          */
1490 #ifdef CONFIG_RT2500PCI_RFKILL
1491         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1492                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1493 #endif /* CONFIG_RT2500PCI_RFKILL */
1494
1495         /*
1496          * Check if the BBP tuning should be enabled.
1497          */
1498         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1499
1500         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1501                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1502
1503         /*
1504          * Read the RSSI <-> dBm offset information.
1505          */
1506         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1507         rt2x00dev->rssi_offset =
1508             rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1509
1510         return 0;
1511 }
1512
1513 /*
1514  * RF value list for RF2522
1515  * Supports: 2.4 GHz
1516  */
1517 static const struct rf_channel rf_vals_bg_2522[] = {
1518         { 1,  0x00002050, 0x000c1fda, 0x00000101, 0 },
1519         { 2,  0x00002050, 0x000c1fee, 0x00000101, 0 },
1520         { 3,  0x00002050, 0x000c2002, 0x00000101, 0 },
1521         { 4,  0x00002050, 0x000c2016, 0x00000101, 0 },
1522         { 5,  0x00002050, 0x000c202a, 0x00000101, 0 },
1523         { 6,  0x00002050, 0x000c203e, 0x00000101, 0 },
1524         { 7,  0x00002050, 0x000c2052, 0x00000101, 0 },
1525         { 8,  0x00002050, 0x000c2066, 0x00000101, 0 },
1526         { 9,  0x00002050, 0x000c207a, 0x00000101, 0 },
1527         { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1528         { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1529         { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1530         { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1531         { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1532 };
1533
1534 /*
1535  * RF value list for RF2523
1536  * Supports: 2.4 GHz
1537  */
1538 static const struct rf_channel rf_vals_bg_2523[] = {
1539         { 1,  0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1540         { 2,  0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1541         { 3,  0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1542         { 4,  0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1543         { 5,  0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1544         { 6,  0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1545         { 7,  0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1546         { 8,  0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1547         { 9,  0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1548         { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1549         { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1550         { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1551         { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1552         { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1553 };
1554
1555 /*
1556  * RF value list for RF2524
1557  * Supports: 2.4 GHz
1558  */
1559 static const struct rf_channel rf_vals_bg_2524[] = {
1560         { 1,  0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1561         { 2,  0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1562         { 3,  0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1563         { 4,  0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1564         { 5,  0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1565         { 6,  0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1566         { 7,  0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1567         { 8,  0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1568         { 9,  0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1569         { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1570         { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1571         { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1572         { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1573         { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1574 };
1575
1576 /*
1577  * RF value list for RF2525
1578  * Supports: 2.4 GHz
1579  */
1580 static const struct rf_channel rf_vals_bg_2525[] = {
1581         { 1,  0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1582         { 2,  0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1583         { 3,  0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1584         { 4,  0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1585         { 5,  0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1586         { 6,  0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1587         { 7,  0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1588         { 8,  0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1589         { 9,  0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1590         { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1591         { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1592         { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1593         { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1594         { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1595 };
1596
1597 /*
1598  * RF value list for RF2525e
1599  * Supports: 2.4 GHz
1600  */
1601 static const struct rf_channel rf_vals_bg_2525e[] = {
1602         { 1,  0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1603         { 2,  0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1604         { 3,  0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1605         { 4,  0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1606         { 5,  0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1607         { 6,  0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1608         { 7,  0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1609         { 8,  0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1610         { 9,  0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1611         { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1612         { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1613         { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1614         { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1615         { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1616 };
1617
1618 /*
1619  * RF value list for RF5222
1620  * Supports: 2.4 GHz & 5.2 GHz
1621  */
1622 static const struct rf_channel rf_vals_5222[] = {
1623         { 1,  0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1624         { 2,  0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1625         { 3,  0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1626         { 4,  0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1627         { 5,  0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1628         { 6,  0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1629         { 7,  0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1630         { 8,  0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1631         { 9,  0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1632         { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1633         { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1634         { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1635         { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1636         { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1637
1638         /* 802.11 UNI / HyperLan 2 */
1639         { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1640         { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1641         { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1642         { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1643         { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1644         { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1645         { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1646         { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1647
1648         /* 802.11 HyperLan 2 */
1649         { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1650         { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1651         { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1652         { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1653         { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1654         { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1655         { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1656         { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1657         { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1658         { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1659
1660         /* 802.11 UNII */
1661         { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1662         { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1663         { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1664         { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1665         { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1666 };
1667
1668 static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1669 {
1670         struct hw_mode_spec *spec = &rt2x00dev->spec;
1671         u8 *txpower;
1672         unsigned int i;
1673
1674         /*
1675          * Initialize all hw fields.
1676          */
1677         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1678         rt2x00dev->hw->extra_tx_headroom = 0;
1679         rt2x00dev->hw->max_signal = MAX_SIGNAL;
1680         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1681         rt2x00dev->hw->queues = 2;
1682
1683         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1684         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1685                                 rt2x00_eeprom_addr(rt2x00dev,
1686                                                    EEPROM_MAC_ADDR_0));
1687
1688         /*
1689          * Convert tx_power array in eeprom.
1690          */
1691         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1692         for (i = 0; i < 14; i++)
1693                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1694
1695         /*
1696          * Initialize hw_mode information.
1697          */
1698         spec->supported_bands = SUPPORT_BAND_2GHZ;
1699         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1700         spec->tx_power_a = NULL;
1701         spec->tx_power_bg = txpower;
1702         spec->tx_power_default = DEFAULT_TXPOWER;
1703
1704         if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1705                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1706                 spec->channels = rf_vals_bg_2522;
1707         } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1708                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1709                 spec->channels = rf_vals_bg_2523;
1710         } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1711                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1712                 spec->channels = rf_vals_bg_2524;
1713         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1714                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1715                 spec->channels = rf_vals_bg_2525;
1716         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1717                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1718                 spec->channels = rf_vals_bg_2525e;
1719         } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1720                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1721                 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1722                 spec->channels = rf_vals_5222;
1723         }
1724 }
1725
1726 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1727 {
1728         int retval;
1729
1730         /*
1731          * Allocate eeprom data.
1732          */
1733         retval = rt2500pci_validate_eeprom(rt2x00dev);
1734         if (retval)
1735                 return retval;
1736
1737         retval = rt2500pci_init_eeprom(rt2x00dev);
1738         if (retval)
1739                 return retval;
1740
1741         /*
1742          * Initialize hw specifications.
1743          */
1744         rt2500pci_probe_hw_mode(rt2x00dev);
1745
1746         /*
1747          * This device requires the atim queue
1748          */
1749         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1750
1751         /*
1752          * Set the rssi offset.
1753          */
1754         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1755
1756         return 0;
1757 }
1758
1759 /*
1760  * IEEE80211 stack callback functions.
1761  */
1762 static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1763                                      u32 short_retry, u32 long_retry)
1764 {
1765         struct rt2x00_dev *rt2x00dev = hw->priv;
1766         u32 reg;
1767
1768         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1769         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1770         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1771         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1772
1773         return 0;
1774 }
1775
1776 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1777 {
1778         struct rt2x00_dev *rt2x00dev = hw->priv;
1779         u64 tsf;
1780         u32 reg;
1781
1782         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1783         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1784         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1785         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1786
1787         return tsf;
1788 }
1789
1790 static int rt2500pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1791                                    struct ieee80211_tx_control *control)
1792 {
1793         struct rt2x00_dev *rt2x00dev = hw->priv;
1794         struct rt2x00_intf *intf = vif_to_intf(control->vif);
1795         struct queue_entry_priv_pci_tx *priv_tx;
1796         struct skb_frame_desc *skbdesc;
1797         u32 reg;
1798
1799         if (unlikely(!intf->beacon))
1800                 return -ENOBUFS;
1801
1802         priv_tx = intf->beacon->priv_data;
1803
1804         /*
1805          * Fill in skb descriptor
1806          */
1807         skbdesc = get_skb_frame_desc(skb);
1808         memset(skbdesc, 0, sizeof(*skbdesc));
1809         skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
1810         skbdesc->data = skb->data;
1811         skbdesc->data_len = skb->len;
1812         skbdesc->desc = priv_tx->desc;
1813         skbdesc->desc_len = intf->beacon->queue->desc_size;
1814         skbdesc->entry = intf->beacon;
1815
1816         /*
1817          * Disable beaconing while we are reloading the beacon data,
1818          * otherwise we might be sending out invalid data.
1819          */
1820         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1821         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1822         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1823         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1824         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1825
1826         /*
1827          * mac80211 doesn't provide the control->queue variable
1828          * for beacons. Set our own queue identification so
1829          * it can be used during descriptor initialization.
1830          */
1831         control->queue = RT2X00_BCN_QUEUE_BEACON;
1832         rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1833
1834         /*
1835          * Enable beacon generation.
1836          * Write entire beacon with descriptor to register,
1837          * and kick the beacon generator.
1838          */
1839         memcpy(priv_tx->data, skb->data, skb->len);
1840         rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
1841
1842         return 0;
1843 }
1844
1845 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1846 {
1847         struct rt2x00_dev *rt2x00dev = hw->priv;
1848         u32 reg;
1849
1850         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1851         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1852 }
1853
1854 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1855         .tx                     = rt2x00mac_tx,
1856         .start                  = rt2x00mac_start,
1857         .stop                   = rt2x00mac_stop,
1858         .add_interface          = rt2x00mac_add_interface,
1859         .remove_interface       = rt2x00mac_remove_interface,
1860         .config                 = rt2x00mac_config,
1861         .config_interface       = rt2x00mac_config_interface,
1862         .configure_filter       = rt2x00mac_configure_filter,
1863         .get_stats              = rt2x00mac_get_stats,
1864         .set_retry_limit        = rt2500pci_set_retry_limit,
1865         .bss_info_changed       = rt2x00mac_bss_info_changed,
1866         .conf_tx                = rt2x00mac_conf_tx,
1867         .get_tx_stats           = rt2x00mac_get_tx_stats,
1868         .get_tsf                = rt2500pci_get_tsf,
1869         .beacon_update          = rt2500pci_beacon_update,
1870         .tx_last_beacon         = rt2500pci_tx_last_beacon,
1871 };
1872
1873 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1874         .irq_handler            = rt2500pci_interrupt,
1875         .probe_hw               = rt2500pci_probe_hw,
1876         .initialize             = rt2x00pci_initialize,
1877         .uninitialize           = rt2x00pci_uninitialize,
1878         .init_rxentry           = rt2500pci_init_rxentry,
1879         .init_txentry           = rt2500pci_init_txentry,
1880         .set_device_state       = rt2500pci_set_device_state,
1881         .rfkill_poll            = rt2500pci_rfkill_poll,
1882         .link_stats             = rt2500pci_link_stats,
1883         .reset_tuner            = rt2500pci_reset_tuner,
1884         .link_tuner             = rt2500pci_link_tuner,
1885         .led_brightness         = rt2500pci_led_brightness,
1886         .write_tx_desc          = rt2500pci_write_tx_desc,
1887         .write_tx_data          = rt2x00pci_write_tx_data,
1888         .kick_tx_queue          = rt2500pci_kick_tx_queue,
1889         .fill_rxdone            = rt2500pci_fill_rxdone,
1890         .config_filter          = rt2500pci_config_filter,
1891         .config_intf            = rt2500pci_config_intf,
1892         .config_erp             = rt2500pci_config_erp,
1893         .config                 = rt2500pci_config,
1894 };
1895
1896 static const struct data_queue_desc rt2500pci_queue_rx = {
1897         .entry_num              = RX_ENTRIES,
1898         .data_size              = DATA_FRAME_SIZE,
1899         .desc_size              = RXD_DESC_SIZE,
1900         .priv_size              = sizeof(struct queue_entry_priv_pci_rx),
1901 };
1902
1903 static const struct data_queue_desc rt2500pci_queue_tx = {
1904         .entry_num              = TX_ENTRIES,
1905         .data_size              = DATA_FRAME_SIZE,
1906         .desc_size              = TXD_DESC_SIZE,
1907         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1908 };
1909
1910 static const struct data_queue_desc rt2500pci_queue_bcn = {
1911         .entry_num              = BEACON_ENTRIES,
1912         .data_size              = MGMT_FRAME_SIZE,
1913         .desc_size              = TXD_DESC_SIZE,
1914         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1915 };
1916
1917 static const struct data_queue_desc rt2500pci_queue_atim = {
1918         .entry_num              = ATIM_ENTRIES,
1919         .data_size              = DATA_FRAME_SIZE,
1920         .desc_size              = TXD_DESC_SIZE,
1921         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1922 };
1923
1924 static const struct rt2x00_ops rt2500pci_ops = {
1925         .name           = KBUILD_MODNAME,
1926         .max_sta_intf   = 1,
1927         .max_ap_intf    = 1,
1928         .eeprom_size    = EEPROM_SIZE,
1929         .rf_size        = RF_SIZE,
1930         .rx             = &rt2500pci_queue_rx,
1931         .tx             = &rt2500pci_queue_tx,
1932         .bcn            = &rt2500pci_queue_bcn,
1933         .atim           = &rt2500pci_queue_atim,
1934         .lib            = &rt2500pci_rt2x00_ops,
1935         .hw             = &rt2500pci_mac80211_ops,
1936 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1937         .debugfs        = &rt2500pci_rt2x00debug,
1938 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1939 };
1940
1941 /*
1942  * RT2500pci module information.
1943  */
1944 static struct pci_device_id rt2500pci_device_table[] = {
1945         { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1946         { 0, }
1947 };
1948
1949 MODULE_AUTHOR(DRV_PROJECT);
1950 MODULE_VERSION(DRV_VERSION);
1951 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1952 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1953 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1954 MODULE_LICENSE("GPL");
1955
1956 static struct pci_driver rt2500pci_driver = {
1957         .name           = KBUILD_MODNAME,
1958         .id_table       = rt2500pci_device_table,
1959         .probe          = rt2x00pci_probe,
1960         .remove         = __devexit_p(rt2x00pci_remove),
1961         .suspend        = rt2x00pci_suspend,
1962         .resume         = rt2x00pci_resume,
1963 };
1964
1965 static int __init rt2500pci_init(void)
1966 {
1967         return pci_register_driver(&rt2500pci_driver);
1968 }
1969
1970 static void __exit rt2500pci_exit(void)
1971 {
1972         pci_unregister_driver(&rt2500pci_driver);
1973 }
1974
1975 module_init(rt2500pci_init);
1976 module_exit(rt2500pci_exit);