SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/rt2x00/rt2500pci.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2500pci
  23         Abstract: rt2500pci device specific routines.
  24         Supported chipsets: RT2560.
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00pci.h"
  37 #include "rt2500pci.h"
  38
  39 /*
  40  * Register access.
  41  * All access to the CSR registers will go through the methods
  42  * rt2x00pci_register_read and rt2x00pci_register_write.
  43  * BBP and RF register require indirect register access,
  44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  45  * These indirect registers work with busy bits,
  46  * and we will try maximal REGISTER_BUSY_COUNT times to access
  47  * the register while taking a REGISTER_BUSY_DELAY us delay
  48  * between each attampt. When the busy bit is still set at that time,
  49  * the access attempt is considered to have failed,
  50  * and we will print an error.
  51  */
  52 static u32 rt2500pci_bbp_check(struct rt2x00_dev *rt2x00dev)
  53 {
  54         u32 reg;
  55         unsigned int i;
  56
  57         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  58                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  59                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  60                         break;
  61                 udelay(REGISTER_BUSY_DELAY);
  62         }
  63
  64         return reg;
  65 }
  66
  67 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  68                                 const unsigned int word, const u8 value)
  69 {
  70         u32 reg;
  71
  72         /*
  73          * Wait until the BBP becomes ready.
  74          */
  75         reg = rt2500pci_bbp_check(rt2x00dev);
  76         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  77                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  78                 return;
  79         }
  80
  81         /*
  82          * Write the data into the BBP.
  83          */
  84         reg = 0;
  85         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  86         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  87         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  88         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  89
  90         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  91 }
  92
  93 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  94                                const unsigned int word, u8 *value)
  95 {
  96         u32 reg;
  97
  98         /*
  99          * Wait until the BBP becomes ready.
 100          */
 101         reg = rt2500pci_bbp_check(rt2x00dev);
 102         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 103                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 104                 return;
 105         }
 106
 107         /*
 108          * Write the request into the BBP.
 109          */
 110         reg = 0;
 111         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 112         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 113         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 114
 115         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 116
 117         /*
 118          * Wait until the BBP becomes ready.
 119          */
 120         reg = rt2500pci_bbp_check(rt2x00dev);
 121         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 122                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 123                 *value = 0xff;
 124                 return;
 125         }
 126
 127         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 128 }
 129
 130 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
 131                                const unsigned int word, const u32 value)
 132 {
 133         u32 reg;
 134         unsigned int i;
 135
 136         if (!word)
 137                 return;
 138
 139         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 140                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
 141                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
 142                         goto rf_write;
 143                 udelay(REGISTER_BUSY_DELAY);
 144         }
 145
 146         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
 147         return;
 148
 149 rf_write:
 150         reg = 0;
 151         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 152         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 153         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 154         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 155
 156         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 157         rt2x00_rf_write(rt2x00dev, word, value);
 158 }
 159
 160 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 161 {
 162         struct rt2x00_dev *rt2x00dev = eeprom->data;
 163         u32 reg;
 164
 165         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 166
 167         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 168         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 169         eeprom->reg_data_clock =
 170             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 171         eeprom->reg_chip_select =
 172             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 173 }
 174
 175 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 176 {
 177         struct rt2x00_dev *rt2x00dev = eeprom->data;
 178         u32 reg = 0;
 179
 180         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 181         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 182         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 183                            !!eeprom->reg_data_clock);
 184         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 185                            !!eeprom->reg_chip_select);
 186
 187         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 188 }
 189
 190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 191 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 192
 193 static void rt2500pci_read_csr(struct rt2x00_dev *rt2x00dev,
 194                                const unsigned int word, u32 *data)
 195 {
 196         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 197 }
 198
 199 static void rt2500pci_write_csr(struct rt2x00_dev *rt2x00dev,
 200                                 const unsigned int word, u32 data)
 201 {
 202         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 203 }
 204
 205 static const struct rt2x00debug rt2500pci_rt2x00debug = {
 206         .owner  = THIS_MODULE,
 207         .csr    = {
 208                 .read           = rt2500pci_read_csr,
 209                 .write          = rt2500pci_write_csr,
 210                 .word_size      = sizeof(u32),
 211                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 212         },
 213         .eeprom = {
 214                 .read           = rt2x00_eeprom_read,
 215                 .write          = rt2x00_eeprom_write,
 216                 .word_size      = sizeof(u16),
 217                 .word_count     = EEPROM_SIZE / sizeof(u16),
 218         },
 219         .bbp    = {
 220                 .read           = rt2500pci_bbp_read,
 221                 .write          = rt2500pci_bbp_write,
 222                 .word_size      = sizeof(u8),
 223                 .word_count     = BBP_SIZE / sizeof(u8),
 224         },
 225         .rf     = {
 226                 .read           = rt2x00_rf_read,
 227                 .write          = rt2500pci_rf_write,
 228                 .word_size      = sizeof(u32),
 229                 .word_count     = RF_SIZE / sizeof(u32),
 230         },
 231 };
 232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 233
 234 #ifdef CONFIG_RT2500PCI_RFKILL
 235 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 236 {
 237         u32 reg;
 238
 239         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 240         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 241 }
 242 #else
 243 #define rt2500pci_rfkill_poll   NULL
 244 #endif /* CONFIG_RT2500PCI_RFKILL */
 245
 246 /*
 247  * Configuration handlers.
 248  */
 249 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
 250                                   struct rt2x00_intf *intf,
 251                                   struct rt2x00intf_conf *conf,
 252                                   const unsigned int flags)
 253 {
 254         struct data_queue *queue =
 255             rt2x00queue_get_queue(rt2x00dev, RT2X00_BCN_QUEUE_BEACON);
 256         unsigned int bcn_preload;
 257         u32 reg;
 258
 259         if (flags & CONFIG_UPDATE_TYPE) {
 260                 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 261
 262                 /*
 263                  * Enable beacon config
 264                  */
 265                 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
 266                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 267                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 268                 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
 269                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 270
 271                 /*
 272                  * Enable synchronisation.
 273                  */
 274                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 275                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 276                 rt2x00_set_field32(&reg, CSR14_TBCN,
 277                                    (conf->sync == TSF_SYNC_BEACON));
 278                 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 279                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 280                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 281         }
 282
 283         if (flags & CONFIG_UPDATE_MAC)
 284                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
 285                                               conf->mac, sizeof(conf->mac));
 286
 287         if (flags & CONFIG_UPDATE_BSSID)
 288                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
 289                                               conf->bssid, sizeof(conf->bssid));
 290 }
 291
 292 static int rt2500pci_config_preamble(struct rt2x00_dev *rt2x00dev,
 293                                      const int short_preamble,
 294                                      const int ack_timeout,
 295                                      const int ack_consume_time)
 296 {
 297         int preamble_mask;
 298         u32 reg;
 299
 300         /*
 301          * When short preamble is enabled, we should set bit 0x08
 302          */
 303         preamble_mask = short_preamble << 3;
 304
 305         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 306         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, ack_timeout);
 307         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
 308         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 309
 310         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 311         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
 312         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 313         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
 314         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 315
 316         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 317         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 318         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 319         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
 320         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 321
 322         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 323         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 324         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 325         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
 326         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 327
 328         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 329         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 330         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 331         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
 332         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 333
 334         return 0;
 335 }
 336
 337 static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 338                                      const int basic_rate_mask)
 339 {
 340         rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
 341 }
 342
 343 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
 344                                      struct rf_channel *rf, const int txpower)
 345 {
 346         u8 r70;
 347
 348         /*
 349          * Set TXpower.
 350          */
 351         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 352
 353         /*
 354          * Switch on tuning bits.
 355          * For RT2523 devices we do not need to update the R1 register.
 356          */
 357         if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
 358                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 359         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 360
 361         /*
 362          * For RT2525 we should first set the channel to half band higher.
 363          */
 364         if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
 365                 static const u32 vals[] = {
 366                         0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
 367                         0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
 368                         0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
 369                         0x00080d2e, 0x00080d3a
 370                 };
 371
 372                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 373                 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
 374                 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 375                 if (rf->rf4)
 376                         rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 377         }
 378
 379         rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 380         rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
 381         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 382         if (rf->rf4)
 383                 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 384
 385         /*
 386          * Channel 14 requires the Japan filter bit to be set.
 387          */
 388         r70 = 0x46;
 389         rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
 390         rt2500pci_bbp_write(rt2x00dev, 70, r70);
 391
 392         msleep(1);
 393
 394         /*
 395          * Switch off tuning bits.
 396          * For RT2523 devices we do not need to update the R1 register.
 397          */
 398         if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
 399                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 400                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 401         }
 402
 403         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 404         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 405
 406         /*
 407          * Clear false CRC during channel switch.
 408          */
 409         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
 410 }
 411
 412 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 413                                      const int txpower)
 414 {
 415         u32 rf3;
 416
 417         rt2x00_rf_read(rt2x00dev, 3, &rf3);
 418         rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 419         rt2500pci_rf_write(rt2x00dev, 3, rf3);
 420 }
 421
 422 static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 423                                      struct antenna_setup *ant)
 424 {
 425         u32 reg;
 426         u8 r14;
 427         u8 r2;
 428
 429         rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
 430         rt2500pci_bbp_read(rt2x00dev, 14, &r14);
 431         rt2500pci_bbp_read(rt2x00dev, 2, &r2);
 432
 433         /*
 434          * Configure the TX antenna.
 435          */
 436         switch (ant->tx) {
 437         case ANTENNA_A:
 438                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
 439                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
 440                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
 441                 break;
 442         case ANTENNA_HW_DIVERSITY:
 443         case ANTENNA_SW_DIVERSITY:
 444                 /*
 445                  * NOTE: We should never come here because rt2x00lib is
 446                  * supposed to catch this and send us the correct antenna
 447                  * explicitely. However we are nog going to bug about this.
 448                  * Instead, just default to antenna B.
 449                  */
 450         case ANTENNA_B:
 451                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
 452                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
 453                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
 454                 break;
 455         }
 456
 457         /*
 458          * Configure the RX antenna.
 459          */
 460         switch (ant->rx) {
 461         case ANTENNA_A:
 462                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
 463                 break;
 464         case ANTENNA_HW_DIVERSITY:
 465         case ANTENNA_SW_DIVERSITY:
 466                 /*
 467                  * NOTE: We should never come here because rt2x00lib is
 468                  * supposed to catch this and send us the correct antenna
 469                  * explicitely. However we are nog going to bug about this.
 470                  * Instead, just default to antenna B.
 471                  */
 472         case ANTENNA_B:
 473                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
 474                 break;
 475         }
 476
 477         /*
 478          * RT2525E and RT5222 need to flip TX I/Q
 479          */
 480         if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
 481             rt2x00_rf(&rt2x00dev->chip, RF5222)) {
 482                 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
 483                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
 484                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
 485
 486                 /*
 487                  * RT2525E does not need RX I/Q Flip.
 488                  */
 489                 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
 490                         rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
 491         } else {
 492                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
 493                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
 494         }
 495
 496         rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
 497         rt2500pci_bbp_write(rt2x00dev, 14, r14);
 498         rt2500pci_bbp_write(rt2x00dev, 2, r2);
 499 }
 500
 501 static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
 502                                       struct rt2x00lib_conf *libconf)
 503 {
 504         u32 reg;
 505
 506         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 507         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
 508         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 509
 510         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 511         rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
 512         rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
 513         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 514
 515         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 516         rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
 517         rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
 518         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 519
 520         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 521         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 522         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 523         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 524
 525         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 526         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
 527                            libconf->conf->beacon_int * 16);
 528         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
 529                            libconf->conf->beacon_int * 16);
 530         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 531 }
 532
 533 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
 534                              struct rt2x00lib_conf *libconf,
 535                              const unsigned int flags)
 536 {
 537         if (flags & CONFIG_UPDATE_PHYMODE)
 538                 rt2500pci_config_phymode(rt2x00dev, libconf->basic_rates);
 539         if (flags & CONFIG_UPDATE_CHANNEL)
 540                 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
 541                                          libconf->conf->power_level);
 542         if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
 543                 rt2500pci_config_txpower(rt2x00dev,
 544                                          libconf->conf->power_level);
 545         if (flags & CONFIG_UPDATE_ANTENNA)
 546                 rt2500pci_config_antenna(rt2x00dev, &libconf->ant);
 547         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 548                 rt2500pci_config_duration(rt2x00dev, libconf);
 549 }
 550
 551 /*
 552  * LED functions.
 553  */
 554 static void rt2500pci_enable_led(struct rt2x00_dev *rt2x00dev)
 555 {
 556         u32 reg;
 557
 558         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 559
 560         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
 561         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
 562         rt2x00_set_field32(&reg, LEDCSR_LINK,
 563                            (rt2x00dev->led_mode != LED_MODE_ASUS));
 564         rt2x00_set_field32(&reg, LEDCSR_ACTIVITY,
 565                            (rt2x00dev->led_mode != LED_MODE_TXRX_ACTIVITY));
 566         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 567 }
 568
 569 static void rt2500pci_disable_led(struct rt2x00_dev *rt2x00dev)
 570 {
 571         u32 reg;
 572
 573         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 574         rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
 575         rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
 576         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 577 }
 578
 579 /*
 580  * Link tuning
 581  */
 582 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
 583                                  struct link_qual *qual)
 584 {
 585         u32 reg;
 586
 587         /*
 588          * Update FCS error count from register.
 589          */
 590         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 591         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 592
 593         /*
 594          * Update False CCA count from register.
 595          */
 596         rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
 597         qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
 598 }
 599
 600 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 601 {
 602         rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
 603         rt2x00dev->link.vgc_level = 0x48;
 604 }
 605
 606 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 607 {
 608         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
 609         u8 r17;
 610
 611         /*
 612          * To prevent collisions with MAC ASIC on chipsets
 613          * up to version C the link tuning should halt after 20
 614          * seconds while being associated.
 615          */
 616         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
 617             rt2x00dev->intf_associated &&
 618             rt2x00dev->link.count > 20)
 619                 return;
 620
 621         rt2500pci_bbp_read(rt2x00dev, 17, &r17);
 622
 623         /*
 624          * Chipset versions C and lower should directly continue
 625          * to the dynamic CCA tuning. Chipset version D and higher
 626          * should go straight to dynamic CCA tuning when they
 627          * are not associated.
 628          */
 629         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D ||
 630             !rt2x00dev->intf_associated)
 631                 goto dynamic_cca_tune;
 632
 633         /*
 634          * A too low RSSI will cause too much false CCA which will
 635          * then corrupt the R17 tuning. To remidy this the tuning should
 636          * be stopped (While making sure the R17 value will not exceed limits)
 637          */
 638         if (rssi < -80 && rt2x00dev->link.count > 20) {
 639                 if (r17 >= 0x41) {
 640                         r17 = rt2x00dev->link.vgc_level;
 641                         rt2500pci_bbp_write(rt2x00dev, 17, r17);
 642                 }
 643                 return;
 644         }
 645
 646         /*
 647          * Special big-R17 for short distance
 648          */
 649         if (rssi >= -58) {
 650                 if (r17 != 0x50)
 651                         rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
 652                 return;
 653         }
 654
 655         /*
 656          * Special mid-R17 for middle distance
 657          */
 658         if (rssi >= -74) {
 659                 if (r17 != 0x41)
 660                         rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
 661                 return;
 662         }
 663
 664         /*
 665          * Leave short or middle distance condition, restore r17
 666          * to the dynamic tuning range.
 667          */
 668         if (r17 >= 0x41) {
 669                 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
 670                 return;
 671         }
 672
 673 dynamic_cca_tune:
 674
 675         /*
 676          * R17 is inside the dynamic tuning range,
 677          * start tuning the link based on the false cca counter.
 678          */
 679         if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
 680                 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
 681                 rt2x00dev->link.vgc_level = r17;
 682         } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
 683                 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
 684                 rt2x00dev->link.vgc_level = r17;
 685         }
 686 }
 687
 688 /*
 689  * Initialization functions.
 690  */
 691 static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
 692                                    struct queue_entry *entry)
 693 {
 694         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
 695         u32 word;
 696
 697         rt2x00_desc_read(priv_rx->desc, 1, &word);
 698         rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->dma);
 699         rt2x00_desc_write(priv_rx->desc, 1, word);
 700
 701         rt2x00_desc_read(priv_rx->desc, 0, &word);
 702         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 703         rt2x00_desc_write(priv_rx->desc, 0, word);
 704 }
 705
 706 static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev,
 707                                    struct queue_entry *entry)
 708 {
 709         struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
 710         u32 word;
 711
 712         rt2x00_desc_read(priv_tx->desc, 1, &word);
 713         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->dma);
 714         rt2x00_desc_write(priv_tx->desc, 1, word);
 715
 716         rt2x00_desc_read(priv_tx->desc, 0, &word);
 717         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 718         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 719         rt2x00_desc_write(priv_tx->desc, 0, word);
 720 }
 721
 722 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
 723 {
 724         struct queue_entry_priv_pci_rx *priv_rx;
 725         struct queue_entry_priv_pci_tx *priv_tx;
 726         u32 reg;
 727
 728         /*
 729          * Initialize registers.
 730          */
 731         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 732         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 733         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 734         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
 735         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 736         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 737
 738         priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
 739         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 740         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER, priv_tx->dma);
 741         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 742
 743         priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
 744         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 745         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER, priv_tx->dma);
 746         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 747
 748         priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
 749         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 750         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER, priv_tx->dma);
 751         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 752
 753         priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
 754         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 755         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER, priv_tx->dma);
 756         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 757
 758         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 759         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 760         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 761         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 762
 763         priv_rx = rt2x00dev->rx->entries[0].priv_data;
 764         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 765         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_tx->dma);
 766         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 767
 768         return 0;
 769 }
 770
 771 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
 772 {
 773         u32 reg;
 774
 775         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 776         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 777         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
 778         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 779
 780         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 781         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 782         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 783         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 784         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 785
 786         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 787         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 788                            rt2x00dev->rx->data_size / 128);
 789         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 790
 791         /*
 792          * Always use CWmin and CWmax set in descriptor.
 793          */
 794         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 795         rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
 796         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 797
 798         rt2x00pci_register_write(rt2x00dev, CNT3, 0);
 799
 800         rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
 801         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
 802         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
 803         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
 804         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
 805         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
 806         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
 807         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
 808         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
 809         rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
 810
 811         rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
 812         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
 813         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
 814         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
 815         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
 816         rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
 817
 818         rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
 819         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
 820         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
 821         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
 822         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
 823         rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
 824
 825         rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
 826         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
 827         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
 828         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
 829         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
 830         rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
 831
 832         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 833         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
 834         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 835         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
 836         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 837         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
 838         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 839         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
 840         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
 841         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 842
 843         rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
 844         rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
 845         rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
 846         rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
 847         rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
 848         rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
 849         rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
 850         rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
 851         rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
 852
 853         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 854
 855         rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
 856         rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
 857
 858         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 859                 return -EBUSY;
 860
 861         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
 862         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 863
 864         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 865         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 866         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 867
 868         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 869         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 870         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
 871         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
 872         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 873         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
 874         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
 875         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 876
 877         rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
 878
 879         rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
 880
 881         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 882         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 883         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 884         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 885         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 886
 887         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 888         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 889         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 890         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 891
 892         /*
 893          * We must clear the FCS and FIFO error count.
 894          * These registers are cleared on read,
 895          * so we may pass a useless variable to store the value.
 896          */
 897         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 898         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 899
 900         return 0;
 901 }
 902
 903 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 904 {
 905         unsigned int i;
 906         u16 eeprom;
 907         u8 reg_id;
 908         u8 value;
 909
 910         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 911                 rt2500pci_bbp_read(rt2x00dev, 0, &value);
 912                 if ((value != 0xff) && (value != 0x00))
 913                         goto continue_csr_init;
 914                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
 915                 udelay(REGISTER_BUSY_DELAY);
 916         }
 917
 918         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 919         return -EACCES;
 920
 921 continue_csr_init:
 922         rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
 923         rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
 924         rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
 925         rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
 926         rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
 927         rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
 928         rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
 929         rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
 930         rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
 931         rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
 932         rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
 933         rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
 934         rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
 935         rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
 936         rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
 937         rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
 938         rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
 939         rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
 940         rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
 941         rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
 942         rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
 943         rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
 944         rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
 945         rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
 946         rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
 947         rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
 948         rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
 949         rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
 950         rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
 951         rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
 952
 953         DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
 954         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 955                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
 956
 957                 if (eeprom != 0xffff && eeprom != 0x0000) {
 958                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
 959                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
 960                         DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
 961                               reg_id, value);
 962                         rt2500pci_bbp_write(rt2x00dev, reg_id, value);
 963                 }
 964         }
 965         DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
 966
 967         return 0;
 968 }
 969
 970 /*
 971  * Device state switch handlers.
 972  */
 973 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 974                                 enum dev_state state)
 975 {
 976         u32 reg;
 977
 978         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 979         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
 980                            state == STATE_RADIO_RX_OFF);
 981         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 982 }
 983
 984 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 985                                  enum dev_state state)
 986 {
 987         int mask = (state == STATE_RADIO_IRQ_OFF);
 988         u32 reg;
 989
 990         /*
 991          * When interrupts are being enabled, the interrupt registers
 992          * should clear the register to assure a clean state.
 993          */
 994         if (state == STATE_RADIO_IRQ_ON) {
 995                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
 996                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
 997         }
 998
 999         /*
1000          * Only toggle the interrupts bits we are going to use.
1001          * Non-checked interrupt bits are disabled by default.
1002          */
1003         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1004         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1005         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1006         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1007         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1008         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1009         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1010 }
1011
1012 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1013 {
1014         /*
1015          * Initialize all registers.
1016          */
1017         if (rt2500pci_init_queues(rt2x00dev) ||
1018             rt2500pci_init_registers(rt2x00dev) ||
1019             rt2500pci_init_bbp(rt2x00dev)) {
1020                 ERROR(rt2x00dev, "Register initialization failed.\n");
1021                 return -EIO;
1022         }
1023
1024         /*
1025          * Enable interrupts.
1026          */
1027         rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1028
1029         /*
1030          * Enable LED
1031          */
1032         rt2500pci_enable_led(rt2x00dev);
1033
1034         return 0;
1035 }
1036
1037 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1038 {
1039         u32 reg;
1040
1041         /*
1042          * Disable LED
1043          */
1044         rt2500pci_disable_led(rt2x00dev);
1045
1046         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1047
1048         /*
1049          * Disable synchronisation.
1050          */
1051         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1052
1053         /*
1054          * Cancel RX and TX.
1055          */
1056         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1057         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1058         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1059
1060         /*
1061          * Disable interrupts.
1062          */
1063         rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1064 }
1065
1066 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1067                                enum dev_state state)
1068 {
1069         u32 reg;
1070         unsigned int i;
1071         char put_to_sleep;
1072         char bbp_state;
1073         char rf_state;
1074
1075         put_to_sleep = (state != STATE_AWAKE);
1076
1077         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1078         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1079         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1080         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1081         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1082         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1083
1084         /*
1085          * Device is not guaranteed to be in the requested state yet.
1086          * We must wait until the register indicates that the
1087          * device has entered the correct state.
1088          */
1089         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1090                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1091                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1092                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1093                 if (bbp_state == state && rf_state == state)
1094                         return 0;
1095                 msleep(10);
1096         }
1097
1098         NOTICE(rt2x00dev, "Device failed to enter state %d, "
1099                "current device state: bbp %d and rf %d.\n",
1100                state, bbp_state, rf_state);
1101
1102         return -EBUSY;
1103 }
1104
1105 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1106                                       enum dev_state state)
1107 {
1108         int retval = 0;
1109
1110         switch (state) {
1111         case STATE_RADIO_ON:
1112                 retval = rt2500pci_enable_radio(rt2x00dev);
1113                 break;
1114         case STATE_RADIO_OFF:
1115                 rt2500pci_disable_radio(rt2x00dev);
1116                 break;
1117         case STATE_RADIO_RX_ON:
1118         case STATE_RADIO_RX_ON_LINK:
1119                 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1120                 break;
1121         case STATE_RADIO_RX_OFF:
1122         case STATE_RADIO_RX_OFF_LINK:
1123                 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
1124                 break;
1125         case STATE_DEEP_SLEEP:
1126         case STATE_SLEEP:
1127         case STATE_STANDBY:
1128         case STATE_AWAKE:
1129                 retval = rt2500pci_set_state(rt2x00dev, state);
1130                 break;
1131         default:
1132                 retval = -ENOTSUPP;
1133                 break;
1134         }
1135
1136         return retval;
1137 }
1138
1139 /*
1140  * TX descriptor initialization
1141  */
1142 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1143                                     struct sk_buff *skb,
1144                                     struct txentry_desc *txdesc,
1145                                     struct ieee80211_tx_control *control)
1146 {
1147         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1148         __le32 *txd = skbdesc->desc;
1149         u32 word;
1150
1151         /*
1152          * Start writing the descriptor words.
1153          */
1154         rt2x00_desc_read(txd, 2, &word);
1155         rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1156         rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1157         rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1158         rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
1159         rt2x00_desc_write(txd, 2, word);
1160
1161         rt2x00_desc_read(txd, 3, &word);
1162         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1163         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1164         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1165         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
1166         rt2x00_desc_write(txd, 3, word);
1167
1168         rt2x00_desc_read(txd, 10, &word);
1169         rt2x00_set_field32(&word, TXD_W10_RTS,
1170                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1171         rt2x00_desc_write(txd, 10, word);
1172
1173         rt2x00_desc_read(txd, 0, &word);
1174         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1175         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1176         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1177                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1178         rt2x00_set_field32(&word, TXD_W0_ACK,
1179                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1180         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1181                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1182         rt2x00_set_field32(&word, TXD_W0_OFDM,
1183                            test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1184         rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1185         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1186         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1187                            !!(control->flags &
1188                               IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1189         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1190         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1191         rt2x00_desc_write(txd, 0, word);
1192 }
1193
1194 /*
1195  * TX data initialization
1196  */
1197 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1198                                     const unsigned int queue)
1199 {
1200         u32 reg;
1201
1202         if (queue == RT2X00_BCN_QUEUE_BEACON) {
1203                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1204                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1205                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1206                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1207                 }
1208                 return;
1209         }
1210
1211         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1212         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO,
1213                            (queue == IEEE80211_TX_QUEUE_DATA0));
1214         rt2x00_set_field32(&reg, TXCSR0_KICK_TX,
1215                            (queue == IEEE80211_TX_QUEUE_DATA1));
1216         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
1217                            (queue == RT2X00_BCN_QUEUE_ATIM));
1218         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1219 }
1220
1221 /*
1222  * RX control handlers
1223  */
1224 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1225                                   struct rxdone_entry_desc *rxdesc)
1226 {
1227         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1228         u32 word0;
1229         u32 word2;
1230
1231         rt2x00_desc_read(priv_rx->desc, 0, &word0);
1232         rt2x00_desc_read(priv_rx->desc, 2, &word2);
1233
1234         rxdesc->flags = 0;
1235         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1236                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1237         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1238                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1239
1240         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1241         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1242             entry->queue->rt2x00dev->rssi_offset;
1243         rxdesc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1244         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1245         rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
1246 }
1247
1248 /*
1249  * Interrupt functions.
1250  */
1251 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1252                              const enum ieee80211_tx_queue queue_idx)
1253 {
1254         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1255         struct queue_entry_priv_pci_tx *priv_tx;
1256         struct queue_entry *entry;
1257         struct txdone_entry_desc txdesc;
1258         u32 word;
1259
1260         while (!rt2x00queue_empty(queue)) {
1261                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1262                 priv_tx = entry->priv_data;
1263                 rt2x00_desc_read(priv_tx->desc, 0, &word);
1264
1265                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1266                     !rt2x00_get_field32(word, TXD_W0_VALID))
1267                         break;
1268
1269                 /*
1270                  * Obtain the status about this packet.
1271                  */
1272                 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT);
1273                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1274
1275                 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1276         }
1277 }
1278
1279 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1280 {
1281         struct rt2x00_dev *rt2x00dev = dev_instance;
1282         u32 reg;
1283
1284         /*
1285          * Get the interrupt sources & saved to local variable.
1286          * Write register value back to clear pending interrupts.
1287          */
1288         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1289         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1290
1291         if (!reg)
1292                 return IRQ_NONE;
1293
1294         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1295                 return IRQ_HANDLED;
1296
1297         /*
1298          * Handle interrupts, walk through all bits
1299          * and run the tasks, the bits are checked in order of
1300          * priority.
1301          */
1302
1303         /*
1304          * 1 - Beacon timer expired interrupt.
1305          */
1306         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1307                 rt2x00lib_beacondone(rt2x00dev);
1308
1309         /*
1310          * 2 - Rx ring done interrupt.
1311          */
1312         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1313                 rt2x00pci_rxdone(rt2x00dev);
1314
1315         /*
1316          * 3 - Atim ring transmit done interrupt.
1317          */
1318         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1319                 rt2500pci_txdone(rt2x00dev, RT2X00_BCN_QUEUE_ATIM);
1320
1321         /*
1322          * 4 - Priority ring transmit done interrupt.
1323          */
1324         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1325                 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1326
1327         /*
1328          * 5 - Tx ring transmit done interrupt.
1329          */
1330         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1331                 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1332
1333         return IRQ_HANDLED;
1334 }
1335
1336 /*
1337  * Device probe functions.
1338  */
1339 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1340 {
1341         struct eeprom_93cx6 eeprom;
1342         u32 reg;
1343         u16 word;
1344         u8 *mac;
1345
1346         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1347
1348         eeprom.data = rt2x00dev;
1349         eeprom.register_read = rt2500pci_eepromregister_read;
1350         eeprom.register_write = rt2500pci_eepromregister_write;
1351         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1352             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1353         eeprom.reg_data_in = 0;
1354         eeprom.reg_data_out = 0;
1355         eeprom.reg_data_clock = 0;
1356         eeprom.reg_chip_select = 0;
1357
1358         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1359                                EEPROM_SIZE / sizeof(u16));
1360
1361         /*
1362          * Start validation of the data that has been read.
1363          */
1364         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1365         if (!is_valid_ether_addr(mac)) {
1366                 DECLARE_MAC_BUF(macbuf);
1367
1368                 random_ether_addr(mac);
1369                 EEPROM(rt2x00dev, "MAC: %s\n",
1370                        print_mac(macbuf, mac));
1371         }
1372
1373         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1374         if (word == 0xffff) {
1375                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1376                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1377                                    ANTENNA_SW_DIVERSITY);
1378                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1379                                    ANTENNA_SW_DIVERSITY);
1380                 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1381                                    LED_MODE_DEFAULT);
1382                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1383                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1384                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1385                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1386                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1387         }
1388
1389         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1390         if (word == 0xffff) {
1391                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1392                 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1393                 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1394                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1395                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1396         }
1397
1398         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1399         if (word == 0xffff) {
1400                 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1401                                    DEFAULT_RSSI_OFFSET);
1402                 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1403                 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1404         }
1405
1406         return 0;
1407 }
1408
1409 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1410 {
1411         u32 reg;
1412         u16 value;
1413         u16 eeprom;
1414
1415         /*
1416          * Read EEPROM word for configuration.
1417          */
1418         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1419
1420         /*
1421          * Identify RF chipset.
1422          */
1423         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1424         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1425         rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1426
1427         if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1428             !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1429             !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1430             !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1431             !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1432             !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1433                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1434                 return -ENODEV;
1435         }
1436
1437         /*
1438          * Identify default antenna configuration.
1439          */
1440         rt2x00dev->default_ant.tx =
1441             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1442         rt2x00dev->default_ant.rx =
1443             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1444
1445         /*
1446          * Store led mode, for correct led behaviour.
1447          */
1448         rt2x00dev->led_mode =
1449             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1450
1451         /*
1452          * Detect if this device has an hardware controlled radio.
1453          */
1454 #ifdef CONFIG_RT2500PCI_RFKILL
1455         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1456                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1457 #endif /* CONFIG_RT2500PCI_RFKILL */
1458
1459         /*
1460          * Check if the BBP tuning should be enabled.
1461          */
1462         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1463
1464         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1465                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1466
1467         /*
1468          * Read the RSSI <-> dBm offset information.
1469          */
1470         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1471         rt2x00dev->rssi_offset =
1472             rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1473
1474         return 0;
1475 }
1476
1477 /*
1478  * RF value list for RF2522
1479  * Supports: 2.4 GHz
1480  */
1481 static const struct rf_channel rf_vals_bg_2522[] = {
1482         { 1,  0x00002050, 0x000c1fda, 0x00000101, 0 },
1483         { 2,  0x00002050, 0x000c1fee, 0x00000101, 0 },
1484         { 3,  0x00002050, 0x000c2002, 0x00000101, 0 },
1485         { 4,  0x00002050, 0x000c2016, 0x00000101, 0 },
1486         { 5,  0x00002050, 0x000c202a, 0x00000101, 0 },
1487         { 6,  0x00002050, 0x000c203e, 0x00000101, 0 },
1488         { 7,  0x00002050, 0x000c2052, 0x00000101, 0 },
1489         { 8,  0x00002050, 0x000c2066, 0x00000101, 0 },
1490         { 9,  0x00002050, 0x000c207a, 0x00000101, 0 },
1491         { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1492         { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1493         { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1494         { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1495         { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1496 };
1497
1498 /*
1499  * RF value list for RF2523
1500  * Supports: 2.4 GHz
1501  */
1502 static const struct rf_channel rf_vals_bg_2523[] = {
1503         { 1,  0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1504         { 2,  0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1505         { 3,  0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1506         { 4,  0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1507         { 5,  0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1508         { 6,  0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1509         { 7,  0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1510         { 8,  0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1511         { 9,  0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1512         { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1513         { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1514         { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1515         { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1516         { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1517 };
1518
1519 /*
1520  * RF value list for RF2524
1521  * Supports: 2.4 GHz
1522  */
1523 static const struct rf_channel rf_vals_bg_2524[] = {
1524         { 1,  0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1525         { 2,  0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1526         { 3,  0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1527         { 4,  0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1528         { 5,  0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1529         { 6,  0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1530         { 7,  0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1531         { 8,  0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1532         { 9,  0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1533         { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1534         { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1535         { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1536         { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1537         { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1538 };
1539
1540 /*
1541  * RF value list for RF2525
1542  * Supports: 2.4 GHz
1543  */
1544 static const struct rf_channel rf_vals_bg_2525[] = {
1545         { 1,  0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1546         { 2,  0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1547         { 3,  0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1548         { 4,  0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1549         { 5,  0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1550         { 6,  0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1551         { 7,  0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1552         { 8,  0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1553         { 9,  0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1554         { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1555         { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1556         { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1557         { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1558         { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1559 };
1560
1561 /*
1562  * RF value list for RF2525e
1563  * Supports: 2.4 GHz
1564  */
1565 static const struct rf_channel rf_vals_bg_2525e[] = {
1566         { 1,  0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1567         { 2,  0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1568         { 3,  0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1569         { 4,  0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1570         { 5,  0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1571         { 6,  0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1572         { 7,  0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1573         { 8,  0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1574         { 9,  0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1575         { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1576         { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1577         { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1578         { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1579         { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1580 };
1581
1582 /*
1583  * RF value list for RF5222
1584  * Supports: 2.4 GHz & 5.2 GHz
1585  */
1586 static const struct rf_channel rf_vals_5222[] = {
1587         { 1,  0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1588         { 2,  0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1589         { 3,  0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1590         { 4,  0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1591         { 5,  0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1592         { 6,  0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1593         { 7,  0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1594         { 8,  0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1595         { 9,  0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1596         { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1597         { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1598         { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1599         { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1600         { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1601
1602         /* 802.11 UNI / HyperLan 2 */
1603         { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1604         { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1605         { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1606         { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1607         { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1608         { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1609         { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1610         { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1611
1612         /* 802.11 HyperLan 2 */
1613         { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1614         { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1615         { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1616         { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1617         { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1618         { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1619         { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1620         { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1621         { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1622         { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1623
1624         /* 802.11 UNII */
1625         { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1626         { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1627         { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1628         { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1629         { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1630 };
1631
1632 static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1633 {
1634         struct hw_mode_spec *spec = &rt2x00dev->spec;
1635         u8 *txpower;
1636         unsigned int i;
1637
1638         /*
1639          * Initialize all hw fields.
1640          */
1641         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1642         rt2x00dev->hw->extra_tx_headroom = 0;
1643         rt2x00dev->hw->max_signal = MAX_SIGNAL;
1644         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1645         rt2x00dev->hw->queues = 2;
1646
1647         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1648         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1649                                 rt2x00_eeprom_addr(rt2x00dev,
1650                                                    EEPROM_MAC_ADDR_0));
1651
1652         /*
1653          * Convert tx_power array in eeprom.
1654          */
1655         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1656         for (i = 0; i < 14; i++)
1657                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1658
1659         /*
1660          * Initialize hw_mode information.
1661          */
1662         spec->num_modes = 2;
1663         spec->num_rates = 12;
1664         spec->tx_power_a = NULL;
1665         spec->tx_power_bg = txpower;
1666         spec->tx_power_default = DEFAULT_TXPOWER;
1667
1668         if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1669                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1670                 spec->channels = rf_vals_bg_2522;
1671         } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1672                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1673                 spec->channels = rf_vals_bg_2523;
1674         } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1675                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1676                 spec->channels = rf_vals_bg_2524;
1677         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1678                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1679                 spec->channels = rf_vals_bg_2525;
1680         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1681                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1682                 spec->channels = rf_vals_bg_2525e;
1683         } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1684                 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1685                 spec->channels = rf_vals_5222;
1686                 spec->num_modes = 3;
1687         }
1688 }
1689
1690 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1691 {
1692         int retval;
1693
1694         /*
1695          * Allocate eeprom data.
1696          */
1697         retval = rt2500pci_validate_eeprom(rt2x00dev);
1698         if (retval)
1699                 return retval;
1700
1701         retval = rt2500pci_init_eeprom(rt2x00dev);
1702         if (retval)
1703                 return retval;
1704
1705         /*
1706          * Initialize hw specifications.
1707          */
1708         rt2500pci_probe_hw_mode(rt2x00dev);
1709
1710         /*
1711          * This device requires the atim queue
1712          */
1713         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1714
1715         /*
1716          * Set the rssi offset.
1717          */
1718         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1719
1720         return 0;
1721 }
1722
1723 /*
1724  * IEEE80211 stack callback functions.
1725  */
1726 static void rt2500pci_configure_filter(struct ieee80211_hw *hw,
1727                                        unsigned int changed_flags,
1728                                        unsigned int *total_flags,
1729                                        int mc_count,
1730                                        struct dev_addr_list *mc_list)
1731 {
1732         struct rt2x00_dev *rt2x00dev = hw->priv;
1733         u32 reg;
1734
1735         /*
1736          * Mask off any flags we are going to ignore from
1737          * the total_flags field.
1738          */
1739         *total_flags &=
1740             FIF_ALLMULTI |
1741             FIF_FCSFAIL |
1742             FIF_PLCPFAIL |
1743             FIF_CONTROL |
1744             FIF_OTHER_BSS |
1745             FIF_PROMISC_IN_BSS;
1746
1747         /*
1748          * Apply some rules to the filters:
1749          * - Some filters imply different filters to be set.
1750          * - Some things we can't filter out at all.
1751          */
1752         if (mc_count)
1753                 *total_flags |= FIF_ALLMULTI;
1754         if (*total_flags & FIF_OTHER_BSS ||
1755             *total_flags & FIF_PROMISC_IN_BSS)
1756                 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1757
1758         /*
1759          * Check if there is any work left for us.
1760          */
1761         if (rt2x00dev->packet_filter == *total_flags)
1762                 return;
1763         rt2x00dev->packet_filter = *total_flags;
1764
1765         /*
1766          * Start configuration steps.
1767          * Note that the version error will always be dropped
1768          * and broadcast frames will always be accepted since
1769          * there is no filter for it at this time.
1770          */
1771         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1772         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1773                            !(*total_flags & FIF_FCSFAIL));
1774         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1775                            !(*total_flags & FIF_PLCPFAIL));
1776         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1777                            !(*total_flags & FIF_CONTROL));
1778         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1779                            !(*total_flags & FIF_PROMISC_IN_BSS));
1780         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1781                            !(*total_flags & FIF_PROMISC_IN_BSS));
1782         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1783         rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
1784                            !(*total_flags & FIF_ALLMULTI));
1785         rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
1786         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1787 }
1788
1789 static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1790                                      u32 short_retry, u32 long_retry)
1791 {
1792         struct rt2x00_dev *rt2x00dev = hw->priv;
1793         u32 reg;
1794
1795         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1796         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1797         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1798         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1799
1800         return 0;
1801 }
1802
1803 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1804 {
1805         struct rt2x00_dev *rt2x00dev = hw->priv;
1806         u64 tsf;
1807         u32 reg;
1808
1809         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1810         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1811         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1812         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1813
1814         return tsf;
1815 }
1816
1817 static void rt2500pci_reset_tsf(struct ieee80211_hw *hw)
1818 {
1819         struct rt2x00_dev *rt2x00dev = hw->priv;
1820
1821         rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1822         rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1823 }
1824
1825 static int rt2500pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1826                                    struct ieee80211_tx_control *control)
1827 {
1828         struct rt2x00_dev *rt2x00dev = hw->priv;
1829         struct rt2x00_intf *intf = vif_to_intf(control->vif);
1830         struct queue_entry_priv_pci_tx *priv_tx;
1831         struct skb_frame_desc *skbdesc;
1832
1833         if (unlikely(!intf->beacon))
1834                 return -ENOBUFS;
1835
1836         priv_tx = intf->beacon->priv_data;
1837
1838         /*
1839          * Fill in skb descriptor
1840          */
1841         skbdesc = get_skb_frame_desc(skb);
1842         memset(skbdesc, 0, sizeof(*skbdesc));
1843         skbdesc->data = skb->data;
1844         skbdesc->data_len = skb->len;
1845         skbdesc->desc = priv_tx->desc;
1846         skbdesc->desc_len = intf->beacon->queue->desc_size;
1847         skbdesc->entry = intf->beacon;
1848
1849         /*
1850          * mac80211 doesn't provide the control->queue variable
1851          * for beacons. Set our own queue identification so
1852          * it can be used during descriptor initialization.
1853          */
1854         control->queue = RT2X00_BCN_QUEUE_BEACON;
1855         rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1856
1857         /*
1858          * Enable beacon generation.
1859          * Write entire beacon with descriptor to register,
1860          * and kick the beacon generator.
1861          */
1862         memcpy(priv_tx->data, skb->data, skb->len);
1863         rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
1864
1865         return 0;
1866 }
1867
1868 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1869 {
1870         struct rt2x00_dev *rt2x00dev = hw->priv;
1871         u32 reg;
1872
1873         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1874         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1875 }
1876
1877 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1878         .tx                     = rt2x00mac_tx,
1879         .start                  = rt2x00mac_start,
1880         .stop                   = rt2x00mac_stop,
1881         .add_interface          = rt2x00mac_add_interface,
1882         .remove_interface       = rt2x00mac_remove_interface,
1883         .config                 = rt2x00mac_config,
1884         .config_interface       = rt2x00mac_config_interface,
1885         .configure_filter       = rt2500pci_configure_filter,
1886         .get_stats              = rt2x00mac_get_stats,
1887         .set_retry_limit        = rt2500pci_set_retry_limit,
1888         .bss_info_changed       = rt2x00mac_bss_info_changed,
1889         .conf_tx                = rt2x00mac_conf_tx,
1890         .get_tx_stats           = rt2x00mac_get_tx_stats,
1891         .get_tsf                = rt2500pci_get_tsf,
1892         .reset_tsf              = rt2500pci_reset_tsf,
1893         .beacon_update          = rt2500pci_beacon_update,
1894         .tx_last_beacon         = rt2500pci_tx_last_beacon,
1895 };
1896
1897 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1898         .irq_handler            = rt2500pci_interrupt,
1899         .probe_hw               = rt2500pci_probe_hw,
1900         .initialize             = rt2x00pci_initialize,
1901         .uninitialize           = rt2x00pci_uninitialize,
1902         .init_rxentry           = rt2500pci_init_rxentry,
1903         .init_txentry           = rt2500pci_init_txentry,
1904         .set_device_state       = rt2500pci_set_device_state,
1905         .rfkill_poll            = rt2500pci_rfkill_poll,
1906         .link_stats             = rt2500pci_link_stats,
1907         .reset_tuner            = rt2500pci_reset_tuner,
1908         .link_tuner             = rt2500pci_link_tuner,
1909         .write_tx_desc          = rt2500pci_write_tx_desc,
1910         .write_tx_data          = rt2x00pci_write_tx_data,
1911         .kick_tx_queue          = rt2500pci_kick_tx_queue,
1912         .fill_rxdone            = rt2500pci_fill_rxdone,
1913         .config_intf            = rt2500pci_config_intf,
1914         .config_preamble        = rt2500pci_config_preamble,
1915         .config                 = rt2500pci_config,
1916 };
1917
1918 static const struct data_queue_desc rt2500pci_queue_rx = {
1919         .entry_num              = RX_ENTRIES,
1920         .data_size              = DATA_FRAME_SIZE,
1921         .desc_size              = RXD_DESC_SIZE,
1922         .priv_size              = sizeof(struct queue_entry_priv_pci_rx),
1923 };
1924
1925 static const struct data_queue_desc rt2500pci_queue_tx = {
1926         .entry_num              = TX_ENTRIES,
1927         .data_size              = DATA_FRAME_SIZE,
1928         .desc_size              = TXD_DESC_SIZE,
1929         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1930 };
1931
1932 static const struct data_queue_desc rt2500pci_queue_bcn = {
1933         .entry_num              = BEACON_ENTRIES,
1934         .data_size              = MGMT_FRAME_SIZE,
1935         .desc_size              = TXD_DESC_SIZE,
1936         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1937 };
1938
1939 static const struct data_queue_desc rt2500pci_queue_atim = {
1940         .entry_num              = ATIM_ENTRIES,
1941         .data_size              = DATA_FRAME_SIZE,
1942         .desc_size              = TXD_DESC_SIZE,
1943         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1944 };
1945
1946 static const struct rt2x00_ops rt2500pci_ops = {
1947         .name           = KBUILD_MODNAME,
1948         .max_sta_intf   = 1,
1949         .max_ap_intf    = 1,
1950         .eeprom_size    = EEPROM_SIZE,
1951         .rf_size        = RF_SIZE,
1952         .rx             = &rt2500pci_queue_rx,
1953         .tx             = &rt2500pci_queue_tx,
1954         .bcn            = &rt2500pci_queue_bcn,
1955         .atim           = &rt2500pci_queue_atim,
1956         .lib            = &rt2500pci_rt2x00_ops,
1957         .hw             = &rt2500pci_mac80211_ops,
1958 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1959         .debugfs        = &rt2500pci_rt2x00debug,
1960 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1961 };
1962
1963 /*
1964  * RT2500pci module information.
1965  */
1966 static struct pci_device_id rt2500pci_device_table[] = {
1967         { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1968         { 0, }
1969 };
1970
1971 MODULE_AUTHOR(DRV_PROJECT);
1972 MODULE_VERSION(DRV_VERSION);
1973 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1974 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1975 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1976 MODULE_LICENSE("GPL");
1977
1978 static struct pci_driver rt2500pci_driver = {
1979         .name           = KBUILD_MODNAME,
1980         .id_table       = rt2500pci_device_table,
1981         .probe          = rt2x00pci_probe,
1982         .remove         = __devexit_p(rt2x00pci_remove),
1983         .suspend        = rt2x00pci_suspend,
1984         .resume         = rt2x00pci_resume,
1985 };
1986
1987 static int __init rt2500pci_init(void)
1988 {
1989         return pci_register_driver(&rt2500pci_driver);
1990 }
1991
1992 static void __exit rt2500pci_exit(void)
1993 {
1994         pci_unregister_driver(&rt2500pci_driver);
1995 }
1996
1997 module_init(rt2500pci_init);
1998 module_exit(rt2500pci_exit);