SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/rt2x00/rt2500pci.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2500pci
  23         Abstract: rt2500pci device specific routines.
  24         Supported chipsets: RT2560.
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00pci.h"
  37 #include "rt2500pci.h"
  38
  39 /*
  40  * Register access.
  41  * All access to the CSR registers will go through the methods
  42  * rt2x00pci_register_read and rt2x00pci_register_write.
  43  * BBP and RF register require indirect register access,
  44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  45  * These indirect registers work with busy bits,
  46  * and we will try maximal REGISTER_BUSY_COUNT times to access
  47  * the register while taking a REGISTER_BUSY_DELAY us delay
  48  * between each attampt. When the busy bit is still set at that time,
  49  * the access attempt is considered to have failed,
  50  * and we will print an error.
  51  */
  52 static u32 rt2500pci_bbp_check(struct rt2x00_dev *rt2x00dev)
  53 {
  54         u32 reg;
  55         unsigned int i;
  56
  57         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  58                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  59                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  60                         break;
  61                 udelay(REGISTER_BUSY_DELAY);
  62         }
  63
  64         return reg;
  65 }
  66
  67 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  68                                 const unsigned int word, const u8 value)
  69 {
  70         u32 reg;
  71
  72         /*
  73          * Wait until the BBP becomes ready.
  74          */
  75         reg = rt2500pci_bbp_check(rt2x00dev);
  76         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  77                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  78                 return;
  79         }
  80
  81         /*
  82          * Write the data into the BBP.
  83          */
  84         reg = 0;
  85         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  86         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  87         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  88         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  89
  90         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  91 }
  92
  93 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  94                                const unsigned int word, u8 *value)
  95 {
  96         u32 reg;
  97
  98         /*
  99          * Wait until the BBP becomes ready.
 100          */
 101         reg = rt2500pci_bbp_check(rt2x00dev);
 102         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 103                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 104                 return;
 105         }
 106
 107         /*
 108          * Write the request into the BBP.
 109          */
 110         reg = 0;
 111         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 112         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 113         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 114
 115         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 116
 117         /*
 118          * Wait until the BBP becomes ready.
 119          */
 120         reg = rt2500pci_bbp_check(rt2x00dev);
 121         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 122                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 123                 *value = 0xff;
 124                 return;
 125         }
 126
 127         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 128 }
 129
 130 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
 131                                const unsigned int word, const u32 value)
 132 {
 133         u32 reg;
 134         unsigned int i;
 135
 136         if (!word)
 137                 return;
 138
 139         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 140                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
 141                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
 142                         goto rf_write;
 143                 udelay(REGISTER_BUSY_DELAY);
 144         }
 145
 146         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
 147         return;
 148
 149 rf_write:
 150         reg = 0;
 151         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 152         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 153         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 154         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 155
 156         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 157         rt2x00_rf_write(rt2x00dev, word, value);
 158 }
 159
 160 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 161 {
 162         struct rt2x00_dev *rt2x00dev = eeprom->data;
 163         u32 reg;
 164
 165         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 166
 167         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 168         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 169         eeprom->reg_data_clock =
 170             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 171         eeprom->reg_chip_select =
 172             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 173 }
 174
 175 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 176 {
 177         struct rt2x00_dev *rt2x00dev = eeprom->data;
 178         u32 reg = 0;
 179
 180         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 181         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 182         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 183                            !!eeprom->reg_data_clock);
 184         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 185                            !!eeprom->reg_chip_select);
 186
 187         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 188 }
 189
 190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 191 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 192
 193 static void rt2500pci_read_csr(struct rt2x00_dev *rt2x00dev,
 194                                const unsigned int word, u32 *data)
 195 {
 196         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 197 }
 198
 199 static void rt2500pci_write_csr(struct rt2x00_dev *rt2x00dev,
 200                                 const unsigned int word, u32 data)
 201 {
 202         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 203 }
 204
 205 static const struct rt2x00debug rt2500pci_rt2x00debug = {
 206         .owner  = THIS_MODULE,
 207         .csr    = {
 208                 .read           = rt2500pci_read_csr,
 209                 .write          = rt2500pci_write_csr,
 210                 .word_size      = sizeof(u32),
 211                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 212         },
 213         .eeprom = {
 214                 .read           = rt2x00_eeprom_read,
 215                 .write          = rt2x00_eeprom_write,
 216                 .word_size      = sizeof(u16),
 217                 .word_count     = EEPROM_SIZE / sizeof(u16),
 218         },
 219         .bbp    = {
 220                 .read           = rt2500pci_bbp_read,
 221                 .write          = rt2500pci_bbp_write,
 222                 .word_size      = sizeof(u8),
 223                 .word_count     = BBP_SIZE / sizeof(u8),
 224         },
 225         .rf     = {
 226                 .read           = rt2x00_rf_read,
 227                 .write          = rt2500pci_rf_write,
 228                 .word_size      = sizeof(u32),
 229                 .word_count     = RF_SIZE / sizeof(u32),
 230         },
 231 };
 232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 233
 234 #ifdef CONFIG_RT2500PCI_RFKILL
 235 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 236 {
 237         u32 reg;
 238
 239         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 240         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 241 }
 242 #else
 243 #define rt2500pci_rfkill_poll   NULL
 244 #endif /* CONFIG_RT2500PCI_RFKILL */
 245
 246 #ifdef CONFIG_RT2500PCI_LEDS
 247 static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
 248                                      enum led_brightness brightness)
 249 {
 250         struct rt2x00_led *led =
 251             container_of(led_cdev, struct rt2x00_led, led_dev);
 252         unsigned int enabled = brightness != LED_OFF;
 253         u32 reg;
 254
 255         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 256
 257         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
 258                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 259         else if (led->type == LED_TYPE_ACTIVITY)
 260                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
 261
 262         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 263 }
 264
 265 static int rt2500pci_blink_set(struct led_classdev *led_cdev,
 266                                unsigned long *delay_on,
 267                                unsigned long *delay_off)
 268 {
 269         struct rt2x00_led *led =
 270             container_of(led_cdev, struct rt2x00_led, led_dev);
 271         u32 reg;
 272
 273         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 274         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
 275         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
 276         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 277
 278         return 0;
 279 }
 280
 281 static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
 282                                struct rt2x00_led *led,
 283                                enum led_type type)
 284 {
 285         led->rt2x00dev = rt2x00dev;
 286         led->type = type;
 287         led->led_dev.brightness_set = rt2500pci_brightness_set;
 288         led->led_dev.blink_set = rt2500pci_blink_set;
 289         led->flags = LED_INITIALIZED;
 290 }
 291 #endif /* CONFIG_RT2500PCI_LEDS */
 292
 293 /*
 294  * Configuration handlers.
 295  */
 296 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
 297                                     const unsigned int filter_flags)
 298 {
 299         u32 reg;
 300
 301         /*
 302          * Start configuration steps.
 303          * Note that the version error will always be dropped
 304          * and broadcast frames will always be accepted since
 305          * there is no filter for it at this time.
 306          */
 307         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 308         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
 309                            !(filter_flags & FIF_FCSFAIL));
 310         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
 311                            !(filter_flags & FIF_PLCPFAIL));
 312         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
 313                            !(filter_flags & FIF_CONTROL));
 314         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
 315                            !(filter_flags & FIF_PROMISC_IN_BSS));
 316         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
 317                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 318                            !rt2x00dev->intf_ap_count);
 319         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 320         rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
 321                            !(filter_flags & FIF_ALLMULTI));
 322         rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
 323         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 324 }
 325
 326 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
 327                                   struct rt2x00_intf *intf,
 328                                   struct rt2x00intf_conf *conf,
 329                                   const unsigned int flags)
 330 {
 331         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
 332         unsigned int bcn_preload;
 333         u32 reg;
 334
 335         if (flags & CONFIG_UPDATE_TYPE) {
 336                 /*
 337                  * Enable beacon config
 338                  */
 339                 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
 340                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 341                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 342                 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
 343                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 344
 345                 /*
 346                  * Enable synchronisation.
 347                  */
 348                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 349                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 350                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 351                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 352                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 353         }
 354
 355         if (flags & CONFIG_UPDATE_MAC)
 356                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
 357                                               conf->mac, sizeof(conf->mac));
 358
 359         if (flags & CONFIG_UPDATE_BSSID)
 360                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
 361                                               conf->bssid, sizeof(conf->bssid));
 362 }
 363
 364 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
 365                                  struct rt2x00lib_erp *erp)
 366 {
 367         int preamble_mask;
 368         u32 reg;
 369
 370         /*
 371          * When short preamble is enabled, we should set bit 0x08
 372          */
 373         preamble_mask = erp->short_preamble << 3;
 374
 375         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 376         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
 377                            erp->ack_timeout);
 378         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
 379                            erp->ack_consume_time);
 380         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 381
 382         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 383         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
 384         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 385         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
 386         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 387
 388         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 389         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 390         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 391         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
 392         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 393
 394         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 395         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 396         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 397         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
 398         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 399
 400         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 401         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 402         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 403         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
 404         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 405 }
 406
 407 static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 408                                      const int basic_rate_mask)
 409 {
 410         rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
 411 }
 412
 413 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
 414                                      struct rf_channel *rf, const int txpower)
 415 {
 416         u8 r70;
 417
 418         /*
 419          * Set TXpower.
 420          */
 421         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 422
 423         /*
 424          * Switch on tuning bits.
 425          * For RT2523 devices we do not need to update the R1 register.
 426          */
 427         if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
 428                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 429         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 430
 431         /*
 432          * For RT2525 we should first set the channel to half band higher.
 433          */
 434         if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
 435                 static const u32 vals[] = {
 436                         0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
 437                         0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
 438                         0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
 439                         0x00080d2e, 0x00080d3a
 440                 };
 441
 442                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 443                 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
 444                 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 445                 if (rf->rf4)
 446                         rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 447         }
 448
 449         rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 450         rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
 451         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 452         if (rf->rf4)
 453                 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 454
 455         /*
 456          * Channel 14 requires the Japan filter bit to be set.
 457          */
 458         r70 = 0x46;
 459         rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
 460         rt2500pci_bbp_write(rt2x00dev, 70, r70);
 461
 462         msleep(1);
 463
 464         /*
 465          * Switch off tuning bits.
 466          * For RT2523 devices we do not need to update the R1 register.
 467          */
 468         if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
 469                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 470                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 471         }
 472
 473         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 474         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 475
 476         /*
 477          * Clear false CRC during channel switch.
 478          */
 479         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
 480 }
 481
 482 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 483                                      const int txpower)
 484 {
 485         u32 rf3;
 486
 487         rt2x00_rf_read(rt2x00dev, 3, &rf3);
 488         rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 489         rt2500pci_rf_write(rt2x00dev, 3, rf3);
 490 }
 491
 492 static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 493                                      struct antenna_setup *ant)
 494 {
 495         u32 reg;
 496         u8 r14;
 497         u8 r2;
 498
 499         /*
 500          * We should never come here because rt2x00lib is supposed
 501          * to catch this and send us the correct antenna explicitely.
 502          */
 503         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 504                ant->tx == ANTENNA_SW_DIVERSITY);
 505
 506         rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
 507         rt2500pci_bbp_read(rt2x00dev, 14, &r14);
 508         rt2500pci_bbp_read(rt2x00dev, 2, &r2);
 509
 510         /*
 511          * Configure the TX antenna.
 512          */
 513         switch (ant->tx) {
 514         case ANTENNA_A:
 515                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
 516                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
 517                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
 518                 break;
 519         case ANTENNA_B:
 520         default:
 521                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
 522                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
 523                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
 524                 break;
 525         }
 526
 527         /*
 528          * Configure the RX antenna.
 529          */
 530         switch (ant->rx) {
 531         case ANTENNA_A:
 532                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
 533                 break;
 534         case ANTENNA_B:
 535         default:
 536                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
 537                 break;
 538         }
 539
 540         /*
 541          * RT2525E and RT5222 need to flip TX I/Q
 542          */
 543         if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
 544             rt2x00_rf(&rt2x00dev->chip, RF5222)) {
 545                 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
 546                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
 547                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
 548
 549                 /*
 550                  * RT2525E does not need RX I/Q Flip.
 551                  */
 552                 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
 553                         rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
 554         } else {
 555                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
 556                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
 557         }
 558
 559         rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
 560         rt2500pci_bbp_write(rt2x00dev, 14, r14);
 561         rt2500pci_bbp_write(rt2x00dev, 2, r2);
 562 }
 563
 564 static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
 565                                       struct rt2x00lib_conf *libconf)
 566 {
 567         u32 reg;
 568
 569         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 570         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
 571         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 572
 573         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 574         rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
 575         rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
 576         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 577
 578         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 579         rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
 580         rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
 581         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 582
 583         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 584         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 585         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 586         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 587
 588         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 589         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
 590                            libconf->conf->beacon_int * 16);
 591         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
 592                            libconf->conf->beacon_int * 16);
 593         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 594 }
 595
 596 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
 597                              struct rt2x00lib_conf *libconf,
 598                              const unsigned int flags)
 599 {
 600         if (flags & CONFIG_UPDATE_PHYMODE)
 601                 rt2500pci_config_phymode(rt2x00dev, libconf->basic_rates);
 602         if (flags & CONFIG_UPDATE_CHANNEL)
 603                 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
 604                                          libconf->conf->power_level);
 605         if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
 606                 rt2500pci_config_txpower(rt2x00dev,
 607                                          libconf->conf->power_level);
 608         if (flags & CONFIG_UPDATE_ANTENNA)
 609                 rt2500pci_config_antenna(rt2x00dev, &libconf->ant);
 610         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 611                 rt2500pci_config_duration(rt2x00dev, libconf);
 612 }
 613
 614 /*
 615  * Link tuning
 616  */
 617 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
 618                                  struct link_qual *qual)
 619 {
 620         u32 reg;
 621
 622         /*
 623          * Update FCS error count from register.
 624          */
 625         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 626         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 627
 628         /*
 629          * Update False CCA count from register.
 630          */
 631         rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
 632         qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
 633 }
 634
 635 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 636 {
 637         rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
 638         rt2x00dev->link.vgc_level = 0x48;
 639 }
 640
 641 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 642 {
 643         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
 644         u8 r17;
 645
 646         /*
 647          * To prevent collisions with MAC ASIC on chipsets
 648          * up to version C the link tuning should halt after 20
 649          * seconds while being associated.
 650          */
 651         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
 652             rt2x00dev->intf_associated &&
 653             rt2x00dev->link.count > 20)
 654                 return;
 655
 656         rt2500pci_bbp_read(rt2x00dev, 17, &r17);
 657
 658         /*
 659          * Chipset versions C and lower should directly continue
 660          * to the dynamic CCA tuning. Chipset version D and higher
 661          * should go straight to dynamic CCA tuning when they
 662          * are not associated.
 663          */
 664         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D ||
 665             !rt2x00dev->intf_associated)
 666                 goto dynamic_cca_tune;
 667
 668         /*
 669          * A too low RSSI will cause too much false CCA which will
 670          * then corrupt the R17 tuning. To remidy this the tuning should
 671          * be stopped (While making sure the R17 value will not exceed limits)
 672          */
 673         if (rssi < -80 && rt2x00dev->link.count > 20) {
 674                 if (r17 >= 0x41) {
 675                         r17 = rt2x00dev->link.vgc_level;
 676                         rt2500pci_bbp_write(rt2x00dev, 17, r17);
 677                 }
 678                 return;
 679         }
 680
 681         /*
 682          * Special big-R17 for short distance
 683          */
 684         if (rssi >= -58) {
 685                 if (r17 != 0x50)
 686                         rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
 687                 return;
 688         }
 689
 690         /*
 691          * Special mid-R17 for middle distance
 692          */
 693         if (rssi >= -74) {
 694                 if (r17 != 0x41)
 695                         rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
 696                 return;
 697         }
 698
 699         /*
 700          * Leave short or middle distance condition, restore r17
 701          * to the dynamic tuning range.
 702          */
 703         if (r17 >= 0x41) {
 704                 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
 705                 return;
 706         }
 707
 708 dynamic_cca_tune:
 709
 710         /*
 711          * R17 is inside the dynamic tuning range,
 712          * start tuning the link based on the false cca counter.
 713          */
 714         if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
 715                 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
 716                 rt2x00dev->link.vgc_level = r17;
 717         } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
 718                 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
 719                 rt2x00dev->link.vgc_level = r17;
 720         }
 721 }
 722
 723 /*
 724  * Initialization functions.
 725  */
 726 static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
 727                                    struct queue_entry *entry)
 728 {
 729         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 730         u32 word;
 731
 732         rt2x00_desc_read(entry_priv->desc, 1, &word);
 733         rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, entry_priv->data_dma);
 734         rt2x00_desc_write(entry_priv->desc, 1, word);
 735
 736         rt2x00_desc_read(entry_priv->desc, 0, &word);
 737         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 738         rt2x00_desc_write(entry_priv->desc, 0, word);
 739 }
 740
 741 static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev,
 742                                    struct queue_entry *entry)
 743 {
 744         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 745         u32 word;
 746
 747         rt2x00_desc_read(entry_priv->desc, 0, &word);
 748         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 749         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 750         rt2x00_desc_write(entry_priv->desc, 0, word);
 751 }
 752
 753 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
 754 {
 755         struct queue_entry_priv_pci *entry_priv;
 756         u32 reg;
 757
 758         /*
 759          * Initialize registers.
 760          */
 761         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 762         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 763         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 764         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
 765         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 766         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 767
 768         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 769         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 770         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 771                            entry_priv->desc_dma);
 772         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 773
 774         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 775         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 776         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 777                            entry_priv->desc_dma);
 778         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 779
 780         entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
 781         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 782         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 783                            entry_priv->desc_dma);
 784         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 785
 786         entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
 787         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 788         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 789                            entry_priv->desc_dma);
 790         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 791
 792         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 793         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 794         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 795         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 796
 797         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 798         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 799         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 800                            entry_priv->desc_dma);
 801         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 802
 803         return 0;
 804 }
 805
 806 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
 807 {
 808         u32 reg;
 809
 810         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 811         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 812         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
 813         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 814
 815         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 816         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 817         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 818         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 819         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 820
 821         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 822         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 823                            rt2x00dev->rx->data_size / 128);
 824         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 825
 826         /*
 827          * Always use CWmin and CWmax set in descriptor.
 828          */
 829         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 830         rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
 831         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 832
 833         rt2x00pci_register_write(rt2x00dev, CNT3, 0);
 834
 835         rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
 836         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
 837         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
 838         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
 839         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
 840         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
 841         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
 842         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
 843         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
 844         rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
 845
 846         rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
 847         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
 848         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
 849         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
 850         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
 851         rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
 852
 853         rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
 854         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
 855         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
 856         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
 857         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
 858         rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
 859
 860         rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
 861         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
 862         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
 863         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
 864         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
 865         rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
 866
 867         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 868         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
 869         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 870         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
 871         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 872         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
 873         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 874         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
 875         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
 876         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 877
 878         rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
 879         rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
 880         rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
 881         rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
 882         rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
 883         rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
 884         rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
 885         rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
 886         rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
 887
 888         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 889
 890         rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
 891         rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
 892
 893         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 894                 return -EBUSY;
 895
 896         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
 897         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 898
 899         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 900         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 901         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 902
 903         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 904         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 905         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
 906         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
 907         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 908         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
 909         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
 910         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 911
 912         rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
 913
 914         rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
 915
 916         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 917         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 918         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 919         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 920         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 921
 922         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 923         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 924         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 925         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 926
 927         /*
 928          * We must clear the FCS and FIFO error count.
 929          * These registers are cleared on read,
 930          * so we may pass a useless variable to store the value.
 931          */
 932         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 933         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 934
 935         return 0;
 936 }
 937
 938 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
 939 {
 940         unsigned int i;
 941         u8 value;
 942
 943         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 944                 rt2500pci_bbp_read(rt2x00dev, 0, &value);
 945                 if ((value != 0xff) && (value != 0x00))
 946                         return 0;
 947                 udelay(REGISTER_BUSY_DELAY);
 948         }
 949
 950         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 951         return -EACCES;
 952 }
 953
 954 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 955 {
 956         unsigned int i;
 957         u16 eeprom;
 958         u8 reg_id;
 959         u8 value;
 960
 961         if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
 962                 return -EACCES;
 963
 964         rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
 965         rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
 966         rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
 967         rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
 968         rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
 969         rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
 970         rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
 971         rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
 972         rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
 973         rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
 974         rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
 975         rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
 976         rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
 977         rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
 978         rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
 979         rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
 980         rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
 981         rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
 982         rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
 983         rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
 984         rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
 985         rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
 986         rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
 987         rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
 988         rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
 989         rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
 990         rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
 991         rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
 992         rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
 993         rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
 994
 995         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 996                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
 997
 998                 if (eeprom != 0xffff && eeprom != 0x0000) {
 999                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1000                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1001                         rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1002                 }
1003         }
1004
1005         return 0;
1006 }
1007
1008 /*
1009  * Device state switch handlers.
1010  */
1011 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1012                                 enum dev_state state)
1013 {
1014         u32 reg;
1015
1016         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1017         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1018                            (state == STATE_RADIO_RX_OFF) ||
1019                            (state == STATE_RADIO_RX_OFF_LINK));
1020         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1021 }
1022
1023 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1024                                  enum dev_state state)
1025 {
1026         int mask = (state == STATE_RADIO_IRQ_OFF);
1027         u32 reg;
1028
1029         /*
1030          * When interrupts are being enabled, the interrupt registers
1031          * should clear the register to assure a clean state.
1032          */
1033         if (state == STATE_RADIO_IRQ_ON) {
1034                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1035                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1036         }
1037
1038         /*
1039          * Only toggle the interrupts bits we are going to use.
1040          * Non-checked interrupt bits are disabled by default.
1041          */
1042         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1043         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1044         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1045         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1046         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1047         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1048         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1049 }
1050
1051 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1052 {
1053         /*
1054          * Initialize all registers.
1055          */
1056         if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1057                      rt2500pci_init_registers(rt2x00dev) ||
1058                      rt2500pci_init_bbp(rt2x00dev)))
1059                 return -EIO;
1060
1061         return 0;
1062 }
1063
1064 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1065 {
1066         u32 reg;
1067
1068         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1069
1070         /*
1071          * Disable synchronisation.
1072          */
1073         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1074
1075         /*
1076          * Cancel RX and TX.
1077          */
1078         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1079         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1080         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1081 }
1082
1083 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1084                                enum dev_state state)
1085 {
1086         u32 reg;
1087         unsigned int i;
1088         char put_to_sleep;
1089         char bbp_state;
1090         char rf_state;
1091
1092         put_to_sleep = (state != STATE_AWAKE);
1093
1094         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1095         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1096         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1097         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1098         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1099         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1100
1101         /*
1102          * Device is not guaranteed to be in the requested state yet.
1103          * We must wait until the register indicates that the
1104          * device has entered the correct state.
1105          */
1106         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1107                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1108                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1109                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1110                 if (bbp_state == state && rf_state == state)
1111                         return 0;
1112                 msleep(10);
1113         }
1114
1115         return -EBUSY;
1116 }
1117
1118 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1119                                       enum dev_state state)
1120 {
1121         int retval = 0;
1122
1123         switch (state) {
1124         case STATE_RADIO_ON:
1125                 retval = rt2500pci_enable_radio(rt2x00dev);
1126                 break;
1127         case STATE_RADIO_OFF:
1128                 rt2500pci_disable_radio(rt2x00dev);
1129                 break;
1130         case STATE_RADIO_RX_ON:
1131         case STATE_RADIO_RX_ON_LINK:
1132         case STATE_RADIO_RX_OFF:
1133         case STATE_RADIO_RX_OFF_LINK:
1134                 rt2500pci_toggle_rx(rt2x00dev, state);
1135                 break;
1136         case STATE_RADIO_IRQ_ON:
1137         case STATE_RADIO_IRQ_OFF:
1138                 rt2500pci_toggle_irq(rt2x00dev, state);
1139                 break;
1140         case STATE_DEEP_SLEEP:
1141         case STATE_SLEEP:
1142         case STATE_STANDBY:
1143         case STATE_AWAKE:
1144                 retval = rt2500pci_set_state(rt2x00dev, state);
1145                 break;
1146         default:
1147                 retval = -ENOTSUPP;
1148                 break;
1149         }
1150
1151         if (unlikely(retval))
1152                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1153                       state, retval);
1154
1155         return retval;
1156 }
1157
1158 /*
1159  * TX descriptor initialization
1160  */
1161 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1162                                     struct sk_buff *skb,
1163                                     struct txentry_desc *txdesc)
1164 {
1165         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1166         struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1167         __le32 *txd = skbdesc->desc;
1168         u32 word;
1169
1170         /*
1171          * Start writing the descriptor words.
1172          */
1173         rt2x00_desc_read(entry_priv->desc, 1, &word);
1174         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, entry_priv->data_dma);
1175         rt2x00_desc_write(entry_priv->desc, 1, word);
1176
1177         rt2x00_desc_read(txd, 2, &word);
1178         rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1179         rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1180         rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1181         rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
1182         rt2x00_desc_write(txd, 2, word);
1183
1184         rt2x00_desc_read(txd, 3, &word);
1185         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1186         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1187         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1188         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
1189         rt2x00_desc_write(txd, 3, word);
1190
1191         rt2x00_desc_read(txd, 10, &word);
1192         rt2x00_set_field32(&word, TXD_W10_RTS,
1193                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1194         rt2x00_desc_write(txd, 10, word);
1195
1196         rt2x00_desc_read(txd, 0, &word);
1197         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1198         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1199         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1200                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1201         rt2x00_set_field32(&word, TXD_W0_ACK,
1202                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1203         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1204                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1205         rt2x00_set_field32(&word, TXD_W0_OFDM,
1206                            test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1207         rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1208         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1209         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1210                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1211         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1212         rt2x00_desc_write(txd, 0, word);
1213 }
1214
1215 /*
1216  * TX data initialization
1217  */
1218 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1219                                     const enum data_queue_qid queue)
1220 {
1221         u32 reg;
1222
1223         if (queue == QID_BEACON) {
1224                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1225                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1226                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1227                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1228                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1229                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1230                 }
1231                 return;
1232         }
1233
1234         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1235         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1236         rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1237         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1238         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1239 }
1240
1241 /*
1242  * RX control handlers
1243  */
1244 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1245                                   struct rxdone_entry_desc *rxdesc)
1246 {
1247         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1248         u32 word0;
1249         u32 word2;
1250
1251         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1252         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1253
1254         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1255                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1256         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1257                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1258
1259         /*
1260          * Obtain the status about this packet.
1261          * When frame was received with an OFDM bitrate,
1262          * the signal is the PLCP value. If it was received with
1263          * a CCK bitrate the signal is the rate in 100kbit/s.
1264          */
1265         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1266         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1267             entry->queue->rt2x00dev->rssi_offset;
1268         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1269
1270         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1271                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1272         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1273                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1274 }
1275
1276 /*
1277  * Interrupt functions.
1278  */
1279 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1280                              const enum data_queue_qid queue_idx)
1281 {
1282         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1283         struct queue_entry_priv_pci *entry_priv;
1284         struct queue_entry *entry;
1285         struct txdone_entry_desc txdesc;
1286         u32 word;
1287
1288         while (!rt2x00queue_empty(queue)) {
1289                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1290                 entry_priv = entry->priv_data;
1291                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1292
1293                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1294                     !rt2x00_get_field32(word, TXD_W0_VALID))
1295                         break;
1296
1297                 /*
1298                  * Obtain the status about this packet.
1299                  */
1300                 txdesc.flags = 0;
1301                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1302                 case 0: /* Success */
1303                 case 1: /* Success with retry */
1304                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1305                         break;
1306                 case 2: /* Failure, excessive retries */
1307                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1308                         /* Don't break, this is a failed frame! */
1309                 default: /* Failure */
1310                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1311                 }
1312                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1313
1314                 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1315         }
1316 }
1317
1318 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1319 {
1320         struct rt2x00_dev *rt2x00dev = dev_instance;
1321         u32 reg;
1322
1323         /*
1324          * Get the interrupt sources & saved to local variable.
1325          * Write register value back to clear pending interrupts.
1326          */
1327         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1328         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1329
1330         if (!reg)
1331                 return IRQ_NONE;
1332
1333         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1334                 return IRQ_HANDLED;
1335
1336         /*
1337          * Handle interrupts, walk through all bits
1338          * and run the tasks, the bits are checked in order of
1339          * priority.
1340          */
1341
1342         /*
1343          * 1 - Beacon timer expired interrupt.
1344          */
1345         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1346                 rt2x00lib_beacondone(rt2x00dev);
1347
1348         /*
1349          * 2 - Rx ring done interrupt.
1350          */
1351         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1352                 rt2x00pci_rxdone(rt2x00dev);
1353
1354         /*
1355          * 3 - Atim ring transmit done interrupt.
1356          */
1357         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1358                 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1359
1360         /*
1361          * 4 - Priority ring transmit done interrupt.
1362          */
1363         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1364                 rt2500pci_txdone(rt2x00dev, QID_AC_BE);
1365
1366         /*
1367          * 5 - Tx ring transmit done interrupt.
1368          */
1369         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1370                 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
1371
1372         return IRQ_HANDLED;
1373 }
1374
1375 /*
1376  * Device probe functions.
1377  */
1378 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1379 {
1380         struct eeprom_93cx6 eeprom;
1381         u32 reg;
1382         u16 word;
1383         u8 *mac;
1384
1385         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1386
1387         eeprom.data = rt2x00dev;
1388         eeprom.register_read = rt2500pci_eepromregister_read;
1389         eeprom.register_write = rt2500pci_eepromregister_write;
1390         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1391             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1392         eeprom.reg_data_in = 0;
1393         eeprom.reg_data_out = 0;
1394         eeprom.reg_data_clock = 0;
1395         eeprom.reg_chip_select = 0;
1396
1397         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1398                                EEPROM_SIZE / sizeof(u16));
1399
1400         /*
1401          * Start validation of the data that has been read.
1402          */
1403         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1404         if (!is_valid_ether_addr(mac)) {
1405                 DECLARE_MAC_BUF(macbuf);
1406
1407                 random_ether_addr(mac);
1408                 EEPROM(rt2x00dev, "MAC: %s\n",
1409                        print_mac(macbuf, mac));
1410         }
1411
1412         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1413         if (word == 0xffff) {
1414                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1415                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1416                                    ANTENNA_SW_DIVERSITY);
1417                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1418                                    ANTENNA_SW_DIVERSITY);
1419                 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1420                                    LED_MODE_DEFAULT);
1421                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1422                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1423                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1424                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1425                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1426         }
1427
1428         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1429         if (word == 0xffff) {
1430                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1431                 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1432                 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1433                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1434                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1435         }
1436
1437         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1438         if (word == 0xffff) {
1439                 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1440                                    DEFAULT_RSSI_OFFSET);
1441                 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1442                 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1443         }
1444
1445         return 0;
1446 }
1447
1448 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1449 {
1450         u32 reg;
1451         u16 value;
1452         u16 eeprom;
1453
1454         /*
1455          * Read EEPROM word for configuration.
1456          */
1457         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1458
1459         /*
1460          * Identify RF chipset.
1461          */
1462         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1463         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1464         rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1465
1466         if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1467             !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1468             !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1469             !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1470             !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1471             !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1472                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1473                 return -ENODEV;
1474         }
1475
1476         /*
1477          * Identify default antenna configuration.
1478          */
1479         rt2x00dev->default_ant.tx =
1480             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1481         rt2x00dev->default_ant.rx =
1482             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1483
1484         /*
1485          * Store led mode, for correct led behaviour.
1486          */
1487 #ifdef CONFIG_RT2500PCI_LEDS
1488         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1489
1490         rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1491         if (value == LED_MODE_TXRX_ACTIVITY)
1492                 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1493                                    LED_TYPE_ACTIVITY);
1494 #endif /* CONFIG_RT2500PCI_LEDS */
1495
1496         /*
1497          * Detect if this device has an hardware controlled radio.
1498          */
1499 #ifdef CONFIG_RT2500PCI_RFKILL
1500         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1501                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1502 #endif /* CONFIG_RT2500PCI_RFKILL */
1503
1504         /*
1505          * Check if the BBP tuning should be enabled.
1506          */
1507         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1508
1509         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1510                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1511
1512         /*
1513          * Read the RSSI <-> dBm offset information.
1514          */
1515         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1516         rt2x00dev->rssi_offset =
1517             rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1518
1519         return 0;
1520 }
1521
1522 /*
1523  * RF value list for RF2522
1524  * Supports: 2.4 GHz
1525  */
1526 static const struct rf_channel rf_vals_bg_2522[] = {
1527         { 1,  0x00002050, 0x000c1fda, 0x00000101, 0 },
1528         { 2,  0x00002050, 0x000c1fee, 0x00000101, 0 },
1529         { 3,  0x00002050, 0x000c2002, 0x00000101, 0 },
1530         { 4,  0x00002050, 0x000c2016, 0x00000101, 0 },
1531         { 5,  0x00002050, 0x000c202a, 0x00000101, 0 },
1532         { 6,  0x00002050, 0x000c203e, 0x00000101, 0 },
1533         { 7,  0x00002050, 0x000c2052, 0x00000101, 0 },
1534         { 8,  0x00002050, 0x000c2066, 0x00000101, 0 },
1535         { 9,  0x00002050, 0x000c207a, 0x00000101, 0 },
1536         { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1537         { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1538         { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1539         { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1540         { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1541 };
1542
1543 /*
1544  * RF value list for RF2523
1545  * Supports: 2.4 GHz
1546  */
1547 static const struct rf_channel rf_vals_bg_2523[] = {
1548         { 1,  0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1549         { 2,  0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1550         { 3,  0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1551         { 4,  0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1552         { 5,  0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1553         { 6,  0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1554         { 7,  0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1555         { 8,  0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1556         { 9,  0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1557         { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1558         { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1559         { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1560         { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1561         { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1562 };
1563
1564 /*
1565  * RF value list for RF2524
1566  * Supports: 2.4 GHz
1567  */
1568 static const struct rf_channel rf_vals_bg_2524[] = {
1569         { 1,  0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1570         { 2,  0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1571         { 3,  0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1572         { 4,  0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1573         { 5,  0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1574         { 6,  0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1575         { 7,  0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1576         { 8,  0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1577         { 9,  0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1578         { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1579         { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1580         { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1581         { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1582         { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1583 };
1584
1585 /*
1586  * RF value list for RF2525
1587  * Supports: 2.4 GHz
1588  */
1589 static const struct rf_channel rf_vals_bg_2525[] = {
1590         { 1,  0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1591         { 2,  0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1592         { 3,  0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1593         { 4,  0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1594         { 5,  0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1595         { 6,  0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1596         { 7,  0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1597         { 8,  0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1598         { 9,  0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1599         { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1600         { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1601         { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1602         { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1603         { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1604 };
1605
1606 /*
1607  * RF value list for RF2525e
1608  * Supports: 2.4 GHz
1609  */
1610 static const struct rf_channel rf_vals_bg_2525e[] = {
1611         { 1,  0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1612         { 2,  0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1613         { 3,  0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1614         { 4,  0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1615         { 5,  0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1616         { 6,  0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1617         { 7,  0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1618         { 8,  0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1619         { 9,  0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1620         { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1621         { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1622         { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1623         { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1624         { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1625 };
1626
1627 /*
1628  * RF value list for RF5222
1629  * Supports: 2.4 GHz & 5.2 GHz
1630  */
1631 static const struct rf_channel rf_vals_5222[] = {
1632         { 1,  0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1633         { 2,  0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1634         { 3,  0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1635         { 4,  0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1636         { 5,  0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1637         { 6,  0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1638         { 7,  0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1639         { 8,  0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1640         { 9,  0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1641         { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1642         { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1643         { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1644         { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1645         { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1646
1647         /* 802.11 UNI / HyperLan 2 */
1648         { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1649         { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1650         { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1651         { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1652         { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1653         { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1654         { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1655         { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1656
1657         /* 802.11 HyperLan 2 */
1658         { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1659         { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1660         { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1661         { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1662         { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1663         { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1664         { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1665         { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1666         { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1667         { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1668
1669         /* 802.11 UNII */
1670         { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1671         { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1672         { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1673         { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1674         { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1675 };
1676
1677 static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1678 {
1679         struct hw_mode_spec *spec = &rt2x00dev->spec;
1680         u8 *txpower;
1681         unsigned int i;
1682
1683         /*
1684          * Initialize all hw fields.
1685          */
1686         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1687                                IEEE80211_HW_SIGNAL_DBM;
1688
1689         rt2x00dev->hw->extra_tx_headroom = 0;
1690
1691         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1692         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1693                                 rt2x00_eeprom_addr(rt2x00dev,
1694                                                    EEPROM_MAC_ADDR_0));
1695
1696         /*
1697          * Convert tx_power array in eeprom.
1698          */
1699         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1700         for (i = 0; i < 14; i++)
1701                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1702
1703         /*
1704          * Initialize hw_mode information.
1705          */
1706         spec->supported_bands = SUPPORT_BAND_2GHZ;
1707         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1708         spec->tx_power_a = NULL;
1709         spec->tx_power_bg = txpower;
1710         spec->tx_power_default = DEFAULT_TXPOWER;
1711
1712         if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1713                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1714                 spec->channels = rf_vals_bg_2522;
1715         } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1716                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1717                 spec->channels = rf_vals_bg_2523;
1718         } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1719                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1720                 spec->channels = rf_vals_bg_2524;
1721         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1722                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1723                 spec->channels = rf_vals_bg_2525;
1724         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1725                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1726                 spec->channels = rf_vals_bg_2525e;
1727         } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1728                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1729                 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1730                 spec->channels = rf_vals_5222;
1731         }
1732 }
1733
1734 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1735 {
1736         int retval;
1737
1738         /*
1739          * Allocate eeprom data.
1740          */
1741         retval = rt2500pci_validate_eeprom(rt2x00dev);
1742         if (retval)
1743                 return retval;
1744
1745         retval = rt2500pci_init_eeprom(rt2x00dev);
1746         if (retval)
1747                 return retval;
1748
1749         /*
1750          * Initialize hw specifications.
1751          */
1752         rt2500pci_probe_hw_mode(rt2x00dev);
1753
1754         /*
1755          * This device requires the atim queue
1756          */
1757         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1758
1759         /*
1760          * Set the rssi offset.
1761          */
1762         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1763
1764         return 0;
1765 }
1766
1767 /*
1768  * IEEE80211 stack callback functions.
1769  */
1770 static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1771                                      u32 short_retry, u32 long_retry)
1772 {
1773         struct rt2x00_dev *rt2x00dev = hw->priv;
1774         u32 reg;
1775
1776         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1777         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1778         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1779         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1780
1781         return 0;
1782 }
1783
1784 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1785 {
1786         struct rt2x00_dev *rt2x00dev = hw->priv;
1787         u64 tsf;
1788         u32 reg;
1789
1790         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1791         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1792         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1793         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1794
1795         return tsf;
1796 }
1797
1798 static int rt2500pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
1799 {
1800         struct rt2x00_dev *rt2x00dev = hw->priv;
1801         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1802         struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
1803         struct queue_entry_priv_pci *entry_priv;
1804         struct skb_frame_desc *skbdesc;
1805         struct txentry_desc txdesc;
1806         u32 reg;
1807
1808         if (unlikely(!intf->beacon))
1809                 return -ENOBUFS;
1810
1811         entry_priv = intf->beacon->priv_data;
1812
1813         /*
1814          * Copy all TX descriptor information into txdesc,
1815          * after that we are free to use the skb->cb array
1816          * for our information.
1817          */
1818         intf->beacon->skb = skb;
1819         rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
1820
1821         /*
1822          * Fill in skb descriptor
1823          */
1824         skbdesc = get_skb_frame_desc(skb);
1825         memset(skbdesc, 0, sizeof(*skbdesc));
1826         skbdesc->desc = entry_priv->desc;
1827         skbdesc->desc_len = intf->beacon->queue->desc_size;
1828         skbdesc->entry = intf->beacon;
1829
1830         /*
1831          * Disable beaconing while we are reloading the beacon data,
1832          * otherwise we might be sending out invalid data.
1833          */
1834         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1835         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1836         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1837         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1838         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1839
1840         /*
1841          * Enable beacon generation.
1842          * Write entire beacon with descriptor to register,
1843          * and kick the beacon generator.
1844          */
1845         memcpy(entry_priv->data, skb->data, skb->len);
1846         rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
1847         rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
1848
1849         return 0;
1850 }
1851
1852 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1853 {
1854         struct rt2x00_dev *rt2x00dev = hw->priv;
1855         u32 reg;
1856
1857         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1858         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1859 }
1860
1861 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1862         .tx                     = rt2x00mac_tx,
1863         .start                  = rt2x00mac_start,
1864         .stop                   = rt2x00mac_stop,
1865         .add_interface          = rt2x00mac_add_interface,
1866         .remove_interface       = rt2x00mac_remove_interface,
1867         .config                 = rt2x00mac_config,
1868         .config_interface       = rt2x00mac_config_interface,
1869         .configure_filter       = rt2x00mac_configure_filter,
1870         .get_stats              = rt2x00mac_get_stats,
1871         .set_retry_limit        = rt2500pci_set_retry_limit,
1872         .bss_info_changed       = rt2x00mac_bss_info_changed,
1873         .conf_tx                = rt2x00mac_conf_tx,
1874         .get_tx_stats           = rt2x00mac_get_tx_stats,
1875         .get_tsf                = rt2500pci_get_tsf,
1876         .beacon_update          = rt2500pci_beacon_update,
1877         .tx_last_beacon         = rt2500pci_tx_last_beacon,
1878 };
1879
1880 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1881         .irq_handler            = rt2500pci_interrupt,
1882         .probe_hw               = rt2500pci_probe_hw,
1883         .initialize             = rt2x00pci_initialize,
1884         .uninitialize           = rt2x00pci_uninitialize,
1885         .init_rxentry           = rt2500pci_init_rxentry,
1886         .init_txentry           = rt2500pci_init_txentry,
1887         .set_device_state       = rt2500pci_set_device_state,
1888         .rfkill_poll            = rt2500pci_rfkill_poll,
1889         .link_stats             = rt2500pci_link_stats,
1890         .reset_tuner            = rt2500pci_reset_tuner,
1891         .link_tuner             = rt2500pci_link_tuner,
1892         .write_tx_desc          = rt2500pci_write_tx_desc,
1893         .write_tx_data          = rt2x00pci_write_tx_data,
1894         .kick_tx_queue          = rt2500pci_kick_tx_queue,
1895         .fill_rxdone            = rt2500pci_fill_rxdone,
1896         .config_filter          = rt2500pci_config_filter,
1897         .config_intf            = rt2500pci_config_intf,
1898         .config_erp             = rt2500pci_config_erp,
1899         .config                 = rt2500pci_config,
1900 };
1901
1902 static const struct data_queue_desc rt2500pci_queue_rx = {
1903         .entry_num              = RX_ENTRIES,
1904         .data_size              = DATA_FRAME_SIZE,
1905         .desc_size              = RXD_DESC_SIZE,
1906         .priv_size              = sizeof(struct queue_entry_priv_pci),
1907 };
1908
1909 static const struct data_queue_desc rt2500pci_queue_tx = {
1910         .entry_num              = TX_ENTRIES,
1911         .data_size              = DATA_FRAME_SIZE,
1912         .desc_size              = TXD_DESC_SIZE,
1913         .priv_size              = sizeof(struct queue_entry_priv_pci),
1914 };
1915
1916 static const struct data_queue_desc rt2500pci_queue_bcn = {
1917         .entry_num              = BEACON_ENTRIES,
1918         .data_size              = MGMT_FRAME_SIZE,
1919         .desc_size              = TXD_DESC_SIZE,
1920         .priv_size              = sizeof(struct queue_entry_priv_pci),
1921 };
1922
1923 static const struct data_queue_desc rt2500pci_queue_atim = {
1924         .entry_num              = ATIM_ENTRIES,
1925         .data_size              = DATA_FRAME_SIZE,
1926         .desc_size              = TXD_DESC_SIZE,
1927         .priv_size              = sizeof(struct queue_entry_priv_pci),
1928 };
1929
1930 static const struct rt2x00_ops rt2500pci_ops = {
1931         .name           = KBUILD_MODNAME,
1932         .max_sta_intf   = 1,
1933         .max_ap_intf    = 1,
1934         .eeprom_size    = EEPROM_SIZE,
1935         .rf_size        = RF_SIZE,
1936         .tx_queues      = NUM_TX_QUEUES,
1937         .rx             = &rt2500pci_queue_rx,
1938         .tx             = &rt2500pci_queue_tx,
1939         .bcn            = &rt2500pci_queue_bcn,
1940         .atim           = &rt2500pci_queue_atim,
1941         .lib            = &rt2500pci_rt2x00_ops,
1942         .hw             = &rt2500pci_mac80211_ops,
1943 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1944         .debugfs        = &rt2500pci_rt2x00debug,
1945 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1946 };
1947
1948 /*
1949  * RT2500pci module information.
1950  */
1951 static struct pci_device_id rt2500pci_device_table[] = {
1952         { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1953         { 0, }
1954 };
1955
1956 MODULE_AUTHOR(DRV_PROJECT);
1957 MODULE_VERSION(DRV_VERSION);
1958 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1959 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1960 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1961 MODULE_LICENSE("GPL");
1962
1963 static struct pci_driver rt2500pci_driver = {
1964         .name           = KBUILD_MODNAME,
1965         .id_table       = rt2500pci_device_table,
1966         .probe          = rt2x00pci_probe,
1967         .remove         = __devexit_p(rt2x00pci_remove),
1968         .suspend        = rt2x00pci_suspend,
1969         .resume         = rt2x00pci_resume,
1970 };
1971
1972 static int __init rt2500pci_init(void)
1973 {
1974         return pci_register_driver(&rt2500pci_driver);
1975 }
1976
1977 static void __exit rt2500pci_exit(void)
1978 {
1979         pci_unregister_driver(&rt2500pci_driver);
1980 }
1981
1982 module_init(rt2500pci_init);
1983 module_exit(rt2500pci_exit);